Gary Z / ENORA-Forth-8xx

LPC8xx Forth in assembler, from a Kiel user Starting point for a Work In Progress

Fork of ENORA-Forth by Gérard Sontag

Original author reports this (original file) compiled with Kiel tools. It is for an NXP LPC812 processor on the 800MAX board. It is considered a Table Token Forth. ARM compiler/assembler is not as robust as the Kiel - per the original author.

lpc8xx.s@1:d7744c74e50f, 2015-12-06 (annotated)

Committer:
olzeke51
Date:
Sun Dec 06 05:18:41 2015 +0000
Revision:
1:d7744c74e50f
Parent:
0:df922596d756 
basic copy of original

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Recifarium 0:df922596d756 1
Recifarium 0:df922596d756 2 RAMForIAP EQU 128
Recifarium 0:df922596d756 3 RomSize EQU 0x4000
Recifarium 0:df922596d756 4
Recifarium 0:df922596d756 5 ;-----------------------------------
Recifarium 0:df922596d756 6 ; This is the specific file for
Recifarium 0:df922596d756 7 ; LPC8xx chip
Recifarium 0:df922596d756 8 ; to be used with forth main program
Recifarium 0:df922596d756 9 ;-----------------------------------
Recifarium 0:df922596d756 10 APB EQU 0x40000000
Recifarium 0:df922596d756 11 PINASSIGN0 EQU 0x4000C000
Recifarium 0:df922596d756 12 SYSAHBCLKCTRL EQU 0x40048080
Recifarium 0:df922596d756 13 UARTCLKDIV EQU 0x40048094
Recifarium 0:df922596d756 14 USART0 EQU 0x40064000
Recifarium 0:df922596d756 15 CFG EQU 0x000
Recifarium 0:df922596d756 16 CTL EQU 0x004
Recifarium 0:df922596d756 17 STAT EQU 0x008
Recifarium 0:df922596d756 18 INTENSET EQU 0x00C
Recifarium 0:df922596d756 19 INTENCLR EQU 0x010
Recifarium 0:df922596d756 20 RXDAT EQU 0x014
Recifarium 0:df922596d756 21 TXDAT EQU 0x01C
Recifarium 0:df922596d756 22 BRG EQU 0x020
Recifarium 0:df922596d756 23 INTSTAT EQU 0x024
Recifarium 0:df922596d756 24 PIO0_1 EQU 1
Recifarium 0:df922596d756 25 PIO0_6 EQU 6
Recifarium 0:df922596d756 26 RX EQU PIO0_1
Recifarium 0:df922596d756 27 TX EQU PIO0_6
Recifarium 0:df922596d756 28
Recifarium 0:df922596d756 29 ;/*****************************************************************************
Recifarium 0:df922596d756 30 ; * @file: startup_LPC8xx.s
Recifarium 0:df922596d756 31 ; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
Recifarium 0:df922596d756 32 ; * for the NXP LPC8xx Device Series
Recifarium 0:df922596d756 33 ; * @version: V1.0
Recifarium 0:df922596d756 34 ; * @date: 16. Aug. 2012
Recifarium 0:df922596d756 35 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
Recifarium 0:df922596d756 36 ; *
Recifarium 0:df922596d756 37 ; * Copyright (C) 2012 ARM Limited. All rights reserved.
Recifarium 0:df922596d756 38 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
Recifarium 0:df922596d756 39 ; * processor based microcontrollers. This file can be freely distributed
Recifarium 0:df922596d756 40 ; * within development tools that are supporting such ARM based processors.
Recifarium 0:df922596d756 41 ; *
Recifarium 0:df922596d756 42 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Recifarium 0:df922596d756 43 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Recifarium 0:df922596d756 44 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Recifarium 0:df922596d756 45 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Recifarium 0:df922596d756 46 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Recifarium 0:df922596d756 47 ; *
Recifarium 0:df922596d756 48 ; *****************************************************************************/
Recifarium 0:df922596d756 49 ; Vector Table Mapped to Address 0 at Reset
Recifarium 0:df922596d756 50 THUMB
Recifarium 0:df922596d756 51 AREA RESET, DATA , READONLY
Recifarium 0:df922596d756 52 EXPORT __Vectors
Recifarium 0:df922596d756 53
Recifarium 0:df922596d756 54 __Vectors DCD __initial_sp ; Top of Stack
Recifarium 0:df922596d756 55 DCD Reset_Handler ; Reset Handler
Recifarium 0:df922596d756 56 DCD NMI_Handler ; NMI Handler
Recifarium 0:df922596d756 57 DCD HardFault_Handler ; Hard Fault Handler
Recifarium 0:df922596d756 58 DCD 0 ; Reserved
Recifarium 0:df922596d756 59 DCD 0 ; Reserved
Recifarium 0:df922596d756 60 DCD 0 ; Reserved
Recifarium 0:df922596d756 61 DCD 0 ; Reserved
Recifarium 0:df922596d756 62 DCD 0 ; Reserved
Recifarium 0:df922596d756 63 DCD 0 ; Reserved
Recifarium 0:df922596d756 64 DCD 0 ; Reserved
Recifarium 0:df922596d756 65 DCD SVC_Handler ; SVCall Handler
Recifarium 0:df922596d756 66 DCD 0 ; Reserved
Recifarium 0:df922596d756 67 DCD 0 ; Reserved
Recifarium 0:df922596d756 68 DCD PendSV_Handler ; PendSV Handler
Recifarium 0:df922596d756 69 DCD SysTick_Handler ; SysTick Handler
Recifarium 0:df922596d756 70
Recifarium 0:df922596d756 71 ; External Interrupts
Recifarium 0:df922596d756 72 DCD SPI0_IRQHandler ; SPI0 controller
Recifarium 0:df922596d756 73 DCD SPI1_IRQHandler ; SPI1 controller
Recifarium 0:df922596d756 74 DCD 0 ; Reserved
Recifarium 0:df922596d756 75 DCD UART0_IRQHandler ; UART0
Recifarium 0:df922596d756 76 DCD UART1_IRQHandler ; UART1
Recifarium 0:df922596d756 77 DCD UART2_IRQHandler ; UART2
Recifarium 0:df922596d756 78 DCD 0 ; Reserved
Recifarium 0:df922596d756 79 DCD 0 ; Reserved
Recifarium 0:df922596d756 80 DCD I2C_IRQHandler ; I2C controller
Recifarium 0:df922596d756 81 DCD SCT_IRQHandler ; Smart Counter Timer
Recifarium 0:df922596d756 82 DCD MRT_IRQHandler ; Multi-Rate Timer
Recifarium 0:df922596d756 83 DCD CMP_IRQHandler ; Comparator
Recifarium 0:df922596d756 84 DCD WDT_IRQHandler ; PIO1 (0:11)
Recifarium 0:df922596d756 85 DCD BOD_IRQHandler ; Brown Out Detect
Recifarium 0:df922596d756 86 DCD 0 ; Reserved
Recifarium 0:df922596d756 87 DCD WKT_IRQHandler ; Wakeup timer
Recifarium 0:df922596d756 88 DCD 0 ; Reserved
Recifarium 0:df922596d756 89 DCD 0 ; Reserved
Recifarium 0:df922596d756 90 DCD 0 ; Reserved
Recifarium 0:df922596d756 91 DCD 0 ; Reserved
Recifarium 0:df922596d756 92 DCD 0 ; Reserved
Recifarium 0:df922596d756 93 DCD 0 ; Reserved
Recifarium 0:df922596d756 94 DCD 0 ; Reserved
Recifarium 0:df922596d756 95 DCD 0 ; Reserved
Recifarium 0:df922596d756 96 DCD PININT0_IRQHandler ; PIO INT0
Recifarium 0:df922596d756 97 DCD PININT1_IRQHandler ; PIO INT1
Recifarium 0:df922596d756 98 DCD PININT2_IRQHandler ; PIO INT2
Recifarium 0:df922596d756 99 DCD PININT3_IRQHandler ; PIO INT3
Recifarium 0:df922596d756 100 DCD PININT4_IRQHandler ; PIO INT4
Recifarium 0:df922596d756 101 DCD PININT5_IRQHandler ; PIO INT5
Recifarium 0:df922596d756 102 DCD PININT6_IRQHandler ; PIO INT6
Recifarium 0:df922596d756 103 DCD PININT7_IRQHandler ; PIO INT7
Recifarium 0:df922596d756 104
Recifarium 0:df922596d756 105 IF :LNOT::DEF:NO_CRP
Recifarium 0:df922596d756 106 AREA |.ARM.__at_0x02FC|, CODE
Recifarium 0:df922596d756 107 ; , READONLY
Recifarium 0:df922596d756 108 CRP_Key DCD 0xFFFFFFFF
Recifarium 0:df922596d756 109 ENDIF
Recifarium 0:df922596d756 110
Recifarium 0:df922596d756 111 AREA |.text|, CODE
Recifarium 0:df922596d756 112 HardFault_Handler\
Recifarium 0:df922596d756 113 PROC
Recifarium 0:df922596d756 114 EXPORT HardFault_Handler [WEAK]
Recifarium 0:df922596d756 115 B .
Recifarium 0:df922596d756 116 ENDP
Recifarium 0:df922596d756 117 SVC_Handler PROC
Recifarium 0:df922596d756 118 EXPORT SVC_Handler [WEAK]
Recifarium 0:df922596d756 119 B .
Recifarium 0:df922596d756 120 ENDP
Recifarium 0:df922596d756 121 PendSV_Handler PROC
Recifarium 0:df922596d756 122 EXPORT PendSV_Handler [WEAK]
Recifarium 0:df922596d756 123 B .
Recifarium 0:df922596d756 124 ENDP
Recifarium 0:df922596d756 125 SysTick_Handler PROC
Recifarium 0:df922596d756 126 EXPORT SysTick_Handler [WEAK]
Recifarium 0:df922596d756 127 B .
Recifarium 0:df922596d756 128 ENDP
Recifarium 0:df922596d756 129
Recifarium 0:df922596d756 130 Default_Handler PROC
Recifarium 0:df922596d756 131
Recifarium 0:df922596d756 132 EXPORT NMI_Handler [WEAK]
Recifarium 0:df922596d756 133 EXPORT SPI0_IRQHandler [WEAK]
Recifarium 0:df922596d756 134 EXPORT SPI1_IRQHandler [WEAK]
Recifarium 0:df922596d756 135 EXPORT UART0_IRQHandler [WEAK]
Recifarium 0:df922596d756 136 EXPORT UART1_IRQHandler [WEAK]
Recifarium 0:df922596d756 137 EXPORT UART2_IRQHandler [WEAK]
Recifarium 0:df922596d756 138 EXPORT I2C_IRQHandler [WEAK]
Recifarium 0:df922596d756 139 EXPORT SCT_IRQHandler [WEAK]
Recifarium 0:df922596d756 140 EXPORT MRT_IRQHandler [WEAK]
Recifarium 0:df922596d756 141 EXPORT CMP_IRQHandler [WEAK]
Recifarium 0:df922596d756 142 EXPORT WDT_IRQHandler [WEAK]
Recifarium 0:df922596d756 143 EXPORT BOD_IRQHandler [WEAK]
Recifarium 0:df922596d756 144 EXPORT WKT_IRQHandler [WEAK]
Recifarium 0:df922596d756 145 EXPORT PININT0_IRQHandler [WEAK]
Recifarium 0:df922596d756 146 EXPORT PININT1_IRQHandler [WEAK]
Recifarium 0:df922596d756 147 EXPORT PININT2_IRQHandler [WEAK]
Recifarium 0:df922596d756 148 EXPORT PININT3_IRQHandler [WEAK]
Recifarium 0:df922596d756 149 EXPORT PININT4_IRQHandler [WEAK]
Recifarium 0:df922596d756 150 EXPORT PININT5_IRQHandler [WEAK]
Recifarium 0:df922596d756 151 EXPORT PININT6_IRQHandler [WEAK]
Recifarium 0:df922596d756 152 EXPORT PININT7_IRQHandler [WEAK]
Recifarium 0:df922596d756 153
Recifarium 0:df922596d756 154 NMI_Handler
Recifarium 0:df922596d756 155 SPI0_IRQHandler
Recifarium 0:df922596d756 156 SPI1_IRQHandler
Recifarium 0:df922596d756 157 UART0_IRQHandler
Recifarium 0:df922596d756 158 UART1_IRQHandler
Recifarium 0:df922596d756 159 UART2_IRQHandler
Recifarium 0:df922596d756 160 I2C_IRQHandler
Recifarium 0:df922596d756 161 SCT_IRQHandler
Recifarium 0:df922596d756 162 MRT_IRQHandler
Recifarium 0:df922596d756 163 CMP_IRQHandler
Recifarium 0:df922596d756 164 WDT_IRQHandler
Recifarium 0:df922596d756 165 BOD_IRQHandler
Recifarium 0:df922596d756 166 WKT_IRQHandler
Recifarium 0:df922596d756 167 PININT0_IRQHandler
Recifarium 0:df922596d756 168 PININT1_IRQHandler
Recifarium 0:df922596d756 169 PININT2_IRQHandler
Recifarium 0:df922596d756 170 PININT3_IRQHandler
Recifarium 0:df922596d756 171 PININT4_IRQHandler
Recifarium 0:df922596d756 172 PININT5_IRQHandler
Recifarium 0:df922596d756 173 PININT6_IRQHandler
Recifarium 0:df922596d756 174 PININT7_IRQHandler
Recifarium 0:df922596d756 175
Recifarium 0:df922596d756 176 B .
Recifarium 0:df922596d756 177
Recifarium 0:df922596d756 178 ENDP
Recifarium 0:df922596d756 179 ALIGN
Recifarium 0:df922596d756 180 ; Configure USART 0/1/2 for receiving and transmitting data:
Recifarium 0:df922596d756 181 ; In the SYSAHBCLKCTRL register, set bit 14 to 16 (Table 18) to enable the clock to the register interface.
Recifarium 0:df922596d756 182
Recifarium 0:df922596d756 183 UartConfig
Recifarium 0:df922596d756 184 MOVS r2, #1
Recifarium 0:df922596d756 185 LSLS r2, #14 ; USART0 (bit 14)
Recifarium 0:df922596d756 186 LDR r1, =SYSAHBCLKCTRL
Recifarium 0:df922596d756 187 LDR r0, [r1]
Recifarium 0:df922596d756 188 ORRS r0, r0, r2
Recifarium 0:df922596d756 189 STR r0, [r1]
Recifarium 0:df922596d756 190 ;Configure the USART0 pin functions through the switch matrix. See Section 15.4.
Recifarium 0:df922596d756 191 Value EQU TX+256*(RX+(256*(255+256*255)))
Recifarium 0:df922596d756 192 LDR r0,=Value
Recifarium 0:df922596d756 193 LDR r1,=PINASSIGN0
Recifarium 0:df922596d756 194 STR r0,[r1]
Recifarium 0:df922596d756 195 ;Configure the UART clock div
Recifarium 0:df922596d756 196 MOVS r0,#3 ; UART clock 4MHz
Recifarium 0:df922596d756 197 LDR r1,=UARTCLKDIV
Recifarium 0:df922596d756 198 STR r0,[r1]
Recifarium 0:df922596d756 199 LDR r1,=(USART0)
Recifarium 0:df922596d756 200 ;Configure data
Recifarium 0:df922596d756 201 MOVS r0,#0x05 ; 8 bits, no Parity, 1 Stop bit */
Recifarium 0:df922596d756 202 STR r0, [r1,#CFG]
Recifarium 0:df922596d756 203 ;Configure BRG
Recifarium 0:df922596d756 204 MOVS r0,#207 ; = 4000000/19200 -1
Recifarium 0:df922596d756 205 STR r0,[r1,#BRG]
Recifarium 0:df922596d756 206 BX lr
Recifarium 0:df922596d756 207 LTORG
Recifarium 0:df922596d756 208 ;-----------------------------------
Recifarium 0:df922596d756 209 ; DONT Change the 3 lines below
Recifarium 0:df922596d756 210 ; and leave the xEmit label on
Recifarium 0:df922596d756 211 ; the same line as instruction
Recifarium 0:df922596d756 212 ;-----------------------------------
Recifarium 0:df922596d756 213 LTx LINK LExit
Recifarium 0:df922596d756 214 DCB 4
Recifarium 0:df922596d756 215 DCB "EMIT"
Recifarium 0:df922596d756 216
Recifarium 0:df922596d756 217 ;-----------------------------------
Recifarium 0:df922596d756 218 ; Place here your code for the Emit
Recifarium 0:df922596d756 219 ; routine
Recifarium 0:df922596d756 220 ; If it is a high level put a doCol
Recifarium 0:df922596d756 221 ; at the begenning and an Exit at the end
Recifarium 0:df922596d756 222 ;-----------------------------------
Recifarium 0:df922596d756 223 xEmit LDR r1,=(USART0)
Recifarium 0:df922596d756 224 Emit1 LDR r2,[r1,#STAT]
Recifarium 0:df922596d756 225 LSRS r2,#3
Recifarium 0:df922596d756 226 BCC Emit1 ; ? ready to Xmit
Recifarium 0:df922596d756 227 STR TOS,[r1,#TXDAT] ; Xmit
Recifarium 0:df922596d756 228 POP {TOS} ; Discard & Update TOS
Recifarium 0:df922596d756 229 RET
Recifarium 0:df922596d756 230
Recifarium 0:df922596d756 231 ;xEmit doCol
Recifarium 0:df922596d756 232 ; DCB Lit32 !ne marche pas
Recifarium 0:df922596d756 233 ; DCD USART0 ; (char, USART0) !
Recifarium 0:df922596d756 234 ;Emit1 DCB Dup ; (char,USART0, USART0) !ne marche pas
Recifarium 0:df922596d756 235 ; DCB Lit8, STAT, Plus, At ; (char, USART0, @Stat)
Recifarium 0:df922596d756 236 ; DCB Lit8, 4, And ; (char, USART0, flag) !ne marche pas
Recifarium 0:df922596d756 237 ; ZBranch Emit1 ; (char, USART0)
Recifarium 0:df922596d756 238 ; DCB Lit8, TX, Plus ; (char, USART0Tx) !ne marche pas
Recifarium 0:df922596d756 239 ; DCB Store
Recifarium 0:df922596d756 240 ; DCB Exit
Recifarium 0:df922596d756 241
Recifarium 0:df922596d756 242 ;-----------------------------------
Recifarium 0:df922596d756 243 ; DONT Change the 4 lines below
Recifarium 0:df922596d756 244 ; and leave the xRecv label on
Recifarium 0:df922596d756 245 ; the same line as instruction
Recifarium 0:df922596d756 246 ;-----------------------------------
Recifarium 0:df922596d756 247 LRecv LINK LTx
Recifarium 0:df922596d756 248 DCB 4
Recifarium 0:df922596d756 249 DCB "KEY?"
Recifarium 0:df922596d756 250
Recifarium 0:df922596d756 251 ;-----------------------------------
Recifarium 0:df922596d756 252 ; Place here your code for the Key?
Recifarium 0:df922596d756 253 ; routine
Recifarium 0:df922596d756 254 ; If it is a high level put a doCol
Recifarium 0:df922596d756 255 ; at the beginning and an Exit at the end
Recifarium 0:df922596d756 256 ;-----------------------------------
Recifarium 0:df922596d756 257 KeyQ PUSH {TOS}
Recifarium 0:df922596d756 258 LDR r1,=(USART0)
Recifarium 0:df922596d756 259 LDR r2,[r1,#STAT]
Recifarium 0:df922596d756 260 LSRS r2,#1
Recifarium 0:df922596d756 261 BCC Recv1
Recifarium 0:df922596d756 262 LDR TOS,=0xffffffff ; True flag
Recifarium 0:df922596d756 263 B Recv2
Recifarium 0:df922596d756 264 Recv1 SUBS TOS,TOS ; Clear TOS (false falg)
Recifarium 0:df922596d756 265 Recv2 RET
Recifarium 0:df922596d756 266
Recifarium 0:df922596d756 267 ;-----------------------------------
Recifarium 0:df922596d756 268 ; DONT Change the 4 lines below
Recifarium 0:df922596d756 269 ;-----------------------------------
Recifarium 0:df922596d756 270 LKey LINK LRecv
Recifarium 0:df922596d756 271 DCB 3
Recifarium 0:df922596d756 272 DCB "KEY"
Recifarium 0:df922596d756 273
Recifarium 0:df922596d756 274 ;-----------------------------------
Recifarium 0:df922596d756 275 ; Place here your code for the Key
Recifarium 0:df922596d756 276 ; routine
Recifarium 0:df922596d756 277 ; If it is a high level put a doCol
Recifarium 0:df922596d756 278 ; at the begenning and an Exit at the end
Recifarium 0:df922596d756 279 ;-----------------------------------
Recifarium 0:df922596d756 280 xKey PUSH {TOS}
Recifarium 0:df922596d756 281 LDR r1,=(USART0)
Recifarium 0:df922596d756 282 Key1 LDR r2,[r1,#STAT]
Recifarium 0:df922596d756 283 LSRS r2,#1
Recifarium 0:df922596d756 284 BCC Key1
Recifarium 0:df922596d756 285 LDR TOS,[r1,#RXDAT]
Recifarium 0:df922596d756 286 RET
Recifarium 0:df922596d756 287 END