Chau Vo / nnio_stm32f10x_rtc

RTC functions for STM32F103

nnio_stm32f10x_rtc.cpp@1:f0b4e50e55a6, 2016-09-25 (annotated)

Committer:
olympux
Date:
Sun Sep 25 20:17:30 2016 +0000
Revision:
1:f0b4e50e55a6
Parent:
0:22eb12b5dd2f 
Added comment to LSE or LSI clock source

Who changed what in which revision?

UserRevisionLine numberNew contents of line
olympux 0:22eb12b5dd2f 1 #include "nnio_stm32f10x_rtc.h"
olympux 0:22eb12b5dd2f 2
olympux 1:f0b4e50e55a6 3 // Enable this to use external clock, or disable to use internal clock
olympux 0:22eb12b5dd2f 4 #define ENABLE_LSE_CLOCK
olympux 0:22eb12b5dd2f 5
olympux 0:22eb12b5dd2f 6 void RTC_Init(void)
olympux 0:22eb12b5dd2f 7 {
olympux 0:22eb12b5dd2f 8 NVIC_InitTypeDef NVIC_InitStructure;
olympux 0:22eb12b5dd2f 9
olympux 0:22eb12b5dd2f 10 NVIC_InitStructure.NVIC_IRQChannel = RTC_IRQn;
olympux 0:22eb12b5dd2f 11 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
olympux 0:22eb12b5dd2f 12 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
olympux 0:22eb12b5dd2f 13 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
olympux 0:22eb12b5dd2f 14 NVIC_Init(&NVIC_InitStructure);
olympux 0:22eb12b5dd2f 15 }
olympux 0:22eb12b5dd2f 16
olympux 0:22eb12b5dd2f 17 /*******************************************************************************
olympux 0:22eb12b5dd2f 18 * Function Name : RTC_Configuration
olympux 0:22eb12b5dd2f 19 * Description : Configures the RTC.
olympux 0:22eb12b5dd2f 20 * Input : None
olympux 0:22eb12b5dd2f 21 * Output : None
olympux 0:22eb12b5dd2f 22 * Return : None
olympux 0:22eb12b5dd2f 23 *******************************************************************************/
olympux 0:22eb12b5dd2f 24 void RTC_Configuration(void)
olympux 0:22eb12b5dd2f 25 {
olympux 0:22eb12b5dd2f 26 /* Enable PWR and BKP clocks */
olympux 0:22eb12b5dd2f 27 RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
olympux 0:22eb12b5dd2f 28
olympux 0:22eb12b5dd2f 29 /* Allow access to BKP Domain */
olympux 0:22eb12b5dd2f 30 PWR_BackupAccessCmd(ENABLE);
olympux 0:22eb12b5dd2f 31
olympux 0:22eb12b5dd2f 32 /* Reset Backup Domain, only the first time */
olympux 0:22eb12b5dd2f 33 if (BKP_ReadBackupRegister(BKP_DR1) != 0xA5A5)
olympux 0:22eb12b5dd2f 34 BKP_DeInit();
olympux 0:22eb12b5dd2f 35
olympux 0:22eb12b5dd2f 36 #if defined(ENABLE_LSE_CLOCK)
olympux 0:22eb12b5dd2f 37 /* Enable LSE */
olympux 0:22eb12b5dd2f 38 RCC_LSEConfig(RCC_LSE_ON);
olympux 0:22eb12b5dd2f 39
olympux 0:22eb12b5dd2f 40 /* Wait till LSE is ready */
olympux 0:22eb12b5dd2f 41 while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
olympux 0:22eb12b5dd2f 42 {}
olympux 0:22eb12b5dd2f 43
olympux 0:22eb12b5dd2f 44 /* Select LSE as RTC Clock Source */
olympux 0:22eb12b5dd2f 45 RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
olympux 0:22eb12b5dd2f 46 #else
olympux 0:22eb12b5dd2f 47 /* Enable LSI */
olympux 0:22eb12b5dd2f 48 RCC_LSICmd(ENABLE);
olympux 0:22eb12b5dd2f 49
olympux 0:22eb12b5dd2f 50 /* Wait till LSI is ready */
olympux 0:22eb12b5dd2f 51 while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET)
olympux 0:22eb12b5dd2f 52 {}
olympux 0:22eb12b5dd2f 53
olympux 0:22eb12b5dd2f 54 /* Select LSI as RTC Clock Source */
olympux 0:22eb12b5dd2f 55 RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI);
olympux 0:22eb12b5dd2f 56 #endif
olympux 0:22eb12b5dd2f 57
olympux 0:22eb12b5dd2f 58 /* Enable RTC Clock */
olympux 0:22eb12b5dd2f 59 RCC_RTCCLKCmd(ENABLE);
olympux 0:22eb12b5dd2f 60
olympux 0:22eb12b5dd2f 61 /* Wait for RTC registers synchronization */
olympux 0:22eb12b5dd2f 62 RTC_WaitForSynchro();
olympux 0:22eb12b5dd2f 63
olympux 0:22eb12b5dd2f 64 /* Wait until last write operation on RTC registers has finished */
olympux 0:22eb12b5dd2f 65 RTC_WaitForLastTask();
olympux 0:22eb12b5dd2f 66
olympux 0:22eb12b5dd2f 67 /* Enable the RTC Second */
olympux 0:22eb12b5dd2f 68 RTC_ITConfig(RTC_IT_SEC, ENABLE);
olympux 0:22eb12b5dd2f 69
olympux 0:22eb12b5dd2f 70 /* Wait until last write operation on RTC registers has finished */
olympux 0:22eb12b5dd2f 71 RTC_WaitForLastTask();
olympux 0:22eb12b5dd2f 72
olympux 0:22eb12b5dd2f 73 /* Set RTC prescaler: set RTC period to 1sec */
olympux 0:22eb12b5dd2f 74 RTC_SetPrescaler(32767); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */
olympux 0:22eb12b5dd2f 75
olympux 0:22eb12b5dd2f 76 /* Wait until last write operation on RTC registers has finished */
olympux 0:22eb12b5dd2f 77 RTC_WaitForLastTask();
olympux 0:22eb12b5dd2f 78 }