Chau Vo / nnio_stm32f10x_rtc

RTC functions for STM32F103

nnio_stm32f10x_rtc.cpp@0:22eb12b5dd2f, 2016-09-16 (annotated)

Committer:
olympux
Date:
Fri Sep 16 19:34:41 2016 +0000
Revision:
0:22eb12b5dd2f
Child:
1:f0b4e50e55a6
Add enable LSE clock

Who changed what in which revision?

UserRevisionLine numberNew contents of line
olympux 0:22eb12b5dd2f 1 #include "nnio_stm32f10x_rtc.h"
olympux 0:22eb12b5dd2f 2
olympux 0:22eb12b5dd2f 3 #define ENABLE_LSE_CLOCK
olympux 0:22eb12b5dd2f 4
olympux 0:22eb12b5dd2f 5 void RTC_Init(void)
olympux 0:22eb12b5dd2f 6 {
olympux 0:22eb12b5dd2f 7 NVIC_InitTypeDef NVIC_InitStructure;
olympux 0:22eb12b5dd2f 8
olympux 0:22eb12b5dd2f 9 NVIC_InitStructure.NVIC_IRQChannel = RTC_IRQn;
olympux 0:22eb12b5dd2f 10 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
olympux 0:22eb12b5dd2f 11 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
olympux 0:22eb12b5dd2f 12 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
olympux 0:22eb12b5dd2f 13 NVIC_Init(&NVIC_InitStructure);
olympux 0:22eb12b5dd2f 14 }
olympux 0:22eb12b5dd2f 15
olympux 0:22eb12b5dd2f 16 /*******************************************************************************
olympux 0:22eb12b5dd2f 17 * Function Name : RTC_Configuration
olympux 0:22eb12b5dd2f 18 * Description : Configures the RTC.
olympux 0:22eb12b5dd2f 19 * Input : None
olympux 0:22eb12b5dd2f 20 * Output : None
olympux 0:22eb12b5dd2f 21 * Return : None
olympux 0:22eb12b5dd2f 22 *******************************************************************************/
olympux 0:22eb12b5dd2f 23 void RTC_Configuration(void)
olympux 0:22eb12b5dd2f 24 {
olympux 0:22eb12b5dd2f 25 /* Enable PWR and BKP clocks */
olympux 0:22eb12b5dd2f 26 RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
olympux 0:22eb12b5dd2f 27
olympux 0:22eb12b5dd2f 28 /* Allow access to BKP Domain */
olympux 0:22eb12b5dd2f 29 PWR_BackupAccessCmd(ENABLE);
olympux 0:22eb12b5dd2f 30
olympux 0:22eb12b5dd2f 31 /* Reset Backup Domain, only the first time */
olympux 0:22eb12b5dd2f 32 if (BKP_ReadBackupRegister(BKP_DR1) != 0xA5A5)
olympux 0:22eb12b5dd2f 33 BKP_DeInit();
olympux 0:22eb12b5dd2f 34
olympux 0:22eb12b5dd2f 35 #if defined(ENABLE_LSE_CLOCK)
olympux 0:22eb12b5dd2f 36 /* Enable LSE */
olympux 0:22eb12b5dd2f 37 RCC_LSEConfig(RCC_LSE_ON);
olympux 0:22eb12b5dd2f 38
olympux 0:22eb12b5dd2f 39 /* Wait till LSE is ready */
olympux 0:22eb12b5dd2f 40 while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
olympux 0:22eb12b5dd2f 41 {}
olympux 0:22eb12b5dd2f 42
olympux 0:22eb12b5dd2f 43 /* Select LSE as RTC Clock Source */
olympux 0:22eb12b5dd2f 44 RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
olympux 0:22eb12b5dd2f 45 #else
olympux 0:22eb12b5dd2f 46 /* Enable LSI */
olympux 0:22eb12b5dd2f 47 RCC_LSICmd(ENABLE);
olympux 0:22eb12b5dd2f 48
olympux 0:22eb12b5dd2f 49 /* Wait till LSI is ready */
olympux 0:22eb12b5dd2f 50 while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET)
olympux 0:22eb12b5dd2f 51 {}
olympux 0:22eb12b5dd2f 52
olympux 0:22eb12b5dd2f 53 /* Select LSI as RTC Clock Source */
olympux 0:22eb12b5dd2f 54 RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI);
olympux 0:22eb12b5dd2f 55 #endif
olympux 0:22eb12b5dd2f 56
olympux 0:22eb12b5dd2f 57 /* Enable RTC Clock */
olympux 0:22eb12b5dd2f 58 RCC_RTCCLKCmd(ENABLE);
olympux 0:22eb12b5dd2f 59
olympux 0:22eb12b5dd2f 60 /* Wait for RTC registers synchronization */
olympux 0:22eb12b5dd2f 61 RTC_WaitForSynchro();
olympux 0:22eb12b5dd2f 62
olympux 0:22eb12b5dd2f 63 /* Wait until last write operation on RTC registers has finished */
olympux 0:22eb12b5dd2f 64 RTC_WaitForLastTask();
olympux 0:22eb12b5dd2f 65
olympux 0:22eb12b5dd2f 66 /* Enable the RTC Second */
olympux 0:22eb12b5dd2f 67 RTC_ITConfig(RTC_IT_SEC, ENABLE);
olympux 0:22eb12b5dd2f 68
olympux 0:22eb12b5dd2f 69 /* Wait until last write operation on RTC registers has finished */
olympux 0:22eb12b5dd2f 70 RTC_WaitForLastTask();
olympux 0:22eb12b5dd2f 71
olympux 0:22eb12b5dd2f 72 /* Set RTC prescaler: set RTC period to 1sec */
olympux 0:22eb12b5dd2f 73 RTC_SetPrescaler(32767); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */
olympux 0:22eb12b5dd2f 74
olympux 0:22eb12b5dd2f 75 /* Wait until last write operation on RTC registers has finished */
olympux 0:22eb12b5dd2f 76 RTC_WaitForLastTask();
olympux 0:22eb12b5dd2f 77 }