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targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h@15:a81a8d6c1dfe, 2015-11-04 (annotated)

Committer:
mbed_official
Date:
Wed Nov 04 16:30:11 2015 +0000
Revision:
15:a81a8d6c1dfe
Synchronized with git revision 46af745ef4405614c3fa49abbd9a706a362ea514



Full URL: https://github.com/mbedmicro/mbed/commit/46af745ef4405614c3fa49abbd9a706a362ea514/



Renamed TARGET_SAM_CortexM0+ to TARGET_SAM_CortexM0P for compatiblity with online compiler

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 15:a81a8d6c1dfe 1 /**
mbed_official 15:a81a8d6c1dfe 2 * \file
mbed_official 15:a81a8d6c1dfe 3 *
mbed_official 15:a81a8d6c1dfe 4 * \brief Component description for SERCOM
mbed_official 15:a81a8d6c1dfe 5 *
mbed_official 15:a81a8d6c1dfe 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
mbed_official 15:a81a8d6c1dfe 7 *
mbed_official 15:a81a8d6c1dfe 8 * \asf_license_start
mbed_official 15:a81a8d6c1dfe 9 *
mbed_official 15:a81a8d6c1dfe 10 * \page License
mbed_official 15:a81a8d6c1dfe 11 *
mbed_official 15:a81a8d6c1dfe 12 * Redistribution and use in source and binary forms, with or without
mbed_official 15:a81a8d6c1dfe 13 * modification, are permitted provided that the following conditions are met:
mbed_official 15:a81a8d6c1dfe 14 *
mbed_official 15:a81a8d6c1dfe 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 15:a81a8d6c1dfe 16 * this list of conditions and the following disclaimer.
mbed_official 15:a81a8d6c1dfe 17 *
mbed_official 15:a81a8d6c1dfe 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 15:a81a8d6c1dfe 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 15:a81a8d6c1dfe 20 * and/or other materials provided with the distribution.
mbed_official 15:a81a8d6c1dfe 21 *
mbed_official 15:a81a8d6c1dfe 22 * 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official 15:a81a8d6c1dfe 23 * from this software without specific prior written permission.
mbed_official 15:a81a8d6c1dfe 24 *
mbed_official 15:a81a8d6c1dfe 25 * 4. This software may only be redistributed and used in connection with an
mbed_official 15:a81a8d6c1dfe 26 * Atmel microcontroller product.
mbed_official 15:a81a8d6c1dfe 27 *
mbed_official 15:a81a8d6c1dfe 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 15:a81a8d6c1dfe 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 15:a81a8d6c1dfe 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official 15:a81a8d6c1dfe 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official 15:a81a8d6c1dfe 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 15:a81a8d6c1dfe 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official 15:a81a8d6c1dfe 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official 15:a81a8d6c1dfe 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official 15:a81a8d6c1dfe 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 15:a81a8d6c1dfe 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 15:a81a8d6c1dfe 38 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 15:a81a8d6c1dfe 39 *
mbed_official 15:a81a8d6c1dfe 40 * \asf_license_stop
mbed_official 15:a81a8d6c1dfe 41 *
mbed_official 15:a81a8d6c1dfe 42 */
mbed_official 15:a81a8d6c1dfe 43 /*
mbed_official 15:a81a8d6c1dfe 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
mbed_official 15:a81a8d6c1dfe 45 */
mbed_official 15:a81a8d6c1dfe 46
mbed_official 15:a81a8d6c1dfe 47 #ifndef _SAMD21_SERCOM_COMPONENT_
mbed_official 15:a81a8d6c1dfe 48 #define _SAMD21_SERCOM_COMPONENT_
mbed_official 15:a81a8d6c1dfe 49
mbed_official 15:a81a8d6c1dfe 50 /* ========================================================================== */
mbed_official 15:a81a8d6c1dfe 51 /** SOFTWARE API DEFINITION FOR SERCOM */
mbed_official 15:a81a8d6c1dfe 52 /* ========================================================================== */
mbed_official 15:a81a8d6c1dfe 53 /** \addtogroup SAMD21_SERCOM Serial Communication Interface */
mbed_official 15:a81a8d6c1dfe 54 /*@{*/
mbed_official 15:a81a8d6c1dfe 55
mbed_official 15:a81a8d6c1dfe 56 #define SERCOM_U2201
mbed_official 15:a81a8d6c1dfe 57 #define REV_SERCOM 0x201
mbed_official 15:a81a8d6c1dfe 58
mbed_official 15:a81a8d6c1dfe 59 /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
mbed_official 15:a81a8d6c1dfe 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 61 typedef union {
mbed_official 15:a81a8d6c1dfe 62 struct {
mbed_official 15:a81a8d6c1dfe 63 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
mbed_official 15:a81a8d6c1dfe 64 uint32_t ENABLE:1; /*!< bit: 1 Enable */
mbed_official 15:a81a8d6c1dfe 65 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
mbed_official 15:a81a8d6c1dfe 66 uint32_t :2; /*!< bit: 5.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 67 uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
mbed_official 15:a81a8d6c1dfe 68 uint32_t :8; /*!< bit: 8..15 Reserved */
mbed_official 15:a81a8d6c1dfe 69 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
mbed_official 15:a81a8d6c1dfe 70 uint32_t :3; /*!< bit: 17..19 Reserved */
mbed_official 15:a81a8d6c1dfe 71 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
mbed_official 15:a81a8d6c1dfe 72 uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
mbed_official 15:a81a8d6c1dfe 73 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
mbed_official 15:a81a8d6c1dfe 74 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
mbed_official 15:a81a8d6c1dfe 75 uint32_t :1; /*!< bit: 26 Reserved */
mbed_official 15:a81a8d6c1dfe 76 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
mbed_official 15:a81a8d6c1dfe 77 uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
mbed_official 15:a81a8d6c1dfe 78 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
mbed_official 15:a81a8d6c1dfe 79 uint32_t :1; /*!< bit: 31 Reserved */
mbed_official 15:a81a8d6c1dfe 80 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 81 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 82 } SERCOM_I2CM_CTRLA_Type;
mbed_official 15:a81a8d6c1dfe 83 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 84
mbed_official 15:a81a8d6c1dfe 85 #define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
mbed_official 15:a81a8d6c1dfe 86 #define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
mbed_official 15:a81a8d6c1dfe 87
mbed_official 15:a81a8d6c1dfe 88 #define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
mbed_official 15:a81a8d6c1dfe 89 #define SERCOM_I2CM_CTRLA_SWRST (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 90 #define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */
mbed_official 15:a81a8d6c1dfe 91 #define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 92 #define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
mbed_official 15:a81a8d6c1dfe 93 #define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 94 #define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)))
mbed_official 15:a81a8d6c1dfe 95 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
mbed_official 15:a81a8d6c1dfe 96 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
mbed_official 15:a81a8d6c1dfe 97 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
mbed_official 15:a81a8d6c1dfe 98 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */
mbed_official 15:a81a8d6c1dfe 99 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */
mbed_official 15:a81a8d6c1dfe 100 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */
mbed_official 15:a81a8d6c1dfe 101 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 102 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 103 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 104 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 105 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 106 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 107 #define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
mbed_official 15:a81a8d6c1dfe 108 #define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
mbed_official 15:a81a8d6c1dfe 109 #define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
mbed_official 15:a81a8d6c1dfe 110 #define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos)
mbed_official 15:a81a8d6c1dfe 111 #define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
mbed_official 15:a81a8d6c1dfe 112 #define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
mbed_official 15:a81a8d6c1dfe 113 #define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)))
mbed_official 15:a81a8d6c1dfe 114 #define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
mbed_official 15:a81a8d6c1dfe 115 #define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
mbed_official 15:a81a8d6c1dfe 116 #define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
mbed_official 15:a81a8d6c1dfe 117 #define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
mbed_official 15:a81a8d6c1dfe 118 #define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
mbed_official 15:a81a8d6c1dfe 119 #define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos)
mbed_official 15:a81a8d6c1dfe 120 #define SERCOM_I2CM_CTRLA_SPEED(value) ((SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos)))
mbed_official 15:a81a8d6c1dfe 121 #define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
mbed_official 15:a81a8d6c1dfe 122 #define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos)
mbed_official 15:a81a8d6c1dfe 123 #define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
mbed_official 15:a81a8d6c1dfe 124 #define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
mbed_official 15:a81a8d6c1dfe 125 #define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)))
mbed_official 15:a81a8d6c1dfe 126 #define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
mbed_official 15:a81a8d6c1dfe 127 #define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
mbed_official 15:a81a8d6c1dfe 128 #define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
mbed_official 15:a81a8d6c1dfe 129
mbed_official 15:a81a8d6c1dfe 130 /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
mbed_official 15:a81a8d6c1dfe 131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 132 typedef union {
mbed_official 15:a81a8d6c1dfe 133 struct {
mbed_official 15:a81a8d6c1dfe 134 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
mbed_official 15:a81a8d6c1dfe 135 uint32_t ENABLE:1; /*!< bit: 1 Enable */
mbed_official 15:a81a8d6c1dfe 136 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
mbed_official 15:a81a8d6c1dfe 137 uint32_t :2; /*!< bit: 5.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 138 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
mbed_official 15:a81a8d6c1dfe 139 uint32_t :8; /*!< bit: 8..15 Reserved */
mbed_official 15:a81a8d6c1dfe 140 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
mbed_official 15:a81a8d6c1dfe 141 uint32_t :3; /*!< bit: 17..19 Reserved */
mbed_official 15:a81a8d6c1dfe 142 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
mbed_official 15:a81a8d6c1dfe 143 uint32_t :1; /*!< bit: 22 Reserved */
mbed_official 15:a81a8d6c1dfe 144 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
mbed_official 15:a81a8d6c1dfe 145 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
mbed_official 15:a81a8d6c1dfe 146 uint32_t :1; /*!< bit: 26 Reserved */
mbed_official 15:a81a8d6c1dfe 147 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
mbed_official 15:a81a8d6c1dfe 148 uint32_t :2; /*!< bit: 28..29 Reserved */
mbed_official 15:a81a8d6c1dfe 149 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
mbed_official 15:a81a8d6c1dfe 150 uint32_t :1; /*!< bit: 31 Reserved */
mbed_official 15:a81a8d6c1dfe 151 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 152 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 153 } SERCOM_I2CS_CTRLA_Type;
mbed_official 15:a81a8d6c1dfe 154 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 155
mbed_official 15:a81a8d6c1dfe 156 #define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
mbed_official 15:a81a8d6c1dfe 157 #define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
mbed_official 15:a81a8d6c1dfe 158
mbed_official 15:a81a8d6c1dfe 159 #define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
mbed_official 15:a81a8d6c1dfe 160 #define SERCOM_I2CS_CTRLA_SWRST (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 161 #define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */
mbed_official 15:a81a8d6c1dfe 162 #define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 163 #define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
mbed_official 15:a81a8d6c1dfe 164 #define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 165 #define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)))
mbed_official 15:a81a8d6c1dfe 166 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
mbed_official 15:a81a8d6c1dfe 167 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
mbed_official 15:a81a8d6c1dfe 168 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
mbed_official 15:a81a8d6c1dfe 169 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */
mbed_official 15:a81a8d6c1dfe 170 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */
mbed_official 15:a81a8d6c1dfe 171 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */
mbed_official 15:a81a8d6c1dfe 172 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 173 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 174 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 175 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 176 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 177 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 178 #define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
mbed_official 15:a81a8d6c1dfe 179 #define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
mbed_official 15:a81a8d6c1dfe 180 #define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
mbed_official 15:a81a8d6c1dfe 181 #define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos)
mbed_official 15:a81a8d6c1dfe 182 #define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
mbed_official 15:a81a8d6c1dfe 183 #define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
mbed_official 15:a81a8d6c1dfe 184 #define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)))
mbed_official 15:a81a8d6c1dfe 185 #define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
mbed_official 15:a81a8d6c1dfe 186 #define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
mbed_official 15:a81a8d6c1dfe 187 #define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
mbed_official 15:a81a8d6c1dfe 188 #define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos)
mbed_official 15:a81a8d6c1dfe 189 #define SERCOM_I2CS_CTRLA_SPEED(value) ((SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos)))
mbed_official 15:a81a8d6c1dfe 190 #define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
mbed_official 15:a81a8d6c1dfe 191 #define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos)
mbed_official 15:a81a8d6c1dfe 192 #define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
mbed_official 15:a81a8d6c1dfe 193 #define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
mbed_official 15:a81a8d6c1dfe 194 #define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
mbed_official 15:a81a8d6c1dfe 195
mbed_official 15:a81a8d6c1dfe 196 /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
mbed_official 15:a81a8d6c1dfe 197 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 198 typedef union {
mbed_official 15:a81a8d6c1dfe 199 struct {
mbed_official 15:a81a8d6c1dfe 200 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
mbed_official 15:a81a8d6c1dfe 201 uint32_t ENABLE:1; /*!< bit: 1 Enable */
mbed_official 15:a81a8d6c1dfe 202 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
mbed_official 15:a81a8d6c1dfe 203 uint32_t :2; /*!< bit: 5.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 204 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
mbed_official 15:a81a8d6c1dfe 205 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
mbed_official 15:a81a8d6c1dfe 206 uint32_t :7; /*!< bit: 9..15 Reserved */
mbed_official 15:a81a8d6c1dfe 207 uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
mbed_official 15:a81a8d6c1dfe 208 uint32_t :2; /*!< bit: 18..19 Reserved */
mbed_official 15:a81a8d6c1dfe 209 uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
mbed_official 15:a81a8d6c1dfe 210 uint32_t :2; /*!< bit: 22..23 Reserved */
mbed_official 15:a81a8d6c1dfe 211 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
mbed_official 15:a81a8d6c1dfe 212 uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
mbed_official 15:a81a8d6c1dfe 213 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
mbed_official 15:a81a8d6c1dfe 214 uint32_t DORD:1; /*!< bit: 30 Data Order */
mbed_official 15:a81a8d6c1dfe 215 uint32_t :1; /*!< bit: 31 Reserved */
mbed_official 15:a81a8d6c1dfe 216 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 217 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 218 } SERCOM_SPI_CTRLA_Type;
mbed_official 15:a81a8d6c1dfe 219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 220
mbed_official 15:a81a8d6c1dfe 221 #define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
mbed_official 15:a81a8d6c1dfe 222 #define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
mbed_official 15:a81a8d6c1dfe 223
mbed_official 15:a81a8d6c1dfe 224 #define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
mbed_official 15:a81a8d6c1dfe 225 #define SERCOM_SPI_CTRLA_SWRST (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 226 #define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */
mbed_official 15:a81a8d6c1dfe 227 #define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 228 #define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
mbed_official 15:a81a8d6c1dfe 229 #define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 230 #define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)))
mbed_official 15:a81a8d6c1dfe 231 #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
mbed_official 15:a81a8d6c1dfe 232 #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
mbed_official 15:a81a8d6c1dfe 233 #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
mbed_official 15:a81a8d6c1dfe 234 #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */
mbed_official 15:a81a8d6c1dfe 235 #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */
mbed_official 15:a81a8d6c1dfe 236 #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */
mbed_official 15:a81a8d6c1dfe 237 #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 238 #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 239 #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 240 #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 241 #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 242 #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 243 #define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
mbed_official 15:a81a8d6c1dfe 244 #define SERCOM_SPI_CTRLA_RUNSTDBY (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
mbed_official 15:a81a8d6c1dfe 245 #define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
mbed_official 15:a81a8d6c1dfe 246 #define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos)
mbed_official 15:a81a8d6c1dfe 247 #define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
mbed_official 15:a81a8d6c1dfe 248 #define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos)
mbed_official 15:a81a8d6c1dfe 249 #define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)))
mbed_official 15:a81a8d6c1dfe 250 #define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
mbed_official 15:a81a8d6c1dfe 251 #define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos)
mbed_official 15:a81a8d6c1dfe 252 #define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)))
mbed_official 15:a81a8d6c1dfe 253 #define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
mbed_official 15:a81a8d6c1dfe 254 #define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos)
mbed_official 15:a81a8d6c1dfe 255 #define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)))
mbed_official 15:a81a8d6c1dfe 256 #define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
mbed_official 15:a81a8d6c1dfe 257 #define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos)
mbed_official 15:a81a8d6c1dfe 258 #define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
mbed_official 15:a81a8d6c1dfe 259 #define SERCOM_SPI_CTRLA_CPOL (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos)
mbed_official 15:a81a8d6c1dfe 260 #define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */
mbed_official 15:a81a8d6c1dfe 261 #define SERCOM_SPI_CTRLA_DORD (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos)
mbed_official 15:a81a8d6c1dfe 262 #define SERCOM_SPI_CTRLA_MASK 0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
mbed_official 15:a81a8d6c1dfe 263
mbed_official 15:a81a8d6c1dfe 264 /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
mbed_official 15:a81a8d6c1dfe 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 266 typedef union {
mbed_official 15:a81a8d6c1dfe 267 struct {
mbed_official 15:a81a8d6c1dfe 268 uint32_t SWRST:1; /*!< bit: 0 Software Reset */
mbed_official 15:a81a8d6c1dfe 269 uint32_t ENABLE:1; /*!< bit: 1 Enable */
mbed_official 15:a81a8d6c1dfe 270 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
mbed_official 15:a81a8d6c1dfe 271 uint32_t :2; /*!< bit: 5.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 272 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
mbed_official 15:a81a8d6c1dfe 273 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
mbed_official 15:a81a8d6c1dfe 274 uint32_t :4; /*!< bit: 9..12 Reserved */
mbed_official 15:a81a8d6c1dfe 275 uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
mbed_official 15:a81a8d6c1dfe 276 uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
mbed_official 15:a81a8d6c1dfe 277 uint32_t :2; /*!< bit: 18..19 Reserved */
mbed_official 15:a81a8d6c1dfe 278 uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
mbed_official 15:a81a8d6c1dfe 279 uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
mbed_official 15:a81a8d6c1dfe 280 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
mbed_official 15:a81a8d6c1dfe 281 uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
mbed_official 15:a81a8d6c1dfe 282 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
mbed_official 15:a81a8d6c1dfe 283 uint32_t DORD:1; /*!< bit: 30 Data Order */
mbed_official 15:a81a8d6c1dfe 284 uint32_t :1; /*!< bit: 31 Reserved */
mbed_official 15:a81a8d6c1dfe 285 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 286 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 287 } SERCOM_USART_CTRLA_Type;
mbed_official 15:a81a8d6c1dfe 288 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 289
mbed_official 15:a81a8d6c1dfe 290 #define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
mbed_official 15:a81a8d6c1dfe 291 #define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
mbed_official 15:a81a8d6c1dfe 292
mbed_official 15:a81a8d6c1dfe 293 #define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */
mbed_official 15:a81a8d6c1dfe 294 #define SERCOM_USART_CTRLA_SWRST (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 295 #define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */
mbed_official 15:a81a8d6c1dfe 296 #define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 297 #define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
mbed_official 15:a81a8d6c1dfe 298 #define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 299 #define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)))
mbed_official 15:a81a8d6c1dfe 300 #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
mbed_official 15:a81a8d6c1dfe 301 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
mbed_official 15:a81a8d6c1dfe 302 #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
mbed_official 15:a81a8d6c1dfe 303 #define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */
mbed_official 15:a81a8d6c1dfe 304 #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */
mbed_official 15:a81a8d6c1dfe 305 #define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */
mbed_official 15:a81a8d6c1dfe 306 #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 307 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 308 #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 309 #define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 310 #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 311 #define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 312 #define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
mbed_official 15:a81a8d6c1dfe 313 #define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
mbed_official 15:a81a8d6c1dfe 314 #define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
mbed_official 15:a81a8d6c1dfe 315 #define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos)
mbed_official 15:a81a8d6c1dfe 316 #define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
mbed_official 15:a81a8d6c1dfe 317 #define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos)
mbed_official 15:a81a8d6c1dfe 318 #define SERCOM_USART_CTRLA_SAMPR(value) ((SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos)))
mbed_official 15:a81a8d6c1dfe 319 #define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
mbed_official 15:a81a8d6c1dfe 320 #define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos)
mbed_official 15:a81a8d6c1dfe 321 #define SERCOM_USART_CTRLA_TXPO(value) ((SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)))
mbed_official 15:a81a8d6c1dfe 322 #define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
mbed_official 15:a81a8d6c1dfe 323 #define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos)
mbed_official 15:a81a8d6c1dfe 324 #define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)))
mbed_official 15:a81a8d6c1dfe 325 #define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
mbed_official 15:a81a8d6c1dfe 326 #define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos)
mbed_official 15:a81a8d6c1dfe 327 #define SERCOM_USART_CTRLA_SAMPA(value) ((SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos)))
mbed_official 15:a81a8d6c1dfe 328 #define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
mbed_official 15:a81a8d6c1dfe 329 #define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos)
mbed_official 15:a81a8d6c1dfe 330 #define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)))
mbed_official 15:a81a8d6c1dfe 331 #define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
mbed_official 15:a81a8d6c1dfe 332 #define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos)
mbed_official 15:a81a8d6c1dfe 333 #define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
mbed_official 15:a81a8d6c1dfe 334 #define SERCOM_USART_CTRLA_CPOL (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos)
mbed_official 15:a81a8d6c1dfe 335 #define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */
mbed_official 15:a81a8d6c1dfe 336 #define SERCOM_USART_CTRLA_DORD (0x1ul << SERCOM_USART_CTRLA_DORD_Pos)
mbed_official 15:a81a8d6c1dfe 337 #define SERCOM_USART_CTRLA_MASK 0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */
mbed_official 15:a81a8d6c1dfe 338
mbed_official 15:a81a8d6c1dfe 339 /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
mbed_official 15:a81a8d6c1dfe 340 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 341 typedef union {
mbed_official 15:a81a8d6c1dfe 342 struct {
mbed_official 15:a81a8d6c1dfe 343 uint32_t :8; /*!< bit: 0.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 344 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
mbed_official 15:a81a8d6c1dfe 345 uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
mbed_official 15:a81a8d6c1dfe 346 uint32_t :6; /*!< bit: 10..15 Reserved */
mbed_official 15:a81a8d6c1dfe 347 uint32_t CMD:2; /*!< bit: 16..17 Command */
mbed_official 15:a81a8d6c1dfe 348 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
mbed_official 15:a81a8d6c1dfe 349 uint32_t :13; /*!< bit: 19..31 Reserved */
mbed_official 15:a81a8d6c1dfe 350 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 351 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 352 } SERCOM_I2CM_CTRLB_Type;
mbed_official 15:a81a8d6c1dfe 353 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 354
mbed_official 15:a81a8d6c1dfe 355 #define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
mbed_official 15:a81a8d6c1dfe 356 #define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
mbed_official 15:a81a8d6c1dfe 357
mbed_official 15:a81a8d6c1dfe 358 #define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
mbed_official 15:a81a8d6c1dfe 359 #define SERCOM_I2CM_CTRLB_SMEN (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos)
mbed_official 15:a81a8d6c1dfe 360 #define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
mbed_official 15:a81a8d6c1dfe 361 #define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos)
mbed_official 15:a81a8d6c1dfe 362 #define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
mbed_official 15:a81a8d6c1dfe 363 #define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos)
mbed_official 15:a81a8d6c1dfe 364 #define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)))
mbed_official 15:a81a8d6c1dfe 365 #define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
mbed_official 15:a81a8d6c1dfe 366 #define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos)
mbed_official 15:a81a8d6c1dfe 367 #define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
mbed_official 15:a81a8d6c1dfe 368
mbed_official 15:a81a8d6c1dfe 369 /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
mbed_official 15:a81a8d6c1dfe 370 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 371 typedef union {
mbed_official 15:a81a8d6c1dfe 372 struct {
mbed_official 15:a81a8d6c1dfe 373 uint32_t :8; /*!< bit: 0.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 374 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
mbed_official 15:a81a8d6c1dfe 375 uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
mbed_official 15:a81a8d6c1dfe 376 uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
mbed_official 15:a81a8d6c1dfe 377 uint32_t :3; /*!< bit: 11..13 Reserved */
mbed_official 15:a81a8d6c1dfe 378 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
mbed_official 15:a81a8d6c1dfe 379 uint32_t CMD:2; /*!< bit: 16..17 Command */
mbed_official 15:a81a8d6c1dfe 380 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
mbed_official 15:a81a8d6c1dfe 381 uint32_t :13; /*!< bit: 19..31 Reserved */
mbed_official 15:a81a8d6c1dfe 382 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 383 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 384 } SERCOM_I2CS_CTRLB_Type;
mbed_official 15:a81a8d6c1dfe 385 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 386
mbed_official 15:a81a8d6c1dfe 387 #define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
mbed_official 15:a81a8d6c1dfe 388 #define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
mbed_official 15:a81a8d6c1dfe 389
mbed_official 15:a81a8d6c1dfe 390 #define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
mbed_official 15:a81a8d6c1dfe 391 #define SERCOM_I2CS_CTRLB_SMEN (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos)
mbed_official 15:a81a8d6c1dfe 392 #define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
mbed_official 15:a81a8d6c1dfe 393 #define SERCOM_I2CS_CTRLB_GCMD (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos)
mbed_official 15:a81a8d6c1dfe 394 #define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
mbed_official 15:a81a8d6c1dfe 395 #define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos)
mbed_official 15:a81a8d6c1dfe 396 #define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
mbed_official 15:a81a8d6c1dfe 397 #define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos)
mbed_official 15:a81a8d6c1dfe 398 #define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)))
mbed_official 15:a81a8d6c1dfe 399 #define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
mbed_official 15:a81a8d6c1dfe 400 #define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos)
mbed_official 15:a81a8d6c1dfe 401 #define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)))
mbed_official 15:a81a8d6c1dfe 402 #define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
mbed_official 15:a81a8d6c1dfe 403 #define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos)
mbed_official 15:a81a8d6c1dfe 404 #define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
mbed_official 15:a81a8d6c1dfe 405
mbed_official 15:a81a8d6c1dfe 406 /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
mbed_official 15:a81a8d6c1dfe 407 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 408 typedef union {
mbed_official 15:a81a8d6c1dfe 409 struct {
mbed_official 15:a81a8d6c1dfe 410 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
mbed_official 15:a81a8d6c1dfe 411 uint32_t :3; /*!< bit: 3.. 5 Reserved */
mbed_official 15:a81a8d6c1dfe 412 uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
mbed_official 15:a81a8d6c1dfe 413 uint32_t :2; /*!< bit: 7.. 8 Reserved */
mbed_official 15:a81a8d6c1dfe 414 uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
mbed_official 15:a81a8d6c1dfe 415 uint32_t :3; /*!< bit: 10..12 Reserved */
mbed_official 15:a81a8d6c1dfe 416 uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
mbed_official 15:a81a8d6c1dfe 417 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
mbed_official 15:a81a8d6c1dfe 418 uint32_t :1; /*!< bit: 16 Reserved */
mbed_official 15:a81a8d6c1dfe 419 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
mbed_official 15:a81a8d6c1dfe 420 uint32_t :14; /*!< bit: 18..31 Reserved */
mbed_official 15:a81a8d6c1dfe 421 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 422 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 423 } SERCOM_SPI_CTRLB_Type;
mbed_official 15:a81a8d6c1dfe 424 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 425
mbed_official 15:a81a8d6c1dfe 426 #define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
mbed_official 15:a81a8d6c1dfe 427 #define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
mbed_official 15:a81a8d6c1dfe 428
mbed_official 15:a81a8d6c1dfe 429 #define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
mbed_official 15:a81a8d6c1dfe 430 #define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 431 #define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)))
mbed_official 15:a81a8d6c1dfe 432 #define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
mbed_official 15:a81a8d6c1dfe 433 #define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos)
mbed_official 15:a81a8d6c1dfe 434 #define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
mbed_official 15:a81a8d6c1dfe 435 #define SERCOM_SPI_CTRLB_SSDE (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos)
mbed_official 15:a81a8d6c1dfe 436 #define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
mbed_official 15:a81a8d6c1dfe 437 #define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos)
mbed_official 15:a81a8d6c1dfe 438 #define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
mbed_official 15:a81a8d6c1dfe 439 #define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos)
mbed_official 15:a81a8d6c1dfe 440 #define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)))
mbed_official 15:a81a8d6c1dfe 441 #define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
mbed_official 15:a81a8d6c1dfe 442 #define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos)
mbed_official 15:a81a8d6c1dfe 443 #define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
mbed_official 15:a81a8d6c1dfe 444
mbed_official 15:a81a8d6c1dfe 445 /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
mbed_official 15:a81a8d6c1dfe 446 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 447 typedef union {
mbed_official 15:a81a8d6c1dfe 448 struct {
mbed_official 15:a81a8d6c1dfe 449 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
mbed_official 15:a81a8d6c1dfe 450 uint32_t :3; /*!< bit: 3.. 5 Reserved */
mbed_official 15:a81a8d6c1dfe 451 uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
mbed_official 15:a81a8d6c1dfe 452 uint32_t :1; /*!< bit: 7 Reserved */
mbed_official 15:a81a8d6c1dfe 453 uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
mbed_official 15:a81a8d6c1dfe 454 uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
mbed_official 15:a81a8d6c1dfe 455 uint32_t ENC:1; /*!< bit: 10 Encoding Format */
mbed_official 15:a81a8d6c1dfe 456 uint32_t :2; /*!< bit: 11..12 Reserved */
mbed_official 15:a81a8d6c1dfe 457 uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
mbed_official 15:a81a8d6c1dfe 458 uint32_t :2; /*!< bit: 14..15 Reserved */
mbed_official 15:a81a8d6c1dfe 459 uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
mbed_official 15:a81a8d6c1dfe 460 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
mbed_official 15:a81a8d6c1dfe 461 uint32_t :14; /*!< bit: 18..31 Reserved */
mbed_official 15:a81a8d6c1dfe 462 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 463 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 464 } SERCOM_USART_CTRLB_Type;
mbed_official 15:a81a8d6c1dfe 465 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 466
mbed_official 15:a81a8d6c1dfe 467 #define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
mbed_official 15:a81a8d6c1dfe 468 #define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
mbed_official 15:a81a8d6c1dfe 469
mbed_official 15:a81a8d6c1dfe 470 #define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
mbed_official 15:a81a8d6c1dfe 471 #define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos)
mbed_official 15:a81a8d6c1dfe 472 #define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)))
mbed_official 15:a81a8d6c1dfe 473 #define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
mbed_official 15:a81a8d6c1dfe 474 #define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos)
mbed_official 15:a81a8d6c1dfe 475 #define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
mbed_official 15:a81a8d6c1dfe 476 #define SERCOM_USART_CTRLB_COLDEN (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos)
mbed_official 15:a81a8d6c1dfe 477 #define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
mbed_official 15:a81a8d6c1dfe 478 #define SERCOM_USART_CTRLB_SFDE (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos)
mbed_official 15:a81a8d6c1dfe 479 #define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
mbed_official 15:a81a8d6c1dfe 480 #define SERCOM_USART_CTRLB_ENC (0x1ul << SERCOM_USART_CTRLB_ENC_Pos)
mbed_official 15:a81a8d6c1dfe 481 #define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
mbed_official 15:a81a8d6c1dfe 482 #define SERCOM_USART_CTRLB_PMODE (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos)
mbed_official 15:a81a8d6c1dfe 483 #define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
mbed_official 15:a81a8d6c1dfe 484 #define SERCOM_USART_CTRLB_TXEN (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos)
mbed_official 15:a81a8d6c1dfe 485 #define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
mbed_official 15:a81a8d6c1dfe 486 #define SERCOM_USART_CTRLB_RXEN (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos)
mbed_official 15:a81a8d6c1dfe 487 #define SERCOM_USART_CTRLB_MASK 0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */
mbed_official 15:a81a8d6c1dfe 488
mbed_official 15:a81a8d6c1dfe 489 /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
mbed_official 15:a81a8d6c1dfe 490 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 491 typedef union {
mbed_official 15:a81a8d6c1dfe 492 struct {
mbed_official 15:a81a8d6c1dfe 493 uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 494 uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
mbed_official 15:a81a8d6c1dfe 495 uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 496 uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
mbed_official 15:a81a8d6c1dfe 497 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 498 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 499 } SERCOM_I2CM_BAUD_Type;
mbed_official 15:a81a8d6c1dfe 500 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 501
mbed_official 15:a81a8d6c1dfe 502 #define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
mbed_official 15:a81a8d6c1dfe 503 #define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
mbed_official 15:a81a8d6c1dfe 504
mbed_official 15:a81a8d6c1dfe 505 #define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 506 #define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos)
mbed_official 15:a81a8d6c1dfe 507 #define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)))
mbed_official 15:a81a8d6c1dfe 508 #define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
mbed_official 15:a81a8d6c1dfe 509 #define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
mbed_official 15:a81a8d6c1dfe 510 #define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)))
mbed_official 15:a81a8d6c1dfe 511 #define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 512 #define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos)
mbed_official 15:a81a8d6c1dfe 513 #define SERCOM_I2CM_BAUD_HSBAUD(value) ((SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)))
mbed_official 15:a81a8d6c1dfe 514 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
mbed_official 15:a81a8d6c1dfe 515 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
mbed_official 15:a81a8d6c1dfe 516 #define SERCOM_I2CM_BAUD_HSBAUDLOW(value) ((SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)))
mbed_official 15:a81a8d6c1dfe 517 #define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
mbed_official 15:a81a8d6c1dfe 518
mbed_official 15:a81a8d6c1dfe 519 /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
mbed_official 15:a81a8d6c1dfe 520 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 521 typedef union {
mbed_official 15:a81a8d6c1dfe 522 struct {
mbed_official 15:a81a8d6c1dfe 523 uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 524 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 525 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 526 } SERCOM_SPI_BAUD_Type;
mbed_official 15:a81a8d6c1dfe 527 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 528
mbed_official 15:a81a8d6c1dfe 529 #define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
mbed_official 15:a81a8d6c1dfe 530 #define SERCOM_SPI_BAUD_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
mbed_official 15:a81a8d6c1dfe 531
mbed_official 15:a81a8d6c1dfe 532 #define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 533 #define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos)
mbed_official 15:a81a8d6c1dfe 534 #define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)))
mbed_official 15:a81a8d6c1dfe 535 #define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */
mbed_official 15:a81a8d6c1dfe 536
mbed_official 15:a81a8d6c1dfe 537 /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
mbed_official 15:a81a8d6c1dfe 538 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 539 typedef union {
mbed_official 15:a81a8d6c1dfe 540 struct {
mbed_official 15:a81a8d6c1dfe 541 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 542 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 543 struct { // FRAC mode
mbed_official 15:a81a8d6c1dfe 544 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 545 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
mbed_official 15:a81a8d6c1dfe 546 } FRAC; /*!< Structure used for FRAC */
mbed_official 15:a81a8d6c1dfe 547 struct { // FRACFP mode
mbed_official 15:a81a8d6c1dfe 548 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 549 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
mbed_official 15:a81a8d6c1dfe 550 } FRACFP; /*!< Structure used for FRACFP */
mbed_official 15:a81a8d6c1dfe 551 struct { // USARTFP mode
mbed_official 15:a81a8d6c1dfe 552 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 553 } USARTFP; /*!< Structure used for USARTFP */
mbed_official 15:a81a8d6c1dfe 554 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 555 } SERCOM_USART_BAUD_Type;
mbed_official 15:a81a8d6c1dfe 556 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 557
mbed_official 15:a81a8d6c1dfe 558 #define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
mbed_official 15:a81a8d6c1dfe 559 #define SERCOM_USART_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
mbed_official 15:a81a8d6c1dfe 560
mbed_official 15:a81a8d6c1dfe 561 #define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 562 #define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos)
mbed_official 15:a81a8d6c1dfe 563 #define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)))
mbed_official 15:a81a8d6c1dfe 564 #define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */
mbed_official 15:a81a8d6c1dfe 565
mbed_official 15:a81a8d6c1dfe 566 // FRAC mode
mbed_official 15:a81a8d6c1dfe 567 #define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 568 #define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
mbed_official 15:a81a8d6c1dfe 569 #define SERCOM_USART_BAUD_FRAC_BAUD(value) ((SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)))
mbed_official 15:a81a8d6c1dfe 570 #define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
mbed_official 15:a81a8d6c1dfe 571 #define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos)
mbed_official 15:a81a8d6c1dfe 572 #define SERCOM_USART_BAUD_FRAC_FP(value) ((SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos)))
mbed_official 15:a81a8d6c1dfe 573 #define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
mbed_official 15:a81a8d6c1dfe 574
mbed_official 15:a81a8d6c1dfe 575 // FRACFP mode
mbed_official 15:a81a8d6c1dfe 576 #define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 577 #define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
mbed_official 15:a81a8d6c1dfe 578 #define SERCOM_USART_BAUD_FRACFP_BAUD(value) ((SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)))
mbed_official 15:a81a8d6c1dfe 579 #define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
mbed_official 15:a81a8d6c1dfe 580 #define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos)
mbed_official 15:a81a8d6c1dfe 581 #define SERCOM_USART_BAUD_FRACFP_FP(value) ((SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos)))
mbed_official 15:a81a8d6c1dfe 582 #define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
mbed_official 15:a81a8d6c1dfe 583
mbed_official 15:a81a8d6c1dfe 584 // USARTFP mode
mbed_official 15:a81a8d6c1dfe 585 #define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
mbed_official 15:a81a8d6c1dfe 586 #define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
mbed_official 15:a81a8d6c1dfe 587 #define SERCOM_USART_BAUD_USARTFP_BAUD(value) ((SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)))
mbed_official 15:a81a8d6c1dfe 588 #define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
mbed_official 15:a81a8d6c1dfe 589
mbed_official 15:a81a8d6c1dfe 590 /* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
mbed_official 15:a81a8d6c1dfe 591 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 592 typedef union {
mbed_official 15:a81a8d6c1dfe 593 struct {
mbed_official 15:a81a8d6c1dfe 594 uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
mbed_official 15:a81a8d6c1dfe 595 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 596 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 597 } SERCOM_USART_RXPL_Type;
mbed_official 15:a81a8d6c1dfe 598 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 599
mbed_official 15:a81a8d6c1dfe 600 #define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
mbed_official 15:a81a8d6c1dfe 601 #define SERCOM_USART_RXPL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
mbed_official 15:a81a8d6c1dfe 602
mbed_official 15:a81a8d6c1dfe 603 #define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
mbed_official 15:a81a8d6c1dfe 604 #define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos)
mbed_official 15:a81a8d6c1dfe 605 #define SERCOM_USART_RXPL_RXPL(value) ((SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos)))
mbed_official 15:a81a8d6c1dfe 606 #define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */
mbed_official 15:a81a8d6c1dfe 607
mbed_official 15:a81a8d6c1dfe 608 /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
mbed_official 15:a81a8d6c1dfe 609 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 610 typedef union {
mbed_official 15:a81a8d6c1dfe 611 struct {
mbed_official 15:a81a8d6c1dfe 612 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 613 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 614 uint8_t :5; /*!< bit: 2.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 615 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 616 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 617 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 618 } SERCOM_I2CM_INTENCLR_Type;
mbed_official 15:a81a8d6c1dfe 619 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 620
mbed_official 15:a81a8d6c1dfe 621 #define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 622 #define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 623
mbed_official 15:a81a8d6c1dfe 624 #define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 625 #define SERCOM_I2CM_INTENCLR_MB (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos)
mbed_official 15:a81a8d6c1dfe 626 #define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 627 #define SERCOM_I2CM_INTENCLR_SB (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos)
mbed_official 15:a81a8d6c1dfe 628 #define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 629 #define SERCOM_I2CM_INTENCLR_ERROR (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos)
mbed_official 15:a81a8d6c1dfe 630 #define SERCOM_I2CM_INTENCLR_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
mbed_official 15:a81a8d6c1dfe 631
mbed_official 15:a81a8d6c1dfe 632 /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
mbed_official 15:a81a8d6c1dfe 633 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 634 typedef union {
mbed_official 15:a81a8d6c1dfe 635 struct {
mbed_official 15:a81a8d6c1dfe 636 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 637 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 638 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 639 uint8_t :4; /*!< bit: 3.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 640 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 641 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 642 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 643 } SERCOM_I2CS_INTENCLR_Type;
mbed_official 15:a81a8d6c1dfe 644 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 645
mbed_official 15:a81a8d6c1dfe 646 #define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 647 #define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 648
mbed_official 15:a81a8d6c1dfe 649 #define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 650 #define SERCOM_I2CS_INTENCLR_PREC (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos)
mbed_official 15:a81a8d6c1dfe 651 #define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 652 #define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
mbed_official 15:a81a8d6c1dfe 653 #define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 654 #define SERCOM_I2CS_INTENCLR_DRDY (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos)
mbed_official 15:a81a8d6c1dfe 655 #define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 656 #define SERCOM_I2CS_INTENCLR_ERROR (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos)
mbed_official 15:a81a8d6c1dfe 657 #define SERCOM_I2CS_INTENCLR_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
mbed_official 15:a81a8d6c1dfe 658
mbed_official 15:a81a8d6c1dfe 659 /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
mbed_official 15:a81a8d6c1dfe 660 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 661 typedef union {
mbed_official 15:a81a8d6c1dfe 662 struct {
mbed_official 15:a81a8d6c1dfe 663 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 664 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 665 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 666 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 667 uint8_t :3; /*!< bit: 4.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 668 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 669 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 670 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 671 } SERCOM_SPI_INTENCLR_Type;
mbed_official 15:a81a8d6c1dfe 672 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 673
mbed_official 15:a81a8d6c1dfe 674 #define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 675 #define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 676
mbed_official 15:a81a8d6c1dfe 677 #define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 678 #define SERCOM_SPI_INTENCLR_DRE (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos)
mbed_official 15:a81a8d6c1dfe 679 #define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 680 #define SERCOM_SPI_INTENCLR_TXC (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos)
mbed_official 15:a81a8d6c1dfe 681 #define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 682 #define SERCOM_SPI_INTENCLR_RXC (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos)
mbed_official 15:a81a8d6c1dfe 683 #define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 684 #define SERCOM_SPI_INTENCLR_SSL (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos)
mbed_official 15:a81a8d6c1dfe 685 #define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 686 #define SERCOM_SPI_INTENCLR_ERROR (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos)
mbed_official 15:a81a8d6c1dfe 687 #define SERCOM_SPI_INTENCLR_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
mbed_official 15:a81a8d6c1dfe 688
mbed_official 15:a81a8d6c1dfe 689 /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
mbed_official 15:a81a8d6c1dfe 690 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 691 typedef union {
mbed_official 15:a81a8d6c1dfe 692 struct {
mbed_official 15:a81a8d6c1dfe 693 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 694 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 695 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 696 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 697 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 698 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 699 uint8_t :1; /*!< bit: 6 Reserved */
mbed_official 15:a81a8d6c1dfe 700 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 701 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 702 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 703 } SERCOM_USART_INTENCLR_Type;
mbed_official 15:a81a8d6c1dfe 704 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 705
mbed_official 15:a81a8d6c1dfe 706 #define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 707 #define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 708
mbed_official 15:a81a8d6c1dfe 709 #define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 710 #define SERCOM_USART_INTENCLR_DRE (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos)
mbed_official 15:a81a8d6c1dfe 711 #define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 712 #define SERCOM_USART_INTENCLR_TXC (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos)
mbed_official 15:a81a8d6c1dfe 713 #define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 714 #define SERCOM_USART_INTENCLR_RXC (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos)
mbed_official 15:a81a8d6c1dfe 715 #define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 716 #define SERCOM_USART_INTENCLR_RXS (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos)
mbed_official 15:a81a8d6c1dfe 717 #define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 718 #define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos)
mbed_official 15:a81a8d6c1dfe 719 #define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 720 #define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos)
mbed_official 15:a81a8d6c1dfe 721 #define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
mbed_official 15:a81a8d6c1dfe 722 #define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos)
mbed_official 15:a81a8d6c1dfe 723 #define SERCOM_USART_INTENCLR_MASK 0xBFul /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
mbed_official 15:a81a8d6c1dfe 724
mbed_official 15:a81a8d6c1dfe 725 /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
mbed_official 15:a81a8d6c1dfe 726 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 727 typedef union {
mbed_official 15:a81a8d6c1dfe 728 struct {
mbed_official 15:a81a8d6c1dfe 729 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 730 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 731 uint8_t :5; /*!< bit: 2.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 732 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 733 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 734 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 735 } SERCOM_I2CM_INTENSET_Type;
mbed_official 15:a81a8d6c1dfe 736 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 737
mbed_official 15:a81a8d6c1dfe 738 #define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 739 #define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 740
mbed_official 15:a81a8d6c1dfe 741 #define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 742 #define SERCOM_I2CM_INTENSET_MB (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos)
mbed_official 15:a81a8d6c1dfe 743 #define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 744 #define SERCOM_I2CM_INTENSET_SB (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos)
mbed_official 15:a81a8d6c1dfe 745 #define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 746 #define SERCOM_I2CM_INTENSET_ERROR (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos)
mbed_official 15:a81a8d6c1dfe 747 #define SERCOM_I2CM_INTENSET_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
mbed_official 15:a81a8d6c1dfe 748
mbed_official 15:a81a8d6c1dfe 749 /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
mbed_official 15:a81a8d6c1dfe 750 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 751 typedef union {
mbed_official 15:a81a8d6c1dfe 752 struct {
mbed_official 15:a81a8d6c1dfe 753 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 754 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 755 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 756 uint8_t :4; /*!< bit: 3.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 757 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 758 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 759 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 760 } SERCOM_I2CS_INTENSET_Type;
mbed_official 15:a81a8d6c1dfe 761 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 762
mbed_official 15:a81a8d6c1dfe 763 #define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 764 #define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 765
mbed_official 15:a81a8d6c1dfe 766 #define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 767 #define SERCOM_I2CS_INTENSET_PREC (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos)
mbed_official 15:a81a8d6c1dfe 768 #define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 769 #define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos)
mbed_official 15:a81a8d6c1dfe 770 #define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 771 #define SERCOM_I2CS_INTENSET_DRDY (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos)
mbed_official 15:a81a8d6c1dfe 772 #define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 773 #define SERCOM_I2CS_INTENSET_ERROR (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos)
mbed_official 15:a81a8d6c1dfe 774 #define SERCOM_I2CS_INTENSET_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
mbed_official 15:a81a8d6c1dfe 775
mbed_official 15:a81a8d6c1dfe 776 /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
mbed_official 15:a81a8d6c1dfe 777 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 778 typedef union {
mbed_official 15:a81a8d6c1dfe 779 struct {
mbed_official 15:a81a8d6c1dfe 780 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 781 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 782 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 783 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 784 uint8_t :3; /*!< bit: 4.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 785 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 786 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 787 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 788 } SERCOM_SPI_INTENSET_Type;
mbed_official 15:a81a8d6c1dfe 789 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 790
mbed_official 15:a81a8d6c1dfe 791 #define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 792 #define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 793
mbed_official 15:a81a8d6c1dfe 794 #define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 795 #define SERCOM_SPI_INTENSET_DRE (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos)
mbed_official 15:a81a8d6c1dfe 796 #define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 797 #define SERCOM_SPI_INTENSET_TXC (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos)
mbed_official 15:a81a8d6c1dfe 798 #define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 799 #define SERCOM_SPI_INTENSET_RXC (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos)
mbed_official 15:a81a8d6c1dfe 800 #define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 801 #define SERCOM_SPI_INTENSET_SSL (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos)
mbed_official 15:a81a8d6c1dfe 802 #define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 803 #define SERCOM_SPI_INTENSET_ERROR (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos)
mbed_official 15:a81a8d6c1dfe 804 #define SERCOM_SPI_INTENSET_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
mbed_official 15:a81a8d6c1dfe 805
mbed_official 15:a81a8d6c1dfe 806 /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
mbed_official 15:a81a8d6c1dfe 807 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 808 typedef union {
mbed_official 15:a81a8d6c1dfe 809 struct {
mbed_official 15:a81a8d6c1dfe 810 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 811 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 812 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 813 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 814 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 815 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 816 uint8_t :1; /*!< bit: 6 Reserved */
mbed_official 15:a81a8d6c1dfe 817 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 818 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 819 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 820 } SERCOM_USART_INTENSET_Type;
mbed_official 15:a81a8d6c1dfe 821 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 822
mbed_official 15:a81a8d6c1dfe 823 #define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 824 #define SERCOM_USART_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 825
mbed_official 15:a81a8d6c1dfe 826 #define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 827 #define SERCOM_USART_INTENSET_DRE (0x1ul << SERCOM_USART_INTENSET_DRE_Pos)
mbed_official 15:a81a8d6c1dfe 828 #define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 829 #define SERCOM_USART_INTENSET_TXC (0x1ul << SERCOM_USART_INTENSET_TXC_Pos)
mbed_official 15:a81a8d6c1dfe 830 #define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 831 #define SERCOM_USART_INTENSET_RXC (0x1ul << SERCOM_USART_INTENSET_RXC_Pos)
mbed_official 15:a81a8d6c1dfe 832 #define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 833 #define SERCOM_USART_INTENSET_RXS (0x1ul << SERCOM_USART_INTENSET_RXS_Pos)
mbed_official 15:a81a8d6c1dfe 834 #define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 835 #define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos)
mbed_official 15:a81a8d6c1dfe 836 #define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 837 #define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos)
mbed_official 15:a81a8d6c1dfe 838 #define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 839 #define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos)
mbed_official 15:a81a8d6c1dfe 840 #define SERCOM_USART_INTENSET_MASK 0xBFul /**< \brief (SERCOM_USART_INTENSET) MASK Register */
mbed_official 15:a81a8d6c1dfe 841
mbed_official 15:a81a8d6c1dfe 842 /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
mbed_official 15:a81a8d6c1dfe 843 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 844 typedef union {
mbed_official 15:a81a8d6c1dfe 845 struct {
mbed_official 15:a81a8d6c1dfe 846 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
mbed_official 15:a81a8d6c1dfe 847 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
mbed_official 15:a81a8d6c1dfe 848 uint8_t :5; /*!< bit: 2.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 849 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
mbed_official 15:a81a8d6c1dfe 850 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 851 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 852 } SERCOM_I2CM_INTFLAG_Type;
mbed_official 15:a81a8d6c1dfe 853 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 854
mbed_official 15:a81a8d6c1dfe 855 #define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 856 #define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 857
mbed_official 15:a81a8d6c1dfe 858 #define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
mbed_official 15:a81a8d6c1dfe 859 #define SERCOM_I2CM_INTFLAG_MB (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos)
mbed_official 15:a81a8d6c1dfe 860 #define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
mbed_official 15:a81a8d6c1dfe 861 #define SERCOM_I2CM_INTFLAG_SB (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos)
mbed_official 15:a81a8d6c1dfe 862 #define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
mbed_official 15:a81a8d6c1dfe 863 #define SERCOM_I2CM_INTFLAG_ERROR (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos)
mbed_official 15:a81a8d6c1dfe 864 #define SERCOM_I2CM_INTFLAG_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
mbed_official 15:a81a8d6c1dfe 865
mbed_official 15:a81a8d6c1dfe 866 /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
mbed_official 15:a81a8d6c1dfe 867 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 868 typedef union {
mbed_official 15:a81a8d6c1dfe 869 struct {
mbed_official 15:a81a8d6c1dfe 870 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
mbed_official 15:a81a8d6c1dfe 871 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
mbed_official 15:a81a8d6c1dfe 872 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
mbed_official 15:a81a8d6c1dfe 873 uint8_t :4; /*!< bit: 3.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 874 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
mbed_official 15:a81a8d6c1dfe 875 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 876 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 877 } SERCOM_I2CS_INTFLAG_Type;
mbed_official 15:a81a8d6c1dfe 878 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 879
mbed_official 15:a81a8d6c1dfe 880 #define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 881 #define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 882
mbed_official 15:a81a8d6c1dfe 883 #define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
mbed_official 15:a81a8d6c1dfe 884 #define SERCOM_I2CS_INTFLAG_PREC (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos)
mbed_official 15:a81a8d6c1dfe 885 #define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
mbed_official 15:a81a8d6c1dfe 886 #define SERCOM_I2CS_INTFLAG_AMATCH (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
mbed_official 15:a81a8d6c1dfe 887 #define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
mbed_official 15:a81a8d6c1dfe 888 #define SERCOM_I2CS_INTFLAG_DRDY (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos)
mbed_official 15:a81a8d6c1dfe 889 #define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
mbed_official 15:a81a8d6c1dfe 890 #define SERCOM_I2CS_INTFLAG_ERROR (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos)
mbed_official 15:a81a8d6c1dfe 891 #define SERCOM_I2CS_INTFLAG_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
mbed_official 15:a81a8d6c1dfe 892
mbed_official 15:a81a8d6c1dfe 893 /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
mbed_official 15:a81a8d6c1dfe 894 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 895 typedef union {
mbed_official 15:a81a8d6c1dfe 896 struct {
mbed_official 15:a81a8d6c1dfe 897 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
mbed_official 15:a81a8d6c1dfe 898 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
mbed_official 15:a81a8d6c1dfe 899 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
mbed_official 15:a81a8d6c1dfe 900 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
mbed_official 15:a81a8d6c1dfe 901 uint8_t :3; /*!< bit: 4.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 902 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
mbed_official 15:a81a8d6c1dfe 903 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 904 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 905 } SERCOM_SPI_INTFLAG_Type;
mbed_official 15:a81a8d6c1dfe 906 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 907
mbed_official 15:a81a8d6c1dfe 908 #define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 909 #define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 910
mbed_official 15:a81a8d6c1dfe 911 #define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
mbed_official 15:a81a8d6c1dfe 912 #define SERCOM_SPI_INTFLAG_DRE (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos)
mbed_official 15:a81a8d6c1dfe 913 #define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
mbed_official 15:a81a8d6c1dfe 914 #define SERCOM_SPI_INTFLAG_TXC (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos)
mbed_official 15:a81a8d6c1dfe 915 #define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
mbed_official 15:a81a8d6c1dfe 916 #define SERCOM_SPI_INTFLAG_RXC (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos)
mbed_official 15:a81a8d6c1dfe 917 #define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
mbed_official 15:a81a8d6c1dfe 918 #define SERCOM_SPI_INTFLAG_SSL (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos)
mbed_official 15:a81a8d6c1dfe 919 #define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
mbed_official 15:a81a8d6c1dfe 920 #define SERCOM_SPI_INTFLAG_ERROR (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos)
mbed_official 15:a81a8d6c1dfe 921 #define SERCOM_SPI_INTFLAG_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
mbed_official 15:a81a8d6c1dfe 922
mbed_official 15:a81a8d6c1dfe 923 /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
mbed_official 15:a81a8d6c1dfe 924 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 925 typedef union {
mbed_official 15:a81a8d6c1dfe 926 struct {
mbed_official 15:a81a8d6c1dfe 927 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
mbed_official 15:a81a8d6c1dfe 928 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
mbed_official 15:a81a8d6c1dfe 929 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
mbed_official 15:a81a8d6c1dfe 930 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
mbed_official 15:a81a8d6c1dfe 931 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
mbed_official 15:a81a8d6c1dfe 932 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
mbed_official 15:a81a8d6c1dfe 933 uint8_t :1; /*!< bit: 6 Reserved */
mbed_official 15:a81a8d6c1dfe 934 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
mbed_official 15:a81a8d6c1dfe 935 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 936 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 937 } SERCOM_USART_INTFLAG_Type;
mbed_official 15:a81a8d6c1dfe 938 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 939
mbed_official 15:a81a8d6c1dfe 940 #define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 941 #define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 942
mbed_official 15:a81a8d6c1dfe 943 #define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
mbed_official 15:a81a8d6c1dfe 944 #define SERCOM_USART_INTFLAG_DRE (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos)
mbed_official 15:a81a8d6c1dfe 945 #define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
mbed_official 15:a81a8d6c1dfe 946 #define SERCOM_USART_INTFLAG_TXC (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos)
mbed_official 15:a81a8d6c1dfe 947 #define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
mbed_official 15:a81a8d6c1dfe 948 #define SERCOM_USART_INTFLAG_RXC (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos)
mbed_official 15:a81a8d6c1dfe 949 #define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
mbed_official 15:a81a8d6c1dfe 950 #define SERCOM_USART_INTFLAG_RXS (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos)
mbed_official 15:a81a8d6c1dfe 951 #define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
mbed_official 15:a81a8d6c1dfe 952 #define SERCOM_USART_INTFLAG_CTSIC (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos)
mbed_official 15:a81a8d6c1dfe 953 #define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
mbed_official 15:a81a8d6c1dfe 954 #define SERCOM_USART_INTFLAG_RXBRK (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos)
mbed_official 15:a81a8d6c1dfe 955 #define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
mbed_official 15:a81a8d6c1dfe 956 #define SERCOM_USART_INTFLAG_ERROR (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos)
mbed_official 15:a81a8d6c1dfe 957 #define SERCOM_USART_INTFLAG_MASK 0xBFul /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
mbed_official 15:a81a8d6c1dfe 958
mbed_official 15:a81a8d6c1dfe 959 /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
mbed_official 15:a81a8d6c1dfe 960 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 961 typedef union {
mbed_official 15:a81a8d6c1dfe 962 struct {
mbed_official 15:a81a8d6c1dfe 963 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
mbed_official 15:a81a8d6c1dfe 964 uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
mbed_official 15:a81a8d6c1dfe 965 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
mbed_official 15:a81a8d6c1dfe 966 uint16_t :1; /*!< bit: 3 Reserved */
mbed_official 15:a81a8d6c1dfe 967 uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
mbed_official 15:a81a8d6c1dfe 968 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
mbed_official 15:a81a8d6c1dfe 969 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
mbed_official 15:a81a8d6c1dfe 970 uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
mbed_official 15:a81a8d6c1dfe 971 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
mbed_official 15:a81a8d6c1dfe 972 uint16_t LENERR:1; /*!< bit: 10 Length Error */
mbed_official 15:a81a8d6c1dfe 973 uint16_t :5; /*!< bit: 11..15 Reserved */
mbed_official 15:a81a8d6c1dfe 974 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 975 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 976 } SERCOM_I2CM_STATUS_Type;
mbed_official 15:a81a8d6c1dfe 977 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 978
mbed_official 15:a81a8d6c1dfe 979 #define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
mbed_official 15:a81a8d6c1dfe 980 #define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
mbed_official 15:a81a8d6c1dfe 981
mbed_official 15:a81a8d6c1dfe 982 #define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
mbed_official 15:a81a8d6c1dfe 983 #define SERCOM_I2CM_STATUS_BUSERR (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos)
mbed_official 15:a81a8d6c1dfe 984 #define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
mbed_official 15:a81a8d6c1dfe 985 #define SERCOM_I2CM_STATUS_ARBLOST (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos)
mbed_official 15:a81a8d6c1dfe 986 #define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
mbed_official 15:a81a8d6c1dfe 987 #define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos)
mbed_official 15:a81a8d6c1dfe 988 #define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
mbed_official 15:a81a8d6c1dfe 989 #define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
mbed_official 15:a81a8d6c1dfe 990 #define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)))
mbed_official 15:a81a8d6c1dfe 991 #define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
mbed_official 15:a81a8d6c1dfe 992 #define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
mbed_official 15:a81a8d6c1dfe 993 #define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
mbed_official 15:a81a8d6c1dfe 994 #define SERCOM_I2CM_STATUS_CLKHOLD (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
mbed_official 15:a81a8d6c1dfe 995 #define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
mbed_official 15:a81a8d6c1dfe 996 #define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
mbed_official 15:a81a8d6c1dfe 997 #define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
mbed_official 15:a81a8d6c1dfe 998 #define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
mbed_official 15:a81a8d6c1dfe 999 #define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */
mbed_official 15:a81a8d6c1dfe 1000 #define SERCOM_I2CM_STATUS_LENERR (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos)
mbed_official 15:a81a8d6c1dfe 1001 #define SERCOM_I2CM_STATUS_MASK 0x07F7ul /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
mbed_official 15:a81a8d6c1dfe 1002
mbed_official 15:a81a8d6c1dfe 1003 /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
mbed_official 15:a81a8d6c1dfe 1004 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1005 typedef union {
mbed_official 15:a81a8d6c1dfe 1006 struct {
mbed_official 15:a81a8d6c1dfe 1007 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
mbed_official 15:a81a8d6c1dfe 1008 uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
mbed_official 15:a81a8d6c1dfe 1009 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
mbed_official 15:a81a8d6c1dfe 1010 uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
mbed_official 15:a81a8d6c1dfe 1011 uint16_t SR:1; /*!< bit: 4 Repeated Start */
mbed_official 15:a81a8d6c1dfe 1012 uint16_t :1; /*!< bit: 5 Reserved */
mbed_official 15:a81a8d6c1dfe 1013 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
mbed_official 15:a81a8d6c1dfe 1014 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
mbed_official 15:a81a8d6c1dfe 1015 uint16_t :1; /*!< bit: 8 Reserved */
mbed_official 15:a81a8d6c1dfe 1016 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
mbed_official 15:a81a8d6c1dfe 1017 uint16_t HS:1; /*!< bit: 10 High Speed */
mbed_official 15:a81a8d6c1dfe 1018 uint16_t :5; /*!< bit: 11..15 Reserved */
mbed_official 15:a81a8d6c1dfe 1019 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1020 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1021 } SERCOM_I2CS_STATUS_Type;
mbed_official 15:a81a8d6c1dfe 1022 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1023
mbed_official 15:a81a8d6c1dfe 1024 #define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
mbed_official 15:a81a8d6c1dfe 1025 #define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
mbed_official 15:a81a8d6c1dfe 1026
mbed_official 15:a81a8d6c1dfe 1027 #define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
mbed_official 15:a81a8d6c1dfe 1028 #define SERCOM_I2CS_STATUS_BUSERR (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos)
mbed_official 15:a81a8d6c1dfe 1029 #define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
mbed_official 15:a81a8d6c1dfe 1030 #define SERCOM_I2CS_STATUS_COLL (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos)
mbed_official 15:a81a8d6c1dfe 1031 #define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
mbed_official 15:a81a8d6c1dfe 1032 #define SERCOM_I2CS_STATUS_RXNACK (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos)
mbed_official 15:a81a8d6c1dfe 1033 #define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
mbed_official 15:a81a8d6c1dfe 1034 #define SERCOM_I2CS_STATUS_DIR (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos)
mbed_official 15:a81a8d6c1dfe 1035 #define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
mbed_official 15:a81a8d6c1dfe 1036 #define SERCOM_I2CS_STATUS_SR (0x1ul << SERCOM_I2CS_STATUS_SR_Pos)
mbed_official 15:a81a8d6c1dfe 1037 #define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
mbed_official 15:a81a8d6c1dfe 1038 #define SERCOM_I2CS_STATUS_LOWTOUT (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
mbed_official 15:a81a8d6c1dfe 1039 #define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
mbed_official 15:a81a8d6c1dfe 1040 #define SERCOM_I2CS_STATUS_CLKHOLD (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
mbed_official 15:a81a8d6c1dfe 1041 #define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
mbed_official 15:a81a8d6c1dfe 1042 #define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
mbed_official 15:a81a8d6c1dfe 1043 #define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */
mbed_official 15:a81a8d6c1dfe 1044 #define SERCOM_I2CS_STATUS_HS (0x1ul << SERCOM_I2CS_STATUS_HS_Pos)
mbed_official 15:a81a8d6c1dfe 1045 #define SERCOM_I2CS_STATUS_MASK 0x06DFul /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
mbed_official 15:a81a8d6c1dfe 1046
mbed_official 15:a81a8d6c1dfe 1047 /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
mbed_official 15:a81a8d6c1dfe 1048 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1049 typedef union {
mbed_official 15:a81a8d6c1dfe 1050 struct {
mbed_official 15:a81a8d6c1dfe 1051 uint16_t :2; /*!< bit: 0.. 1 Reserved */
mbed_official 15:a81a8d6c1dfe 1052 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
mbed_official 15:a81a8d6c1dfe 1053 uint16_t :13; /*!< bit: 3..15 Reserved */
mbed_official 15:a81a8d6c1dfe 1054 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1055 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1056 } SERCOM_SPI_STATUS_Type;
mbed_official 15:a81a8d6c1dfe 1057 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1058
mbed_official 15:a81a8d6c1dfe 1059 #define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
mbed_official 15:a81a8d6c1dfe 1060 #define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
mbed_official 15:a81a8d6c1dfe 1061
mbed_official 15:a81a8d6c1dfe 1062 #define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
mbed_official 15:a81a8d6c1dfe 1063 #define SERCOM_SPI_STATUS_BUFOVF (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos)
mbed_official 15:a81a8d6c1dfe 1064 #define SERCOM_SPI_STATUS_MASK 0x0004ul /**< \brief (SERCOM_SPI_STATUS) MASK Register */
mbed_official 15:a81a8d6c1dfe 1065
mbed_official 15:a81a8d6c1dfe 1066 /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
mbed_official 15:a81a8d6c1dfe 1067 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1068 typedef union {
mbed_official 15:a81a8d6c1dfe 1069 struct {
mbed_official 15:a81a8d6c1dfe 1070 uint16_t PERR:1; /*!< bit: 0 Parity Error */
mbed_official 15:a81a8d6c1dfe 1071 uint16_t FERR:1; /*!< bit: 1 Frame Error */
mbed_official 15:a81a8d6c1dfe 1072 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
mbed_official 15:a81a8d6c1dfe 1073 uint16_t CTS:1; /*!< bit: 3 Clear To Send */
mbed_official 15:a81a8d6c1dfe 1074 uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
mbed_official 15:a81a8d6c1dfe 1075 uint16_t COLL:1; /*!< bit: 5 Collision Detected */
mbed_official 15:a81a8d6c1dfe 1076 uint16_t :10; /*!< bit: 6..15 Reserved */
mbed_official 15:a81a8d6c1dfe 1077 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1078 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1079 } SERCOM_USART_STATUS_Type;
mbed_official 15:a81a8d6c1dfe 1080 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1081
mbed_official 15:a81a8d6c1dfe 1082 #define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */
mbed_official 15:a81a8d6c1dfe 1083 #define SERCOM_USART_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
mbed_official 15:a81a8d6c1dfe 1084
mbed_official 15:a81a8d6c1dfe 1085 #define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */
mbed_official 15:a81a8d6c1dfe 1086 #define SERCOM_USART_STATUS_PERR (0x1ul << SERCOM_USART_STATUS_PERR_Pos)
mbed_official 15:a81a8d6c1dfe 1087 #define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */
mbed_official 15:a81a8d6c1dfe 1088 #define SERCOM_USART_STATUS_FERR (0x1ul << SERCOM_USART_STATUS_FERR_Pos)
mbed_official 15:a81a8d6c1dfe 1089 #define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
mbed_official 15:a81a8d6c1dfe 1090 #define SERCOM_USART_STATUS_BUFOVF (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos)
mbed_official 15:a81a8d6c1dfe 1091 #define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */
mbed_official 15:a81a8d6c1dfe 1092 #define SERCOM_USART_STATUS_CTS (0x1ul << SERCOM_USART_STATUS_CTS_Pos)
mbed_official 15:a81a8d6c1dfe 1093 #define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
mbed_official 15:a81a8d6c1dfe 1094 #define SERCOM_USART_STATUS_ISF (0x1ul << SERCOM_USART_STATUS_ISF_Pos)
mbed_official 15:a81a8d6c1dfe 1095 #define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */
mbed_official 15:a81a8d6c1dfe 1096 #define SERCOM_USART_STATUS_COLL (0x1ul << SERCOM_USART_STATUS_COLL_Pos)
mbed_official 15:a81a8d6c1dfe 1097 #define SERCOM_USART_STATUS_MASK 0x003Ful /**< \brief (SERCOM_USART_STATUS) MASK Register */
mbed_official 15:a81a8d6c1dfe 1098
mbed_official 15:a81a8d6c1dfe 1099 /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */
mbed_official 15:a81a8d6c1dfe 1100 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1101 typedef union {
mbed_official 15:a81a8d6c1dfe 1102 struct {
mbed_official 15:a81a8d6c1dfe 1103 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1104 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1105 uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1106 uint32_t :29; /*!< bit: 3..31 Reserved */
mbed_official 15:a81a8d6c1dfe 1107 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1108 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1109 } SERCOM_I2CM_SYNCBUSY_Type;
mbed_official 15:a81a8d6c1dfe 1110 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1111
mbed_official 15:a81a8d6c1dfe 1112 #define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */
mbed_official 15:a81a8d6c1dfe 1113 #define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */
mbed_official 15:a81a8d6c1dfe 1114
mbed_official 15:a81a8d6c1dfe 1115 #define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1116 #define SERCOM_I2CM_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 1117 #define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1118 #define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 1119 #define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1120 #define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
mbed_official 15:a81a8d6c1dfe 1121 #define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
mbed_official 15:a81a8d6c1dfe 1122
mbed_official 15:a81a8d6c1dfe 1123 /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */
mbed_official 15:a81a8d6c1dfe 1124 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1125 typedef union {
mbed_official 15:a81a8d6c1dfe 1126 struct {
mbed_official 15:a81a8d6c1dfe 1127 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1128 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1129 uint32_t :30; /*!< bit: 2..31 Reserved */
mbed_official 15:a81a8d6c1dfe 1130 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1131 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1132 } SERCOM_I2CS_SYNCBUSY_Type;
mbed_official 15:a81a8d6c1dfe 1133 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1134
mbed_official 15:a81a8d6c1dfe 1135 #define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */
mbed_official 15:a81a8d6c1dfe 1136 #define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */
mbed_official 15:a81a8d6c1dfe 1137
mbed_official 15:a81a8d6c1dfe 1138 #define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1139 #define SERCOM_I2CS_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 1140 #define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1141 #define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 1142 #define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
mbed_official 15:a81a8d6c1dfe 1143
mbed_official 15:a81a8d6c1dfe 1144 /* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */
mbed_official 15:a81a8d6c1dfe 1145 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1146 typedef union {
mbed_official 15:a81a8d6c1dfe 1147 struct {
mbed_official 15:a81a8d6c1dfe 1148 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1149 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1150 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1151 uint32_t :29; /*!< bit: 3..31 Reserved */
mbed_official 15:a81a8d6c1dfe 1152 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1153 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1154 } SERCOM_SPI_SYNCBUSY_Type;
mbed_official 15:a81a8d6c1dfe 1155 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1156
mbed_official 15:a81a8d6c1dfe 1157 #define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */
mbed_official 15:a81a8d6c1dfe 1158 #define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */
mbed_official 15:a81a8d6c1dfe 1159
mbed_official 15:a81a8d6c1dfe 1160 #define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1161 #define SERCOM_SPI_SYNCBUSY_SWRST (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 1162 #define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1163 #define SERCOM_SPI_SYNCBUSY_ENABLE (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 1164 #define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1165 #define SERCOM_SPI_SYNCBUSY_CTRLB (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
mbed_official 15:a81a8d6c1dfe 1166 #define SERCOM_SPI_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
mbed_official 15:a81a8d6c1dfe 1167
mbed_official 15:a81a8d6c1dfe 1168 /* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */
mbed_official 15:a81a8d6c1dfe 1169 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1170 typedef union {
mbed_official 15:a81a8d6c1dfe 1171 struct {
mbed_official 15:a81a8d6c1dfe 1172 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1173 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1174 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1175 uint32_t :29; /*!< bit: 3..31 Reserved */
mbed_official 15:a81a8d6c1dfe 1176 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1177 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1178 } SERCOM_USART_SYNCBUSY_Type;
mbed_official 15:a81a8d6c1dfe 1179 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1180
mbed_official 15:a81a8d6c1dfe 1181 #define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */
mbed_official 15:a81a8d6c1dfe 1182 #define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */
mbed_official 15:a81a8d6c1dfe 1183
mbed_official 15:a81a8d6c1dfe 1184 #define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1185 #define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 1186 #define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1187 #define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 1188 #define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 1189 #define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
mbed_official 15:a81a8d6c1dfe 1190 #define SERCOM_USART_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
mbed_official 15:a81a8d6c1dfe 1191
mbed_official 15:a81a8d6c1dfe 1192 /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
mbed_official 15:a81a8d6c1dfe 1193 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1194 typedef union {
mbed_official 15:a81a8d6c1dfe 1195 struct {
mbed_official 15:a81a8d6c1dfe 1196 uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
mbed_official 15:a81a8d6c1dfe 1197 uint32_t :2; /*!< bit: 11..12 Reserved */
mbed_official 15:a81a8d6c1dfe 1198 uint32_t LENEN:1; /*!< bit: 13 Length Enable */
mbed_official 15:a81a8d6c1dfe 1199 uint32_t HS:1; /*!< bit: 14 High Speed Mode */
mbed_official 15:a81a8d6c1dfe 1200 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
mbed_official 15:a81a8d6c1dfe 1201 uint32_t LEN:8; /*!< bit: 16..23 Length */
mbed_official 15:a81a8d6c1dfe 1202 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 15:a81a8d6c1dfe 1203 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1204 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1205 } SERCOM_I2CM_ADDR_Type;
mbed_official 15:a81a8d6c1dfe 1206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1207
mbed_official 15:a81a8d6c1dfe 1208 #define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
mbed_official 15:a81a8d6c1dfe 1209 #define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
mbed_official 15:a81a8d6c1dfe 1210
mbed_official 15:a81a8d6c1dfe 1211 #define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
mbed_official 15:a81a8d6c1dfe 1212 #define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos)
mbed_official 15:a81a8d6c1dfe 1213 #define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)))
mbed_official 15:a81a8d6c1dfe 1214 #define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
mbed_official 15:a81a8d6c1dfe 1215 #define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos)
mbed_official 15:a81a8d6c1dfe 1216 #define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
mbed_official 15:a81a8d6c1dfe 1217 #define SERCOM_I2CM_ADDR_HS (0x1ul << SERCOM_I2CM_ADDR_HS_Pos)
mbed_official 15:a81a8d6c1dfe 1218 #define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
mbed_official 15:a81a8d6c1dfe 1219 #define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos)
mbed_official 15:a81a8d6c1dfe 1220 #define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
mbed_official 15:a81a8d6c1dfe 1221 #define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos)
mbed_official 15:a81a8d6c1dfe 1222 #define SERCOM_I2CM_ADDR_LEN(value) ((SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos)))
mbed_official 15:a81a8d6c1dfe 1223 #define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
mbed_official 15:a81a8d6c1dfe 1224
mbed_official 15:a81a8d6c1dfe 1225 /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
mbed_official 15:a81a8d6c1dfe 1226 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1227 typedef union {
mbed_official 15:a81a8d6c1dfe 1228 struct {
mbed_official 15:a81a8d6c1dfe 1229 uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
mbed_official 15:a81a8d6c1dfe 1230 uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
mbed_official 15:a81a8d6c1dfe 1231 uint32_t :4; /*!< bit: 11..14 Reserved */
mbed_official 15:a81a8d6c1dfe 1232 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
mbed_official 15:a81a8d6c1dfe 1233 uint32_t :1; /*!< bit: 16 Reserved */
mbed_official 15:a81a8d6c1dfe 1234 uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
mbed_official 15:a81a8d6c1dfe 1235 uint32_t :5; /*!< bit: 27..31 Reserved */
mbed_official 15:a81a8d6c1dfe 1236 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1237 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1238 } SERCOM_I2CS_ADDR_Type;
mbed_official 15:a81a8d6c1dfe 1239 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1240
mbed_official 15:a81a8d6c1dfe 1241 #define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
mbed_official 15:a81a8d6c1dfe 1242 #define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
mbed_official 15:a81a8d6c1dfe 1243
mbed_official 15:a81a8d6c1dfe 1244 #define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
mbed_official 15:a81a8d6c1dfe 1245 #define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos)
mbed_official 15:a81a8d6c1dfe 1246 #define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
mbed_official 15:a81a8d6c1dfe 1247 #define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos)
mbed_official 15:a81a8d6c1dfe 1248 #define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)))
mbed_official 15:a81a8d6c1dfe 1249 #define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
mbed_official 15:a81a8d6c1dfe 1250 #define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos)
mbed_official 15:a81a8d6c1dfe 1251 #define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
mbed_official 15:a81a8d6c1dfe 1252 #define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
mbed_official 15:a81a8d6c1dfe 1253 #define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)))
mbed_official 15:a81a8d6c1dfe 1254 #define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
mbed_official 15:a81a8d6c1dfe 1255
mbed_official 15:a81a8d6c1dfe 1256 /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
mbed_official 15:a81a8d6c1dfe 1257 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1258 typedef union {
mbed_official 15:a81a8d6c1dfe 1259 struct {
mbed_official 15:a81a8d6c1dfe 1260 uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
mbed_official 15:a81a8d6c1dfe 1261 uint32_t :8; /*!< bit: 8..15 Reserved */
mbed_official 15:a81a8d6c1dfe 1262 uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
mbed_official 15:a81a8d6c1dfe 1263 uint32_t :8; /*!< bit: 24..31 Reserved */
mbed_official 15:a81a8d6c1dfe 1264 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1265 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1266 } SERCOM_SPI_ADDR_Type;
mbed_official 15:a81a8d6c1dfe 1267 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1268
mbed_official 15:a81a8d6c1dfe 1269 #define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
mbed_official 15:a81a8d6c1dfe 1270 #define SERCOM_SPI_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
mbed_official 15:a81a8d6c1dfe 1271
mbed_official 15:a81a8d6c1dfe 1272 #define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
mbed_official 15:a81a8d6c1dfe 1273 #define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos)
mbed_official 15:a81a8d6c1dfe 1274 #define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)))
mbed_official 15:a81a8d6c1dfe 1275 #define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
mbed_official 15:a81a8d6c1dfe 1276 #define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos)
mbed_official 15:a81a8d6c1dfe 1277 #define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)))
mbed_official 15:a81a8d6c1dfe 1278 #define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */
mbed_official 15:a81a8d6c1dfe 1279
mbed_official 15:a81a8d6c1dfe 1280 /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
mbed_official 15:a81a8d6c1dfe 1281 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1282 typedef union {
mbed_official 15:a81a8d6c1dfe 1283 struct {
mbed_official 15:a81a8d6c1dfe 1284 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
mbed_official 15:a81a8d6c1dfe 1285 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1286 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1287 } SERCOM_I2CM_DATA_Type;
mbed_official 15:a81a8d6c1dfe 1288 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1289
mbed_official 15:a81a8d6c1dfe 1290 #define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
mbed_official 15:a81a8d6c1dfe 1291 #define SERCOM_I2CM_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
mbed_official 15:a81a8d6c1dfe 1292
mbed_official 15:a81a8d6c1dfe 1293 #define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
mbed_official 15:a81a8d6c1dfe 1294 #define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos)
mbed_official 15:a81a8d6c1dfe 1295 #define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)))
mbed_official 15:a81a8d6c1dfe 1296 #define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */
mbed_official 15:a81a8d6c1dfe 1297
mbed_official 15:a81a8d6c1dfe 1298 /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
mbed_official 15:a81a8d6c1dfe 1299 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1300 typedef union {
mbed_official 15:a81a8d6c1dfe 1301 struct {
mbed_official 15:a81a8d6c1dfe 1302 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
mbed_official 15:a81a8d6c1dfe 1303 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1304 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1305 } SERCOM_I2CS_DATA_Type;
mbed_official 15:a81a8d6c1dfe 1306 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1307
mbed_official 15:a81a8d6c1dfe 1308 #define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
mbed_official 15:a81a8d6c1dfe 1309 #define SERCOM_I2CS_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
mbed_official 15:a81a8d6c1dfe 1310
mbed_official 15:a81a8d6c1dfe 1311 #define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
mbed_official 15:a81a8d6c1dfe 1312 #define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos)
mbed_official 15:a81a8d6c1dfe 1313 #define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)))
mbed_official 15:a81a8d6c1dfe 1314 #define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */
mbed_official 15:a81a8d6c1dfe 1315
mbed_official 15:a81a8d6c1dfe 1316 /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
mbed_official 15:a81a8d6c1dfe 1317 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1318 typedef union {
mbed_official 15:a81a8d6c1dfe 1319 struct {
mbed_official 15:a81a8d6c1dfe 1320 uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
mbed_official 15:a81a8d6c1dfe 1321 uint32_t :23; /*!< bit: 9..31 Reserved */
mbed_official 15:a81a8d6c1dfe 1322 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1323 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1324 } SERCOM_SPI_DATA_Type;
mbed_official 15:a81a8d6c1dfe 1325 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1326
mbed_official 15:a81a8d6c1dfe 1327 #define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
mbed_official 15:a81a8d6c1dfe 1328 #define SERCOM_SPI_DATA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
mbed_official 15:a81a8d6c1dfe 1329
mbed_official 15:a81a8d6c1dfe 1330 #define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
mbed_official 15:a81a8d6c1dfe 1331 #define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos)
mbed_official 15:a81a8d6c1dfe 1332 #define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)))
mbed_official 15:a81a8d6c1dfe 1333 #define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */
mbed_official 15:a81a8d6c1dfe 1334
mbed_official 15:a81a8d6c1dfe 1335 /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
mbed_official 15:a81a8d6c1dfe 1336 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1337 typedef union {
mbed_official 15:a81a8d6c1dfe 1338 struct {
mbed_official 15:a81a8d6c1dfe 1339 uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
mbed_official 15:a81a8d6c1dfe 1340 uint16_t :7; /*!< bit: 9..15 Reserved */
mbed_official 15:a81a8d6c1dfe 1341 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1342 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1343 } SERCOM_USART_DATA_Type;
mbed_official 15:a81a8d6c1dfe 1344 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1345
mbed_official 15:a81a8d6c1dfe 1346 #define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */
mbed_official 15:a81a8d6c1dfe 1347 #define SERCOM_USART_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
mbed_official 15:a81a8d6c1dfe 1348
mbed_official 15:a81a8d6c1dfe 1349 #define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
mbed_official 15:a81a8d6c1dfe 1350 #define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos)
mbed_official 15:a81a8d6c1dfe 1351 #define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)))
mbed_official 15:a81a8d6c1dfe 1352 #define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */
mbed_official 15:a81a8d6c1dfe 1353
mbed_official 15:a81a8d6c1dfe 1354 /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
mbed_official 15:a81a8d6c1dfe 1355 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1356 typedef union {
mbed_official 15:a81a8d6c1dfe 1357 struct {
mbed_official 15:a81a8d6c1dfe 1358 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
mbed_official 15:a81a8d6c1dfe 1359 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 1360 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1361 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1362 } SERCOM_I2CM_DBGCTRL_Type;
mbed_official 15:a81a8d6c1dfe 1363 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1364
mbed_official 15:a81a8d6c1dfe 1365 #define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
mbed_official 15:a81a8d6c1dfe 1366 #define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
mbed_official 15:a81a8d6c1dfe 1367
mbed_official 15:a81a8d6c1dfe 1368 #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
mbed_official 15:a81a8d6c1dfe 1369 #define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
mbed_official 15:a81a8d6c1dfe 1370 #define SERCOM_I2CM_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 1371
mbed_official 15:a81a8d6c1dfe 1372 /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
mbed_official 15:a81a8d6c1dfe 1373 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1374 typedef union {
mbed_official 15:a81a8d6c1dfe 1375 struct {
mbed_official 15:a81a8d6c1dfe 1376 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
mbed_official 15:a81a8d6c1dfe 1377 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 1378 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1379 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1380 } SERCOM_SPI_DBGCTRL_Type;
mbed_official 15:a81a8d6c1dfe 1381 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1382
mbed_official 15:a81a8d6c1dfe 1383 #define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
mbed_official 15:a81a8d6c1dfe 1384 #define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
mbed_official 15:a81a8d6c1dfe 1385
mbed_official 15:a81a8d6c1dfe 1386 #define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
mbed_official 15:a81a8d6c1dfe 1387 #define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
mbed_official 15:a81a8d6c1dfe 1388 #define SERCOM_SPI_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 1389
mbed_official 15:a81a8d6c1dfe 1390 /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
mbed_official 15:a81a8d6c1dfe 1391 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1392 typedef union {
mbed_official 15:a81a8d6c1dfe 1393 struct {
mbed_official 15:a81a8d6c1dfe 1394 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
mbed_official 15:a81a8d6c1dfe 1395 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 1396 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 1397 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 1398 } SERCOM_USART_DBGCTRL_Type;
mbed_official 15:a81a8d6c1dfe 1399 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1400
mbed_official 15:a81a8d6c1dfe 1401 #define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
mbed_official 15:a81a8d6c1dfe 1402 #define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
mbed_official 15:a81a8d6c1dfe 1403
mbed_official 15:a81a8d6c1dfe 1404 #define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
mbed_official 15:a81a8d6c1dfe 1405 #define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
mbed_official 15:a81a8d6c1dfe 1406 #define SERCOM_USART_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 1407
mbed_official 15:a81a8d6c1dfe 1408 /** \brief SERCOM_I2CM hardware registers */
mbed_official 15:a81a8d6c1dfe 1409 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1410 typedef struct { /* I2C Master Mode */
mbed_official 15:a81a8d6c1dfe 1411 __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
mbed_official 15:a81a8d6c1dfe 1412 __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
mbed_official 15:a81a8d6c1dfe 1413 RoReg8 Reserved1[0x4];
mbed_official 15:a81a8d6c1dfe 1414 __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
mbed_official 15:a81a8d6c1dfe 1415 RoReg8 Reserved2[0x4];
mbed_official 15:a81a8d6c1dfe 1416 __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 1417 RoReg8 Reserved3[0x1];
mbed_official 15:a81a8d6c1dfe 1418 __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 1419 RoReg8 Reserved4[0x1];
mbed_official 15:a81a8d6c1dfe 1420 __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 1421 RoReg8 Reserved5[0x1];
mbed_official 15:a81a8d6c1dfe 1422 __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
mbed_official 15:a81a8d6c1dfe 1423 __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
mbed_official 15:a81a8d6c1dfe 1424 RoReg8 Reserved6[0x4];
mbed_official 15:a81a8d6c1dfe 1425 __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
mbed_official 15:a81a8d6c1dfe 1426 __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
mbed_official 15:a81a8d6c1dfe 1427 RoReg8 Reserved7[0x7];
mbed_official 15:a81a8d6c1dfe 1428 __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
mbed_official 15:a81a8d6c1dfe 1429 } SercomI2cm;
mbed_official 15:a81a8d6c1dfe 1430 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1431
mbed_official 15:a81a8d6c1dfe 1432 /** \brief SERCOM_I2CS hardware registers */
mbed_official 15:a81a8d6c1dfe 1433 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1434 typedef struct { /* I2C Slave Mode */
mbed_official 15:a81a8d6c1dfe 1435 __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
mbed_official 15:a81a8d6c1dfe 1436 __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
mbed_official 15:a81a8d6c1dfe 1437 RoReg8 Reserved1[0xC];
mbed_official 15:a81a8d6c1dfe 1438 __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 1439 RoReg8 Reserved2[0x1];
mbed_official 15:a81a8d6c1dfe 1440 __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 1441 RoReg8 Reserved3[0x1];
mbed_official 15:a81a8d6c1dfe 1442 __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 1443 RoReg8 Reserved4[0x1];
mbed_official 15:a81a8d6c1dfe 1444 __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
mbed_official 15:a81a8d6c1dfe 1445 __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
mbed_official 15:a81a8d6c1dfe 1446 RoReg8 Reserved5[0x4];
mbed_official 15:a81a8d6c1dfe 1447 __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
mbed_official 15:a81a8d6c1dfe 1448 __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
mbed_official 15:a81a8d6c1dfe 1449 } SercomI2cs;
mbed_official 15:a81a8d6c1dfe 1450 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1451
mbed_official 15:a81a8d6c1dfe 1452 /** \brief SERCOM_SPI hardware registers */
mbed_official 15:a81a8d6c1dfe 1453 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1454 typedef struct { /* SPI Mode */
mbed_official 15:a81a8d6c1dfe 1455 __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
mbed_official 15:a81a8d6c1dfe 1456 __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
mbed_official 15:a81a8d6c1dfe 1457 RoReg8 Reserved1[0x4];
mbed_official 15:a81a8d6c1dfe 1458 __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
mbed_official 15:a81a8d6c1dfe 1459 RoReg8 Reserved2[0x7];
mbed_official 15:a81a8d6c1dfe 1460 __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 1461 RoReg8 Reserved3[0x1];
mbed_official 15:a81a8d6c1dfe 1462 __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 1463 RoReg8 Reserved4[0x1];
mbed_official 15:a81a8d6c1dfe 1464 __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 1465 RoReg8 Reserved5[0x1];
mbed_official 15:a81a8d6c1dfe 1466 __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
mbed_official 15:a81a8d6c1dfe 1467 __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
mbed_official 15:a81a8d6c1dfe 1468 RoReg8 Reserved6[0x4];
mbed_official 15:a81a8d6c1dfe 1469 __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
mbed_official 15:a81a8d6c1dfe 1470 __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
mbed_official 15:a81a8d6c1dfe 1471 RoReg8 Reserved7[0x4];
mbed_official 15:a81a8d6c1dfe 1472 __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
mbed_official 15:a81a8d6c1dfe 1473 } SercomSpi;
mbed_official 15:a81a8d6c1dfe 1474 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1475
mbed_official 15:a81a8d6c1dfe 1476 /** \brief SERCOM_USART hardware registers */
mbed_official 15:a81a8d6c1dfe 1477 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1478 typedef struct { /* USART Mode */
mbed_official 15:a81a8d6c1dfe 1479 __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
mbed_official 15:a81a8d6c1dfe 1480 __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
mbed_official 15:a81a8d6c1dfe 1481 RoReg8 Reserved1[0x4];
mbed_official 15:a81a8d6c1dfe 1482 __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
mbed_official 15:a81a8d6c1dfe 1483 __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
mbed_official 15:a81a8d6c1dfe 1484 RoReg8 Reserved2[0x5];
mbed_official 15:a81a8d6c1dfe 1485 __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 1486 RoReg8 Reserved3[0x1];
mbed_official 15:a81a8d6c1dfe 1487 __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 1488 RoReg8 Reserved4[0x1];
mbed_official 15:a81a8d6c1dfe 1489 __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 1490 RoReg8 Reserved5[0x1];
mbed_official 15:a81a8d6c1dfe 1491 __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
mbed_official 15:a81a8d6c1dfe 1492 __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
mbed_official 15:a81a8d6c1dfe 1493 RoReg8 Reserved6[0x8];
mbed_official 15:a81a8d6c1dfe 1494 __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
mbed_official 15:a81a8d6c1dfe 1495 RoReg8 Reserved7[0x6];
mbed_official 15:a81a8d6c1dfe 1496 __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
mbed_official 15:a81a8d6c1dfe 1497 } SercomUsart;
mbed_official 15:a81a8d6c1dfe 1498 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1499
mbed_official 15:a81a8d6c1dfe 1500 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1501 typedef union {
mbed_official 15:a81a8d6c1dfe 1502 SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
mbed_official 15:a81a8d6c1dfe 1503 SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
mbed_official 15:a81a8d6c1dfe 1504 SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
mbed_official 15:a81a8d6c1dfe 1505 SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
mbed_official 15:a81a8d6c1dfe 1506 } Sercom;
mbed_official 15:a81a8d6c1dfe 1507 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1508
mbed_official 15:a81a8d6c1dfe 1509 /*@}*/
mbed_official 15:a81a8d6c1dfe 1510
mbed_official 15:a81a8d6c1dfe 1511 #endif /* _SAMD21_SERCOM_COMPONENT_ */