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targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h@15:a81a8d6c1dfe, 2015-11-04 (annotated)

Committer:
mbed_official
Date:
Wed Nov 04 16:30:11 2015 +0000
Revision:
15:a81a8d6c1dfe
Synchronized with git revision 46af745ef4405614c3fa49abbd9a706a362ea514



Full URL: https://github.com/mbedmicro/mbed/commit/46af745ef4405614c3fa49abbd9a706a362ea514/



Renamed TARGET_SAM_CortexM0+ to TARGET_SAM_CortexM0P for compatiblity with online compiler

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 15:a81a8d6c1dfe 1 /**
mbed_official 15:a81a8d6c1dfe 2 * \file
mbed_official 15:a81a8d6c1dfe 3 *
mbed_official 15:a81a8d6c1dfe 4 * \brief Component description for RTC
mbed_official 15:a81a8d6c1dfe 5 *
mbed_official 15:a81a8d6c1dfe 6 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
mbed_official 15:a81a8d6c1dfe 7 *
mbed_official 15:a81a8d6c1dfe 8 * \asf_license_start
mbed_official 15:a81a8d6c1dfe 9 *
mbed_official 15:a81a8d6c1dfe 10 * \page License
mbed_official 15:a81a8d6c1dfe 11 *
mbed_official 15:a81a8d6c1dfe 12 * Redistribution and use in source and binary forms, with or without
mbed_official 15:a81a8d6c1dfe 13 * modification, are permitted provided that the following conditions are met:
mbed_official 15:a81a8d6c1dfe 14 *
mbed_official 15:a81a8d6c1dfe 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 15:a81a8d6c1dfe 16 * this list of conditions and the following disclaimer.
mbed_official 15:a81a8d6c1dfe 17 *
mbed_official 15:a81a8d6c1dfe 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 15:a81a8d6c1dfe 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 15:a81a8d6c1dfe 20 * and/or other materials provided with the distribution.
mbed_official 15:a81a8d6c1dfe 21 *
mbed_official 15:a81a8d6c1dfe 22 * 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official 15:a81a8d6c1dfe 23 * from this software without specific prior written permission.
mbed_official 15:a81a8d6c1dfe 24 *
mbed_official 15:a81a8d6c1dfe 25 * 4. This software may only be redistributed and used in connection with an
mbed_official 15:a81a8d6c1dfe 26 * Atmel microcontroller product.
mbed_official 15:a81a8d6c1dfe 27 *
mbed_official 15:a81a8d6c1dfe 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 15:a81a8d6c1dfe 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 15:a81a8d6c1dfe 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official 15:a81a8d6c1dfe 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official 15:a81a8d6c1dfe 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 15:a81a8d6c1dfe 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official 15:a81a8d6c1dfe 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official 15:a81a8d6c1dfe 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official 15:a81a8d6c1dfe 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 15:a81a8d6c1dfe 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 15:a81a8d6c1dfe 38 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 15:a81a8d6c1dfe 39 *
mbed_official 15:a81a8d6c1dfe 40 * \asf_license_stop
mbed_official 15:a81a8d6c1dfe 41 *
mbed_official 15:a81a8d6c1dfe 42 */
mbed_official 15:a81a8d6c1dfe 43 /*
mbed_official 15:a81a8d6c1dfe 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
mbed_official 15:a81a8d6c1dfe 45 */
mbed_official 15:a81a8d6c1dfe 46
mbed_official 15:a81a8d6c1dfe 47 #ifndef _SAMD21_RTC_COMPONENT_
mbed_official 15:a81a8d6c1dfe 48 #define _SAMD21_RTC_COMPONENT_
mbed_official 15:a81a8d6c1dfe 49
mbed_official 15:a81a8d6c1dfe 50 /* ========================================================================== */
mbed_official 15:a81a8d6c1dfe 51 /** SOFTWARE API DEFINITION FOR RTC */
mbed_official 15:a81a8d6c1dfe 52 /* ========================================================================== */
mbed_official 15:a81a8d6c1dfe 53 /** \addtogroup SAMD21_RTC Real-Time Counter */
mbed_official 15:a81a8d6c1dfe 54 /*@{*/
mbed_official 15:a81a8d6c1dfe 55
mbed_official 15:a81a8d6c1dfe 56 #define RTC_U2202
mbed_official 15:a81a8d6c1dfe 57 #define REV_RTC 0x101
mbed_official 15:a81a8d6c1dfe 58
mbed_official 15:a81a8d6c1dfe 59 /* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
mbed_official 15:a81a8d6c1dfe 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 61 typedef union {
mbed_official 15:a81a8d6c1dfe 62 struct {
mbed_official 15:a81a8d6c1dfe 63 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
mbed_official 15:a81a8d6c1dfe 64 uint16_t ENABLE:1; /*!< bit: 1 Enable */
mbed_official 15:a81a8d6c1dfe 65 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
mbed_official 15:a81a8d6c1dfe 66 uint16_t :3; /*!< bit: 4.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 67 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
mbed_official 15:a81a8d6c1dfe 68 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
mbed_official 15:a81a8d6c1dfe 69 uint16_t :4; /*!< bit: 12..15 Reserved */
mbed_official 15:a81a8d6c1dfe 70 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 71 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 72 } RTC_MODE0_CTRL_Type;
mbed_official 15:a81a8d6c1dfe 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 74
mbed_official 15:a81a8d6c1dfe 75 #define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */
mbed_official 15:a81a8d6c1dfe 76 #define RTC_MODE0_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */
mbed_official 15:a81a8d6c1dfe 77
mbed_official 15:a81a8d6c1dfe 78 #define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */
mbed_official 15:a81a8d6c1dfe 79 #define RTC_MODE0_CTRL_SWRST (0x1ul << RTC_MODE0_CTRL_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 80 #define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */
mbed_official 15:a81a8d6c1dfe 81 #define RTC_MODE0_CTRL_ENABLE (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 82 #define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */
mbed_official 15:a81a8d6c1dfe 83 #define RTC_MODE0_CTRL_MODE_Msk (0x3ul << RTC_MODE0_CTRL_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 84 #define RTC_MODE0_CTRL_MODE(value) ((RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos)))
mbed_official 15:a81a8d6c1dfe 85 #define RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
mbed_official 15:a81a8d6c1dfe 86 #define RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
mbed_official 15:a81a8d6c1dfe 87 #define RTC_MODE0_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
mbed_official 15:a81a8d6c1dfe 88 #define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 89 #define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 90 #define RTC_MODE0_CTRL_MODE_CLOCK (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 91 #define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Clear on Match */
mbed_official 15:a81a8d6c1dfe 92 #define RTC_MODE0_CTRL_MATCHCLR (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos)
mbed_official 15:a81a8d6c1dfe 93 #define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */
mbed_official 15:a81a8d6c1dfe 94 #define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 95 #define RTC_MODE0_CTRL_PRESCALER(value) ((RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos)))
mbed_official 15:a81a8d6c1dfe 96 #define RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
mbed_official 15:a81a8d6c1dfe 97 #define RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
mbed_official 15:a81a8d6c1dfe 98 #define RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
mbed_official 15:a81a8d6c1dfe 99 #define RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
mbed_official 15:a81a8d6c1dfe 100 #define RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
mbed_official 15:a81a8d6c1dfe 101 #define RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
mbed_official 15:a81a8d6c1dfe 102 #define RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
mbed_official 15:a81a8d6c1dfe 103 #define RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
mbed_official 15:a81a8d6c1dfe 104 #define RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
mbed_official 15:a81a8d6c1dfe 105 #define RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
mbed_official 15:a81a8d6c1dfe 106 #define RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
mbed_official 15:a81a8d6c1dfe 107 #define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 108 #define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 109 #define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 110 #define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 111 #define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 112 #define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 113 #define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 114 #define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 115 #define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 116 #define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 117 #define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 118 #define RTC_MODE0_CTRL_MASK 0x0F8Ful /**< \brief (RTC_MODE0_CTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 119
mbed_official 15:a81a8d6c1dfe 120 /* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
mbed_official 15:a81a8d6c1dfe 121 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 122 typedef union {
mbed_official 15:a81a8d6c1dfe 123 struct {
mbed_official 15:a81a8d6c1dfe 124 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
mbed_official 15:a81a8d6c1dfe 125 uint16_t ENABLE:1; /*!< bit: 1 Enable */
mbed_official 15:a81a8d6c1dfe 126 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
mbed_official 15:a81a8d6c1dfe 127 uint16_t :4; /*!< bit: 4.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 128 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
mbed_official 15:a81a8d6c1dfe 129 uint16_t :4; /*!< bit: 12..15 Reserved */
mbed_official 15:a81a8d6c1dfe 130 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 131 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 132 } RTC_MODE1_CTRL_Type;
mbed_official 15:a81a8d6c1dfe 133 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 134
mbed_official 15:a81a8d6c1dfe 135 #define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */
mbed_official 15:a81a8d6c1dfe 136 #define RTC_MODE1_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */
mbed_official 15:a81a8d6c1dfe 137
mbed_official 15:a81a8d6c1dfe 138 #define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */
mbed_official 15:a81a8d6c1dfe 139 #define RTC_MODE1_CTRL_SWRST (0x1ul << RTC_MODE1_CTRL_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 140 #define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */
mbed_official 15:a81a8d6c1dfe 141 #define RTC_MODE1_CTRL_ENABLE (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 142 #define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */
mbed_official 15:a81a8d6c1dfe 143 #define RTC_MODE1_CTRL_MODE_Msk (0x3ul << RTC_MODE1_CTRL_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 144 #define RTC_MODE1_CTRL_MODE(value) ((RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos)))
mbed_official 15:a81a8d6c1dfe 145 #define RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
mbed_official 15:a81a8d6c1dfe 146 #define RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
mbed_official 15:a81a8d6c1dfe 147 #define RTC_MODE1_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
mbed_official 15:a81a8d6c1dfe 148 #define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 149 #define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 150 #define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 151 #define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */
mbed_official 15:a81a8d6c1dfe 152 #define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 153 #define RTC_MODE1_CTRL_PRESCALER(value) ((RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos)))
mbed_official 15:a81a8d6c1dfe 154 #define RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
mbed_official 15:a81a8d6c1dfe 155 #define RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
mbed_official 15:a81a8d6c1dfe 156 #define RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
mbed_official 15:a81a8d6c1dfe 157 #define RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
mbed_official 15:a81a8d6c1dfe 158 #define RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
mbed_official 15:a81a8d6c1dfe 159 #define RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
mbed_official 15:a81a8d6c1dfe 160 #define RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
mbed_official 15:a81a8d6c1dfe 161 #define RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
mbed_official 15:a81a8d6c1dfe 162 #define RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
mbed_official 15:a81a8d6c1dfe 163 #define RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
mbed_official 15:a81a8d6c1dfe 164 #define RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
mbed_official 15:a81a8d6c1dfe 165 #define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 166 #define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 167 #define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 168 #define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 169 #define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 170 #define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 171 #define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 172 #define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 173 #define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 174 #define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 175 #define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 176 #define RTC_MODE1_CTRL_MASK 0x0F0Ful /**< \brief (RTC_MODE1_CTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 177
mbed_official 15:a81a8d6c1dfe 178 /* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
mbed_official 15:a81a8d6c1dfe 179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 180 typedef union {
mbed_official 15:a81a8d6c1dfe 181 struct {
mbed_official 15:a81a8d6c1dfe 182 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
mbed_official 15:a81a8d6c1dfe 183 uint16_t ENABLE:1; /*!< bit: 1 Enable */
mbed_official 15:a81a8d6c1dfe 184 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
mbed_official 15:a81a8d6c1dfe 185 uint16_t :2; /*!< bit: 4.. 5 Reserved */
mbed_official 15:a81a8d6c1dfe 186 uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
mbed_official 15:a81a8d6c1dfe 187 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
mbed_official 15:a81a8d6c1dfe 188 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
mbed_official 15:a81a8d6c1dfe 189 uint16_t :4; /*!< bit: 12..15 Reserved */
mbed_official 15:a81a8d6c1dfe 190 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 191 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 192 } RTC_MODE2_CTRL_Type;
mbed_official 15:a81a8d6c1dfe 193 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 194
mbed_official 15:a81a8d6c1dfe 195 #define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */
mbed_official 15:a81a8d6c1dfe 196 #define RTC_MODE2_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */
mbed_official 15:a81a8d6c1dfe 197
mbed_official 15:a81a8d6c1dfe 198 #define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */
mbed_official 15:a81a8d6c1dfe 199 #define RTC_MODE2_CTRL_SWRST (0x1ul << RTC_MODE2_CTRL_SWRST_Pos)
mbed_official 15:a81a8d6c1dfe 200 #define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */
mbed_official 15:a81a8d6c1dfe 201 #define RTC_MODE2_CTRL_ENABLE (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos)
mbed_official 15:a81a8d6c1dfe 202 #define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */
mbed_official 15:a81a8d6c1dfe 203 #define RTC_MODE2_CTRL_MODE_Msk (0x3ul << RTC_MODE2_CTRL_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 204 #define RTC_MODE2_CTRL_MODE(value) ((RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos)))
mbed_official 15:a81a8d6c1dfe 205 #define RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
mbed_official 15:a81a8d6c1dfe 206 #define RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
mbed_official 15:a81a8d6c1dfe 207 #define RTC_MODE2_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
mbed_official 15:a81a8d6c1dfe 208 #define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 209 #define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 210 #define RTC_MODE2_CTRL_MODE_CLOCK (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos)
mbed_official 15:a81a8d6c1dfe 211 #define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */
mbed_official 15:a81a8d6c1dfe 212 #define RTC_MODE2_CTRL_CLKREP (0x1ul << RTC_MODE2_CTRL_CLKREP_Pos)
mbed_official 15:a81a8d6c1dfe 213 #define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Clear on Match */
mbed_official 15:a81a8d6c1dfe 214 #define RTC_MODE2_CTRL_MATCHCLR (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos)
mbed_official 15:a81a8d6c1dfe 215 #define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */
mbed_official 15:a81a8d6c1dfe 216 #define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 217 #define RTC_MODE2_CTRL_PRESCALER(value) ((RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos)))
mbed_official 15:a81a8d6c1dfe 218 #define RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
mbed_official 15:a81a8d6c1dfe 219 #define RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
mbed_official 15:a81a8d6c1dfe 220 #define RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
mbed_official 15:a81a8d6c1dfe 221 #define RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
mbed_official 15:a81a8d6c1dfe 222 #define RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
mbed_official 15:a81a8d6c1dfe 223 #define RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
mbed_official 15:a81a8d6c1dfe 224 #define RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
mbed_official 15:a81a8d6c1dfe 225 #define RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
mbed_official 15:a81a8d6c1dfe 226 #define RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
mbed_official 15:a81a8d6c1dfe 227 #define RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
mbed_official 15:a81a8d6c1dfe 228 #define RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
mbed_official 15:a81a8d6c1dfe 229 #define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 230 #define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 231 #define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 232 #define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 233 #define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 234 #define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 235 #define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 236 #define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 237 #define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 238 #define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 239 #define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
mbed_official 15:a81a8d6c1dfe 240 #define RTC_MODE2_CTRL_MASK 0x0FCFul /**< \brief (RTC_MODE2_CTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 241
mbed_official 15:a81a8d6c1dfe 242 /* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
mbed_official 15:a81a8d6c1dfe 243 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 244 typedef union {
mbed_official 15:a81a8d6c1dfe 245 struct {
mbed_official 15:a81a8d6c1dfe 246 uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
mbed_official 15:a81a8d6c1dfe 247 uint16_t :8; /*!< bit: 6..13 Reserved */
mbed_official 15:a81a8d6c1dfe 248 uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
mbed_official 15:a81a8d6c1dfe 249 uint16_t RREQ:1; /*!< bit: 15 Read Request */
mbed_official 15:a81a8d6c1dfe 250 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 251 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 252 } RTC_READREQ_Type;
mbed_official 15:a81a8d6c1dfe 253 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 254
mbed_official 15:a81a8d6c1dfe 255 #define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request */
mbed_official 15:a81a8d6c1dfe 256 #define RTC_READREQ_RESETVALUE 0x0010ul /**< \brief (RTC_READREQ reset_value) Read Request */
mbed_official 15:a81a8d6c1dfe 257
mbed_official 15:a81a8d6c1dfe 258 #define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */
mbed_official 15:a81a8d6c1dfe 259 #define RTC_READREQ_ADDR_Msk (0x3Ful << RTC_READREQ_ADDR_Pos)
mbed_official 15:a81a8d6c1dfe 260 #define RTC_READREQ_ADDR(value) ((RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos)))
mbed_official 15:a81a8d6c1dfe 261 #define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */
mbed_official 15:a81a8d6c1dfe 262 #define RTC_READREQ_RCONT (0x1ul << RTC_READREQ_RCONT_Pos)
mbed_official 15:a81a8d6c1dfe 263 #define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */
mbed_official 15:a81a8d6c1dfe 264 #define RTC_READREQ_RREQ (0x1ul << RTC_READREQ_RREQ_Pos)
mbed_official 15:a81a8d6c1dfe 265 #define RTC_READREQ_MASK 0xC03Ful /**< \brief (RTC_READREQ) MASK Register */
mbed_official 15:a81a8d6c1dfe 266
mbed_official 15:a81a8d6c1dfe 267 /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
mbed_official 15:a81a8d6c1dfe 268 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 269 typedef union {
mbed_official 15:a81a8d6c1dfe 270 struct {
mbed_official 15:a81a8d6c1dfe 271 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 272 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 273 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 274 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 275 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 276 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 277 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 278 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 279 uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 280 uint16_t :6; /*!< bit: 9..14 Reserved */
mbed_official 15:a81a8d6c1dfe 281 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
mbed_official 15:a81a8d6c1dfe 282 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 283 struct {
mbed_official 15:a81a8d6c1dfe 284 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
mbed_official 15:a81a8d6c1dfe 285 uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
mbed_official 15:a81a8d6c1dfe 286 uint16_t :7; /*!< bit: 9..15 Reserved */
mbed_official 15:a81a8d6c1dfe 287 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 288 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 289 } RTC_MODE0_EVCTRL_Type;
mbed_official 15:a81a8d6c1dfe 290 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 291
mbed_official 15:a81a8d6c1dfe 292 #define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
mbed_official 15:a81a8d6c1dfe 293 #define RTC_MODE0_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
mbed_official 15:a81a8d6c1dfe 294
mbed_official 15:a81a8d6c1dfe 295 #define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 296 #define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos)
mbed_official 15:a81a8d6c1dfe 297 #define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 298 #define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
mbed_official 15:a81a8d6c1dfe 299 #define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 300 #define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos)
mbed_official 15:a81a8d6c1dfe 301 #define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 302 #define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos)
mbed_official 15:a81a8d6c1dfe 303 #define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 304 #define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos)
mbed_official 15:a81a8d6c1dfe 305 #define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 306 #define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos)
mbed_official 15:a81a8d6c1dfe 307 #define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 308 #define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos)
mbed_official 15:a81a8d6c1dfe 309 #define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 310 #define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
mbed_official 15:a81a8d6c1dfe 311 #define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
mbed_official 15:a81a8d6c1dfe 312 #define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos)
mbed_official 15:a81a8d6c1dfe 313 #define RTC_MODE0_EVCTRL_PEREO(value) ((RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos)))
mbed_official 15:a81a8d6c1dfe 314 #define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 315 #define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
mbed_official 15:a81a8d6c1dfe 316 #define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
mbed_official 15:a81a8d6c1dfe 317 #define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos)
mbed_official 15:a81a8d6c1dfe 318 #define RTC_MODE0_EVCTRL_CMPEO(value) ((RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos)))
mbed_official 15:a81a8d6c1dfe 319 #define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
mbed_official 15:a81a8d6c1dfe 320 #define RTC_MODE0_EVCTRL_OVFEO (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos)
mbed_official 15:a81a8d6c1dfe 321 #define RTC_MODE0_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 322
mbed_official 15:a81a8d6c1dfe 323 /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
mbed_official 15:a81a8d6c1dfe 324 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 325 typedef union {
mbed_official 15:a81a8d6c1dfe 326 struct {
mbed_official 15:a81a8d6c1dfe 327 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 328 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 329 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 330 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 331 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 332 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 333 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 334 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 335 uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 336 uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 337 uint16_t :5; /*!< bit: 10..14 Reserved */
mbed_official 15:a81a8d6c1dfe 338 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
mbed_official 15:a81a8d6c1dfe 339 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 340 struct {
mbed_official 15:a81a8d6c1dfe 341 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
mbed_official 15:a81a8d6c1dfe 342 uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
mbed_official 15:a81a8d6c1dfe 343 uint16_t :6; /*!< bit: 10..15 Reserved */
mbed_official 15:a81a8d6c1dfe 344 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 345 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 346 } RTC_MODE1_EVCTRL_Type;
mbed_official 15:a81a8d6c1dfe 347 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 348
mbed_official 15:a81a8d6c1dfe 349 #define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
mbed_official 15:a81a8d6c1dfe 350 #define RTC_MODE1_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
mbed_official 15:a81a8d6c1dfe 351
mbed_official 15:a81a8d6c1dfe 352 #define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 353 #define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos)
mbed_official 15:a81a8d6c1dfe 354 #define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 355 #define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos)
mbed_official 15:a81a8d6c1dfe 356 #define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 357 #define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos)
mbed_official 15:a81a8d6c1dfe 358 #define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 359 #define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos)
mbed_official 15:a81a8d6c1dfe 360 #define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 361 #define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos)
mbed_official 15:a81a8d6c1dfe 362 #define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 363 #define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos)
mbed_official 15:a81a8d6c1dfe 364 #define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 365 #define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos)
mbed_official 15:a81a8d6c1dfe 366 #define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 367 #define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
mbed_official 15:a81a8d6c1dfe 368 #define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
mbed_official 15:a81a8d6c1dfe 369 #define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos)
mbed_official 15:a81a8d6c1dfe 370 #define RTC_MODE1_EVCTRL_PEREO(value) ((RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos)))
mbed_official 15:a81a8d6c1dfe 371 #define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 372 #define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
mbed_official 15:a81a8d6c1dfe 373 #define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 374 #define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
mbed_official 15:a81a8d6c1dfe 375 #define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
mbed_official 15:a81a8d6c1dfe 376 #define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos)
mbed_official 15:a81a8d6c1dfe 377 #define RTC_MODE1_EVCTRL_CMPEO(value) ((RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos)))
mbed_official 15:a81a8d6c1dfe 378 #define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
mbed_official 15:a81a8d6c1dfe 379 #define RTC_MODE1_EVCTRL_OVFEO (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos)
mbed_official 15:a81a8d6c1dfe 380 #define RTC_MODE1_EVCTRL_MASK 0x83FFul /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 381
mbed_official 15:a81a8d6c1dfe 382 /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
mbed_official 15:a81a8d6c1dfe 383 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 384 typedef union {
mbed_official 15:a81a8d6c1dfe 385 struct {
mbed_official 15:a81a8d6c1dfe 386 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 387 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 388 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 389 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 390 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 391 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 392 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 393 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 394 uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 395 uint16_t :6; /*!< bit: 9..14 Reserved */
mbed_official 15:a81a8d6c1dfe 396 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
mbed_official 15:a81a8d6c1dfe 397 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 398 struct {
mbed_official 15:a81a8d6c1dfe 399 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
mbed_official 15:a81a8d6c1dfe 400 uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
mbed_official 15:a81a8d6c1dfe 401 uint16_t :7; /*!< bit: 9..15 Reserved */
mbed_official 15:a81a8d6c1dfe 402 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 403 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 404 } RTC_MODE2_EVCTRL_Type;
mbed_official 15:a81a8d6c1dfe 405 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 406
mbed_official 15:a81a8d6c1dfe 407 #define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
mbed_official 15:a81a8d6c1dfe 408 #define RTC_MODE2_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
mbed_official 15:a81a8d6c1dfe 409
mbed_official 15:a81a8d6c1dfe 410 #define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 411 #define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos)
mbed_official 15:a81a8d6c1dfe 412 #define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 413 #define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos)
mbed_official 15:a81a8d6c1dfe 414 #define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 415 #define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos)
mbed_official 15:a81a8d6c1dfe 416 #define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 417 #define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos)
mbed_official 15:a81a8d6c1dfe 418 #define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 419 #define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos)
mbed_official 15:a81a8d6c1dfe 420 #define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 421 #define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos)
mbed_official 15:a81a8d6c1dfe 422 #define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 423 #define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos)
mbed_official 15:a81a8d6c1dfe 424 #define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 425 #define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
mbed_official 15:a81a8d6c1dfe 426 #define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
mbed_official 15:a81a8d6c1dfe 427 #define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos)
mbed_official 15:a81a8d6c1dfe 428 #define RTC_MODE2_EVCTRL_PEREO(value) ((RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos)))
mbed_official 15:a81a8d6c1dfe 429 #define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
mbed_official 15:a81a8d6c1dfe 430 #define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
mbed_official 15:a81a8d6c1dfe 431 #define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
mbed_official 15:a81a8d6c1dfe 432 #define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos)
mbed_official 15:a81a8d6c1dfe 433 #define RTC_MODE2_EVCTRL_ALARMEO(value) ((RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)))
mbed_official 15:a81a8d6c1dfe 434 #define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
mbed_official 15:a81a8d6c1dfe 435 #define RTC_MODE2_EVCTRL_OVFEO (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos)
mbed_official 15:a81a8d6c1dfe 436 #define RTC_MODE2_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 437
mbed_official 15:a81a8d6c1dfe 438 /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
mbed_official 15:a81a8d6c1dfe 439 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 440 typedef union {
mbed_official 15:a81a8d6c1dfe 441 struct {
mbed_official 15:a81a8d6c1dfe 442 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 443 uint8_t :5; /*!< bit: 1.. 5 Reserved */
mbed_official 15:a81a8d6c1dfe 444 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 445 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 446 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 447 struct {
mbed_official 15:a81a8d6c1dfe 448 uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 449 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 450 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 451 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 452 } RTC_MODE0_INTENCLR_Type;
mbed_official 15:a81a8d6c1dfe 453 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 454
mbed_official 15:a81a8d6c1dfe 455 #define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 456 #define RTC_MODE0_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 457
mbed_official 15:a81a8d6c1dfe 458 #define RTC_MODE0_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 459 #define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
mbed_official 15:a81a8d6c1dfe 460 #define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 461 #define RTC_MODE0_INTENCLR_CMP_Msk (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos)
mbed_official 15:a81a8d6c1dfe 462 #define RTC_MODE0_INTENCLR_CMP(value) ((RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos)))
mbed_official 15:a81a8d6c1dfe 463 #define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 464 #define RTC_MODE0_INTENCLR_SYNCRDY (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
mbed_official 15:a81a8d6c1dfe 465 #define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 466 #define RTC_MODE0_INTENCLR_OVF (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos)
mbed_official 15:a81a8d6c1dfe 467 #define RTC_MODE0_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
mbed_official 15:a81a8d6c1dfe 468
mbed_official 15:a81a8d6c1dfe 469 /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
mbed_official 15:a81a8d6c1dfe 470 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 471 typedef union {
mbed_official 15:a81a8d6c1dfe 472 struct {
mbed_official 15:a81a8d6c1dfe 473 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 474 uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 475 uint8_t :4; /*!< bit: 2.. 5 Reserved */
mbed_official 15:a81a8d6c1dfe 476 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 477 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 478 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 479 struct {
mbed_official 15:a81a8d6c1dfe 480 uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 481 uint8_t :6; /*!< bit: 2.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 482 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 483 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 484 } RTC_MODE1_INTENCLR_Type;
mbed_official 15:a81a8d6c1dfe 485 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 486
mbed_official 15:a81a8d6c1dfe 487 #define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 488 #define RTC_MODE1_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 489
mbed_official 15:a81a8d6c1dfe 490 #define RTC_MODE1_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 491 #define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos)
mbed_official 15:a81a8d6c1dfe 492 #define RTC_MODE1_INTENCLR_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 493 #define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
mbed_official 15:a81a8d6c1dfe 494 #define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 495 #define RTC_MODE1_INTENCLR_CMP_Msk (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos)
mbed_official 15:a81a8d6c1dfe 496 #define RTC_MODE1_INTENCLR_CMP(value) ((RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos)))
mbed_official 15:a81a8d6c1dfe 497 #define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 498 #define RTC_MODE1_INTENCLR_SYNCRDY (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
mbed_official 15:a81a8d6c1dfe 499 #define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 500 #define RTC_MODE1_INTENCLR_OVF (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos)
mbed_official 15:a81a8d6c1dfe 501 #define RTC_MODE1_INTENCLR_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
mbed_official 15:a81a8d6c1dfe 502
mbed_official 15:a81a8d6c1dfe 503 /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
mbed_official 15:a81a8d6c1dfe 504 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 505 typedef union {
mbed_official 15:a81a8d6c1dfe 506 struct {
mbed_official 15:a81a8d6c1dfe 507 uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 508 uint8_t :5; /*!< bit: 1.. 5 Reserved */
mbed_official 15:a81a8d6c1dfe 509 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 510 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 511 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 512 struct {
mbed_official 15:a81a8d6c1dfe 513 uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 514 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 515 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 516 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 517 } RTC_MODE2_INTENCLR_Type;
mbed_official 15:a81a8d6c1dfe 518 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 519
mbed_official 15:a81a8d6c1dfe 520 #define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 521 #define RTC_MODE2_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 522
mbed_official 15:a81a8d6c1dfe 523 #define RTC_MODE2_INTENCLR_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 524 #define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
mbed_official 15:a81a8d6c1dfe 525 #define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 526 #define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos)
mbed_official 15:a81a8d6c1dfe 527 #define RTC_MODE2_INTENCLR_ALARM(value) ((RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos)))
mbed_official 15:a81a8d6c1dfe 528 #define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 529 #define RTC_MODE2_INTENCLR_SYNCRDY (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
mbed_official 15:a81a8d6c1dfe 530 #define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 531 #define RTC_MODE2_INTENCLR_OVF (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos)
mbed_official 15:a81a8d6c1dfe 532 #define RTC_MODE2_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
mbed_official 15:a81a8d6c1dfe 533
mbed_official 15:a81a8d6c1dfe 534 /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
mbed_official 15:a81a8d6c1dfe 535 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 536 typedef union {
mbed_official 15:a81a8d6c1dfe 537 struct {
mbed_official 15:a81a8d6c1dfe 538 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 539 uint8_t :5; /*!< bit: 1.. 5 Reserved */
mbed_official 15:a81a8d6c1dfe 540 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 541 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 542 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 543 struct {
mbed_official 15:a81a8d6c1dfe 544 uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 545 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 546 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 547 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 548 } RTC_MODE0_INTENSET_Type;
mbed_official 15:a81a8d6c1dfe 549 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 550
mbed_official 15:a81a8d6c1dfe 551 #define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 552 #define RTC_MODE0_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 553
mbed_official 15:a81a8d6c1dfe 554 #define RTC_MODE0_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 555 #define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos)
mbed_official 15:a81a8d6c1dfe 556 #define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 557 #define RTC_MODE0_INTENSET_CMP_Msk (0x1ul << RTC_MODE0_INTENSET_CMP_Pos)
mbed_official 15:a81a8d6c1dfe 558 #define RTC_MODE0_INTENSET_CMP(value) ((RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos)))
mbed_official 15:a81a8d6c1dfe 559 #define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 560 #define RTC_MODE0_INTENSET_SYNCRDY (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos)
mbed_official 15:a81a8d6c1dfe 561 #define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 562 #define RTC_MODE0_INTENSET_OVF (0x1ul << RTC_MODE0_INTENSET_OVF_Pos)
mbed_official 15:a81a8d6c1dfe 563 #define RTC_MODE0_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENSET) MASK Register */
mbed_official 15:a81a8d6c1dfe 564
mbed_official 15:a81a8d6c1dfe 565 /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
mbed_official 15:a81a8d6c1dfe 566 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 567 typedef union {
mbed_official 15:a81a8d6c1dfe 568 struct {
mbed_official 15:a81a8d6c1dfe 569 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 570 uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 571 uint8_t :4; /*!< bit: 2.. 5 Reserved */
mbed_official 15:a81a8d6c1dfe 572 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 573 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 574 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 575 struct {
mbed_official 15:a81a8d6c1dfe 576 uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 577 uint8_t :6; /*!< bit: 2.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 578 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 579 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 580 } RTC_MODE1_INTENSET_Type;
mbed_official 15:a81a8d6c1dfe 581 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 582
mbed_official 15:a81a8d6c1dfe 583 #define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 584 #define RTC_MODE1_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 585
mbed_official 15:a81a8d6c1dfe 586 #define RTC_MODE1_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 587 #define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos)
mbed_official 15:a81a8d6c1dfe 588 #define RTC_MODE1_INTENSET_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 589 #define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos)
mbed_official 15:a81a8d6c1dfe 590 #define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 591 #define RTC_MODE1_INTENSET_CMP_Msk (0x3ul << RTC_MODE1_INTENSET_CMP_Pos)
mbed_official 15:a81a8d6c1dfe 592 #define RTC_MODE1_INTENSET_CMP(value) ((RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos)))
mbed_official 15:a81a8d6c1dfe 593 #define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 594 #define RTC_MODE1_INTENSET_SYNCRDY (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos)
mbed_official 15:a81a8d6c1dfe 595 #define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 596 #define RTC_MODE1_INTENSET_OVF (0x1ul << RTC_MODE1_INTENSET_OVF_Pos)
mbed_official 15:a81a8d6c1dfe 597 #define RTC_MODE1_INTENSET_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENSET) MASK Register */
mbed_official 15:a81a8d6c1dfe 598
mbed_official 15:a81a8d6c1dfe 599 /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
mbed_official 15:a81a8d6c1dfe 600 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 601 typedef union {
mbed_official 15:a81a8d6c1dfe 602 struct {
mbed_official 15:a81a8d6c1dfe 603 uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 604 uint8_t :5; /*!< bit: 1.. 5 Reserved */
mbed_official 15:a81a8d6c1dfe 605 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 606 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 607 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 608 struct {
mbed_official 15:a81a8d6c1dfe 609 uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 610 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 611 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 612 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 613 } RTC_MODE2_INTENSET_Type;
mbed_official 15:a81a8d6c1dfe 614 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 615
mbed_official 15:a81a8d6c1dfe 616 #define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 617 #define RTC_MODE2_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 618
mbed_official 15:a81a8d6c1dfe 619 #define RTC_MODE2_INTENSET_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 620 #define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
mbed_official 15:a81a8d6c1dfe 621 #define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 622 #define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos)
mbed_official 15:a81a8d6c1dfe 623 #define RTC_MODE2_INTENSET_ALARM(value) ((RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos)))
mbed_official 15:a81a8d6c1dfe 624 #define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 625 #define RTC_MODE2_INTENSET_SYNCRDY (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos)
mbed_official 15:a81a8d6c1dfe 626 #define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
mbed_official 15:a81a8d6c1dfe 627 #define RTC_MODE2_INTENSET_OVF (0x1ul << RTC_MODE2_INTENSET_OVF_Pos)
mbed_official 15:a81a8d6c1dfe 628 #define RTC_MODE2_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENSET) MASK Register */
mbed_official 15:a81a8d6c1dfe 629
mbed_official 15:a81a8d6c1dfe 630 /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
mbed_official 15:a81a8d6c1dfe 631 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 632 typedef union {
mbed_official 15:a81a8d6c1dfe 633 struct {
mbed_official 15:a81a8d6c1dfe 634 uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
mbed_official 15:a81a8d6c1dfe 635 uint8_t :5; /*!< bit: 1.. 5 Reserved */
mbed_official 15:a81a8d6c1dfe 636 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
mbed_official 15:a81a8d6c1dfe 637 uint8_t OVF:1; /*!< bit: 7 Overflow */
mbed_official 15:a81a8d6c1dfe 638 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 639 struct {
mbed_official 15:a81a8d6c1dfe 640 uint8_t CMP:1; /*!< bit: 0 Compare x */
mbed_official 15:a81a8d6c1dfe 641 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 642 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 643 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 644 } RTC_MODE0_INTFLAG_Type;
mbed_official 15:a81a8d6c1dfe 645 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 646
mbed_official 15:a81a8d6c1dfe 647 #define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 648 #define RTC_MODE0_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 649
mbed_official 15:a81a8d6c1dfe 650 #define RTC_MODE0_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
mbed_official 15:a81a8d6c1dfe 651 #define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
mbed_official 15:a81a8d6c1dfe 652 #define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
mbed_official 15:a81a8d6c1dfe 653 #define RTC_MODE0_INTFLAG_CMP_Msk (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos)
mbed_official 15:a81a8d6c1dfe 654 #define RTC_MODE0_INTFLAG_CMP(value) ((RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos)))
mbed_official 15:a81a8d6c1dfe 655 #define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
mbed_official 15:a81a8d6c1dfe 656 #define RTC_MODE0_INTFLAG_SYNCRDY (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
mbed_official 15:a81a8d6c1dfe 657 #define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
mbed_official 15:a81a8d6c1dfe 658 #define RTC_MODE0_INTFLAG_OVF (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos)
mbed_official 15:a81a8d6c1dfe 659 #define RTC_MODE0_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
mbed_official 15:a81a8d6c1dfe 660
mbed_official 15:a81a8d6c1dfe 661 /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
mbed_official 15:a81a8d6c1dfe 662 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 663 typedef union {
mbed_official 15:a81a8d6c1dfe 664 struct {
mbed_official 15:a81a8d6c1dfe 665 uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
mbed_official 15:a81a8d6c1dfe 666 uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
mbed_official 15:a81a8d6c1dfe 667 uint8_t :4; /*!< bit: 2.. 5 Reserved */
mbed_official 15:a81a8d6c1dfe 668 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
mbed_official 15:a81a8d6c1dfe 669 uint8_t OVF:1; /*!< bit: 7 Overflow */
mbed_official 15:a81a8d6c1dfe 670 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 671 struct {
mbed_official 15:a81a8d6c1dfe 672 uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
mbed_official 15:a81a8d6c1dfe 673 uint8_t :6; /*!< bit: 2.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 674 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 675 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 676 } RTC_MODE1_INTFLAG_Type;
mbed_official 15:a81a8d6c1dfe 677 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 678
mbed_official 15:a81a8d6c1dfe 679 #define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 680 #define RTC_MODE1_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 681
mbed_official 15:a81a8d6c1dfe 682 #define RTC_MODE1_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
mbed_official 15:a81a8d6c1dfe 683 #define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos)
mbed_official 15:a81a8d6c1dfe 684 #define RTC_MODE1_INTFLAG_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
mbed_official 15:a81a8d6c1dfe 685 #define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
mbed_official 15:a81a8d6c1dfe 686 #define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
mbed_official 15:a81a8d6c1dfe 687 #define RTC_MODE1_INTFLAG_CMP_Msk (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos)
mbed_official 15:a81a8d6c1dfe 688 #define RTC_MODE1_INTFLAG_CMP(value) ((RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos)))
mbed_official 15:a81a8d6c1dfe 689 #define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
mbed_official 15:a81a8d6c1dfe 690 #define RTC_MODE1_INTFLAG_SYNCRDY (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
mbed_official 15:a81a8d6c1dfe 691 #define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
mbed_official 15:a81a8d6c1dfe 692 #define RTC_MODE1_INTFLAG_OVF (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos)
mbed_official 15:a81a8d6c1dfe 693 #define RTC_MODE1_INTFLAG_MASK 0xC3ul /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
mbed_official 15:a81a8d6c1dfe 694
mbed_official 15:a81a8d6c1dfe 695 /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
mbed_official 15:a81a8d6c1dfe 696 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 697 typedef union {
mbed_official 15:a81a8d6c1dfe 698 struct {
mbed_official 15:a81a8d6c1dfe 699 uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
mbed_official 15:a81a8d6c1dfe 700 uint8_t :5; /*!< bit: 1.. 5 Reserved */
mbed_official 15:a81a8d6c1dfe 701 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
mbed_official 15:a81a8d6c1dfe 702 uint8_t OVF:1; /*!< bit: 7 Overflow */
mbed_official 15:a81a8d6c1dfe 703 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 704 struct {
mbed_official 15:a81a8d6c1dfe 705 uint8_t ALARM:1; /*!< bit: 0 Alarm x */
mbed_official 15:a81a8d6c1dfe 706 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 707 } vec; /*!< Structure used for vec access */
mbed_official 15:a81a8d6c1dfe 708 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 709 } RTC_MODE2_INTFLAG_Type;
mbed_official 15:a81a8d6c1dfe 710 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 711
mbed_official 15:a81a8d6c1dfe 712 #define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 713 #define RTC_MODE2_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 714
mbed_official 15:a81a8d6c1dfe 715 #define RTC_MODE2_INTFLAG_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
mbed_official 15:a81a8d6c1dfe 716 #define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
mbed_official 15:a81a8d6c1dfe 717 #define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
mbed_official 15:a81a8d6c1dfe 718 #define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos)
mbed_official 15:a81a8d6c1dfe 719 #define RTC_MODE2_INTFLAG_ALARM(value) ((RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos)))
mbed_official 15:a81a8d6c1dfe 720 #define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
mbed_official 15:a81a8d6c1dfe 721 #define RTC_MODE2_INTFLAG_SYNCRDY (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
mbed_official 15:a81a8d6c1dfe 722 #define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
mbed_official 15:a81a8d6c1dfe 723 #define RTC_MODE2_INTFLAG_OVF (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos)
mbed_official 15:a81a8d6c1dfe 724 #define RTC_MODE2_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
mbed_official 15:a81a8d6c1dfe 725
mbed_official 15:a81a8d6c1dfe 726 /* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
mbed_official 15:a81a8d6c1dfe 727 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 728 typedef union {
mbed_official 15:a81a8d6c1dfe 729 struct {
mbed_official 15:a81a8d6c1dfe 730 uint8_t :7; /*!< bit: 0.. 6 Reserved */
mbed_official 15:a81a8d6c1dfe 731 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 732 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 733 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 734 } RTC_STATUS_Type;
mbed_official 15:a81a8d6c1dfe 735 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 736
mbed_official 15:a81a8d6c1dfe 737 #define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status */
mbed_official 15:a81a8d6c1dfe 738 #define RTC_STATUS_RESETVALUE 0x00ul /**< \brief (RTC_STATUS reset_value) Status */
mbed_official 15:a81a8d6c1dfe 739
mbed_official 15:a81a8d6c1dfe 740 #define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy */
mbed_official 15:a81a8d6c1dfe 741 #define RTC_STATUS_SYNCBUSY (0x1ul << RTC_STATUS_SYNCBUSY_Pos)
mbed_official 15:a81a8d6c1dfe 742 #define RTC_STATUS_MASK 0x80ul /**< \brief (RTC_STATUS) MASK Register */
mbed_official 15:a81a8d6c1dfe 743
mbed_official 15:a81a8d6c1dfe 744 /* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
mbed_official 15:a81a8d6c1dfe 745 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 746 typedef union {
mbed_official 15:a81a8d6c1dfe 747 struct {
mbed_official 15:a81a8d6c1dfe 748 uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
mbed_official 15:a81a8d6c1dfe 749 uint8_t :7; /*!< bit: 1.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 750 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 751 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 752 } RTC_DBGCTRL_Type;
mbed_official 15:a81a8d6c1dfe 753 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 754
mbed_official 15:a81a8d6c1dfe 755 #define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Control */
mbed_official 15:a81a8d6c1dfe 756 #define RTC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
mbed_official 15:a81a8d6c1dfe 757
mbed_official 15:a81a8d6c1dfe 758 #define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */
mbed_official 15:a81a8d6c1dfe 759 #define RTC_DBGCTRL_DBGRUN (0x1ul << RTC_DBGCTRL_DBGRUN_Pos)
mbed_official 15:a81a8d6c1dfe 760 #define RTC_DBGCTRL_MASK 0x01ul /**< \brief (RTC_DBGCTRL) MASK Register */
mbed_official 15:a81a8d6c1dfe 761
mbed_official 15:a81a8d6c1dfe 762 /* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
mbed_official 15:a81a8d6c1dfe 763 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 764 typedef union {
mbed_official 15:a81a8d6c1dfe 765 struct {
mbed_official 15:a81a8d6c1dfe 766 uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
mbed_official 15:a81a8d6c1dfe 767 uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
mbed_official 15:a81a8d6c1dfe 768 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 769 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 770 } RTC_FREQCORR_Type;
mbed_official 15:a81a8d6c1dfe 771 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 772
mbed_official 15:a81a8d6c1dfe 773 #define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction */
mbed_official 15:a81a8d6c1dfe 774 #define RTC_FREQCORR_RESETVALUE 0x00ul /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
mbed_official 15:a81a8d6c1dfe 775
mbed_official 15:a81a8d6c1dfe 776 #define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
mbed_official 15:a81a8d6c1dfe 777 #define RTC_FREQCORR_VALUE_Msk (0x7Ful << RTC_FREQCORR_VALUE_Pos)
mbed_official 15:a81a8d6c1dfe 778 #define RTC_FREQCORR_VALUE(value) ((RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos)))
mbed_official 15:a81a8d6c1dfe 779 #define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
mbed_official 15:a81a8d6c1dfe 780 #define RTC_FREQCORR_SIGN (0x1ul << RTC_FREQCORR_SIGN_Pos)
mbed_official 15:a81a8d6c1dfe 781 #define RTC_FREQCORR_MASK 0xFFul /**< \brief (RTC_FREQCORR) MASK Register */
mbed_official 15:a81a8d6c1dfe 782
mbed_official 15:a81a8d6c1dfe 783 /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
mbed_official 15:a81a8d6c1dfe 784 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 785 typedef union {
mbed_official 15:a81a8d6c1dfe 786 struct {
mbed_official 15:a81a8d6c1dfe 787 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
mbed_official 15:a81a8d6c1dfe 788 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 789 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 790 } RTC_MODE0_COUNT_Type;
mbed_official 15:a81a8d6c1dfe 791 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 792
mbed_official 15:a81a8d6c1dfe 793 #define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
mbed_official 15:a81a8d6c1dfe 794 #define RTC_MODE0_COUNT_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
mbed_official 15:a81a8d6c1dfe 795
mbed_official 15:a81a8d6c1dfe 796 #define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
mbed_official 15:a81a8d6c1dfe 797 #define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos)
mbed_official 15:a81a8d6c1dfe 798 #define RTC_MODE0_COUNT_COUNT(value) ((RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos)))
mbed_official 15:a81a8d6c1dfe 799 #define RTC_MODE0_COUNT_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */
mbed_official 15:a81a8d6c1dfe 800
mbed_official 15:a81a8d6c1dfe 801 /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
mbed_official 15:a81a8d6c1dfe 802 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 803 typedef union {
mbed_official 15:a81a8d6c1dfe 804 struct {
mbed_official 15:a81a8d6c1dfe 805 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
mbed_official 15:a81a8d6c1dfe 806 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 807 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 808 } RTC_MODE1_COUNT_Type;
mbed_official 15:a81a8d6c1dfe 809 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 810
mbed_official 15:a81a8d6c1dfe 811 #define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
mbed_official 15:a81a8d6c1dfe 812 #define RTC_MODE1_COUNT_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
mbed_official 15:a81a8d6c1dfe 813
mbed_official 15:a81a8d6c1dfe 814 #define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
mbed_official 15:a81a8d6c1dfe 815 #define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos)
mbed_official 15:a81a8d6c1dfe 816 #define RTC_MODE1_COUNT_COUNT(value) ((RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos)))
mbed_official 15:a81a8d6c1dfe 817 #define RTC_MODE1_COUNT_MASK 0xFFFFul /**< \brief (RTC_MODE1_COUNT) MASK Register */
mbed_official 15:a81a8d6c1dfe 818
mbed_official 15:a81a8d6c1dfe 819 /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
mbed_official 15:a81a8d6c1dfe 820 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 821 typedef union {
mbed_official 15:a81a8d6c1dfe 822 struct {
mbed_official 15:a81a8d6c1dfe 823 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
mbed_official 15:a81a8d6c1dfe 824 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
mbed_official 15:a81a8d6c1dfe 825 uint32_t HOUR:5; /*!< bit: 12..16 Hour */
mbed_official 15:a81a8d6c1dfe 826 uint32_t DAY:5; /*!< bit: 17..21 Day */
mbed_official 15:a81a8d6c1dfe 827 uint32_t MONTH:4; /*!< bit: 22..25 Month */
mbed_official 15:a81a8d6c1dfe 828 uint32_t YEAR:6; /*!< bit: 26..31 Year */
mbed_official 15:a81a8d6c1dfe 829 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 830 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 831 } RTC_MODE2_CLOCK_Type;
mbed_official 15:a81a8d6c1dfe 832 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 833
mbed_official 15:a81a8d6c1dfe 834 #define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
mbed_official 15:a81a8d6c1dfe 835 #define RTC_MODE2_CLOCK_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
mbed_official 15:a81a8d6c1dfe 836
mbed_official 15:a81a8d6c1dfe 837 #define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
mbed_official 15:a81a8d6c1dfe 838 #define RTC_MODE2_CLOCK_SECOND_Msk (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos)
mbed_official 15:a81a8d6c1dfe 839 #define RTC_MODE2_CLOCK_SECOND(value) ((RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos)))
mbed_official 15:a81a8d6c1dfe 840 #define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
mbed_official 15:a81a8d6c1dfe 841 #define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos)
mbed_official 15:a81a8d6c1dfe 842 #define RTC_MODE2_CLOCK_MINUTE(value) ((RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos)))
mbed_official 15:a81a8d6c1dfe 843 #define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
mbed_official 15:a81a8d6c1dfe 844 #define RTC_MODE2_CLOCK_HOUR_Msk (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos)
mbed_official 15:a81a8d6c1dfe 845 #define RTC_MODE2_CLOCK_HOUR(value) ((RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos)))
mbed_official 15:a81a8d6c1dfe 846 #define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10ul /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */
mbed_official 15:a81a8d6c1dfe 847 #define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
mbed_official 15:a81a8d6c1dfe 848 #define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
mbed_official 15:a81a8d6c1dfe 849 #define RTC_MODE2_CLOCK_DAY_Msk (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos)
mbed_official 15:a81a8d6c1dfe 850 #define RTC_MODE2_CLOCK_DAY(value) ((RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos)))
mbed_official 15:a81a8d6c1dfe 851 #define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
mbed_official 15:a81a8d6c1dfe 852 #define RTC_MODE2_CLOCK_MONTH_Msk (0xFul << RTC_MODE2_CLOCK_MONTH_Pos)
mbed_official 15:a81a8d6c1dfe 853 #define RTC_MODE2_CLOCK_MONTH(value) ((RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos)))
mbed_official 15:a81a8d6c1dfe 854 #define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
mbed_official 15:a81a8d6c1dfe 855 #define RTC_MODE2_CLOCK_YEAR_Msk (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos)
mbed_official 15:a81a8d6c1dfe 856 #define RTC_MODE2_CLOCK_YEAR(value) ((RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos)))
mbed_official 15:a81a8d6c1dfe 857 #define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */
mbed_official 15:a81a8d6c1dfe 858
mbed_official 15:a81a8d6c1dfe 859 /* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
mbed_official 15:a81a8d6c1dfe 860 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 861 typedef union {
mbed_official 15:a81a8d6c1dfe 862 struct {
mbed_official 15:a81a8d6c1dfe 863 uint16_t PER:16; /*!< bit: 0..15 Counter Period */
mbed_official 15:a81a8d6c1dfe 864 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 865 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 866 } RTC_MODE1_PER_Type;
mbed_official 15:a81a8d6c1dfe 867 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 868
mbed_official 15:a81a8d6c1dfe 869 #define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
mbed_official 15:a81a8d6c1dfe 870 #define RTC_MODE1_PER_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
mbed_official 15:a81a8d6c1dfe 871
mbed_official 15:a81a8d6c1dfe 872 #define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
mbed_official 15:a81a8d6c1dfe 873 #define RTC_MODE1_PER_PER_Msk (0xFFFFul << RTC_MODE1_PER_PER_Pos)
mbed_official 15:a81a8d6c1dfe 874 #define RTC_MODE1_PER_PER(value) ((RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos)))
mbed_official 15:a81a8d6c1dfe 875 #define RTC_MODE1_PER_MASK 0xFFFFul /**< \brief (RTC_MODE1_PER) MASK Register */
mbed_official 15:a81a8d6c1dfe 876
mbed_official 15:a81a8d6c1dfe 877 /* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
mbed_official 15:a81a8d6c1dfe 878 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 879 typedef union {
mbed_official 15:a81a8d6c1dfe 880 struct {
mbed_official 15:a81a8d6c1dfe 881 uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
mbed_official 15:a81a8d6c1dfe 882 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 883 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 884 } RTC_MODE0_COMP_Type;
mbed_official 15:a81a8d6c1dfe 885 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 886
mbed_official 15:a81a8d6c1dfe 887 #define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
mbed_official 15:a81a8d6c1dfe 888 #define RTC_MODE0_COMP_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
mbed_official 15:a81a8d6c1dfe 889
mbed_official 15:a81a8d6c1dfe 890 #define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
mbed_official 15:a81a8d6c1dfe 891 #define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos)
mbed_official 15:a81a8d6c1dfe 892 #define RTC_MODE0_COMP_COMP(value) ((RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos)))
mbed_official 15:a81a8d6c1dfe 893 #define RTC_MODE0_COMP_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */
mbed_official 15:a81a8d6c1dfe 894
mbed_official 15:a81a8d6c1dfe 895 /* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
mbed_official 15:a81a8d6c1dfe 896 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 897 typedef union {
mbed_official 15:a81a8d6c1dfe 898 struct {
mbed_official 15:a81a8d6c1dfe 899 uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
mbed_official 15:a81a8d6c1dfe 900 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 901 uint16_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 902 } RTC_MODE1_COMP_Type;
mbed_official 15:a81a8d6c1dfe 903 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 904
mbed_official 15:a81a8d6c1dfe 905 #define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
mbed_official 15:a81a8d6c1dfe 906 #define RTC_MODE1_COMP_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
mbed_official 15:a81a8d6c1dfe 907
mbed_official 15:a81a8d6c1dfe 908 #define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
mbed_official 15:a81a8d6c1dfe 909 #define RTC_MODE1_COMP_COMP_Msk (0xFFFFul << RTC_MODE1_COMP_COMP_Pos)
mbed_official 15:a81a8d6c1dfe 910 #define RTC_MODE1_COMP_COMP(value) ((RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos)))
mbed_official 15:a81a8d6c1dfe 911 #define RTC_MODE1_COMP_MASK 0xFFFFul /**< \brief (RTC_MODE1_COMP) MASK Register */
mbed_official 15:a81a8d6c1dfe 912
mbed_official 15:a81a8d6c1dfe 913 /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
mbed_official 15:a81a8d6c1dfe 914 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 915 typedef union {
mbed_official 15:a81a8d6c1dfe 916 struct {
mbed_official 15:a81a8d6c1dfe 917 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
mbed_official 15:a81a8d6c1dfe 918 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
mbed_official 15:a81a8d6c1dfe 919 uint32_t HOUR:5; /*!< bit: 12..16 Hour */
mbed_official 15:a81a8d6c1dfe 920 uint32_t DAY:5; /*!< bit: 17..21 Day */
mbed_official 15:a81a8d6c1dfe 921 uint32_t MONTH:4; /*!< bit: 22..25 Month */
mbed_official 15:a81a8d6c1dfe 922 uint32_t YEAR:6; /*!< bit: 26..31 Year */
mbed_official 15:a81a8d6c1dfe 923 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 924 uint32_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 925 } RTC_MODE2_ALARM_Type;
mbed_official 15:a81a8d6c1dfe 926 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 927
mbed_official 15:a81a8d6c1dfe 928 #define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
mbed_official 15:a81a8d6c1dfe 929 #define RTC_MODE2_ALARM_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
mbed_official 15:a81a8d6c1dfe 930
mbed_official 15:a81a8d6c1dfe 931 #define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
mbed_official 15:a81a8d6c1dfe 932 #define RTC_MODE2_ALARM_SECOND_Msk (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos)
mbed_official 15:a81a8d6c1dfe 933 #define RTC_MODE2_ALARM_SECOND(value) ((RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)))
mbed_official 15:a81a8d6c1dfe 934 #define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
mbed_official 15:a81a8d6c1dfe 935 #define RTC_MODE2_ALARM_MINUTE_Msk (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos)
mbed_official 15:a81a8d6c1dfe 936 #define RTC_MODE2_ALARM_MINUTE(value) ((RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)))
mbed_official 15:a81a8d6c1dfe 937 #define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
mbed_official 15:a81a8d6c1dfe 938 #define RTC_MODE2_ALARM_HOUR_Msk (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos)
mbed_official 15:a81a8d6c1dfe 939 #define RTC_MODE2_ALARM_HOUR(value) ((RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)))
mbed_official 15:a81a8d6c1dfe 940 #define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
mbed_official 15:a81a8d6c1dfe 941 #define RTC_MODE2_ALARM_DAY_Msk (0x1Ful << RTC_MODE2_ALARM_DAY_Pos)
mbed_official 15:a81a8d6c1dfe 942 #define RTC_MODE2_ALARM_DAY(value) ((RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)))
mbed_official 15:a81a8d6c1dfe 943 #define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
mbed_official 15:a81a8d6c1dfe 944 #define RTC_MODE2_ALARM_MONTH_Msk (0xFul << RTC_MODE2_ALARM_MONTH_Pos)
mbed_official 15:a81a8d6c1dfe 945 #define RTC_MODE2_ALARM_MONTH(value) ((RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)))
mbed_official 15:a81a8d6c1dfe 946 #define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
mbed_official 15:a81a8d6c1dfe 947 #define RTC_MODE2_ALARM_YEAR_Msk (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos)
mbed_official 15:a81a8d6c1dfe 948 #define RTC_MODE2_ALARM_YEAR(value) ((RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)))
mbed_official 15:a81a8d6c1dfe 949 #define RTC_MODE2_ALARM_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */
mbed_official 15:a81a8d6c1dfe 950
mbed_official 15:a81a8d6c1dfe 951 /* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
mbed_official 15:a81a8d6c1dfe 952 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 953 typedef union {
mbed_official 15:a81a8d6c1dfe 954 struct {
mbed_official 15:a81a8d6c1dfe 955 uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
mbed_official 15:a81a8d6c1dfe 956 uint8_t :5; /*!< bit: 3.. 7 Reserved */
mbed_official 15:a81a8d6c1dfe 957 } bit; /*!< Structure used for bit access */
mbed_official 15:a81a8d6c1dfe 958 uint8_t reg; /*!< Type used for register access */
mbed_official 15:a81a8d6c1dfe 959 } RTC_MODE2_MASK_Type;
mbed_official 15:a81a8d6c1dfe 960 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 961
mbed_official 15:a81a8d6c1dfe 962 #define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
mbed_official 15:a81a8d6c1dfe 963 #define RTC_MODE2_MASK_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
mbed_official 15:a81a8d6c1dfe 964
mbed_official 15:a81a8d6c1dfe 965 #define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
mbed_official 15:a81a8d6c1dfe 966 #define RTC_MODE2_MASK_SEL_Msk (0x7ul << RTC_MODE2_MASK_SEL_Pos)
mbed_official 15:a81a8d6c1dfe 967 #define RTC_MODE2_MASK_SEL(value) ((RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)))
mbed_official 15:a81a8d6c1dfe 968 #define RTC_MODE2_MASK_SEL_OFF_Val 0x0ul /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
mbed_official 15:a81a8d6c1dfe 969 #define RTC_MODE2_MASK_SEL_SS_Val 0x1ul /**< \brief (RTC_MODE2_MASK) Match seconds only */
mbed_official 15:a81a8d6c1dfe 970 #define RTC_MODE2_MASK_SEL_MMSS_Val 0x2ul /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
mbed_official 15:a81a8d6c1dfe 971 #define RTC_MODE2_MASK_SEL_HHMMSS_Val 0x3ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
mbed_official 15:a81a8d6c1dfe 972 #define RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
mbed_official 15:a81a8d6c1dfe 973 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
mbed_official 15:a81a8d6c1dfe 974 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
mbed_official 15:a81a8d6c1dfe 975 #define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)
mbed_official 15:a81a8d6c1dfe 976 #define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)
mbed_official 15:a81a8d6c1dfe 977 #define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)
mbed_official 15:a81a8d6c1dfe 978 #define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
mbed_official 15:a81a8d6c1dfe 979 #define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
mbed_official 15:a81a8d6c1dfe 980 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
mbed_official 15:a81a8d6c1dfe 981 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
mbed_official 15:a81a8d6c1dfe 982 #define RTC_MODE2_MASK_MASK 0x07ul /**< \brief (RTC_MODE2_MASK) MASK Register */
mbed_official 15:a81a8d6c1dfe 983
mbed_official 15:a81a8d6c1dfe 984 /** \brief RtcMode2Alarm hardware registers */
mbed_official 15:a81a8d6c1dfe 985 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 986 typedef struct {
mbed_official 15:a81a8d6c1dfe 987 __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
mbed_official 15:a81a8d6c1dfe 988 __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
mbed_official 15:a81a8d6c1dfe 989 RoReg8 Reserved1[0x3];
mbed_official 15:a81a8d6c1dfe 990 } RtcMode2Alarm;
mbed_official 15:a81a8d6c1dfe 991 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 992
mbed_official 15:a81a8d6c1dfe 993 /** \brief RTC_MODE0 hardware registers */
mbed_official 15:a81a8d6c1dfe 994 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 995 typedef struct { /* 32-bit Counter with Single 32-bit Compare */
mbed_official 15:a81a8d6c1dfe 996 __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
mbed_official 15:a81a8d6c1dfe 997 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
mbed_official 15:a81a8d6c1dfe 998 __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
mbed_official 15:a81a8d6c1dfe 999 __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 1000 __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 1001 __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 1002 RoReg8 Reserved1[0x1];
mbed_official 15:a81a8d6c1dfe 1003 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
mbed_official 15:a81a8d6c1dfe 1004 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
mbed_official 15:a81a8d6c1dfe 1005 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
mbed_official 15:a81a8d6c1dfe 1006 RoReg8 Reserved2[0x3];
mbed_official 15:a81a8d6c1dfe 1007 __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
mbed_official 15:a81a8d6c1dfe 1008 RoReg8 Reserved3[0x4];
mbed_official 15:a81a8d6c1dfe 1009 __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
mbed_official 15:a81a8d6c1dfe 1010 } RtcMode0;
mbed_official 15:a81a8d6c1dfe 1011 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1012
mbed_official 15:a81a8d6c1dfe 1013 /** \brief RTC_MODE1 hardware registers */
mbed_official 15:a81a8d6c1dfe 1014 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1015 typedef struct { /* 16-bit Counter with Two 16-bit Compares */
mbed_official 15:a81a8d6c1dfe 1016 __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
mbed_official 15:a81a8d6c1dfe 1017 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
mbed_official 15:a81a8d6c1dfe 1018 __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
mbed_official 15:a81a8d6c1dfe 1019 __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 1020 __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 1021 __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 1022 RoReg8 Reserved1[0x1];
mbed_official 15:a81a8d6c1dfe 1023 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
mbed_official 15:a81a8d6c1dfe 1024 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
mbed_official 15:a81a8d6c1dfe 1025 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
mbed_official 15:a81a8d6c1dfe 1026 RoReg8 Reserved2[0x3];
mbed_official 15:a81a8d6c1dfe 1027 __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
mbed_official 15:a81a8d6c1dfe 1028 RoReg8 Reserved3[0x2];
mbed_official 15:a81a8d6c1dfe 1029 __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
mbed_official 15:a81a8d6c1dfe 1030 RoReg8 Reserved4[0x2];
mbed_official 15:a81a8d6c1dfe 1031 __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
mbed_official 15:a81a8d6c1dfe 1032 } RtcMode1;
mbed_official 15:a81a8d6c1dfe 1033 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1034
mbed_official 15:a81a8d6c1dfe 1035 /** \brief RTC_MODE2 hardware registers */
mbed_official 15:a81a8d6c1dfe 1036 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1037 typedef struct { /* Clock/Calendar with Alarm */
mbed_official 15:a81a8d6c1dfe 1038 __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
mbed_official 15:a81a8d6c1dfe 1039 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
mbed_official 15:a81a8d6c1dfe 1040 __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
mbed_official 15:a81a8d6c1dfe 1041 __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
mbed_official 15:a81a8d6c1dfe 1042 __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
mbed_official 15:a81a8d6c1dfe 1043 __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
mbed_official 15:a81a8d6c1dfe 1044 RoReg8 Reserved1[0x1];
mbed_official 15:a81a8d6c1dfe 1045 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
mbed_official 15:a81a8d6c1dfe 1046 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
mbed_official 15:a81a8d6c1dfe 1047 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
mbed_official 15:a81a8d6c1dfe 1048 RoReg8 Reserved2[0x3];
mbed_official 15:a81a8d6c1dfe 1049 __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
mbed_official 15:a81a8d6c1dfe 1050 RoReg8 Reserved3[0x4];
mbed_official 15:a81a8d6c1dfe 1051 RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
mbed_official 15:a81a8d6c1dfe 1052 } RtcMode2;
mbed_official 15:a81a8d6c1dfe 1053 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1054
mbed_official 15:a81a8d6c1dfe 1055 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 15:a81a8d6c1dfe 1056 typedef union {
mbed_official 15:a81a8d6c1dfe 1057 RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
mbed_official 15:a81a8d6c1dfe 1058 RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
mbed_official 15:a81a8d6c1dfe 1059 RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
mbed_official 15:a81a8d6c1dfe 1060 } Rtc;
mbed_official 15:a81a8d6c1dfe 1061 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 15:a81a8d6c1dfe 1062
mbed_official 15:a81a8d6c1dfe 1063 /*@}*/
mbed_official 15:a81a8d6c1dfe 1064
mbed_official 15:a81a8d6c1dfe 1065 #endif /* _SAMD21_RTC_COMPONENT_ */