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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_prs.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 50:a417edff4437
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 2 | * @file efm32hg_prs.h |
| bogdanm | 0:9b334a45a8ff | 3 | * @brief EFM32HG_PRS register and bit field definitions |
| bogdanm | 0:9b334a45a8ff | 4 | * @version 3.20.12 |
| bogdanm | 0:9b334a45a8ff | 5 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 6 | * @section License |
| bogdanm | 0:9b334a45a8ff | 7 | * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * |
| bogdanm | 0:9b334a45a8ff | 10 | * Permission is granted to anyone to use this software for any purpose, |
| bogdanm | 0:9b334a45a8ff | 11 | * including commercial applications, and to alter it and redistribute it |
| bogdanm | 0:9b334a45a8ff | 12 | * freely, subject to the following restrictions: |
| bogdanm | 0:9b334a45a8ff | 13 | * |
| bogdanm | 0:9b334a45a8ff | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| bogdanm | 0:9b334a45a8ff | 15 | * claim that you wrote the original software.@n |
| bogdanm | 0:9b334a45a8ff | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| bogdanm | 0:9b334a45a8ff | 17 | * misrepresented as being the original software.@n |
| bogdanm | 0:9b334a45a8ff | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| bogdanm | 0:9b334a45a8ff | 19 | * |
| bogdanm | 0:9b334a45a8ff | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| bogdanm | 0:9b334a45a8ff | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| bogdanm | 0:9b334a45a8ff | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| bogdanm | 0:9b334a45a8ff | 23 | * kind, including, but not limited to, any implied warranties of |
| bogdanm | 0:9b334a45a8ff | 24 | * merchantability or fitness for any particular purpose or warranties against |
| bogdanm | 0:9b334a45a8ff | 25 | * infringement of any proprietary rights of a third party. |
| bogdanm | 0:9b334a45a8ff | 26 | * |
| bogdanm | 0:9b334a45a8ff | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| bogdanm | 0:9b334a45a8ff | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| bogdanm | 0:9b334a45a8ff | 29 | * any third party, arising from your use of this Software. |
| bogdanm | 0:9b334a45a8ff | 30 | * |
| bogdanm | 0:9b334a45a8ff | 31 | *****************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 32 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 33 | * @defgroup EFM32HG_PRS |
| bogdanm | 0:9b334a45a8ff | 34 | * @{ |
| bogdanm | 0:9b334a45a8ff | 35 | * @brief EFM32HG_PRS Register Declaration |
| bogdanm | 0:9b334a45a8ff | 36 | *****************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 37 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 38 | { |
| bogdanm | 0:9b334a45a8ff | 39 | __IO uint32_t SWPULSE; /**< Software Pulse Register */ |
| bogdanm | 0:9b334a45a8ff | 40 | __IO uint32_t SWLEVEL; /**< Software Level Register */ |
| bogdanm | 0:9b334a45a8ff | 41 | __IO uint32_t ROUTE; /**< I/O Routing Register */ |
| bogdanm | 0:9b334a45a8ff | 42 | |
| bogdanm | 0:9b334a45a8ff | 43 | uint32_t RESERVED0[1]; /**< Reserved registers */ |
| bogdanm | 0:9b334a45a8ff | 44 | PRS_CH_TypeDef CH[6]; /**< Channel registers */ |
| bogdanm | 0:9b334a45a8ff | 45 | |
| bogdanm | 0:9b334a45a8ff | 46 | uint32_t RESERVED1[6]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 47 | __IO uint32_t TRACECTRL; /**< MTB Trace Control Register */ |
| bogdanm | 0:9b334a45a8ff | 48 | } PRS_TypeDef; /** @} */ |
| bogdanm | 0:9b334a45a8ff | 49 | |
| bogdanm | 0:9b334a45a8ff | 50 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 51 | * @defgroup EFM32HG_PRS_BitFields |
| bogdanm | 0:9b334a45a8ff | 52 | * @{ |
| bogdanm | 0:9b334a45a8ff | 53 | *****************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 54 | |
| bogdanm | 0:9b334a45a8ff | 55 | /* Bit fields for PRS SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 56 | #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 57 | #define _PRS_SWPULSE_MASK 0x0000003FUL /**< Mask for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 58 | #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */ |
| bogdanm | 0:9b334a45a8ff | 59 | #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ |
| bogdanm | 0:9b334a45a8ff | 60 | #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ |
| bogdanm | 0:9b334a45a8ff | 61 | #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 62 | #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 63 | #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */ |
| bogdanm | 0:9b334a45a8ff | 64 | #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ |
| bogdanm | 0:9b334a45a8ff | 65 | #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ |
| bogdanm | 0:9b334a45a8ff | 66 | #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 67 | #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 68 | #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */ |
| bogdanm | 0:9b334a45a8ff | 69 | #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ |
| bogdanm | 0:9b334a45a8ff | 70 | #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ |
| bogdanm | 0:9b334a45a8ff | 71 | #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 72 | #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 73 | #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */ |
| bogdanm | 0:9b334a45a8ff | 74 | #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ |
| bogdanm | 0:9b334a45a8ff | 75 | #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ |
| bogdanm | 0:9b334a45a8ff | 76 | #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 77 | #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 78 | #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */ |
| bogdanm | 0:9b334a45a8ff | 79 | #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ |
| bogdanm | 0:9b334a45a8ff | 80 | #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ |
| bogdanm | 0:9b334a45a8ff | 81 | #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 82 | #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 83 | #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */ |
| bogdanm | 0:9b334a45a8ff | 84 | #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ |
| bogdanm | 0:9b334a45a8ff | 85 | #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ |
| bogdanm | 0:9b334a45a8ff | 86 | #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 87 | #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */ |
| bogdanm | 0:9b334a45a8ff | 88 | |
| bogdanm | 0:9b334a45a8ff | 89 | /* Bit fields for PRS SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 90 | #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 91 | #define _PRS_SWLEVEL_MASK 0x0000003FUL /**< Mask for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 92 | #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */ |
| bogdanm | 0:9b334a45a8ff | 93 | #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ |
| bogdanm | 0:9b334a45a8ff | 94 | #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ |
| bogdanm | 0:9b334a45a8ff | 95 | #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 96 | #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 97 | #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */ |
| bogdanm | 0:9b334a45a8ff | 98 | #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ |
| bogdanm | 0:9b334a45a8ff | 99 | #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ |
| bogdanm | 0:9b334a45a8ff | 100 | #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 101 | #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 102 | #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */ |
| bogdanm | 0:9b334a45a8ff | 103 | #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ |
| bogdanm | 0:9b334a45a8ff | 104 | #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ |
| bogdanm | 0:9b334a45a8ff | 105 | #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 106 | #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 107 | #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */ |
| bogdanm | 0:9b334a45a8ff | 108 | #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ |
| bogdanm | 0:9b334a45a8ff | 109 | #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ |
| bogdanm | 0:9b334a45a8ff | 110 | #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 111 | #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 112 | #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */ |
| bogdanm | 0:9b334a45a8ff | 113 | #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ |
| bogdanm | 0:9b334a45a8ff | 114 | #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ |
| bogdanm | 0:9b334a45a8ff | 115 | #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 116 | #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 117 | #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */ |
| bogdanm | 0:9b334a45a8ff | 118 | #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ |
| bogdanm | 0:9b334a45a8ff | 119 | #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ |
| bogdanm | 0:9b334a45a8ff | 120 | #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 121 | #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */ |
| bogdanm | 0:9b334a45a8ff | 122 | |
| bogdanm | 0:9b334a45a8ff | 123 | /* Bit fields for PRS ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 124 | #define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 125 | #define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 126 | #define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */ |
| bogdanm | 0:9b334a45a8ff | 127 | #define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */ |
| bogdanm | 0:9b334a45a8ff | 128 | #define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */ |
| bogdanm | 0:9b334a45a8ff | 129 | #define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 130 | #define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 131 | #define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */ |
| bogdanm | 0:9b334a45a8ff | 132 | #define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */ |
| bogdanm | 0:9b334a45a8ff | 133 | #define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */ |
| bogdanm | 0:9b334a45a8ff | 134 | #define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 135 | #define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 136 | #define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */ |
| bogdanm | 0:9b334a45a8ff | 137 | #define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */ |
| bogdanm | 0:9b334a45a8ff | 138 | #define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */ |
| bogdanm | 0:9b334a45a8ff | 139 | #define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 140 | #define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 141 | #define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */ |
| bogdanm | 0:9b334a45a8ff | 142 | #define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */ |
| bogdanm | 0:9b334a45a8ff | 143 | #define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */ |
| bogdanm | 0:9b334a45a8ff | 144 | #define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 145 | #define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 146 | #define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */ |
| bogdanm | 0:9b334a45a8ff | 147 | #define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */ |
| bogdanm | 0:9b334a45a8ff | 148 | #define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 149 | #define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 150 | #define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 151 | #define _PRS_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 152 | #define _PRS_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 153 | #define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 154 | #define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 155 | #define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 156 | #define PRS_ROUTE_LOCATION_LOC2 (_PRS_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 157 | #define PRS_ROUTE_LOCATION_LOC3 (_PRS_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 158 | |
| bogdanm | 0:9b334a45a8ff | 159 | /* Bit fields for PRS CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 160 | #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 161 | #define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 162 | #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ |
| bogdanm | 0:9b334a45a8ff | 163 | #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ |
| bogdanm | 0:9b334a45a8ff | 164 | #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 165 | #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 166 | #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 167 | #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 168 | #define _PRS_CH_CTRL_SIGSEL_USART1IRTX 0x00000000UL /**< Mode USART1IRTX for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 169 | #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 170 | #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 171 | #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 172 | #define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 173 | #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 174 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 175 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 176 | #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 177 | #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 178 | #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 179 | #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 180 | #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 181 | #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 182 | #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 183 | #define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 184 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 185 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 186 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 187 | #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 188 | #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 189 | #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 190 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 191 | #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 192 | #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 193 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 194 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 195 | #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 196 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 197 | #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 198 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 199 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 200 | #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 201 | #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 202 | #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 203 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 204 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 205 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 206 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 207 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 208 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 209 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 210 | #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 211 | #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 212 | #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 213 | #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 214 | #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 215 | #define PRS_CH_CTRL_SIGSEL_USART1IRTX (_PRS_CH_CTRL_SIGSEL_USART1IRTX << 0) /**< Shifted mode USART1IRTX for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 216 | #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 217 | #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 218 | #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 219 | #define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 220 | #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 221 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 222 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 223 | #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 224 | #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 225 | #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 226 | #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 227 | #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 228 | #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 229 | #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 230 | #define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 231 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 232 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 233 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 234 | #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 235 | #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 236 | #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 237 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 238 | #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 239 | #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 240 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 241 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 242 | #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 243 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 244 | #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 245 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 246 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 247 | #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 248 | #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 249 | #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 250 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 251 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 252 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 253 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 254 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 255 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 256 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 257 | #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 258 | #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */ |
| bogdanm | 0:9b334a45a8ff | 259 | #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */ |
| bogdanm | 0:9b334a45a8ff | 260 | #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 261 | #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 262 | #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 263 | #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 264 | #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 265 | #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 266 | #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 267 | #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 268 | #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 269 | #define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 270 | #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 271 | #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 272 | #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 273 | #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x00000036UL /**< Mode PCNT0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 274 | #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 275 | #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 276 | #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 277 | #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 278 | #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 279 | #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 280 | #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 281 | #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 282 | #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 283 | #define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 284 | #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 285 | #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 286 | #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 287 | #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 16) /**< Shifted mode PCNT0 for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 288 | #define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */ |
| bogdanm | 0:9b334a45a8ff | 289 | #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */ |
| bogdanm | 0:9b334a45a8ff | 290 | #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 291 | #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 292 | #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 293 | #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 294 | #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 295 | #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 296 | #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 297 | #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 298 | #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 299 | #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 300 | #define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */ |
| bogdanm | 0:9b334a45a8ff | 301 | #define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */ |
| bogdanm | 0:9b334a45a8ff | 302 | #define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */ |
| bogdanm | 0:9b334a45a8ff | 303 | #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 304 | #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 305 | |
| bogdanm | 0:9b334a45a8ff | 306 | /* Bit fields for PRS TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 307 | #define _PRS_TRACECTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 308 | #define _PRS_TRACECTRL_MASK 0x00000F0FUL /**< Mask for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 309 | #define PRS_TRACECTRL_TSTARTEN (0x1UL << 0) /**< PRS TSTART Enable */ |
| bogdanm | 0:9b334a45a8ff | 310 | #define _PRS_TRACECTRL_TSTARTEN_SHIFT 0 /**< Shift value for PRS_TSTARTEN */ |
| bogdanm | 0:9b334a45a8ff | 311 | #define _PRS_TRACECTRL_TSTARTEN_MASK 0x1UL /**< Bit mask for PRS_TSTARTEN */ |
| bogdanm | 0:9b334a45a8ff | 312 | #define _PRS_TRACECTRL_TSTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 313 | #define PRS_TRACECTRL_TSTARTEN_DEFAULT (_PRS_TRACECTRL_TSTARTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 314 | #define _PRS_TRACECTRL_TSTART_SHIFT 1 /**< Shift value for PRS_TSTART */ |
| bogdanm | 0:9b334a45a8ff | 315 | #define _PRS_TRACECTRL_TSTART_MASK 0xEUL /**< Bit mask for PRS_TSTART */ |
| bogdanm | 0:9b334a45a8ff | 316 | #define _PRS_TRACECTRL_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 317 | #define _PRS_TRACECTRL_TSTART_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 318 | #define _PRS_TRACECTRL_TSTART_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 319 | #define _PRS_TRACECTRL_TSTART_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 320 | #define _PRS_TRACECTRL_TSTART_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 321 | #define _PRS_TRACECTRL_TSTART_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 322 | #define _PRS_TRACECTRL_TSTART_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 323 | #define PRS_TRACECTRL_TSTART_DEFAULT (_PRS_TRACECTRL_TSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 324 | #define PRS_TRACECTRL_TSTART_PRSCH0 (_PRS_TRACECTRL_TSTART_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 325 | #define PRS_TRACECTRL_TSTART_PRSCH1 (_PRS_TRACECTRL_TSTART_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 326 | #define PRS_TRACECTRL_TSTART_PRSCH2 (_PRS_TRACECTRL_TSTART_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 327 | #define PRS_TRACECTRL_TSTART_PRSCH3 (_PRS_TRACECTRL_TSTART_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 328 | #define PRS_TRACECTRL_TSTART_PRSCH4 (_PRS_TRACECTRL_TSTART_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 329 | #define PRS_TRACECTRL_TSTART_PRSCH5 (_PRS_TRACECTRL_TSTART_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 330 | #define PRS_TRACECTRL_TSTOPEN (0x1UL << 8) /**< PRS TSTOP Enable */ |
| bogdanm | 0:9b334a45a8ff | 331 | #define _PRS_TRACECTRL_TSTOPEN_SHIFT 8 /**< Shift value for PRS_TSTOPEN */ |
| bogdanm | 0:9b334a45a8ff | 332 | #define _PRS_TRACECTRL_TSTOPEN_MASK 0x100UL /**< Bit mask for PRS_TSTOPEN */ |
| bogdanm | 0:9b334a45a8ff | 333 | #define _PRS_TRACECTRL_TSTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 334 | #define PRS_TRACECTRL_TSTOPEN_DEFAULT (_PRS_TRACECTRL_TSTOPEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 335 | #define _PRS_TRACECTRL_TSTOP_SHIFT 9 /**< Shift value for PRS_TSTOP */ |
| bogdanm | 0:9b334a45a8ff | 336 | #define _PRS_TRACECTRL_TSTOP_MASK 0xE00UL /**< Bit mask for PRS_TSTOP */ |
| bogdanm | 0:9b334a45a8ff | 337 | #define _PRS_TRACECTRL_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 338 | #define _PRS_TRACECTRL_TSTOP_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 339 | #define _PRS_TRACECTRL_TSTOP_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 340 | #define _PRS_TRACECTRL_TSTOP_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 341 | #define _PRS_TRACECTRL_TSTOP_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 342 | #define _PRS_TRACECTRL_TSTOP_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 343 | #define _PRS_TRACECTRL_TSTOP_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 344 | #define PRS_TRACECTRL_TSTOP_DEFAULT (_PRS_TRACECTRL_TSTOP_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 345 | #define PRS_TRACECTRL_TSTOP_PRSCH0 (_PRS_TRACECTRL_TSTOP_PRSCH0 << 9) /**< Shifted mode PRSCH0 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 346 | #define PRS_TRACECTRL_TSTOP_PRSCH1 (_PRS_TRACECTRL_TSTOP_PRSCH1 << 9) /**< Shifted mode PRSCH1 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 347 | #define PRS_TRACECTRL_TSTOP_PRSCH2 (_PRS_TRACECTRL_TSTOP_PRSCH2 << 9) /**< Shifted mode PRSCH2 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 348 | #define PRS_TRACECTRL_TSTOP_PRSCH3 (_PRS_TRACECTRL_TSTOP_PRSCH3 << 9) /**< Shifted mode PRSCH3 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 349 | #define PRS_TRACECTRL_TSTOP_PRSCH4 (_PRS_TRACECTRL_TSTOP_PRSCH4 << 9) /**< Shifted mode PRSCH4 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 350 | #define PRS_TRACECTRL_TSTOP_PRSCH5 (_PRS_TRACECTRL_TSTOP_PRSCH5 << 9) /**< Shifted mode PRSCH5 for PRS_TRACECTRL */ |
| bogdanm | 0:9b334a45a8ff | 351 | |
| bogdanm | 0:9b334a45a8ff | 352 | /** @} End of group EFM32HG_PRS */ |
| bogdanm | 0:9b334a45a8ff | 353 | |
| bogdanm | 0:9b334a45a8ff | 354 |