Chau Vo / mbed-dev

mbed library sources. Supersedes mbed-src. RTC working even after reset

Fork of mbed-dev by mbed official

targets/cmsis/core_ca9.h@148:161ebc35dc3a, 2016-09-28 (annotated)

Committer:
olympux
Date:
Wed Sep 28 20:59:47 2016 +0000
Revision:
148:161ebc35dc3a
Parent:
144:ef7eb2e8f9f7 
RTC working

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file core_ca9.h
<> 144:ef7eb2e8f9f7 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
<> 144:ef7eb2e8f9f7 4 * @version
<> 144:ef7eb2e8f9f7 5 * @date 25 March 2013
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * @note
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 ******************************************************************************/
<> 144:ef7eb2e8f9f7 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
<> 144:ef7eb2e8f9f7 11
<> 144:ef7eb2e8f9f7 12 All rights reserved.
<> 144:ef7eb2e8f9f7 13 Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 14 modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 16 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 18 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 19 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 21 to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 22 specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 34 POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #if defined ( __ICCARM__ )
<> 144:ef7eb2e8f9f7 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 144:ef7eb2e8f9f7 40 #endif
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 #ifndef __CORE_CA9_H_GENERIC
<> 144:ef7eb2e8f9f7 47 #define __CORE_CA9_H_GENERIC
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 144:ef7eb2e8f9f7 51 CMSIS violates the following MISRA-C:2004 rules:
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 \li Required Rule 8.5, object/function definition in header file.<br>
<> 144:ef7eb2e8f9f7 54 Function definitions in header files are used to allow 'inlining'.
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 144:ef7eb2e8f9f7 57 Unions are used for effective representation of core registers.
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 144:ef7eb2e8f9f7 60 Function-like macros are used to allow more efficient code.
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /*******************************************************************************
<> 144:ef7eb2e8f9f7 65 * CMSIS definitions
<> 144:ef7eb2e8f9f7 66 ******************************************************************************/
<> 144:ef7eb2e8f9f7 67 /** \ingroup Cortex_A9
<> 144:ef7eb2e8f9f7 68 @{
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /* CMSIS CA9 definitions */
<> 144:ef7eb2e8f9f7 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
<> 144:ef7eb2e8f9f7 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
<> 144:ef7eb2e8f9f7 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
<> 144:ef7eb2e8f9f7 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 144:ef7eb2e8f9f7 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 144:ef7eb2e8f9f7 83 #define __STATIC_INLINE static __inline
<> 144:ef7eb2e8f9f7 84 #define __STATIC_ASM static __asm
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #elif defined ( __ICCARM__ )
<> 144:ef7eb2e8f9f7 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 144:ef7eb2e8f9f7 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 144:ef7eb2e8f9f7 89 #define __STATIC_INLINE static inline
<> 144:ef7eb2e8f9f7 90 #define __STATIC_ASM static __asm
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #include <stdint.h>
<> 144:ef7eb2e8f9f7 93 inline uint32_t __get_PSR(void) {
<> 144:ef7eb2e8f9f7 94 __ASM("mrs r0, cpsr");
<> 144:ef7eb2e8f9f7 95 }
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 #elif defined ( __TMS470__ )
<> 144:ef7eb2e8f9f7 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 144:ef7eb2e8f9f7 99 #define __STATIC_INLINE static inline
<> 144:ef7eb2e8f9f7 100 #define __STATIC_ASM static __asm
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 #elif defined ( __GNUC__ )
<> 144:ef7eb2e8f9f7 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 144:ef7eb2e8f9f7 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 144:ef7eb2e8f9f7 105 #define __STATIC_INLINE static inline
<> 144:ef7eb2e8f9f7 106 #define __STATIC_ASM static __asm
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 #elif defined ( __TASKING__ )
<> 144:ef7eb2e8f9f7 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 144:ef7eb2e8f9f7 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 144:ef7eb2e8f9f7 111 #define __STATIC_INLINE static inline
<> 144:ef7eb2e8f9f7 112 #define __STATIC_ASM static __asm
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 #endif
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 119 #if defined __TARGET_FPU_VFP
<> 144:ef7eb2e8f9f7 120 #if (__FPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 121 #define __FPU_USED 1
<> 144:ef7eb2e8f9f7 122 #else
<> 144:ef7eb2e8f9f7 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 124 #define __FPU_USED 0
<> 144:ef7eb2e8f9f7 125 #endif
<> 144:ef7eb2e8f9f7 126 #else
<> 144:ef7eb2e8f9f7 127 #define __FPU_USED 0
<> 144:ef7eb2e8f9f7 128 #endif
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 #elif defined ( __ICCARM__ )
<> 144:ef7eb2e8f9f7 131 #if defined __ARMVFP__
<> 144:ef7eb2e8f9f7 132 #if (__FPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 133 #define __FPU_USED 1
<> 144:ef7eb2e8f9f7 134 #else
<> 144:ef7eb2e8f9f7 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 136 #define __FPU_USED 0
<> 144:ef7eb2e8f9f7 137 #endif
<> 144:ef7eb2e8f9f7 138 #else
<> 144:ef7eb2e8f9f7 139 #define __FPU_USED 0
<> 144:ef7eb2e8f9f7 140 #endif
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 #elif defined ( __TMS470__ )
<> 144:ef7eb2e8f9f7 143 #if defined __TI_VFP_SUPPORT__
<> 144:ef7eb2e8f9f7 144 #if (__FPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 145 #define __FPU_USED 1
<> 144:ef7eb2e8f9f7 146 #else
<> 144:ef7eb2e8f9f7 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 148 #define __FPU_USED 0
<> 144:ef7eb2e8f9f7 149 #endif
<> 144:ef7eb2e8f9f7 150 #else
<> 144:ef7eb2e8f9f7 151 #define __FPU_USED 0
<> 144:ef7eb2e8f9f7 152 #endif
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 #elif defined ( __GNUC__ )
<> 144:ef7eb2e8f9f7 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 144:ef7eb2e8f9f7 156 #if (__FPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 157 #define __FPU_USED 1
<> 144:ef7eb2e8f9f7 158 #else
<> 144:ef7eb2e8f9f7 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 160 #define __FPU_USED 0
<> 144:ef7eb2e8f9f7 161 #endif
<> 144:ef7eb2e8f9f7 162 #else
<> 144:ef7eb2e8f9f7 163 #define __FPU_USED 0
<> 144:ef7eb2e8f9f7 164 #endif
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 #elif defined ( __TASKING__ )
<> 144:ef7eb2e8f9f7 167 #if defined __FPU_VFP__
<> 144:ef7eb2e8f9f7 168 #if (__FPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 169 #define __FPU_USED 1
<> 144:ef7eb2e8f9f7 170 #else
<> 144:ef7eb2e8f9f7 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 144:ef7eb2e8f9f7 172 #define __FPU_USED 0
<> 144:ef7eb2e8f9f7 173 #endif
<> 144:ef7eb2e8f9f7 174 #else
<> 144:ef7eb2e8f9f7 175 #define __FPU_USED 0
<> 144:ef7eb2e8f9f7 176 #endif
<> 144:ef7eb2e8f9f7 177 #endif
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 #include <stdint.h> /*!< standard types definitions */
<> 144:ef7eb2e8f9f7 180 #include "core_caInstr.h" /*!< Core Instruction Access */
<> 144:ef7eb2e8f9f7 181 #include "core_caFunc.h" /*!< Core Function Access */
<> 144:ef7eb2e8f9f7 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 #endif /* __CORE_CA9_H_GENERIC */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 #ifndef __CMSIS_GENERIC
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 #ifndef __CORE_CA9_H_DEPENDANT
<> 144:ef7eb2e8f9f7 189 #define __CORE_CA9_H_DEPENDANT
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* check device defines and use defaults */
<> 144:ef7eb2e8f9f7 192 #if defined __CHECK_DEVICE_DEFINES
<> 144:ef7eb2e8f9f7 193 #ifndef __CA9_REV
<> 144:ef7eb2e8f9f7 194 #define __CA9_REV 0x0000
<> 144:ef7eb2e8f9f7 195 #warning "__CA9_REV not defined in device header file; using default!"
<> 144:ef7eb2e8f9f7 196 #endif
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 #ifndef __FPU_PRESENT
<> 144:ef7eb2e8f9f7 199 #define __FPU_PRESENT 1
<> 144:ef7eb2e8f9f7 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
<> 144:ef7eb2e8f9f7 201 #endif
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 #ifndef __Vendor_SysTickConfig
<> 144:ef7eb2e8f9f7 204 #define __Vendor_SysTickConfig 1
<> 144:ef7eb2e8f9f7 205 #endif
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 #if __Vendor_SysTickConfig == 0
<> 144:ef7eb2e8f9f7 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
<> 144:ef7eb2e8f9f7 209 #endif
<> 144:ef7eb2e8f9f7 210 #endif
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* IO definitions (access restrictions to peripheral registers) */
<> 144:ef7eb2e8f9f7 213 /**
<> 144:ef7eb2e8f9f7 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 <strong>IO Type Qualifiers</strong> are used
<> 144:ef7eb2e8f9f7 217 \li to specify the access to peripheral variables.
<> 144:ef7eb2e8f9f7 218 \li for automatic generation of peripheral register debug information.
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 221 #define __I volatile /*!< Defines 'read only' permissions */
<> 144:ef7eb2e8f9f7 222 #else
<> 144:ef7eb2e8f9f7 223 #define __I volatile const /*!< Defines 'read only' permissions */
<> 144:ef7eb2e8f9f7 224 #endif
<> 144:ef7eb2e8f9f7 225 #define __O volatile /*!< Defines 'write only' permissions */
<> 144:ef7eb2e8f9f7 226 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /*@} end of group Cortex_A9 */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /*******************************************************************************
<> 144:ef7eb2e8f9f7 232 * Register Abstraction
<> 144:ef7eb2e8f9f7 233 ******************************************************************************/
<> 144:ef7eb2e8f9f7 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 144:ef7eb2e8f9f7 235 \brief Type definitions and defines for Cortex-A processor based devices.
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /** \ingroup CMSIS_core_register
<> 144:ef7eb2e8f9f7 239 \defgroup CMSIS_CORE Status and Control Registers
<> 144:ef7eb2e8f9f7 240 \brief Core Register type definitions.
<> 144:ef7eb2e8f9f7 241 @{
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /** \brief Union type to access the Application Program Status Register (APSR).
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246 typedef union
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 struct
<> 144:ef7eb2e8f9f7 249 {
<> 144:ef7eb2e8f9f7 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
<> 144:ef7eb2e8f9f7 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
<> 144:ef7eb2e8f9f7 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
<> 144:ef7eb2e8f9f7 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 144:ef7eb2e8f9f7 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 144:ef7eb2e8f9f7 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 144:ef7eb2e8f9f7 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 144:ef7eb2e8f9f7 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 144:ef7eb2e8f9f7 258 } b; /*!< Structure used for bit access */
<> 144:ef7eb2e8f9f7 259 uint32_t w; /*!< Type used for word access */
<> 144:ef7eb2e8f9f7 260 } APSR_Type;
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /*@} end of group CMSIS_CORE */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /*@} end of CMSIS_Core_FPUFunctions */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 #endif /* __CORE_CA9_H_GENERIC */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 #endif /* __CMSIS_GENERIC */
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 #endif