Suga koubou / PowerDown-LPC81x

see: http://mbed.org/users/okini3939/notebook/low-power-lpc81x/

system_LPC8xx.c@1:f336c9774f7a, 2013-06-07 (annotated)

Committer:
okini3939
Date:
Fri Jun 07 22:47:35 2013 +0000
Revision:
1:f336c9774f7a
fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
okini3939 1:f336c9774f7a 1 // Updated - Code Red Technologies - 18 March 2013
okini3939 1:f336c9774f7a 2 //
okini3939 1:f336c9774f7a 3 // Defines in system_LPC8xx.c changed so that clock setup is
okini3939 1:f336c9774f7a 4 // done based on IRC rather than XTAL, so as to function with
okini3939 1:f336c9774f7a 5 // LPC800-MAX board as well as LPCXpresso812. SystemCoreClock
okini3939 1:f336c9774f7a 6 // thus now defaults to 12MHz
okini3939 1:f336c9774f7a 7 //
okini3939 1:f336c9774f7a 8 /******************************************************************************
okini3939 1:f336c9774f7a 9 * @file: system_LPC8xx.c
okini3939 1:f336c9774f7a 10 * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
okini3939 1:f336c9774f7a 11 * for the NXP LPC8xx Device Series
okini3939 1:f336c9774f7a 12 * @version: V1.0
okini3939 1:f336c9774f7a 13 * @date: 16. Aug. 2012
okini3939 1:f336c9774f7a 14 *----------------------------------------------------------------------------
okini3939 1:f336c9774f7a 15 *
okini3939 1:f336c9774f7a 16 * Copyright (C) 2012 ARM Limited. All rights reserved.
okini3939 1:f336c9774f7a 17 *
okini3939 1:f336c9774f7a 18 * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
okini3939 1:f336c9774f7a 19 * processor based microcontrollers. This file can be freely distributed
okini3939 1:f336c9774f7a 20 * within development tools that are supporting such ARM based processors.
okini3939 1:f336c9774f7a 21 *
okini3939 1:f336c9774f7a 22 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
okini3939 1:f336c9774f7a 23 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
okini3939 1:f336c9774f7a 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
okini3939 1:f336c9774f7a 25 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
okini3939 1:f336c9774f7a 26 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
okini3939 1:f336c9774f7a 27 *
okini3939 1:f336c9774f7a 28 ******************************************************************************/
okini3939 1:f336c9774f7a 29 #include <stdint.h>
okini3939 1:f336c9774f7a 30 #include "LPC8xx.h"
okini3939 1:f336c9774f7a 31
okini3939 1:f336c9774f7a 32 /*
okini3939 1:f336c9774f7a 33 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
okini3939 1:f336c9774f7a 34 */
okini3939 1:f336c9774f7a 35
okini3939 1:f336c9774f7a 36 /*--------------------- Clock Configuration ----------------------------------
okini3939 1:f336c9774f7a 37 //
okini3939 1:f336c9774f7a 38 // <e> Clock Configuration
okini3939 1:f336c9774f7a 39 // <h> System Oscillator Control Register (SYSOSCCTRL)
okini3939 1:f336c9774f7a 40 // <o1.0> BYPASS: System Oscillator Bypass Enable
okini3939 1:f336c9774f7a 41 // <i> If enabled then PLL input (sys_osc_clk) is fed
okini3939 1:f336c9774f7a 42 // <i> directly from XTALIN and XTALOUT pins.
okini3939 1:f336c9774f7a 43 // <o1.9> FREQRANGE: System Oscillator Frequency Range
okini3939 1:f336c9774f7a 44 // <i> Determines frequency range for Low-power oscillator.
okini3939 1:f336c9774f7a 45 // <0=> 1 - 20 MHz
okini3939 1:f336c9774f7a 46 // <1=> 15 - 25 MHz
okini3939 1:f336c9774f7a 47 // </h>
okini3939 1:f336c9774f7a 48 //
okini3939 1:f336c9774f7a 49 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
okini3939 1:f336c9774f7a 50 // <o2.0..4> DIVSEL: Select Divider for Fclkana
okini3939 1:f336c9774f7a 51 // <i> wdt_osc_clk = Fclkana/ (2 ・ｽ (1 + DIVSEL))
okini3939 1:f336c9774f7a 52 // <0-31>
okini3939 1:f336c9774f7a 53 // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
okini3939 1:f336c9774f7a 54 // <0=> Undefined
okini3939 1:f336c9774f7a 55 // <1=> 0.5 MHz
okini3939 1:f336c9774f7a 56 // <2=> 0.8 MHz
okini3939 1:f336c9774f7a 57 // <3=> 1.1 MHz
okini3939 1:f336c9774f7a 58 // <4=> 1.4 MHz
okini3939 1:f336c9774f7a 59 // <5=> 1.6 MHz
okini3939 1:f336c9774f7a 60 // <6=> 1.8 MHz
okini3939 1:f336c9774f7a 61 // <7=> 2.0 MHz
okini3939 1:f336c9774f7a 62 // <8=> 2.2 MHz
okini3939 1:f336c9774f7a 63 // <9=> 2.4 MHz
okini3939 1:f336c9774f7a 64 // <10=> 2.6 MHz
okini3939 1:f336c9774f7a 65 // <11=> 2.7 MHz
okini3939 1:f336c9774f7a 66 // <12=> 2.9 MHz
okini3939 1:f336c9774f7a 67 // <13=> 3.1 MHz
okini3939 1:f336c9774f7a 68 // <14=> 3.2 MHz
okini3939 1:f336c9774f7a 69 // <15=> 3.4 MHz
okini3939 1:f336c9774f7a 70 // </h>
okini3939 1:f336c9774f7a 71 //
okini3939 1:f336c9774f7a 72 // <h> System PLL Control Register (SYSPLLCTRL)
okini3939 1:f336c9774f7a 73 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
okini3939 1:f336c9774f7a 74 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
okini3939 1:f336c9774f7a 75 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
okini3939 1:f336c9774f7a 76 // <o3.0..4> MSEL: Feedback Divider Selection
okini3939 1:f336c9774f7a 77 // <i> M = MSEL + 1
okini3939 1:f336c9774f7a 78 // <0-31>
okini3939 1:f336c9774f7a 79 // <o3.5..6> PSEL: Post Divider Selection
okini3939 1:f336c9774f7a 80 // <0=> P = 1
okini3939 1:f336c9774f7a 81 // <1=> P = 2
okini3939 1:f336c9774f7a 82 // <2=> P = 4
okini3939 1:f336c9774f7a 83 // <3=> P = 8
okini3939 1:f336c9774f7a 84 // </h>
okini3939 1:f336c9774f7a 85 //
okini3939 1:f336c9774f7a 86 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
okini3939 1:f336c9774f7a 87 // <o4.0..1> SEL: System PLL Clock Source
okini3939 1:f336c9774f7a 88 // <0=> IRC Oscillator
okini3939 1:f336c9774f7a 89 // <1=> System Oscillator
okini3939 1:f336c9774f7a 90 // <2=> Reserved
okini3939 1:f336c9774f7a 91 // <3=> CLKIN pin
okini3939 1:f336c9774f7a 92 // </h>
okini3939 1:f336c9774f7a 93 //
okini3939 1:f336c9774f7a 94 // <h> Main Clock Source Select Register (MAINCLKSEL)
okini3939 1:f336c9774f7a 95 // <o5.0..1> SEL: Clock Source for Main Clock
okini3939 1:f336c9774f7a 96 // <0=> IRC Oscillator
okini3939 1:f336c9774f7a 97 // <1=> Input Clock to System PLL
okini3939 1:f336c9774f7a 98 // <2=> WDT Oscillator
okini3939 1:f336c9774f7a 99 // <3=> System PLL Clock Out
okini3939 1:f336c9774f7a 100 // </h>
okini3939 1:f336c9774f7a 101 //
okini3939 1:f336c9774f7a 102 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
okini3939 1:f336c9774f7a 103 // <o6.0..7> DIV: System AHB Clock Divider
okini3939 1:f336c9774f7a 104 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
okini3939 1:f336c9774f7a 105 // <i> 0 = is disabled
okini3939 1:f336c9774f7a 106 // <0-255>
okini3939 1:f336c9774f7a 107 // </h>
okini3939 1:f336c9774f7a 108 // </e>
okini3939 1:f336c9774f7a 109 */
okini3939 1:f336c9774f7a 110 #define CLOCK_SETUP 0
okini3939 1:f336c9774f7a 111 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
okini3939 1:f336c9774f7a 112 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
okini3939 1:f336c9774f7a 113 #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
okini3939 1:f336c9774f7a 114 #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
okini3939 1:f336c9774f7a 115 #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
okini3939 1:f336c9774f7a 116 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
okini3939 1:f336c9774f7a 117
okini3939 1:f336c9774f7a 118 /*
okini3939 1:f336c9774f7a 119 //-------- <<< end of configuration section >>> ------------------------------
okini3939 1:f336c9774f7a 120 */
okini3939 1:f336c9774f7a 121
okini3939 1:f336c9774f7a 122 /*----------------------------------------------------------------------------
okini3939 1:f336c9774f7a 123 Check the register settings
okini3939 1:f336c9774f7a 124 *----------------------------------------------------------------------------*/
okini3939 1:f336c9774f7a 125 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
okini3939 1:f336c9774f7a 126 #define CHECK_RSVD(val, mask) (val & mask)
okini3939 1:f336c9774f7a 127
okini3939 1:f336c9774f7a 128 /* Clock Configuration -------------------------------------------------------*/
okini3939 1:f336c9774f7a 129 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
okini3939 1:f336c9774f7a 130 #error "SYSOSCCTRL: Invalid values of reserved bits!"
okini3939 1:f336c9774f7a 131 #endif
okini3939 1:f336c9774f7a 132
okini3939 1:f336c9774f7a 133 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
okini3939 1:f336c9774f7a 134 #error "WDTOSCCTRL: Invalid values of reserved bits!"
okini3939 1:f336c9774f7a 135 #endif
okini3939 1:f336c9774f7a 136
okini3939 1:f336c9774f7a 137 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
okini3939 1:f336c9774f7a 138 #error "SYSPLLCLKSEL: Value out of range!"
okini3939 1:f336c9774f7a 139 #endif
okini3939 1:f336c9774f7a 140
okini3939 1:f336c9774f7a 141 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
okini3939 1:f336c9774f7a 142 #error "SYSPLLCTRL: Invalid values of reserved bits!"
okini3939 1:f336c9774f7a 143 #endif
okini3939 1:f336c9774f7a 144
okini3939 1:f336c9774f7a 145 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
okini3939 1:f336c9774f7a 146 #error "MAINCLKSEL: Invalid values of reserved bits!"
okini3939 1:f336c9774f7a 147 #endif
okini3939 1:f336c9774f7a 148
okini3939 1:f336c9774f7a 149 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
okini3939 1:f336c9774f7a 150 #error "SYSAHBCLKDIV: Value out of range!"
okini3939 1:f336c9774f7a 151 #endif
okini3939 1:f336c9774f7a 152
okini3939 1:f336c9774f7a 153
okini3939 1:f336c9774f7a 154 /*----------------------------------------------------------------------------
okini3939 1:f336c9774f7a 155 DEFINES
okini3939 1:f336c9774f7a 156 *----------------------------------------------------------------------------*/
okini3939 1:f336c9774f7a 157
okini3939 1:f336c9774f7a 158 /*----------------------------------------------------------------------------
okini3939 1:f336c9774f7a 159 Define clocks
okini3939 1:f336c9774f7a 160 *----------------------------------------------------------------------------*/
okini3939 1:f336c9774f7a 161 #define __XTAL (12000000UL) /* Oscillator frequency */
okini3939 1:f336c9774f7a 162 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
okini3939 1:f336c9774f7a 163 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
okini3939 1:f336c9774f7a 164 #define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
okini3939 1:f336c9774f7a 165
okini3939 1:f336c9774f7a 166
okini3939 1:f336c9774f7a 167 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
okini3939 1:f336c9774f7a 168 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
okini3939 1:f336c9774f7a 169
okini3939 1:f336c9774f7a 170 #if (CLOCK_SETUP) /* Clock Setup */
okini3939 1:f336c9774f7a 171 #if (__FREQSEL == 0)
okini3939 1:f336c9774f7a 172 #define __WDT_OSC_CLK ( 0) /* undefined */
okini3939 1:f336c9774f7a 173 #elif (__FREQSEL == 1)
okini3939 1:f336c9774f7a 174 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
okini3939 1:f336c9774f7a 175 #elif (__FREQSEL == 2)
okini3939 1:f336c9774f7a 176 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
okini3939 1:f336c9774f7a 177 #elif (__FREQSEL == 3)
okini3939 1:f336c9774f7a 178 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
okini3939 1:f336c9774f7a 179 #elif (__FREQSEL == 4)
okini3939 1:f336c9774f7a 180 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
okini3939 1:f336c9774f7a 181 #elif (__FREQSEL == 5)
okini3939 1:f336c9774f7a 182 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
okini3939 1:f336c9774f7a 183 #elif (__FREQSEL == 6)
okini3939 1:f336c9774f7a 184 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
okini3939 1:f336c9774f7a 185 #elif (__FREQSEL == 7)
okini3939 1:f336c9774f7a 186 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
okini3939 1:f336c9774f7a 187 #elif (__FREQSEL == 8)
okini3939 1:f336c9774f7a 188 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
okini3939 1:f336c9774f7a 189 #elif (__FREQSEL == 9)
okini3939 1:f336c9774f7a 190 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
okini3939 1:f336c9774f7a 191 #elif (__FREQSEL == 10)
okini3939 1:f336c9774f7a 192 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
okini3939 1:f336c9774f7a 193 #elif (__FREQSEL == 11)
okini3939 1:f336c9774f7a 194 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
okini3939 1:f336c9774f7a 195 #elif (__FREQSEL == 12)
okini3939 1:f336c9774f7a 196 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
okini3939 1:f336c9774f7a 197 #elif (__FREQSEL == 13)
okini3939 1:f336c9774f7a 198 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
okini3939 1:f336c9774f7a 199 #elif (__FREQSEL == 14)
okini3939 1:f336c9774f7a 200 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
okini3939 1:f336c9774f7a 201 #else
okini3939 1:f336c9774f7a 202 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
okini3939 1:f336c9774f7a 203 #endif
okini3939 1:f336c9774f7a 204
okini3939 1:f336c9774f7a 205 /* sys_pllclkin calculation */
okini3939 1:f336c9774f7a 206 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
okini3939 1:f336c9774f7a 207 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
okini3939 1:f336c9774f7a 208 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
okini3939 1:f336c9774f7a 209 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
okini3939 1:f336c9774f7a 210 #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
okini3939 1:f336c9774f7a 211 #define __SYS_PLLCLKIN (__CLKIN_CLK)
okini3939 1:f336c9774f7a 212 #else
okini3939 1:f336c9774f7a 213 #define __SYS_PLLCLKIN (0)
okini3939 1:f336c9774f7a 214 #endif
okini3939 1:f336c9774f7a 215
okini3939 1:f336c9774f7a 216 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
okini3939 1:f336c9774f7a 217
okini3939 1:f336c9774f7a 218 /* main clock calculation */
okini3939 1:f336c9774f7a 219 #if ((MAINCLKSEL_Val & 0x03) == 0)
okini3939 1:f336c9774f7a 220 #define __MAIN_CLOCK (__IRC_OSC_CLK)
okini3939 1:f336c9774f7a 221 #elif ((MAINCLKSEL_Val & 0x03) == 1)
okini3939 1:f336c9774f7a 222 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
okini3939 1:f336c9774f7a 223 #elif ((MAINCLKSEL_Val & 0x03) == 2)
okini3939 1:f336c9774f7a 224 #if (__FREQSEL == 0)
okini3939 1:f336c9774f7a 225 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
okini3939 1:f336c9774f7a 226 #else
okini3939 1:f336c9774f7a 227 #define __MAIN_CLOCK (__WDT_OSC_CLK)
okini3939 1:f336c9774f7a 228 #endif
okini3939 1:f336c9774f7a 229 #elif ((MAINCLKSEL_Val & 0x03) == 3)
okini3939 1:f336c9774f7a 230 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
okini3939 1:f336c9774f7a 231 #else
okini3939 1:f336c9774f7a 232 #define __MAIN_CLOCK (0)
okini3939 1:f336c9774f7a 233 #endif
okini3939 1:f336c9774f7a 234
okini3939 1:f336c9774f7a 235 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
okini3939 1:f336c9774f7a 236
okini3939 1:f336c9774f7a 237 #else
okini3939 1:f336c9774f7a 238 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
okini3939 1:f336c9774f7a 239 #endif // CLOCK_SETUP
okini3939 1:f336c9774f7a 240
okini3939 1:f336c9774f7a 241
okini3939 1:f336c9774f7a 242 /*----------------------------------------------------------------------------
okini3939 1:f336c9774f7a 243 Clock Variable definitions
okini3939 1:f336c9774f7a 244 *----------------------------------------------------------------------------*/
okini3939 1:f336c9774f7a 245 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
okini3939 1:f336c9774f7a 246
okini3939 1:f336c9774f7a 247
okini3939 1:f336c9774f7a 248 /*----------------------------------------------------------------------------
okini3939 1:f336c9774f7a 249 Clock functions
okini3939 1:f336c9774f7a 250 *----------------------------------------------------------------------------*/
okini3939 1:f336c9774f7a 251 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
okini3939 1:f336c9774f7a 252 {
okini3939 1:f336c9774f7a 253 uint32_t wdt_osc = 0;
okini3939 1:f336c9774f7a 254
okini3939 1:f336c9774f7a 255 /* Determine clock frequency according to clock register values */
okini3939 1:f336c9774f7a 256 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
okini3939 1:f336c9774f7a 257 case 0: wdt_osc = 0; break;
okini3939 1:f336c9774f7a 258 case 1: wdt_osc = 500000; break;
okini3939 1:f336c9774f7a 259 case 2: wdt_osc = 800000; break;
okini3939 1:f336c9774f7a 260 case 3: wdt_osc = 1100000; break;
okini3939 1:f336c9774f7a 261 case 4: wdt_osc = 1400000; break;
okini3939 1:f336c9774f7a 262 case 5: wdt_osc = 1600000; break;
okini3939 1:f336c9774f7a 263 case 6: wdt_osc = 1800000; break;
okini3939 1:f336c9774f7a 264 case 7: wdt_osc = 2000000; break;
okini3939 1:f336c9774f7a 265 case 8: wdt_osc = 2200000; break;
okini3939 1:f336c9774f7a 266 case 9: wdt_osc = 2400000; break;
okini3939 1:f336c9774f7a 267 case 10: wdt_osc = 2600000; break;
okini3939 1:f336c9774f7a 268 case 11: wdt_osc = 2700000; break;
okini3939 1:f336c9774f7a 269 case 12: wdt_osc = 2900000; break;
okini3939 1:f336c9774f7a 270 case 13: wdt_osc = 3100000; break;
okini3939 1:f336c9774f7a 271 case 14: wdt_osc = 3200000; break;
okini3939 1:f336c9774f7a 272 case 15: wdt_osc = 3400000; break;
okini3939 1:f336c9774f7a 273 }
okini3939 1:f336c9774f7a 274 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
okini3939 1:f336c9774f7a 275
okini3939 1:f336c9774f7a 276 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
okini3939 1:f336c9774f7a 277 case 0: /* Internal RC oscillator */
okini3939 1:f336c9774f7a 278 SystemCoreClock = __IRC_OSC_CLK;
okini3939 1:f336c9774f7a 279 break;
okini3939 1:f336c9774f7a 280 case 1: /* Input Clock to System PLL */
okini3939 1:f336c9774f7a 281 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
okini3939 1:f336c9774f7a 282 case 0: /* Internal RC oscillator */
okini3939 1:f336c9774f7a 283 SystemCoreClock = __IRC_OSC_CLK;
okini3939 1:f336c9774f7a 284 break;
okini3939 1:f336c9774f7a 285 case 1: /* System oscillator */
okini3939 1:f336c9774f7a 286 SystemCoreClock = __SYS_OSC_CLK;
okini3939 1:f336c9774f7a 287 break;
okini3939 1:f336c9774f7a 288 case 2: /* Reserved */
okini3939 1:f336c9774f7a 289 SystemCoreClock = 0;
okini3939 1:f336c9774f7a 290 break;
okini3939 1:f336c9774f7a 291 case 3: /* CLKIN pin */
okini3939 1:f336c9774f7a 292 SystemCoreClock = __CLKIN_CLK;
okini3939 1:f336c9774f7a 293 break;
okini3939 1:f336c9774f7a 294 }
okini3939 1:f336c9774f7a 295 break;
okini3939 1:f336c9774f7a 296 case 2: /* WDT Oscillator */
okini3939 1:f336c9774f7a 297 SystemCoreClock = wdt_osc;
okini3939 1:f336c9774f7a 298 break;
okini3939 1:f336c9774f7a 299 case 3: /* System PLL Clock Out */
okini3939 1:f336c9774f7a 300 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
okini3939 1:f336c9774f7a 301 case 0: /* Internal RC oscillator */
okini3939 1:f336c9774f7a 302 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
okini3939 1:f336c9774f7a 303 break;
okini3939 1:f336c9774f7a 304 case 1: /* System oscillator */
okini3939 1:f336c9774f7a 305 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
okini3939 1:f336c9774f7a 306 break;
okini3939 1:f336c9774f7a 307 case 2: /* Reserved */
okini3939 1:f336c9774f7a 308 SystemCoreClock = 0;
okini3939 1:f336c9774f7a 309 break;
okini3939 1:f336c9774f7a 310 case 3: /* CLKIN pin */
okini3939 1:f336c9774f7a 311 SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
okini3939 1:f336c9774f7a 312 break;
okini3939 1:f336c9774f7a 313 }
okini3939 1:f336c9774f7a 314 break;
okini3939 1:f336c9774f7a 315 }
okini3939 1:f336c9774f7a 316
okini3939 1:f336c9774f7a 317 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
okini3939 1:f336c9774f7a 318
okini3939 1:f336c9774f7a 319 }
okini3939 1:f336c9774f7a 320
okini3939 1:f336c9774f7a 321 /**
okini3939 1:f336c9774f7a 322 * Initialize the system
okini3939 1:f336c9774f7a 323 *
okini3939 1:f336c9774f7a 324 * @param none
okini3939 1:f336c9774f7a 325 * @return none
okini3939 1:f336c9774f7a 326 *
okini3939 1:f336c9774f7a 327 * @brief Setup the microcontroller system.
okini3939 1:f336c9774f7a 328 * Initialize the System.
okini3939 1:f336c9774f7a 329 */
okini3939 1:f336c9774f7a 330 void SystemInit (void) {
okini3939 1:f336c9774f7a 331 volatile uint32_t i;
okini3939 1:f336c9774f7a 332
okini3939 1:f336c9774f7a 333 /* System clock to the IOCON & the SWM need to be enabled or
okini3939 1:f336c9774f7a 334 most of the I/O related peripherals won't work. */
okini3939 1:f336c9774f7a 335 LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
okini3939 1:f336c9774f7a 336
okini3939 1:f336c9774f7a 337 #if (CLOCK_SETUP) /* Clock Setup */
okini3939 1:f336c9774f7a 338
okini3939 1:f336c9774f7a 339 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
okini3939 1:f336c9774f7a 340 LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
okini3939 1:f336c9774f7a 341 LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
okini3939 1:f336c9774f7a 342 LPC_SWM->PINENABLE0 &= ~(0x3 << 4);
okini3939 1:f336c9774f7a 343 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
okini3939 1:f336c9774f7a 344 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
okini3939 1:f336c9774f7a 345 for (i = 0; i < 200; i++) __NOP();
okini3939 1:f336c9774f7a 346 #endif
okini3939 1:f336c9774f7a 347 #if ((SYSPLLCLKSEL_Val & 0x03) == 3)
okini3939 1:f336c9774f7a 348 LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
okini3939 1:f336c9774f7a 349 LPC_SWM->PINENABLE0 &= ~(0x1 << 7);
okini3939 1:f336c9774f7a 350 for (i = 0; i < 200; i++) __NOP();
okini3939 1:f336c9774f7a 351 #endif
okini3939 1:f336c9774f7a 352
okini3939 1:f336c9774f7a 353 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
okini3939 1:f336c9774f7a 354 LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
okini3939 1:f336c9774f7a 355 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
okini3939 1:f336c9774f7a 356 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
okini3939 1:f336c9774f7a 357 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
okini3939 1:f336c9774f7a 358 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
okini3939 1:f336c9774f7a 359 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
okini3939 1:f336c9774f7a 360 #endif
okini3939 1:f336c9774f7a 361
okini3939 1:f336c9774f7a 362 #if (((MAINCLKSEL_Val & 0x03) == 2) )
okini3939 1:f336c9774f7a 363 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
okini3939 1:f336c9774f7a 364 LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
okini3939 1:f336c9774f7a 365 for (i = 0; i < 200; i++) __NOP();
okini3939 1:f336c9774f7a 366 #endif
okini3939 1:f336c9774f7a 367
okini3939 1:f336c9774f7a 368 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
okini3939 1:f336c9774f7a 369 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
okini3939 1:f336c9774f7a 370 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
okini3939 1:f336c9774f7a 371
okini3939 1:f336c9774f7a 372 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
okini3939 1:f336c9774f7a 373 #endif
okini3939 1:f336c9774f7a 374 }