Suga koubou
GPDMA (Direct Memory Access) and LLI (Link List Item) test see: http://mbed.org/users/okini3939/notebook/dma_jp/
MODDMA/iomacros.h@0:de79d4a48e63, 2013-09-13 (annotated)
- Committer:
- okini3939
- Date:
- Fri Sep 13 14:49:52 2013 +0000
- Revision:
- 0:de79d4a48e63
GPDMA (Direct Memory Access) and LLI (Link List Item) test
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| okini3939 | 0:de79d4a48e63 | 1 | /* |
| okini3939 | 0:de79d4a48e63 | 2 | Copyright (c) 2011 Andy Kirkham |
| okini3939 | 0:de79d4a48e63 | 3 | |
| okini3939 | 0:de79d4a48e63 | 4 | Permission is hereby granted, free of charge, to any person obtaining a copy |
| okini3939 | 0:de79d4a48e63 | 5 | of this software and associated documentation files (the "Software"), to deal |
| okini3939 | 0:de79d4a48e63 | 6 | in the Software without restriction, including without limitation the rights |
| okini3939 | 0:de79d4a48e63 | 7 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| okini3939 | 0:de79d4a48e63 | 8 | copies of the Software, and to permit persons to whom the Software is |
| okini3939 | 0:de79d4a48e63 | 9 | furnished to do so, subject to the following conditions: |
| okini3939 | 0:de79d4a48e63 | 10 | |
| okini3939 | 0:de79d4a48e63 | 11 | The above copyright notice and this permission notice shall be included in |
| okini3939 | 0:de79d4a48e63 | 12 | all copies or substantial portions of the Software. |
| okini3939 | 0:de79d4a48e63 | 13 | |
| okini3939 | 0:de79d4a48e63 | 14 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| okini3939 | 0:de79d4a48e63 | 15 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| okini3939 | 0:de79d4a48e63 | 16 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| okini3939 | 0:de79d4a48e63 | 17 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| okini3939 | 0:de79d4a48e63 | 18 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| okini3939 | 0:de79d4a48e63 | 19 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| okini3939 | 0:de79d4a48e63 | 20 | THE SOFTWARE. |
| okini3939 | 0:de79d4a48e63 | 21 | */ |
| okini3939 | 0:de79d4a48e63 | 22 | |
| okini3939 | 0:de79d4a48e63 | 23 | #ifndef IOMACROS_H |
| okini3939 | 0:de79d4a48e63 | 24 | #define IOMACROS_H |
| okini3939 | 0:de79d4a48e63 | 25 | |
| okini3939 | 0:de79d4a48e63 | 26 | #ifndef __LPC17xx_H__ |
| okini3939 | 0:de79d4a48e63 | 27 | #include "LPC17xx.h" |
| okini3939 | 0:de79d4a48e63 | 28 | #endif |
| okini3939 | 0:de79d4a48e63 | 29 | |
| okini3939 | 0:de79d4a48e63 | 30 | #define PIN_PULLUP 0UL |
| okini3939 | 0:de79d4a48e63 | 31 | #define PIN_REPEAT 1UL |
| okini3939 | 0:de79d4a48e63 | 32 | #define PIN_NONE 2UL |
| okini3939 | 0:de79d4a48e63 | 33 | #define PIN_PULLDOWN 3UL |
| okini3939 | 0:de79d4a48e63 | 34 | |
| okini3939 | 0:de79d4a48e63 | 35 | /* p5 is P0.9 */ |
| okini3939 | 0:de79d4a48e63 | 36 | #define p5_SEL_MASK ~(3UL << 18) |
| okini3939 | 0:de79d4a48e63 | 37 | #define p5_SET_MASK (1UL << 9) |
| okini3939 | 0:de79d4a48e63 | 38 | #define p5_CLR_MASK ~(p5_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 39 | #define p5_AS_OUTPUT LPC_PINCON->PINSEL0&=p5_SEL_MASK;LPC_GPIO0->FIODIR|=p5_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 40 | #define p5_AS_INPUT LPC_GPIO0->FIOMASK &= p5_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 41 | #define p5_SET LPC_GPIO0->FIOSET = p5_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 42 | #define p5_CLR LPC_GPIO0->FIOCLR = p5_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 43 | #define p5_IS_SET (bool)(LPC_GPIO0->FIOPIN & p5_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 44 | #define p5_IS_CLR !(p5_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 45 | #define p5_MODE(x) LPC_PINCON->PINMODE0&=p5_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<18) |
| okini3939 | 0:de79d4a48e63 | 46 | |
| okini3939 | 0:de79d4a48e63 | 47 | /* p6 is P0.8 */ |
| okini3939 | 0:de79d4a48e63 | 48 | #define p6_SEL_MASK ~(3UL << 16) |
| okini3939 | 0:de79d4a48e63 | 49 | #define p6_SET_MASK (1UL << 8) |
| okini3939 | 0:de79d4a48e63 | 50 | #define p6_CLR_MASK ~(p6_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 51 | #define p6_AS_OUTPUT LPC_PINCON->PINSEL0&=p6_SEL_MASK;LPC_GPIO0->FIODIR|=p6-SET_MASK |
| okini3939 | 0:de79d4a48e63 | 52 | #define p6_AS_INPUT LPC_GPIO0->FIOMASK &= p6_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 53 | #define p6_SET LPC_GPIO0->FIOSET = p6_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 54 | #define p6_CLR LPC_GPIO0->FIOCLR = p6_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 55 | #define p6_IS_SET (bool)(LPC_GPIO0->FIOPIN & p6_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 56 | #define p6_IS_CLR !(p6_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 57 | #define p6_MODE(x) LPC_PINCON->PINMODE0&=p6_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<16) |
| okini3939 | 0:de79d4a48e63 | 58 | |
| okini3939 | 0:de79d4a48e63 | 59 | /* p7 is P0.7 */ |
| okini3939 | 0:de79d4a48e63 | 60 | #define p7_SEL_MASK ~(3UL << 14) |
| okini3939 | 0:de79d4a48e63 | 61 | #define p7_SET_MASK (1UL << 7) |
| okini3939 | 0:de79d4a48e63 | 62 | #define p7_CLR_MASK ~(p7_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 63 | #define p7_AS_OUTPUT LPC_PINCON->PINSEL0&=p7_SEL_MASK;LPC_GPIO0->FIODIR|=p7_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 64 | #define p7_AS_INPUT LPC_GPIO0->FIOMASK &= p7_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 65 | #define p7_SET LPC_GPIO0->FIOSET = p7_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 66 | #define p7_CLR LPC_GPIO0->FIOCLR = p7_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 67 | #define p7_IS_SET (bool)(LPC_GPIO0->FIOPIN & p7_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 68 | #define p7_IS_CLR !(p7_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 69 | #define p7_MODE(x) LPC_PINCON->PINMODE0&=p7_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<14) |
| okini3939 | 0:de79d4a48e63 | 70 | |
| okini3939 | 0:de79d4a48e63 | 71 | /* p8 is P0.6 */ |
| okini3939 | 0:de79d4a48e63 | 72 | #define p8_SEL_MASK ~(3UL << 12) |
| okini3939 | 0:de79d4a48e63 | 73 | #define p8_SET_MASK (1UL << 6) |
| okini3939 | 0:de79d4a48e63 | 74 | #define p8_CLR_MASK ~(p8_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 75 | #define p8_AS_OUTPUT LPC_PINCON->PINSEL0&=p8_SEL_MASK;LPC_GPIO0->FIODIR|=p8_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 76 | #define p8_AS_INPUT LPC_GPIO0->FIOMASK &= p8_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 77 | #define p8_SET LPC_GPIO0->FIOSET = p8_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 78 | #define p8_CLR LPC_GPIO0->FIOCLR = p8_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 79 | #define p8_IS_SET (bool)(LPC_GPIO0->FIOPIN & p8_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 80 | #define p8_IS_CLR !(p8_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 81 | #define p8_MODE(x) LPC_PINCON->PINMODE0&=p8_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<12) |
| okini3939 | 0:de79d4a48e63 | 82 | |
| okini3939 | 0:de79d4a48e63 | 83 | /* p9 is P0.0 */ |
| okini3939 | 0:de79d4a48e63 | 84 | #define p9_SEL_MASK ~(3UL << 0) |
| okini3939 | 0:de79d4a48e63 | 85 | #define p9_SET_MASK (1UL << 0) |
| okini3939 | 0:de79d4a48e63 | 86 | #define p9_CLR_MASK ~(p9_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 87 | #define p9_AS_OUTPUT LPC_PINCON->PINSEL0&=p9_SEL_MASK;LPC_GPIO0->FIODIR|=p9_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 88 | #define p9_AS_INPUT LPC_GPIO0->FIOMASK &= p9_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 89 | #define p9_SET LPC_GPIO0->FIOSET = p9_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 90 | #define p9_CLR LPC_GPIO0->FIOCLR = p9_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 91 | #define p9_IS_SET (bool)(LPC_GPIO0->FIOPIN & p9_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 92 | #define p9_IS_CLR !(p9_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 93 | #define p9_MODE(x) LPC_PINCON->PINMODE0&=p9_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<0) |
| okini3939 | 0:de79d4a48e63 | 94 | |
| okini3939 | 0:de79d4a48e63 | 95 | /* p10 is P0.1 */ |
| okini3939 | 0:de79d4a48e63 | 96 | #define p10_SEL_MASK ~(3UL << 2) |
| okini3939 | 0:de79d4a48e63 | 97 | #define p10_SET_MASK (1UL << 1) |
| okini3939 | 0:de79d4a48e63 | 98 | #define p10_CLR_MASK ~(p10_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 99 | #define p10_AS_OUTPUT LPC_PINCON->PINSEL0&=p10_SEL_MASK;LPC_GPIO0->FIODIR|=p10_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 100 | #define p10_AS_INPUT LPC_GPIO0->FIOMASK &= p10_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 101 | #define p10_SET LPC_GPIO0->FIOSET = p10_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 102 | #define p10_CLR LPC_GPIO0->FIOCLR = p10_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 103 | #define p10_IS_SET (bool)(LPC_GPIO0->FIOPIN & p10_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 104 | #define p10_IS_CLR !(p10_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 105 | #define p10_MODE(x) LPC_PINCON->PINMODE0&=p10_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<2) |
| okini3939 | 0:de79d4a48e63 | 106 | |
| okini3939 | 0:de79d4a48e63 | 107 | /* p11 is P0.18 */ |
| okini3939 | 0:de79d4a48e63 | 108 | #define p11_SEL_MASK ~(3UL << 4) |
| okini3939 | 0:de79d4a48e63 | 109 | #define p11_SET_MASK (1UL << 18) |
| okini3939 | 0:de79d4a48e63 | 110 | #define p11_CLR_MASK ~(p11_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 111 | #define p11_AS_OUTPUT LPC_PINCON->PINSEL1&=p11_SEL_MASK;LPC_GPIO0->FIODIR|=p11_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 112 | #define p11_AS_INPUT LPC_GPIO0->FIOMASK &= p11_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 113 | #define p11_SET LPC_GPIO0->FIOSET = p11_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 114 | #define p11_CLR LPC_GPIO0->FIOCLR = p11_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 115 | #define p11_IS_SET (bool)(LPC_GPIO0->FIOPIN & p11_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 116 | #define p11_IS_CLR !(p11_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 117 | #define p11_MODE(x) LPC_PINCON->PINMODE1&=p11_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<4) |
| okini3939 | 0:de79d4a48e63 | 118 | |
| okini3939 | 0:de79d4a48e63 | 119 | /* p12 is P0.17 */ |
| okini3939 | 0:de79d4a48e63 | 120 | #define p12_SEL_MASK ~(3UL << 2) |
| okini3939 | 0:de79d4a48e63 | 121 | #define p12_SET_MASK (1UL << 17) |
| okini3939 | 0:de79d4a48e63 | 122 | #define p12_CLR_MASK ~(p12_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 123 | #define p12_AS_OUTPUT LPC_PINCON->PINSEL1&=p12_SEL_MASK;LPC_GPIO0->FIODIR|=p12_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 124 | #define p12_AS_INPUT LPC_GPIO0->FIOMASK &= p12_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 125 | #define p12_SET LPC_GPIO0->FIOSET = p12_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 126 | #define p12_CLR LPC_GPIO0->FIOCLR = p12_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 127 | #define p12_IS_SET (bool)(LPC_GPIO0->FIOPIN & p12_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 128 | #define p12_IS_CLR !(p12_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 129 | #define p12_MODE(x) LPC_PINCON->PINMODE1&=p12_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<2) |
| okini3939 | 0:de79d4a48e63 | 130 | |
| okini3939 | 0:de79d4a48e63 | 131 | /* p13 is P0.15 */ |
| okini3939 | 0:de79d4a48e63 | 132 | #define p13_SEL_MASK ~(3UL << 30) |
| okini3939 | 0:de79d4a48e63 | 133 | #define p13_SET_MASK (1UL << 15) |
| okini3939 | 0:de79d4a48e63 | 134 | #define p13_CLR_MASK ~(p13_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 135 | #define p13_AS_OUTPUT LPC_PINCON->PINSEL0&=p13_SEL_MASK;LPC_GPIO0->FIODIR|=p13_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 136 | #define p13_AS_INPUT LPC_GPIO0->FIOMASK &= p13_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 137 | #define p13_SET LPC_GPIO0->FIOSET = p13_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 138 | #define p13_CLR LPC_GPIO0->FIOCLR = p13_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 139 | #define p13_IS_SET (bool)(LPC_GPIO0->FIOPIN & p13_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 140 | #define p13_IS_CLR !(p13_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 141 | #define p13_MODE(x) LPC_PINCON->PINMODE0&=p13_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<30) |
| okini3939 | 0:de79d4a48e63 | 142 | |
| okini3939 | 0:de79d4a48e63 | 143 | /* p14 is P0.16 */ |
| okini3939 | 0:de79d4a48e63 | 144 | #define p14_SEL_MASK ~(3UL << 0) |
| okini3939 | 0:de79d4a48e63 | 145 | #define p14_SET_MASK (1UL << 16) |
| okini3939 | 0:de79d4a48e63 | 146 | #define p14_CLR_MASK ~(p14_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 147 | #define p14_AS_OUTPUT LPC_PINCON->PINSEL1&=p14_SEL_MASK;LPC_GPIO0->FIODIR|=p14_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 148 | #define p14_AS_INPUT LPC_GPIO0->FIOMASK &= p14_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 149 | #define p14_SET LPC_GPIO0->FIOSET = p14_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 150 | #define p14_CLR LPC_GPIO0->FIOCLR = p14_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 151 | #define p14_IS_SET (bool)(LPC_GPIO0->FIOPIN & p14_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 152 | #define p14_IS_CLR !(p14_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 153 | #define p14_MODE(x) LPC_PINCON->PINMODE1&=p14_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<0) |
| okini3939 | 0:de79d4a48e63 | 154 | |
| okini3939 | 0:de79d4a48e63 | 155 | /* p15 is P0.23 */ |
| okini3939 | 0:de79d4a48e63 | 156 | #define p15_SEL_MASK ~(3UL << 14) |
| okini3939 | 0:de79d4a48e63 | 157 | #define p15_SET_MASK (1UL << 23) |
| okini3939 | 0:de79d4a48e63 | 158 | #define p15_CLR_MASK ~(p15_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 159 | #define p15_AS_OUTPUT LPC_PINCON->PINSEL1&=p15_SEL_MASK;LPC_GPIO0->FIODIR|=p15_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 160 | #define p15_AS_INPUT LPC_GPIO0->FIOMASK &= p15_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 161 | #define p15_SET LPC_GPIO0->FIOSET = p15_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 162 | #define p15_CLR LPC_GPIO0->FIOCLR = p15_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 163 | #define p15_IS_SET (bool)(LPC_GPIO0->FIOPIN & p15_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 164 | #define p15_IS_CLR !(p15_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 165 | #define p15_MODE(x) LPC_PINCON->PINMODE1&=p15_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<14) |
| okini3939 | 0:de79d4a48e63 | 166 | |
| okini3939 | 0:de79d4a48e63 | 167 | /* p16 is P0.24 */ |
| okini3939 | 0:de79d4a48e63 | 168 | #define p16_SEL_MASK ~(3UL << 16) |
| okini3939 | 0:de79d4a48e63 | 169 | #define p16_SET_MASK (1UL << 24) |
| okini3939 | 0:de79d4a48e63 | 170 | #define p16_CLR_MASK ~(p16_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 171 | #define p16_AS_OUTPUT LPC_PINCON->PINSEL1&=p16_SEL_MASK;LPC_GPIO0->FIODIR|=p16_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 172 | #define p16_AS_INPUT LPC_GPIO0->FIOMASK &= p16_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 173 | #define p16_SET LPC_GPIO0->FIOSET = p16_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 174 | #define p16_CLR LPC_GPIO0->FIOCLR = p16_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 175 | #define p16_IS_SET (bool)(LPC_GPIO0->FIOPIN & p16_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 176 | #define p16_IS_CLR !(p16_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 177 | #define p16_MODE(x) LPC_PINCON->PINMODE1&=p16_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<16) |
| okini3939 | 0:de79d4a48e63 | 178 | |
| okini3939 | 0:de79d4a48e63 | 179 | /* p17 is P0.25 */ |
| okini3939 | 0:de79d4a48e63 | 180 | #define p17_SEL_MASK ~(3UL << 18) |
| okini3939 | 0:de79d4a48e63 | 181 | #define p17_SET_MASK (1UL << 25) |
| okini3939 | 0:de79d4a48e63 | 182 | #define p17_CLR_MASK ~(p17_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 183 | #define p17_AS_OUTPUT LPC_PINCON->PINSEL1&=p17_SEL_MASK;LPC_GPIO0->FIODIR|=p17_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 184 | #define p17_AS_INPUT LPC_GPIO0->FIOMASK &= p17_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 185 | #define p17_SET LPC_GPIO0->FIOSET = p17_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 186 | #define p17_CLR LPC_GPIO0->FIOCLR = p17_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 187 | #define p17_IS_SET (bool)(LPC_GPIO0->FIOPIN & p17_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 188 | #define p17_IS_CLR !(p17_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 189 | #define p17_MODE(x) LPC_PINCON->PINMODE1&=p17_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<18) |
| okini3939 | 0:de79d4a48e63 | 190 | |
| okini3939 | 0:de79d4a48e63 | 191 | /* p18 is P0.26 */ |
| okini3939 | 0:de79d4a48e63 | 192 | #define p18_SEL_MASK ~(3UL << 20) |
| okini3939 | 0:de79d4a48e63 | 193 | #define p18_SET_MASK (1UL << 26) |
| okini3939 | 0:de79d4a48e63 | 194 | #define p18_CLR_MASK ~(p18_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 195 | #define p18_AS_OUTPUT LPC_PINCON->PINSEL1&=p18_SEL_MASK;LPC_GPIO0->FIODIR|=p18_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 196 | #define p18_AS_INPUT LPC_GPIO0->FIOMASK &= p18_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 197 | #define p18_SET LPC_GPIO0->FIOSET = p18_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 198 | #define p18_CLR LPC_GPIO0->FIOCLR = p18_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 199 | #define p18_IS_SET (bool)(LPC_GPIO0->FIOPIN & p18_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 200 | #define p18_IS_CLR !(p18_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 201 | #define p18_MODE(x) LPC_PINCON->PINMODE1&=p18_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<20) |
| okini3939 | 0:de79d4a48e63 | 202 | |
| okini3939 | 0:de79d4a48e63 | 203 | /* p19 is P1.30 */ |
| okini3939 | 0:de79d4a48e63 | 204 | #define p19_SEL_MASK ~(3UL << 28) |
| okini3939 | 0:de79d4a48e63 | 205 | #define p19_SET_MASK (1UL << 30) |
| okini3939 | 0:de79d4a48e63 | 206 | #define p19_AS_OUTPUT LPC_PINCON->PINSEL3&=p19_SEL_MASK;LPC_GPIO1->FIODIR|=p19_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 207 | #define p19_AS_INPUT LPC_GPIO1->FIOMASK &= p19_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 208 | #define p19_SET LPC_GPIO1->FIOSET = p19_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 209 | #define p19_CLR LPC_GPIO1->FIOCLR = p19_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 210 | #define p19_IS_SET (bool)(LPC_GPIO1->FIOPIN & p19_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 211 | #define p19_IS_CLR !(p19_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 212 | #define p19_MODE(x) LPC_PINCON->PINMODE3&=p19_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<28) |
| okini3939 | 0:de79d4a48e63 | 213 | |
| okini3939 | 0:de79d4a48e63 | 214 | /* p20 is P1.31 */ |
| okini3939 | 0:de79d4a48e63 | 215 | #define p20_SEL_MASK ~(3UL << 30) |
| okini3939 | 0:de79d4a48e63 | 216 | #define p20_SET_MASK (1UL << 31) |
| okini3939 | 0:de79d4a48e63 | 217 | #define p20_CLR_MASK ~(p20_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 218 | #define p20_AS_OUTPUT LPC_PINCON->PINSEL3&=p20_SEL_MASK;LPC_GPIO1->FIODIR|=p20_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 219 | #define p20_AS_INPUT LPC_GPIO1->FIOMASK &= p20_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 220 | #define p20_SET LPC_GPIO1->FIOSET = p20_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 221 | #define p20_CLR LPC_GPIO1->FIOCLR = p20_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 222 | #define p20_IS_SET (bool)(LPC_GPIO1->FIOPIN & p20_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 223 | #define p20_IS_CLR !(p20_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 224 | #define p20_MODE(x) LPC_PINCON->PINMODE3&=p20_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<30) |
| okini3939 | 0:de79d4a48e63 | 225 | |
| okini3939 | 0:de79d4a48e63 | 226 | /* p21 is P2.5 */ |
| okini3939 | 0:de79d4a48e63 | 227 | #define p21_SEL_MASK ~(3UL << 10) |
| okini3939 | 0:de79d4a48e63 | 228 | #define p21_SET_MASK (1UL << 5) |
| okini3939 | 0:de79d4a48e63 | 229 | #define p21_CLR_MASK ~(p21_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 230 | #define p21_AS_OUTPUT LPC_PINCON->PINSEL4&=p21_SEL_MASK;LPC_GPIO2->FIODIR|=p21_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 231 | #define p21_AS_INPUT LPC_GPIO2->FIOMASK &= p21_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 232 | #define p21_SET LPC_GPIO2->FIOSET = p21_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 233 | #define p21_CLR LPC_GPIO2->FIOCLR = p21_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 234 | #define p21_IS_SET (bool)(LPC_GPIO2->FIOPIN & p21_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 235 | #define p21_IS_CLR !(p21_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 236 | #define p21_TOGGLE p21_IS_SET?p21_CLR:p21_SET |
| okini3939 | 0:de79d4a48e63 | 237 | #define p21_MODE(x) LPC_PINCON->PINMODE4&=p21_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<10) |
| okini3939 | 0:de79d4a48e63 | 238 | |
| okini3939 | 0:de79d4a48e63 | 239 | /* p22 is P2.4 */ |
| okini3939 | 0:de79d4a48e63 | 240 | #define p22_SEL_MASK ~(3UL << 8) |
| okini3939 | 0:de79d4a48e63 | 241 | #define p22_SET_MASK (1UL << 4) |
| okini3939 | 0:de79d4a48e63 | 242 | #define p22_CLR_MASK ~(p22_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 243 | #define p22_AS_OUTPUT LPC_PINCON->PINSEL4&=p22_SEL_MASK;LPC_GPIO2->FIODIR|=p22_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 244 | #define p22_AS_INPUT LPC_GPIO2->FIOMASK &= p22_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 245 | #define p22_SET LPC_GPIO2->FIOSET = p22_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 246 | #define p22_CLR LPC_GPIO2->FIOCLR = p22_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 247 | #define p22_IS_SET (bool)(LPC_GPIO2->FIOPIN & p22_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 248 | #define p22_IS_CLR !(p22_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 249 | #define p22_TOGGLE p22_IS_SET?p22_CLR:p22_SET |
| okini3939 | 0:de79d4a48e63 | 250 | #define p22_MODE(x) LPC_PINCON->PINMODE4&=p22_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<8) |
| okini3939 | 0:de79d4a48e63 | 251 | |
| okini3939 | 0:de79d4a48e63 | 252 | /* p23 is P2.3 */ |
| okini3939 | 0:de79d4a48e63 | 253 | #define p23_SEL_MASK ~(3UL << 6) |
| okini3939 | 0:de79d4a48e63 | 254 | #define p23_SET_MASK (1UL << 3) |
| okini3939 | 0:de79d4a48e63 | 255 | #define p23_CLR_MASK ~(p23_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 256 | #define p23_AS_OUTPUT LPC_PINCON->PINSEL4&=p23_SEL_MASK;LPC_GPIO2->FIODIR|=p23_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 257 | #define p23_AS_INPUT LPC_GPIO2->FIOMASK &= p23_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 258 | #define p23_SET LPC_GPIO2->FIOSET = p23_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 259 | #define p23_CLR LPC_GPIO2->FIOCLR = p23_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 260 | #define p23_IS_SET (bool)(LPC_GPIO2->FIOPIN & p23_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 261 | #define p23_IS_CLR !(p23_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 262 | #define p23_TOGGLE p23_IS_SET?p23_CLR:p23_SET |
| okini3939 | 0:de79d4a48e63 | 263 | #define p23_MODE(x) LPC_PINCON->PINMODE4&=p23_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<6) |
| okini3939 | 0:de79d4a48e63 | 264 | |
| okini3939 | 0:de79d4a48e63 | 265 | /* p24 is P2.2 */ |
| okini3939 | 0:de79d4a48e63 | 266 | #define p24_SEL_MASK ~(3UL << 4) |
| okini3939 | 0:de79d4a48e63 | 267 | #define p24_SET_MASK (1UL << 2) |
| okini3939 | 0:de79d4a48e63 | 268 | #define p24_CLR_MASK ~(p24_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 269 | #define p24_AS_OUTPUT LPC_PINCON->PINSEL4&=p24_SEL_MASK;LPC_GPIO2->FIODIR|=p24_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 270 | #define p24_AS_INPUT LPC_GPIO2->FIOMASK &= p24_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 271 | #define p24_SET LPC_GPIO2->FIOSET = p24_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 272 | #define p24_CLR LPC_GPIO2->FIOCLR = p24_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 273 | #define p24_IS_SET (bool)(LPC_GPIO2->FIOPIN & p24_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 274 | #define p24_IS_CLR !(p24_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 275 | #define p24_TOGGLE p24_IS_SET?p24_CLR:p24_SET |
| okini3939 | 0:de79d4a48e63 | 276 | #define p24_MODE(x) LPC_PINCON->PINMODE4&=p24_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<4) |
| okini3939 | 0:de79d4a48e63 | 277 | |
| okini3939 | 0:de79d4a48e63 | 278 | /* p25 is P2.1 */ |
| okini3939 | 0:de79d4a48e63 | 279 | #define p25_SEL_MASK ~(3UL << 2) |
| okini3939 | 0:de79d4a48e63 | 280 | #define p25_SET_MASK (1UL << 1) |
| okini3939 | 0:de79d4a48e63 | 281 | #define p25_CLR_MASK ~(p25_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 282 | #define p25_AS_OUTPUT LPC_PINCON->PINSEL4&=p25_SEL_MASK;LPC_GPIO2->FIODIR|=p25_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 283 | #define p25_AS_INPUT LPC_GPIO2->FIOMASK &= p25_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 284 | #define p25_SET LPC_GPIO2->FIOSET = p25_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 285 | #define p25_CLR LPC_GPIO2->FIOCLR = p25_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 286 | #define p25_IS_SET (bool)(LPC_GPIO2->FIOPIN & p25_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 287 | #define p25_IS_CLR !(p25_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 288 | #define p25_MODE(x) LPC_PINCON->PINMODE4&=p25_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<2) |
| okini3939 | 0:de79d4a48e63 | 289 | |
| okini3939 | 0:de79d4a48e63 | 290 | /* p26 is P2.0 */ |
| okini3939 | 0:de79d4a48e63 | 291 | #define p26_SEL_MASK ~(3UL << 0) |
| okini3939 | 0:de79d4a48e63 | 292 | #define p26_SET_MASK (1UL << 0) |
| okini3939 | 0:de79d4a48e63 | 293 | #define p26_CLR_MASK ~(p26_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 294 | #define p26_AS_OUTPUT LPC_PINCON->PINSEL4&=p26_SEL_MASK;LPC_GPIO2->FIODIR|=p26_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 295 | #define p26_AS_INPUT LPC_GPIO2->FIOMASK &= p26_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 296 | #define p26_SET LPC_GPIO2->FIOSET = p26_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 297 | #define p26_CLR LPC_GPIO2->FIOCLR = p26_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 298 | #define p26_IS_SET (bool)(LPC_GPIO2->FIOPIN & p26_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 299 | #define p26_IS_CLR !(p26_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 300 | #define p26_MODE(x) LPC_PINCON->PINMODE4&=p26_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<0) |
| okini3939 | 0:de79d4a48e63 | 301 | |
| okini3939 | 0:de79d4a48e63 | 302 | /* p27 is P0.11 */ |
| okini3939 | 0:de79d4a48e63 | 303 | #define p27_SEL_MASK ~(3UL << 22) |
| okini3939 | 0:de79d4a48e63 | 304 | #define p27_SET_MASK (1UL << 11) |
| okini3939 | 0:de79d4a48e63 | 305 | #define p27_CLR_MASK ~(p27_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 306 | #define p27_AS_OUTPUT LPC_PINCON->PINSEL0&=p27_SEL_MASK;LPC_GPIO0->FIODIR|=p27_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 307 | #define p27_AS_INPUT LPC_GPIO0->FIOMASK &= p27_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 308 | #define p27_SET LPC_GPIO0->FIOSET = p27_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 309 | #define p27_CLR LPC_GPIO0->FIOCLR = p27_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 310 | #define p27_IS_SET (bool)(LPC_GPIO0->FIOPIN & p27_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 311 | #define p27_IS_CLR !(p27_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 312 | #define p27_MODE(x) LPC_PINCON->PINMODE0&=p27_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<22) |
| okini3939 | 0:de79d4a48e63 | 313 | |
| okini3939 | 0:de79d4a48e63 | 314 | /* p28 is P0.10 */ |
| okini3939 | 0:de79d4a48e63 | 315 | #define p28_SEL_MASK ~(3UL << 20) |
| okini3939 | 0:de79d4a48e63 | 316 | #define p28_SET_MASK (1UL << 10) |
| okini3939 | 0:de79d4a48e63 | 317 | #define p28_CLR_MASK ~(p28_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 318 | #define p28_AS_OUTPUT LPC_PINCON->PINSEL0&=p28_SEL_MASK;LPC_GPIO0->FIODIR|=p28_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 319 | #define p28_AS_INPUT LPC_GPIO0->FIOMASK &= p28_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 320 | #define p28_SET LPC_GPIO0->FIOSET = p28_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 321 | #define p28_CLR LPC_GPIO0->FIOCLR = p28_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 322 | #define p28_IS_SET (bool)(LPC_GPIO0->FIOPIN & p28_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 323 | #define p28_IS_CLR !(p28_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 324 | #define p28_MODE(x) LPC_PINCON->PINMODE0&=p28_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<20) |
| okini3939 | 0:de79d4a48e63 | 325 | |
| okini3939 | 0:de79d4a48e63 | 326 | /* p29 is P0.5 */ |
| okini3939 | 0:de79d4a48e63 | 327 | #define p29_SEL_MASK ~(3UL << 10) |
| okini3939 | 0:de79d4a48e63 | 328 | #define p29_SET_MASK (1UL << 5) |
| okini3939 | 0:de79d4a48e63 | 329 | #define p29_CLR_MASK ~(p29_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 330 | #define p29_AS_OUTPUT LPC_PINCON->PINSEL0&=p29_SEL_MASK;LPC_GPIO0->FIODIR|=p29_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 331 | #define p29_AS_INPUT LPC_GPIO0->FIOMASK &= p29_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 332 | #define p29_SET LPC_GPIO0->FIOSET = p29_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 333 | #define p29_CLR LPC_GPIO0->FIOCLR = p29_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 334 | #define p29_IS_SET (bool)(LPC_GPIO0->FIOPIN & p29_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 335 | #define p29_IS_CLR !(p29_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 336 | #define p29_TOGGLE p29_IS_SET?p29_CLR:p29_SET |
| okini3939 | 0:de79d4a48e63 | 337 | #define p29_MODE(x) LPC_PINCON->PINMODE0&=p29_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<10) |
| okini3939 | 0:de79d4a48e63 | 338 | |
| okini3939 | 0:de79d4a48e63 | 339 | /* p30 is P0.4 */ |
| okini3939 | 0:de79d4a48e63 | 340 | #define p30_SEL_MASK ~(3UL << 8) |
| okini3939 | 0:de79d4a48e63 | 341 | #define p30_SET_MASK (1UL << 4) |
| okini3939 | 0:de79d4a48e63 | 342 | #define p30_CLR_MASK ~(p30_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 343 | #define p30_AS_OUTPUT LPC_PINCON->PINSEL0&=p30_SEL_MASK;LPC_GPIO0->FIODIR|=p30_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 344 | #define p30_AS_INPUT LPC_GPIO0->FIOMASK &= p30_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 345 | #define p30_SET LPC_GPIO0->FIOSET = p30_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 346 | #define p30_CLR LPC_GPIO0->FIOCLR = p30_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 347 | #define p30_IS_SET (bool)(LPC_GPIO0->FIOPIN & p30_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 348 | #define p30_IS_CLR !(p30_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 349 | #define p30_MODE(x) LPC_PINCON->PINMODE0&=p30_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<8) |
| okini3939 | 0:de79d4a48e63 | 350 | |
| okini3939 | 0:de79d4a48e63 | 351 | /* The following definitions are for the four Mbed LEDs. |
| okini3939 | 0:de79d4a48e63 | 352 | LED1 = P1.18 |
| okini3939 | 0:de79d4a48e63 | 353 | LED2 = P1.20 |
| okini3939 | 0:de79d4a48e63 | 354 | LED3 = P1.21 |
| okini3939 | 0:de79d4a48e63 | 355 | LED4 = P1.23 */ |
| okini3939 | 0:de79d4a48e63 | 356 | |
| okini3939 | 0:de79d4a48e63 | 357 | #define P1_18_SEL_MASK ~(3UL << 4) |
| okini3939 | 0:de79d4a48e63 | 358 | #define P1_18_SET_MASK (1UL << 18) |
| okini3939 | 0:de79d4a48e63 | 359 | #define P1_18_CLR_MASK ~(P1_18_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 360 | #define P1_18_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_18_SEL_MASK;LPC_GPIO1->FIODIR|=P1_18_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 361 | #define P1_18_AS_INPUT LPC_GPIO1->FIOMASK &= P1_18_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 362 | #define P1_18_SET LPC_GPIO1->FIOSET = P1_18_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 363 | #define P1_18_CLR LPC_GPIO1->FIOCLR = P1_18_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 364 | #define P1_18_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_18_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 365 | #define P1_18_IS_CLR !(P1_18_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 366 | #define LED1_USE P1_18_AS_OUTPUT;P1_18_AS_INPUT |
| okini3939 | 0:de79d4a48e63 | 367 | #define LED1_ON P1_18_SET |
| okini3939 | 0:de79d4a48e63 | 368 | #define LED1_OFF P1_18_CLR |
| okini3939 | 0:de79d4a48e63 | 369 | #define LED1_IS_ON P1_18_IS_SET |
| okini3939 | 0:de79d4a48e63 | 370 | #define LED1_TOGGLE P1_18_IS_SET?LED1_OFF:LED1_ON |
| okini3939 | 0:de79d4a48e63 | 371 | |
| okini3939 | 0:de79d4a48e63 | 372 | #define P1_20_SEL_MASK ~(3UL << 8) |
| okini3939 | 0:de79d4a48e63 | 373 | #define P1_20_SET_MASK (1UL << 20) |
| okini3939 | 0:de79d4a48e63 | 374 | #define P1_20_CLR_MASK ~(P1_20_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 375 | #define P1_20_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_20_SEL_MASK;LPC_GPIO1->FIODIR|=P1_20_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 376 | #define P1_20_AS_INPUT LPC_GPIO1->FIOMASK &= P1_20_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 377 | #define P1_20_SET LPC_GPIO1->FIOSET = P1_20_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 378 | #define P1_20_CLR LPC_GPIO1->FIOCLR = P1_20_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 379 | #define P1_20_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_20_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 380 | #define P1_20_IS_CLR !(P1_20_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 381 | #define LED2_USE P1_20_AS_OUTPUT;P1_20_AS_INPUT |
| okini3939 | 0:de79d4a48e63 | 382 | #define LED2_ON P1_20_SET |
| okini3939 | 0:de79d4a48e63 | 383 | #define LED2_OFF P1_20_CLR |
| okini3939 | 0:de79d4a48e63 | 384 | #define LED2_IS_ON P1_20_IS_SET |
| okini3939 | 0:de79d4a48e63 | 385 | #define LED2_TOGGLE P1_20_IS_SET?LED2_OFF:LED2_ON |
| okini3939 | 0:de79d4a48e63 | 386 | |
| okini3939 | 0:de79d4a48e63 | 387 | #define P1_21_SEL_MASK ~(3UL << 10) |
| okini3939 | 0:de79d4a48e63 | 388 | #define P1_21_SET_MASK (1UL << 21) |
| okini3939 | 0:de79d4a48e63 | 389 | #define P1_21_CLR_MASK ~(P1_21_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 390 | #define P1_21_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_21_SEL_MASK;LPC_GPIO1->FIODIR|=P1_21_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 391 | #define P1_21_AS_INPUT LPC_GPIO1->FIOMASK &= P1_21_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 392 | #define P1_21_SET LPC_GPIO1->FIOSET = P1_21_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 393 | #define P1_21_CLR LPC_GPIO1->FIOCLR = P1_21_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 394 | #define P1_21_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_21_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 395 | #define P1_21_IS_CLR !(P1_21_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 396 | #define LED3_USE P1_21_AS_OUTPUT;P1_21_AS_INPUT |
| okini3939 | 0:de79d4a48e63 | 397 | #define LED3_ON P1_21_SET |
| okini3939 | 0:de79d4a48e63 | 398 | #define LED3_OFF P1_21_CLR |
| okini3939 | 0:de79d4a48e63 | 399 | #define LED3_IS_ON P1_21_IS_SET |
| okini3939 | 0:de79d4a48e63 | 400 | #define LED3_TOGGLE P1_21_IS_SET?LED3_OFF:LED3_ON |
| okini3939 | 0:de79d4a48e63 | 401 | |
| okini3939 | 0:de79d4a48e63 | 402 | #define P1_23_SEL_MASK ~(3UL << 14) |
| okini3939 | 0:de79d4a48e63 | 403 | #define P1_23_SET_MASK (1UL << 23) |
| okini3939 | 0:de79d4a48e63 | 404 | #define P1_23_CLR_MASK ~(P1_23_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 405 | #define P1_23_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_23_SEL_MASK;LPC_GPIO1->FIODIR|=P1_23_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 406 | #define P1_23_AS_INPUT LPC_GPIO1->FIOMASK &= P1_23_CLR_MASK; |
| okini3939 | 0:de79d4a48e63 | 407 | #define P1_23_SET LPC_GPIO1->FIOSET = P1_23_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 408 | #define P1_23_CLR LPC_GPIO1->FIOCLR = P1_23_SET_MASK |
| okini3939 | 0:de79d4a48e63 | 409 | #define P1_23_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_23_SET_MASK) |
| okini3939 | 0:de79d4a48e63 | 410 | #define P1_23_IS_CLR !(P1_23_IS_SET) |
| okini3939 | 0:de79d4a48e63 | 411 | #define LED4_USE P1_23_AS_OUTPUT;P1_23_AS_INPUT |
| okini3939 | 0:de79d4a48e63 | 412 | #define LED4_ON P1_23_SET |
| okini3939 | 0:de79d4a48e63 | 413 | #define LED4_OFF P1_23_CLR |
| okini3939 | 0:de79d4a48e63 | 414 | #define LED4_IS_ON P1_23_IS_SET |
| okini3939 | 0:de79d4a48e63 | 415 | #define LED4_TOGGLE P1_23_IS_SET?LED4_OFF:LED4_ON |
| okini3939 | 0:de79d4a48e63 | 416 | |
| okini3939 | 0:de79d4a48e63 | 417 | #endif |
| okini3939 | 0:de79d4a48e63 | 418 |