N K / Mbed 2 deprecated foc-ed_in_the_bot_compact

last working

Dependencies:   FastPWM3 mbed

Fork of foc-ed_in_the_bot_compact by Bayley Wang

main.cpp@9:074575151e4b, 2016-05-17 (annotated)

Committer:
bwang
Date:
Tue May 17 06:44:09 2016 +0000
Revision:
9:074575151e4b
Parent:
4:a6669248ce4d
Child:
10:6829abb438fc
prepping for altermotter operation

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bwang 0:bac9c3a3a6ca 1 #include "mbed.h"
bwang 0:bac9c3a3a6ca 2 #include "math.h"
bwang 0:bac9c3a3a6ca 3 #include "PositionSensor.h"
bwang 0:bac9c3a3a6ca 4 #include "FastPWM.h"
bwang 0:bac9c3a3a6ca 5 #include "Transforms.h"
bwang 0:bac9c3a3a6ca 6 #include "config.h"
bwang 0:bac9c3a3a6ca 7
bwang 1:7b61790f6be9 8 FastPWM *a;
bwang 1:7b61790f6be9 9 FastPWM *b;
bwang 1:7b61790f6be9 10 FastPWM *c;
bwang 0:bac9c3a3a6ca 11 DigitalOut en(EN);
bwang 1:7b61790f6be9 12 DigitalOut toggle(PC_10);
bwang 0:bac9c3a3a6ca 13
bwang 0:bac9c3a3a6ca 14 PositionSensorEncoder pos(CPR, 0);
bwang 0:bac9c3a3a6ca 15
bwang 0:bac9c3a3a6ca 16 Serial pc(USBTX, USBRX);
bwang 0:bac9c3a3a6ca 17
bwang 1:7b61790f6be9 18 int state = 0;
bwang 1:7b61790f6be9 19 int adval1, adval2;
bwang 2:eabe8feaaabb 20 float ia, ib, ic, alpha, beta, d, q, vd, vq, p;
bwang 2:eabe8feaaabb 21
bwang 1:7b61790f6be9 22 float ia_supp_offset = 0.0f, ib_supp_offset = 0.0f; //current sensor offset due to bias resistor inaccuracies, etc (mV)
bwang 1:7b61790f6be9 23
bwang 2:eabe8feaaabb 24 float d_integral = 0.0f, q_integral = 0.0f;
bwang 2:eabe8feaaabb 25 float last_d = 0.0f, last_q = 0.0f;
bwang 3:9b20da3f0055 26 float d_ref = -0.0f, q_ref = -50.0f;
bwang 2:eabe8feaaabb 27
bwang 4:a6669248ce4d 28 void commutate();
bwang 3:9b20da3f0055 29 void zero_current();
bwang 3:9b20da3f0055 30 void config_globals();
bwang 3:9b20da3f0055 31 void startup_msg();
bwang 2:eabe8feaaabb 32
bwang 1:7b61790f6be9 33 extern "C" void TIM1_UP_TIM10_IRQHandler(void) {
bwang 1:7b61790f6be9 34 if (TIM1->SR & TIM_SR_UIF ) {
bwang 4:a6669248ce4d 35 toggle = 1;
bwang 4:a6669248ce4d 36 ADC1->CR2 |= 0x40000000;
bwang 4:a6669248ce4d 37 volatile int delay;
bwang 4:a6669248ce4d 38 for (delay = 0; delay < 35; delay++);
bwang 4:a6669248ce4d 39 toggle = 0;
bwang 1:7b61790f6be9 40 adval1 = ADC1->DR;
bwang 1:7b61790f6be9 41 adval2 = ADC2->DR;
bwang 4:a6669248ce4d 42 commutate();
bwang 1:7b61790f6be9 43 }
bwang 1:7b61790f6be9 44 TIM1->SR = 0x00;
bwang 1:7b61790f6be9 45 }
bwang 1:7b61790f6be9 46
bwang 1:7b61790f6be9 47 void zero_current(){
bwang 1:7b61790f6be9 48 for (int i = 0; i < 1000; i++){
bwang 1:7b61790f6be9 49 ia_supp_offset += (float) (ADC1->DR);
bwang 1:7b61790f6be9 50 ib_supp_offset += (float) (ADC2->DR);
bwang 1:7b61790f6be9 51 ADC1->CR2 |= 0x40000000;
bwang 1:7b61790f6be9 52 wait_us(100);
bwang 1:7b61790f6be9 53 }
bwang 1:7b61790f6be9 54 ia_supp_offset /= 1000.0f;
bwang 1:7b61790f6be9 55 ib_supp_offset /= 1000.0f;
bwang 1:7b61790f6be9 56 ia_supp_offset = ia_supp_offset / 4096.0f * AVDD - I_OFFSET;
bwang 1:7b61790f6be9 57 ib_supp_offset = ib_supp_offset / 4096.0f * AVDD - I_OFFSET;
bwang 1:7b61790f6be9 58 }
bwang 0:bac9c3a3a6ca 59
bwang 0:bac9c3a3a6ca 60 void config_globals() {
bwang 0:bac9c3a3a6ca 61 pc.baud(115200);
bwang 0:bac9c3a3a6ca 62
bwang 1:7b61790f6be9 63 //Enable clocks for GPIOs
bwang 1:7b61790f6be9 64 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
bwang 1:7b61790f6be9 65 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;
bwang 1:7b61790f6be9 66 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
bwang 1:7b61790f6be9 67
bwang 1:7b61790f6be9 68 RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; //enable TIM1 clock
bwang 1:7b61790f6be9 69
bwang 1:7b61790f6be9 70 a = new FastPWM(PWMA);
bwang 1:7b61790f6be9 71 b = new FastPWM(PWMB);
bwang 1:7b61790f6be9 72 c = new FastPWM(PWMC);
bwang 1:7b61790f6be9 73
bwang 1:7b61790f6be9 74 NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); //Enable TIM1 IRQ
bwang 1:7b61790f6be9 75
bwang 1:7b61790f6be9 76 TIM1->DIER |= TIM_DIER_UIE; //enable update interrupt
bwang 1:7b61790f6be9 77 TIM1->CR1 = 0x40; //CMS = 10, interrupt only when counting up
bwang 1:7b61790f6be9 78 TIM1->CR1 |= TIM_CR1_ARPE; //autoreload on,
bwang 1:7b61790f6be9 79 TIM1->RCR |= 0x01; //update event once per up/down count of tim1
bwang 1:7b61790f6be9 80 TIM1->EGR |= TIM_EGR_UG;
bwang 1:7b61790f6be9 81
bwang 1:7b61790f6be9 82 TIM1->PSC = 0x00; //no prescaler, timer counts up in sync with the peripheral clock
bwang 1:7b61790f6be9 83 TIM1->ARR = 0x4650; //5 Khz
bwang 1:7b61790f6be9 84 TIM1->CCER |= ~(TIM_CCER_CC1NP); //Interupt when low side is on.
bwang 1:7b61790f6be9 85 TIM1->CR1 |= TIM_CR1_CEN;
bwang 1:7b61790f6be9 86
bwang 1:7b61790f6be9 87 //ADC Setup
bwang 1:7b61790f6be9 88 RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // clock for ADC1
bwang 1:7b61790f6be9 89 RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; // clock for ADC2
bwang 1:7b61790f6be9 90
bwang 1:7b61790f6be9 91 ADC->CCR = 0x00000006; //Regular simultaneous mode, 3 channels
bwang 1:7b61790f6be9 92
bwang 1:7b61790f6be9 93 ADC1->CR2 |= ADC_CR2_ADON; //ADC1 on
bwang 1:7b61790f6be9 94 ADC1->SQR3 = 0x0000004; //PA_4 as ADC1, sequence 0
bwang 0:bac9c3a3a6ca 95
bwang 1:7b61790f6be9 96 ADC2->CR2 |= ADC_CR2_ADON; //ADC2 ON
bwang 1:7b61790f6be9 97 ADC2->SQR3 = 0x00000008; //PB_0 as ADC2, sequence 1
bwang 1:7b61790f6be9 98
bwang 1:7b61790f6be9 99 GPIOA->MODER |= (1 << 8);
bwang 1:7b61790f6be9 100 GPIOA->MODER |= (1 << 9);
bwang 1:7b61790f6be9 101
bwang 1:7b61790f6be9 102 GPIOA->MODER |= (1 << 2);
bwang 1:7b61790f6be9 103 GPIOA->MODER |= (1 << 3);
bwang 1:7b61790f6be9 104
bwang 1:7b61790f6be9 105 GPIOA->MODER |= (1 << 0);
bwang 1:7b61790f6be9 106 GPIOA->MODER |= (1 << 1);
bwang 1:7b61790f6be9 107
bwang 1:7b61790f6be9 108 GPIOB->MODER |= (1 << 0);
bwang 1:7b61790f6be9 109 GPIOB->MODER |= (1 << 1);
bwang 1:7b61790f6be9 110
bwang 1:7b61790f6be9 111 GPIOC->MODER |= (1 << 2);
bwang 1:7b61790f6be9 112 GPIOC->MODER |= (1 << 3);
bwang 1:7b61790f6be9 113
bwang 1:7b61790f6be9 114 //DAC setup
bwang 1:7b61790f6be9 115 RCC->APB1ENR |= 0x20000000;
bwang 1:7b61790f6be9 116 DAC->CR |= DAC_CR_EN2;
bwang 1:7b61790f6be9 117
bwang 1:7b61790f6be9 118 GPIOA->MODER |= (1 << 10);
bwang 1:7b61790f6be9 119 GPIOA->MODER |= (1 << 11);
bwang 1:7b61790f6be9 120
bwang 1:7b61790f6be9 121 //Zero duty cycles
bwang 1:7b61790f6be9 122 set_dtc(a, 0.0f);
bwang 1:7b61790f6be9 123 set_dtc(b, 0.0f);
bwang 1:7b61790f6be9 124 set_dtc(c, 0.0f);
bwang 1:7b61790f6be9 125
bwang 1:7b61790f6be9 126 wait_ms(250);
bwang 1:7b61790f6be9 127 zero_current();
bwang 0:bac9c3a3a6ca 128 en = 1;
bwang 0:bac9c3a3a6ca 129 }
bwang 0:bac9c3a3a6ca 130
bwang 0:bac9c3a3a6ca 131 void startup_msg() {
bwang 0:bac9c3a3a6ca 132 pc.printf("%s\n\r\n\r", "FOC'ed in the Bot Rev A.");
bwang 0:bac9c3a3a6ca 133 pc.printf("%s\n\r", "====Config Data====");
bwang 0:bac9c3a3a6ca 134 pc.printf("Current Sensor Offset: %f mV\n\r", I_OFFSET);
bwang 0:bac9c3a3a6ca 135 pc.printf("Current Sensor Scale: %f mv/A\n\r", I_SCALE);
bwang 0:bac9c3a3a6ca 136 pc.printf("Bus Voltage: %f V\n\r", BUS_VOLTAGE);
bwang 9:074575151e4b 137 pc.printf("Pole pairs: %d\n\r", (int) POLE_PAIRS);
bwang 9:074575151e4b 138 pc.printf("Resolver lobes: %d\n\r", (int) RESOLVER_LOBES);
bwang 0:bac9c3a3a6ca 139 pc.printf("Loop KP: %f\n\r", KP);
bwang 0:bac9c3a3a6ca 140 pc.printf("Loop KI: %f\n\r", KI);
bwang 1:7b61790f6be9 141 pc.printf("Ia offset: %f mV\n\r", ia_supp_offset);
bwang 1:7b61790f6be9 142 pc.printf("Ib offset: %f mV\n\r", ib_supp_offset);
bwang 0:bac9c3a3a6ca 143 pc.printf("\n\r");
bwang 0:bac9c3a3a6ca 144 }
bwang 0:bac9c3a3a6ca 145
bwang 4:a6669248ce4d 146 void commutate() {
bwang 2:eabe8feaaabb 147 p = pos.GetElecPosition() - POS_OFFSET;
bwang 0:bac9c3a3a6ca 148 if (p < 0) p += 2 * PI;
bwang 0:bac9c3a3a6ca 149
bwang 2:eabe8feaaabb 150 float sin_p = sinf(p);
bwang 2:eabe8feaaabb 151 float cos_p = cosf(p);
bwang 2:eabe8feaaabb 152
bwang 4:a6669248ce4d 153 //float pos_dac = 0.85f * p / (2 * PI) + 0.05f;
bwang 4:a6669248ce4d 154 //DAC->DHR12R2 = (unsigned int) (pos_dac * 4096);
bwang 0:bac9c3a3a6ca 155
bwang 1:7b61790f6be9 156 ia = ((float) adval1 / 4096.0f * AVDD - I_OFFSET - ia_supp_offset) / I_SCALE;
bwang 1:7b61790f6be9 157 ib = ((float) adval2 / 4096.0f * AVDD - I_OFFSET - ib_supp_offset) / I_SCALE;
bwang 2:eabe8feaaabb 158 ic = -ia - ib;
bwang 0:bac9c3a3a6ca 159
bwang 3:9b20da3f0055 160 float u = ib;
bwang 3:9b20da3f0055 161 float v = ic;
bwang 2:eabe8feaaabb 162
bwang 2:eabe8feaaabb 163 alpha = u;
bwang 2:eabe8feaaabb 164 beta = 1 / sqrtf(3.0f) * u + 2 / sqrtf(3.0f) * v;
bwang 2:eabe8feaaabb 165
bwang 2:eabe8feaaabb 166 d = alpha * cos_p - beta * sin_p;
bwang 2:eabe8feaaabb 167 q = -alpha * sin_p - beta * cos_p;
bwang 2:eabe8feaaabb 168
bwang 3:9b20da3f0055 169 float d_err = d_ref - d;
bwang 3:9b20da3f0055 170 float q_err = q_ref - q;
bwang 2:eabe8feaaabb 171
bwang 2:eabe8feaaabb 172 d_integral += d_err * KI;
bwang 2:eabe8feaaabb 173 q_integral += q_err * KI;
bwang 2:eabe8feaaabb 174
bwang 2:eabe8feaaabb 175 if (q_integral > INTEGRAL_MAX) q_integral = INTEGRAL_MAX;
bwang 2:eabe8feaaabb 176 if (d_integral > INTEGRAL_MAX) d_integral = INTEGRAL_MAX;
bwang 2:eabe8feaaabb 177 if (q_integral < -INTEGRAL_MAX) q_integral = -INTEGRAL_MAX;
bwang 2:eabe8feaaabb 178 if (d_integral < -INTEGRAL_MAX) d_integral = -INTEGRAL_MAX;
bwang 2:eabe8feaaabb 179
bwang 2:eabe8feaaabb 180 vd = KP * d_err + d_integral;
bwang 2:eabe8feaaabb 181 vq = KP * q_err + q_integral;
bwang 2:eabe8feaaabb 182
bwang 2:eabe8feaaabb 183 if (vd < -1.0f) vd = -1.0f;
bwang 2:eabe8feaaabb 184 if (vd > 1.0f) vd = 1.0f;
bwang 2:eabe8feaaabb 185 if (vq < -1.0f) vq = -1.0f;
bwang 2:eabe8feaaabb 186 if (vq > 1.0f) vq = 1.0f;
bwang 2:eabe8feaaabb 187
bwang 4:a6669248ce4d 188 DAC->DHR12R2 = (unsigned int) (-q * 20 + 2048);
bwang 2:eabe8feaaabb 189 //DAC->DHR12R2 = (unsigned int) (-vd * 2000 + 2048);
bwang 2:eabe8feaaabb 190
bwang 4:a6669248ce4d 191 //vd = 0.0f;
bwang 4:a6669248ce4d 192 //vq = -1.0f;
bwang 4:a6669248ce4d 193
bwang 2:eabe8feaaabb 194 float valpha = vd * cos_p - vq * sin_p;
bwang 2:eabe8feaaabb 195 float vbeta = vd * sin_p + vq * cos_p;
bwang 2:eabe8feaaabb 196
bwang 2:eabe8feaaabb 197 float va = valpha;
bwang 2:eabe8feaaabb 198 float vb = -0.5f * valpha - sqrtf(3) / 2.0f * vbeta;
bwang 2:eabe8feaaabb 199 float vc = -0.5f * valpha + sqrtf(3) / 2.0f * vbeta;
bwang 2:eabe8feaaabb 200
bwang 2:eabe8feaaabb 201 set_dtc(a, 0.5f + 0.5f * va);
bwang 2:eabe8feaaabb 202 set_dtc(b, 0.5f + 0.5f * vb);
bwang 2:eabe8feaaabb 203 set_dtc(c, 0.5f + 0.5f * vc);
bwang 0:bac9c3a3a6ca 204 }
bwang 0:bac9c3a3a6ca 205
bwang 0:bac9c3a3a6ca 206 int main() {
bwang 0:bac9c3a3a6ca 207 config_globals();
bwang 0:bac9c3a3a6ca 208 startup_msg();
bwang 0:bac9c3a3a6ca 209
bwang 0:bac9c3a3a6ca 210 for (;;) {
bwang 0:bac9c3a3a6ca 211 }
bwang 0:bac9c3a3a6ca 212 }