Nick melas
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Fork of
MMA8451Q
by 
Johan Kritzinger
Diff: MMA8451Q.cpp
- Revision:
- 6:26a391348e7c
- Parent:
- 5:2d14600116fc
--- a/MMA8451Q.cpp Sun Mar 10 04:34:03 2013 +0000
+++ b/MMA8451Q.cpp Wed Mar 07 11:40:05 2018 +0000
@@ -1,25 +1,8 @@
-/* Copyright (c) 2010-2011 mbed.org, MIT License
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
-* and associated documentation files (the "Software"), to deal in the Software without
-* restriction, including without limitation the rights to use, copy, modify, merge, publish,
-* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
-* Software is furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in all copies or
-* substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
-* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
#include "MMA8451Q.h"
#define INT_SOURCE 0x0C
#define REG_WHO_AM_I 0x0D
+#define XYZ_DATA_CFG 0X0E
#define HP_FILTER_CUTOFF 0x0F
#define PULSE_CFG 0x21
#define PULSE_SRC 0x22
@@ -47,6 +30,20 @@
MMA8451Q::~MMA8451Q() { }
+//read sr value to understand if a tap has occured and in which axe\axes
+uint8_t MMA8451Q::get_source_reg_value(){
+ uint8_t srch_val = 0;
+ readRegs(PULSE_SRC, &srch_val, 1);
+ return srch_val;
+ }
+
+void MMA8451Q::disable_lpfilter(){
+ //disable LOW PASS FILTER
+ uint8_t data[2] = {HP_FILTER_CUTOFF , 0x00};
+ writeRegs(data,2);
+
+ }
+
uint8_t MMA8451Q::getWhoAmI() {
uint8_t who_am_i = 0;
readRegs(REG_WHO_AM_I, &who_am_i, 1);
@@ -84,13 +81,78 @@
return acc;
}
+
+void MMA8451Q::lv1setSingleTap(){
+
+ uint8_t CTRL_REG1_Data;
+// int adds;
+ uint8_t data[2] = {REG_CTRL_REG_1, 0x00}; //data rate 400hz (0x08), 800hz 0x00
+
+
+ //800 Hz, Standby Mode
+ writeRegs(data,2);
+
+ //8g (0x10) dynamic range (0x00 for 2g and 0x01 for 4g)
+ //enable the 4th bit means enable the hpfilter to both fifo and data registers(0b000010xx)-> enable hpf for xx dynamic range
+ data[0] = XYZ_DATA_CFG; data[1] = 0x00;
+ writeRegs(data,2);
+
+ //Enable X, Y and Z Single Pulse with DPA = 0 no double pulse abort
+ // 0x55 gia na einai setarismeno to ele bit, diladi oi times ston pulse_src reg na paramenoun statikes mexri na diavastoun
+ //0x3f gia simgle kai double pulse enable se olous tous aksones
+ data[0]=PULSE_CFG;data[1]=0x15; //0x15 to involved all 3 axis to tap detection , 0x04 only Y axis
+ writeRegs(data,2);
+
+
+ //SetThreshold 2g on X and Y and 2.64g on Z
+ //Note: Every step is 0.063g
+ //2.0 /0.063g = 32 counts
+ //3g/0.063g = 48 counts
+ data[0]=PULSE_THSX;data[1]=0x40; //0x40
+ writeRegs(data,2);//Set X Threshold to 2g
+ data[0]=PULSE_THSY;data[1]=0x40; //0x40
+ writeRegs(data,2);//Set Y Threshold to 2g
+ data[0]=PULSE_THSZ;data[1]=0xFF; //0x40
+ writeRegs(data,2);//Set Z Threshold to 3g
+
+ //Set Time Limit for Tap Detection to 50 ms NO LP Mode
+ //Note: 400 Hz ODR, Time step is 0.625 ms per step
+ //50 ms/0.625 ms = 80 counts
+ data[0]=PULSE_TMLT;data[1]=0x50;
+ writeRegs(data,2);//200 ms
+
+ //Set Latency Time to 300 ms
+ //Note: 400 Hz ODR LPMode, Time step is 1.25 ms per step 200 ms/1.25 ms = 160 counts
+ data[0]=PULSE_LTCY;data[1]=0xFF;
+ writeRegs(data,2);//200 ms
+
+
+ //Route INT1 to System Interrupt
+
+ data[0]=CTRL_REG4;data[1]=0x08;
+ writeRegs(data,2);//Enable Pulse Interrupt in System CTRL_REG4
+ data[0]=CTRL_REG5;data[1]= 0x08;
+ writeRegs(data,2);//Route Pulse Interrupt to INT1 hardware Pin CTRL_REG5
+
+
+ //Set the device to Active Mode
+ readRegs(0x2A,&CTRL_REG1_Data,1);//Read out the contents of the register
+ CTRL_REG1_Data |= 0x01; //Change the value in the register to Active Mode.
+ data[0]=REG_CTRL_REG_1;
+ data[1]=CTRL_REG1_Data;
+ writeRegs(data,2);//Write in the updated value to put the device in Active Mode
+
+}
+
+
+
void MMA8451Q::setDoubleTap(void){
//Implemented directly from Freescale's AN4072
//Added to MMA8451Q lib
uint8_t CTRL_REG1_Data;
// int adds;
- uint8_t data[2] = {REG_CTRL_REG_1, 0x08};
+ uint8_t data[2] = {REG_CTRL_REG_1, 0x08};
//400 Hz, Standby Mode
writeRegs(data,2);
@@ -103,29 +165,29 @@
//Note: Every step is 0.063g
//3 g/0.063g = 48 counts
//5g/0.063g = 79 counts
- data[0]=PULSE_THSX;data[1]=0x30;
+ data[0]=PULSE_THSX;data[1]=0x4f;
writeRegs(data,2);//Set X Threshold to 3g
- data[0]=PULSE_THSY;data[1]=0x30;
+ data[0]=PULSE_THSY;data[1]=0x4f;
writeRegs(data,2);//Set Y Threshold to 3g
- data[0]=PULSE_THSZ;data[1]=0x4F;
+ data[0]=PULSE_THSZ;data[1]=0x5F;
writeRegs(data,2);//Set Z Threshold to 5g
//Set Time Limit for Tap Detection to 60 ms LP Mode
//Note: 400 Hz ODR, Time step is 1.25 ms per step
//60 ms/1.25 ms = 48 counts
- data[0]=PULSE_TMLT;data[1]=0x30;
+ data[0]=PULSE_TMLT;data[1]=0x50;
writeRegs(data,2);//60 ms
//Set Latency Time to 200 ms
//Note: 400 Hz ODR LPMode, Time step is 2.5 ms per step 00 ms/2.5 ms = 80 counts
- data[0]=PULSE_LTCY;data[1]=0x50;
+ data[0]=PULSE_LTCY;data[1]=0xF0;
writeRegs(data,2);//200 ms
//Set Time Window for second tap to 300 ms
//Note: 400 Hz ODR LP Mode, Time step is 2.5 ms per step
//300 ms/2.5 ms = 120 counts
- data[0]=PULSE_WIND;data[1]=0x78;
- writeRegs(data,2);//300 ms
+ data[0]=PULSE_WIND;data[1]=0x78;
+ writeRegs(data,2);//300 ms
//Route INT1 to System Interrupt
data[0]=CTRL_REG4;data[1]=0x08;
@@ -139,7 +201,8 @@
data[0]=REG_CTRL_REG_1;
data[1]=CTRL_REG1_Data;
writeRegs(data,2);//Write in the updated value to put the device in Active Mode
-}
+}
+
void MMA8451Q::readRegs(int addr, uint8_t * data, int len) {
@@ -153,3 +216,4 @@
void MMA8451Q::writeRegs(uint8_t * data, int len) {
m_i2c.write(m_addr, (char *)data, len);
}
+