nguyen nam / Mbed 2 deprecated BSP_DISCO_F746NG

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Dependencies:   mbed

Drivers/BSP/Components/wm8994/wm8994.c@10:e4fe96f3a891, 2019-06-07 (annotated)

Committer:
phungductung
Date:
Fri Jun 07 15:36:42 2019 +0000
Revision:
10:e4fe96f3a891
Parent:
6:e1d9da7fe856 
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Who changed what in which revision?

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bcostm 6:e1d9da7fe856 1 /**
bcostm 6:e1d9da7fe856 2 ******************************************************************************
bcostm 6:e1d9da7fe856 3 * @file wm8994.c
bcostm 6:e1d9da7fe856 4 * @author MCD Application Team
bcostm 6:e1d9da7fe856 5 * @version V2.1.0
bcostm 6:e1d9da7fe856 6 * @date 22-February-2016
bcostm 6:e1d9da7fe856 7 * @brief This file provides the WM8994 Audio Codec driver.
bcostm 6:e1d9da7fe856 8 ******************************************************************************
bcostm 6:e1d9da7fe856 9 * @attention
bcostm 6:e1d9da7fe856 10 *
bcostm 6:e1d9da7fe856 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bcostm 6:e1d9da7fe856 12 *
bcostm 6:e1d9da7fe856 13 * Redistribution and use in source and binary forms, with or without modification,
bcostm 6:e1d9da7fe856 14 * are permitted provided that the following conditions are met:
bcostm 6:e1d9da7fe856 15 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 6:e1d9da7fe856 16 * this list of conditions and the following disclaimer.
bcostm 6:e1d9da7fe856 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 6:e1d9da7fe856 18 * this list of conditions and the following disclaimer in the documentation
bcostm 6:e1d9da7fe856 19 * and/or other materials provided with the distribution.
bcostm 6:e1d9da7fe856 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 6:e1d9da7fe856 21 * may be used to endorse or promote products derived from this software
bcostm 6:e1d9da7fe856 22 * without specific prior written permission.
bcostm 6:e1d9da7fe856 23 *
bcostm 6:e1d9da7fe856 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 6:e1d9da7fe856 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 6:e1d9da7fe856 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 6:e1d9da7fe856 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 6:e1d9da7fe856 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 6:e1d9da7fe856 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 6:e1d9da7fe856 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 6:e1d9da7fe856 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 6:e1d9da7fe856 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 6:e1d9da7fe856 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 6:e1d9da7fe856 34 *
bcostm 6:e1d9da7fe856 35 ******************************************************************************
bcostm 6:e1d9da7fe856 36 */
bcostm 6:e1d9da7fe856 37
bcostm 6:e1d9da7fe856 38 /* Includes ------------------------------------------------------------------*/
bcostm 6:e1d9da7fe856 39 #include "wm8994.h"
bcostm 6:e1d9da7fe856 40
bcostm 6:e1d9da7fe856 41 /** @addtogroup BSP
bcostm 6:e1d9da7fe856 42 * @{
bcostm 6:e1d9da7fe856 43 */
bcostm 6:e1d9da7fe856 44
bcostm 6:e1d9da7fe856 45 /** @addtogroup Components
bcostm 6:e1d9da7fe856 46 * @{
bcostm 6:e1d9da7fe856 47 */
bcostm 6:e1d9da7fe856 48
bcostm 6:e1d9da7fe856 49 /** @addtogroup wm8994
bcostm 6:e1d9da7fe856 50 * @brief This file provides a set of functions needed to drive the
bcostm 6:e1d9da7fe856 51 * WM8994 audio codec.
bcostm 6:e1d9da7fe856 52 * @{
bcostm 6:e1d9da7fe856 53 */
bcostm 6:e1d9da7fe856 54
bcostm 6:e1d9da7fe856 55 /** @defgroup WM8994_Private_Types
bcostm 6:e1d9da7fe856 56 * @{
bcostm 6:e1d9da7fe856 57 */
bcostm 6:e1d9da7fe856 58
bcostm 6:e1d9da7fe856 59 /**
bcostm 6:e1d9da7fe856 60 * @}
bcostm 6:e1d9da7fe856 61 */
bcostm 6:e1d9da7fe856 62
bcostm 6:e1d9da7fe856 63 /** @defgroup WM8994_Private_Defines
bcostm 6:e1d9da7fe856 64 * @{
bcostm 6:e1d9da7fe856 65 */
bcostm 6:e1d9da7fe856 66 /* Uncomment this line to enable verifying data sent to codec after each write
bcostm 6:e1d9da7fe856 67 operation (for debug purpose) */
bcostm 6:e1d9da7fe856 68 #if !defined (VERIFY_WRITTENDATA)
bcostm 6:e1d9da7fe856 69 /*#define VERIFY_WRITTENDATA*/
bcostm 6:e1d9da7fe856 70 #endif /* VERIFY_WRITTENDATA */
bcostm 6:e1d9da7fe856 71 /**
bcostm 6:e1d9da7fe856 72 * @}
bcostm 6:e1d9da7fe856 73 */
bcostm 6:e1d9da7fe856 74
bcostm 6:e1d9da7fe856 75 /** @defgroup WM8994_Private_Macros
bcostm 6:e1d9da7fe856 76 * @{
bcostm 6:e1d9da7fe856 77 */
bcostm 6:e1d9da7fe856 78
bcostm 6:e1d9da7fe856 79 /**
bcostm 6:e1d9da7fe856 80 * @}
bcostm 6:e1d9da7fe856 81 */
bcostm 6:e1d9da7fe856 82
bcostm 6:e1d9da7fe856 83 /** @defgroup WM8994_Private_Variables
bcostm 6:e1d9da7fe856 84 * @{
bcostm 6:e1d9da7fe856 85 */
bcostm 6:e1d9da7fe856 86
bcostm 6:e1d9da7fe856 87 /* Audio codec driver structure initialization */
bcostm 6:e1d9da7fe856 88 AUDIO_DrvTypeDef wm8994_drv =
bcostm 6:e1d9da7fe856 89 {
bcostm 6:e1d9da7fe856 90 wm8994_Init,
bcostm 6:e1d9da7fe856 91 wm8994_DeInit,
bcostm 6:e1d9da7fe856 92 wm8994_ReadID,
bcostm 6:e1d9da7fe856 93
bcostm 6:e1d9da7fe856 94 wm8994_Play,
bcostm 6:e1d9da7fe856 95 wm8994_Pause,
bcostm 6:e1d9da7fe856 96 wm8994_Resume,
bcostm 6:e1d9da7fe856 97 wm8994_Stop,
bcostm 6:e1d9da7fe856 98
bcostm 6:e1d9da7fe856 99 wm8994_SetFrequency,
bcostm 6:e1d9da7fe856 100 wm8994_SetVolume,
bcostm 6:e1d9da7fe856 101 wm8994_SetMute,
bcostm 6:e1d9da7fe856 102 wm8994_SetOutputMode,
bcostm 6:e1d9da7fe856 103
bcostm 6:e1d9da7fe856 104 wm8994_Reset
bcostm 6:e1d9da7fe856 105 };
bcostm 6:e1d9da7fe856 106
bcostm 6:e1d9da7fe856 107 static uint32_t outputEnabled = 0;
bcostm 6:e1d9da7fe856 108 static uint32_t inputEnabled = 0;
bcostm 6:e1d9da7fe856 109 /**
bcostm 6:e1d9da7fe856 110 * @}
bcostm 6:e1d9da7fe856 111 */
bcostm 6:e1d9da7fe856 112
bcostm 6:e1d9da7fe856 113 /** @defgroup WM8994_Function_Prototypes
bcostm 6:e1d9da7fe856 114 * @{
bcostm 6:e1d9da7fe856 115 */
bcostm 6:e1d9da7fe856 116 static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value);
bcostm 6:e1d9da7fe856 117 /**
bcostm 6:e1d9da7fe856 118 * @}
bcostm 6:e1d9da7fe856 119 */
bcostm 6:e1d9da7fe856 120
bcostm 6:e1d9da7fe856 121 /** @defgroup WM8994_Private_Functions
bcostm 6:e1d9da7fe856 122 * @{
bcostm 6:e1d9da7fe856 123 */
bcostm 6:e1d9da7fe856 124
bcostm 6:e1d9da7fe856 125 /**
bcostm 6:e1d9da7fe856 126 * @brief Initializes the audio codec and the control interface.
bcostm 6:e1d9da7fe856 127 * @param DeviceAddr: Device address on communication Bus.
bcostm 6:e1d9da7fe856 128 * @param OutputInputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
bcostm 6:e1d9da7fe856 129 * OUTPUT_DEVICE_BOTH, OUTPUT_DEVICE_AUTO, INPUT_DEVICE_DIGITAL_MICROPHONE_1,
bcostm 6:e1d9da7fe856 130 * INPUT_DEVICE_DIGITAL_MICROPHONE_2, INPUT_DEVICE_DIGITAL_MIC1_MIC2,
bcostm 6:e1d9da7fe856 131 * INPUT_DEVICE_INPUT_LINE_1 or INPUT_DEVICE_INPUT_LINE_2.
bcostm 6:e1d9da7fe856 132 * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max))
bcostm 6:e1d9da7fe856 133 * @param AudioFreq: Audio Frequency
bcostm 6:e1d9da7fe856 134 * @retval 0 if correct communication, else wrong communication
bcostm 6:e1d9da7fe856 135 */
bcostm 6:e1d9da7fe856 136 uint32_t wm8994_Init(uint16_t DeviceAddr, uint16_t OutputInputDevice, uint8_t Volume, uint32_t AudioFreq)
bcostm 6:e1d9da7fe856 137 {
bcostm 6:e1d9da7fe856 138 uint32_t counter = 0;
bcostm 6:e1d9da7fe856 139 uint16_t output_device = OutputInputDevice & 0xFF;
bcostm 6:e1d9da7fe856 140 uint16_t input_device = OutputInputDevice & 0xFF00;
bcostm 6:e1d9da7fe856 141 uint16_t power_mgnt_reg_1 = 0;
bcostm 6:e1d9da7fe856 142
bcostm 6:e1d9da7fe856 143 /* Initialize the Control interface of the Audio Codec */
bcostm 6:e1d9da7fe856 144 AUDIO_IO_Init();
bcostm 6:e1d9da7fe856 145 /* wm8994 Errata Work-Arounds */
bcostm 6:e1d9da7fe856 146 counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0003);
bcostm 6:e1d9da7fe856 147 counter += CODEC_IO_Write(DeviceAddr, 0x817, 0x0000);
bcostm 6:e1d9da7fe856 148 counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0000);
bcostm 6:e1d9da7fe856 149
bcostm 6:e1d9da7fe856 150 /* Enable VMID soft start (fast), Start-up Bias Current Enabled */
bcostm 6:e1d9da7fe856 151 counter += CODEC_IO_Write(DeviceAddr, 0x39, 0x006C);
bcostm 6:e1d9da7fe856 152
bcostm 6:e1d9da7fe856 153 /* Enable bias generator, Enable VMID */
bcostm 6:e1d9da7fe856 154 if (input_device > 0)
bcostm 6:e1d9da7fe856 155 {
bcostm 6:e1d9da7fe856 156 counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x0013);
bcostm 6:e1d9da7fe856 157 }
bcostm 6:e1d9da7fe856 158 else
bcostm 6:e1d9da7fe856 159 {
bcostm 6:e1d9da7fe856 160 counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x0003);
bcostm 6:e1d9da7fe856 161 }
bcostm 6:e1d9da7fe856 162
bcostm 6:e1d9da7fe856 163 /* Add Delay */
bcostm 6:e1d9da7fe856 164 AUDIO_IO_Delay(50);
bcostm 6:e1d9da7fe856 165
bcostm 6:e1d9da7fe856 166 /* Path Configurations for output */
bcostm 6:e1d9da7fe856 167 if (output_device > 0)
bcostm 6:e1d9da7fe856 168 {
bcostm 6:e1d9da7fe856 169 outputEnabled = 1;
bcostm 6:e1d9da7fe856 170 switch (output_device)
bcostm 6:e1d9da7fe856 171 {
bcostm 6:e1d9da7fe856 172 case OUTPUT_DEVICE_SPEAKER:
bcostm 6:e1d9da7fe856 173 /* Enable DAC1 (Left), Enable DAC1 (Right),
bcostm 6:e1d9da7fe856 174 Disable DAC2 (Left), Disable DAC2 (Right)*/
bcostm 6:e1d9da7fe856 175 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C);
bcostm 6:e1d9da7fe856 176
bcostm 6:e1d9da7fe856 177 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 6:e1d9da7fe856 178 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000);
bcostm 6:e1d9da7fe856 179
bcostm 6:e1d9da7fe856 180 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 6:e1d9da7fe856 181 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000);
bcostm 6:e1d9da7fe856 182
bcostm 6:e1d9da7fe856 183 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 6:e1d9da7fe856 184 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
bcostm 6:e1d9da7fe856 185
bcostm 6:e1d9da7fe856 186 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 6:e1d9da7fe856 187 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
bcostm 6:e1d9da7fe856 188 break;
bcostm 6:e1d9da7fe856 189
bcostm 6:e1d9da7fe856 190 case OUTPUT_DEVICE_HEADPHONE:
bcostm 6:e1d9da7fe856 191 /* Disable DAC1 (Left), Disable DAC1 (Right),
bcostm 6:e1d9da7fe856 192 Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 6:e1d9da7fe856 193 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
bcostm 6:e1d9da7fe856 194
bcostm 6:e1d9da7fe856 195 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 6:e1d9da7fe856 196 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
bcostm 6:e1d9da7fe856 197
bcostm 6:e1d9da7fe856 198 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 6:e1d9da7fe856 199 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
bcostm 6:e1d9da7fe856 200
bcostm 6:e1d9da7fe856 201 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 6:e1d9da7fe856 202 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
bcostm 6:e1d9da7fe856 203
bcostm 6:e1d9da7fe856 204 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 6:e1d9da7fe856 205 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
bcostm 6:e1d9da7fe856 206 break;
bcostm 6:e1d9da7fe856 207
bcostm 6:e1d9da7fe856 208 case OUTPUT_DEVICE_BOTH:
bcostm 6:e1d9da7fe856 209 if (input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2)
bcostm 6:e1d9da7fe856 210 {
bcostm 6:e1d9da7fe856 211 /* Enable DAC1 (Left), Enable DAC1 (Right),
bcostm 6:e1d9da7fe856 212 also Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 6:e1d9da7fe856 213 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
bcostm 6:e1d9da7fe856 214
bcostm 6:e1d9da7fe856 215 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path
bcostm 6:e1d9da7fe856 216 Enable the AIF1 Timeslot 1 (Left) to DAC 1 (Left) mixer path */
bcostm 6:e1d9da7fe856 217 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0003);
bcostm 6:e1d9da7fe856 218
bcostm 6:e1d9da7fe856 219 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path
bcostm 6:e1d9da7fe856 220 Enable the AIF1 Timeslot 1 (Right) to DAC 1 (Right) mixer path */
bcostm 6:e1d9da7fe856 221 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0003);
bcostm 6:e1d9da7fe856 222
bcostm 6:e1d9da7fe856 223 /* Enable the AIF1 Timeslot 0 (Left) to DAC 2 (Left) mixer path
bcostm 6:e1d9da7fe856 224 Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 6:e1d9da7fe856 225 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0003);
bcostm 6:e1d9da7fe856 226
bcostm 6:e1d9da7fe856 227 /* Enable the AIF1 Timeslot 0 (Right) to DAC 2 (Right) mixer path
bcostm 6:e1d9da7fe856 228 Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 6:e1d9da7fe856 229 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0003);
bcostm 6:e1d9da7fe856 230 }
bcostm 6:e1d9da7fe856 231 else
bcostm 6:e1d9da7fe856 232 {
bcostm 6:e1d9da7fe856 233 /* Enable DAC1 (Left), Enable DAC1 (Right),
bcostm 6:e1d9da7fe856 234 also Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 6:e1d9da7fe856 235 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
bcostm 6:e1d9da7fe856 236
bcostm 6:e1d9da7fe856 237 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 6:e1d9da7fe856 238 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
bcostm 6:e1d9da7fe856 239
bcostm 6:e1d9da7fe856 240 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 6:e1d9da7fe856 241 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
bcostm 6:e1d9da7fe856 242
bcostm 6:e1d9da7fe856 243 /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 6:e1d9da7fe856 244 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
bcostm 6:e1d9da7fe856 245
bcostm 6:e1d9da7fe856 246 /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 6:e1d9da7fe856 247 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
bcostm 6:e1d9da7fe856 248 }
bcostm 6:e1d9da7fe856 249 break;
bcostm 6:e1d9da7fe856 250
bcostm 6:e1d9da7fe856 251 case OUTPUT_DEVICE_AUTO :
bcostm 6:e1d9da7fe856 252 default:
bcostm 6:e1d9da7fe856 253 /* Disable DAC1 (Left), Disable DAC1 (Right),
bcostm 6:e1d9da7fe856 254 Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 6:e1d9da7fe856 255 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
bcostm 6:e1d9da7fe856 256
bcostm 6:e1d9da7fe856 257 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 6:e1d9da7fe856 258 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
bcostm 6:e1d9da7fe856 259
bcostm 6:e1d9da7fe856 260 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 6:e1d9da7fe856 261 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
bcostm 6:e1d9da7fe856 262
bcostm 6:e1d9da7fe856 263 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 6:e1d9da7fe856 264 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
bcostm 6:e1d9da7fe856 265
bcostm 6:e1d9da7fe856 266 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 6:e1d9da7fe856 267 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
bcostm 6:e1d9da7fe856 268 break;
bcostm 6:e1d9da7fe856 269 }
bcostm 6:e1d9da7fe856 270 }
bcostm 6:e1d9da7fe856 271 else
bcostm 6:e1d9da7fe856 272 {
bcostm 6:e1d9da7fe856 273 outputEnabled = 0;
bcostm 6:e1d9da7fe856 274 }
bcostm 6:e1d9da7fe856 275
bcostm 6:e1d9da7fe856 276 /* Path Configurations for input */
bcostm 6:e1d9da7fe856 277 if (input_device > 0)
bcostm 6:e1d9da7fe856 278 {
bcostm 6:e1d9da7fe856 279 inputEnabled = 1;
bcostm 6:e1d9da7fe856 280 switch (input_device)
bcostm 6:e1d9da7fe856 281 {
bcostm 6:e1d9da7fe856 282 case INPUT_DEVICE_DIGITAL_MICROPHONE_2 :
bcostm 6:e1d9da7fe856 283 /* Enable AIF1ADC2 (Left), Enable AIF1ADC2 (Right)
bcostm 6:e1d9da7fe856 284 * Enable DMICDAT2 (Left), Enable DMICDAT2 (Right)
bcostm 6:e1d9da7fe856 285 * Enable Left ADC, Enable Right ADC */
bcostm 6:e1d9da7fe856 286 counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0C30);
bcostm 6:e1d9da7fe856 287
bcostm 6:e1d9da7fe856 288 /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */
bcostm 6:e1d9da7fe856 289 counter += CODEC_IO_Write(DeviceAddr, 0x450, 0x00DB);
bcostm 6:e1d9da7fe856 290
bcostm 6:e1d9da7fe856 291 /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */
bcostm 6:e1d9da7fe856 292 counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6000);
bcostm 6:e1d9da7fe856 293
bcostm 6:e1d9da7fe856 294 /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */
bcostm 6:e1d9da7fe856 295 counter += CODEC_IO_Write(DeviceAddr, 0x608, 0x0002);
bcostm 6:e1d9da7fe856 296
bcostm 6:e1d9da7fe856 297 /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */
bcostm 6:e1d9da7fe856 298 counter += CODEC_IO_Write(DeviceAddr, 0x609, 0x0002);
bcostm 6:e1d9da7fe856 299
bcostm 6:e1d9da7fe856 300 /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC2 signal detect */
bcostm 6:e1d9da7fe856 301 counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000E);
bcostm 6:e1d9da7fe856 302 break;
bcostm 6:e1d9da7fe856 303
bcostm 6:e1d9da7fe856 304 case INPUT_DEVICE_INPUT_LINE_1 :
bcostm 6:e1d9da7fe856 305 /* IN1LN_TO_IN1L, IN1LP_TO_VMID, IN1RN_TO_IN1R, IN1RP_TO_VMID */
bcostm 6:e1d9da7fe856 306 counter += CODEC_IO_Write(DeviceAddr, 0x28, 0x0011);
bcostm 6:e1d9da7fe856 307
bcostm 6:e1d9da7fe856 308 /* Disable mute on IN1L_TO_MIXINL and +30dB on IN1L PGA output */
bcostm 6:e1d9da7fe856 309 counter += CODEC_IO_Write(DeviceAddr, 0x29, 0x0035);
bcostm 6:e1d9da7fe856 310
bcostm 6:e1d9da7fe856 311 /* Disable mute on IN1R_TO_MIXINL, Gain = +30dB */
bcostm 6:e1d9da7fe856 312 counter += CODEC_IO_Write(DeviceAddr, 0x2A, 0x0035);
bcostm 6:e1d9da7fe856 313
bcostm 6:e1d9da7fe856 314 /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
bcostm 6:e1d9da7fe856 315 * Enable Left ADC, Enable Right ADC */
bcostm 6:e1d9da7fe856 316 counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0303);
bcostm 6:e1d9da7fe856 317
bcostm 6:e1d9da7fe856 318 /* Enable AIF1 DRC1 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
bcostm 6:e1d9da7fe856 319 counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB);
bcostm 6:e1d9da7fe856 320
bcostm 6:e1d9da7fe856 321 /* Enable IN1L and IN1R, Disable IN2L and IN2R, Enable Thermal sensor & shutdown */
bcostm 6:e1d9da7fe856 322 counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6350);
bcostm 6:e1d9da7fe856 323
bcostm 6:e1d9da7fe856 324 /* Enable the ADCL(Left) to AIF1 Timeslot 0 (Left) mixer path */
bcostm 6:e1d9da7fe856 325 counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002);
bcostm 6:e1d9da7fe856 326
bcostm 6:e1d9da7fe856 327 /* Enable the ADCR(Right) to AIF1 Timeslot 0 (Right) mixer path */
bcostm 6:e1d9da7fe856 328 counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002);
bcostm 6:e1d9da7fe856 329
bcostm 6:e1d9da7fe856 330 /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
bcostm 6:e1d9da7fe856 331 counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D);
bcostm 6:e1d9da7fe856 332 break;
bcostm 6:e1d9da7fe856 333
bcostm 6:e1d9da7fe856 334 case INPUT_DEVICE_DIGITAL_MICROPHONE_1 :
bcostm 6:e1d9da7fe856 335 /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
bcostm 6:e1d9da7fe856 336 * Enable DMICDAT1 (Left), Enable DMICDAT1 (Right)
bcostm 6:e1d9da7fe856 337 * Enable Left ADC, Enable Right ADC */
bcostm 6:e1d9da7fe856 338 counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x030C);
bcostm 6:e1d9da7fe856 339
bcostm 6:e1d9da7fe856 340 /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
bcostm 6:e1d9da7fe856 341 counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB);
bcostm 6:e1d9da7fe856 342
bcostm 6:e1d9da7fe856 343 /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */
bcostm 6:e1d9da7fe856 344 counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6350);
bcostm 6:e1d9da7fe856 345
bcostm 6:e1d9da7fe856 346 /* Enable the DMIC2(Left) to AIF1 Timeslot 0 (Left) mixer path */
bcostm 6:e1d9da7fe856 347 counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002);
bcostm 6:e1d9da7fe856 348
bcostm 6:e1d9da7fe856 349 /* Enable the DMIC2(Right) to AIF1 Timeslot 0 (Right) mixer path */
bcostm 6:e1d9da7fe856 350 counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002);
bcostm 6:e1d9da7fe856 351
bcostm 6:e1d9da7fe856 352 /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
bcostm 6:e1d9da7fe856 353 counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D);
bcostm 6:e1d9da7fe856 354 break;
bcostm 6:e1d9da7fe856 355 case INPUT_DEVICE_DIGITAL_MIC1_MIC2 :
bcostm 6:e1d9da7fe856 356 /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
bcostm 6:e1d9da7fe856 357 * Enable DMICDAT1 (Left), Enable DMICDAT1 (Right)
bcostm 6:e1d9da7fe856 358 * Enable Left ADC, Enable Right ADC */
bcostm 6:e1d9da7fe856 359 counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0F3C);
bcostm 6:e1d9da7fe856 360
bcostm 6:e1d9da7fe856 361 /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */
bcostm 6:e1d9da7fe856 362 counter += CODEC_IO_Write(DeviceAddr, 0x450, 0x00DB);
bcostm 6:e1d9da7fe856 363
bcostm 6:e1d9da7fe856 364 /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
bcostm 6:e1d9da7fe856 365 counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB);
bcostm 6:e1d9da7fe856 366
bcostm 6:e1d9da7fe856 367 /* Disable IN1L, IN1R, Enable IN2L, IN2R, Thermal sensor & shutdown */
bcostm 6:e1d9da7fe856 368 counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x63A0);
bcostm 6:e1d9da7fe856 369
bcostm 6:e1d9da7fe856 370 /* Enable the DMIC2(Left) to AIF1 Timeslot 0 (Left) mixer path */
bcostm 6:e1d9da7fe856 371 counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002);
bcostm 6:e1d9da7fe856 372
bcostm 6:e1d9da7fe856 373 /* Enable the DMIC2(Right) to AIF1 Timeslot 0 (Right) mixer path */
bcostm 6:e1d9da7fe856 374 counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002);
bcostm 6:e1d9da7fe856 375
bcostm 6:e1d9da7fe856 376 /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */
bcostm 6:e1d9da7fe856 377 counter += CODEC_IO_Write(DeviceAddr, 0x608, 0x0002);
bcostm 6:e1d9da7fe856 378
bcostm 6:e1d9da7fe856 379 /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */
bcostm 6:e1d9da7fe856 380 counter += CODEC_IO_Write(DeviceAddr, 0x609, 0x0002);
bcostm 6:e1d9da7fe856 381
bcostm 6:e1d9da7fe856 382 /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
bcostm 6:e1d9da7fe856 383 counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D);
bcostm 6:e1d9da7fe856 384 break;
bcostm 6:e1d9da7fe856 385 case INPUT_DEVICE_INPUT_LINE_2 :
bcostm 6:e1d9da7fe856 386 default:
bcostm 6:e1d9da7fe856 387 /* Actually, no other input devices supported */
bcostm 6:e1d9da7fe856 388 counter++;
bcostm 6:e1d9da7fe856 389 break;
bcostm 6:e1d9da7fe856 390 }
bcostm 6:e1d9da7fe856 391 }
bcostm 6:e1d9da7fe856 392 else
bcostm 6:e1d9da7fe856 393 {
bcostm 6:e1d9da7fe856 394 inputEnabled = 0;
bcostm 6:e1d9da7fe856 395 }
bcostm 6:e1d9da7fe856 396
bcostm 6:e1d9da7fe856 397 /* Clock Configurations */
bcostm 6:e1d9da7fe856 398 switch (AudioFreq)
bcostm 6:e1d9da7fe856 399 {
bcostm 6:e1d9da7fe856 400 case AUDIO_FREQUENCY_8K:
bcostm 6:e1d9da7fe856 401 /* AIF1 Sample Rate = 8 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 402 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003);
bcostm 6:e1d9da7fe856 403 break;
bcostm 6:e1d9da7fe856 404
bcostm 6:e1d9da7fe856 405 case AUDIO_FREQUENCY_16K:
bcostm 6:e1d9da7fe856 406 /* AIF1 Sample Rate = 16 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 407 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033);
bcostm 6:e1d9da7fe856 408 break;
bcostm 6:e1d9da7fe856 409
bcostm 6:e1d9da7fe856 410 case AUDIO_FREQUENCY_32K:
bcostm 6:e1d9da7fe856 411 /* AIF1 Sample Rate = 32 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 412 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0063);
bcostm 6:e1d9da7fe856 413 break;
bcostm 6:e1d9da7fe856 414
bcostm 6:e1d9da7fe856 415 case AUDIO_FREQUENCY_48K:
bcostm 6:e1d9da7fe856 416 /* AIF1 Sample Rate = 48 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 417 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
bcostm 6:e1d9da7fe856 418 break;
bcostm 6:e1d9da7fe856 419
bcostm 6:e1d9da7fe856 420 case AUDIO_FREQUENCY_96K:
bcostm 6:e1d9da7fe856 421 /* AIF1 Sample Rate = 96 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 422 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3);
bcostm 6:e1d9da7fe856 423 break;
bcostm 6:e1d9da7fe856 424
bcostm 6:e1d9da7fe856 425 case AUDIO_FREQUENCY_11K:
bcostm 6:e1d9da7fe856 426 /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 427 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013);
bcostm 6:e1d9da7fe856 428 break;
bcostm 6:e1d9da7fe856 429
bcostm 6:e1d9da7fe856 430 case AUDIO_FREQUENCY_22K:
bcostm 6:e1d9da7fe856 431 /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 432 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043);
bcostm 6:e1d9da7fe856 433 break;
bcostm 6:e1d9da7fe856 434
bcostm 6:e1d9da7fe856 435 case AUDIO_FREQUENCY_44K:
bcostm 6:e1d9da7fe856 436 /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 437 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073);
bcostm 6:e1d9da7fe856 438 break;
bcostm 6:e1d9da7fe856 439
bcostm 6:e1d9da7fe856 440 default:
bcostm 6:e1d9da7fe856 441 /* AIF1 Sample Rate = 48 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 442 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
bcostm 6:e1d9da7fe856 443 break;
bcostm 6:e1d9da7fe856 444 }
bcostm 6:e1d9da7fe856 445
bcostm 6:e1d9da7fe856 446 if(input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2)
bcostm 6:e1d9da7fe856 447 {
bcostm 6:e1d9da7fe856 448 /* AIF1 Word Length = 16-bits, AIF1 Format = DSP mode */
bcostm 6:e1d9da7fe856 449 counter += CODEC_IO_Write(DeviceAddr, 0x300, 0x4018);
bcostm 6:e1d9da7fe856 450 }
bcostm 6:e1d9da7fe856 451 else
bcostm 6:e1d9da7fe856 452 {
bcostm 6:e1d9da7fe856 453 /* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */
bcostm 6:e1d9da7fe856 454 counter += CODEC_IO_Write(DeviceAddr, 0x300, 0x4010);
bcostm 6:e1d9da7fe856 455 }
bcostm 6:e1d9da7fe856 456
bcostm 6:e1d9da7fe856 457 /* slave mode */
bcostm 6:e1d9da7fe856 458 counter += CODEC_IO_Write(DeviceAddr, 0x302, 0x0000);
bcostm 6:e1d9da7fe856 459
bcostm 6:e1d9da7fe856 460 /* Enable the DSP processing clock for AIF1, Enable the core clock */
bcostm 6:e1d9da7fe856 461 counter += CODEC_IO_Write(DeviceAddr, 0x208, 0x000A);
bcostm 6:e1d9da7fe856 462
bcostm 6:e1d9da7fe856 463 /* Enable AIF1 Clock, AIF1 Clock Source = MCLK1 pin */
bcostm 6:e1d9da7fe856 464 counter += CODEC_IO_Write(DeviceAddr, 0x200, 0x0001);
bcostm 6:e1d9da7fe856 465
bcostm 6:e1d9da7fe856 466 if (output_device > 0) /* Audio output selected */
bcostm 6:e1d9da7fe856 467 {
bcostm 6:e1d9da7fe856 468 /* Analog Output Configuration */
bcostm 6:e1d9da7fe856 469
bcostm 6:e1d9da7fe856 470 /* Enable SPKRVOL PGA, Enable SPKMIXR, Enable SPKLVOL PGA, Enable SPKMIXL */
bcostm 6:e1d9da7fe856 471 counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0300);
bcostm 6:e1d9da7fe856 472
bcostm 6:e1d9da7fe856 473 /* Left Speaker Mixer Volume = 0dB */
bcostm 6:e1d9da7fe856 474 counter += CODEC_IO_Write(DeviceAddr, 0x22, 0x0000);
bcostm 6:e1d9da7fe856 475
bcostm 6:e1d9da7fe856 476 /* Speaker output mode = Class D, Right Speaker Mixer Volume = 0dB ((0x23, 0x0100) = class AB)*/
bcostm 6:e1d9da7fe856 477 counter += CODEC_IO_Write(DeviceAddr, 0x23, 0x0000);
bcostm 6:e1d9da7fe856 478
bcostm 6:e1d9da7fe856 479 /* Unmute DAC2 (Left) to Left Speaker Mixer (SPKMIXL) path,
bcostm 6:e1d9da7fe856 480 Unmute DAC2 (Right) to Right Speaker Mixer (SPKMIXR) path */
bcostm 6:e1d9da7fe856 481 counter += CODEC_IO_Write(DeviceAddr, 0x36, 0x0300);
bcostm 6:e1d9da7fe856 482
bcostm 6:e1d9da7fe856 483 /* Enable bias generator, Enable VMID, Enable SPKOUTL, Enable SPKOUTR */
bcostm 6:e1d9da7fe856 484 counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x3003);
bcostm 6:e1d9da7fe856 485
bcostm 6:e1d9da7fe856 486 /* Headphone/Speaker Enable */
bcostm 6:e1d9da7fe856 487
bcostm 6:e1d9da7fe856 488 if (input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2)
bcostm 6:e1d9da7fe856 489 {
bcostm 6:e1d9da7fe856 490 /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslots 0 and 1 */
bcostm 6:e1d9da7fe856 491 counter += CODEC_IO_Write(DeviceAddr, 0x51, 0x0205);
bcostm 6:e1d9da7fe856 492 }
bcostm 6:e1d9da7fe856 493 else
bcostm 6:e1d9da7fe856 494 {
bcostm 6:e1d9da7fe856 495 /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslot 0 */
bcostm 6:e1d9da7fe856 496 counter += CODEC_IO_Write(DeviceAddr, 0x51, 0x0005);
bcostm 6:e1d9da7fe856 497 }
bcostm 6:e1d9da7fe856 498
bcostm 6:e1d9da7fe856 499 /* Enable bias generator, Enable VMID, Enable HPOUT1 (Left) and Enable HPOUT1 (Right) input stages */
bcostm 6:e1d9da7fe856 500 /* idem for Speaker */
bcostm 6:e1d9da7fe856 501 power_mgnt_reg_1 |= 0x0303 | 0x3003;
bcostm 6:e1d9da7fe856 502 counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
bcostm 6:e1d9da7fe856 503
bcostm 6:e1d9da7fe856 504 /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate stages */
bcostm 6:e1d9da7fe856 505 counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x0022);
bcostm 6:e1d9da7fe856 506
bcostm 6:e1d9da7fe856 507 /* Enable Charge Pump */
bcostm 6:e1d9da7fe856 508 counter += CODEC_IO_Write(DeviceAddr, 0x4C, 0x9F25);
bcostm 6:e1d9da7fe856 509
bcostm 6:e1d9da7fe856 510 /* Add Delay */
bcostm 6:e1d9da7fe856 511 AUDIO_IO_Delay(15);
bcostm 6:e1d9da7fe856 512
bcostm 6:e1d9da7fe856 513 /* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */
bcostm 6:e1d9da7fe856 514 counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0001);
bcostm 6:e1d9da7fe856 515
bcostm 6:e1d9da7fe856 516 /* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */
bcostm 6:e1d9da7fe856 517 counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0001);
bcostm 6:e1d9da7fe856 518
bcostm 6:e1d9da7fe856 519 /* Enable Left Output Mixer (MIXOUTL), Enable Right Output Mixer (MIXOUTR) */
bcostm 6:e1d9da7fe856 520 /* idem for SPKOUTL and SPKOUTR */
bcostm 6:e1d9da7fe856 521 counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0030 | 0x0300);
bcostm 6:e1d9da7fe856 522
bcostm 6:e1d9da7fe856 523 /* Enable DC Servo and trigger start-up mode on left and right channels */
bcostm 6:e1d9da7fe856 524 counter += CODEC_IO_Write(DeviceAddr, 0x54, 0x0033);
bcostm 6:e1d9da7fe856 525
bcostm 6:e1d9da7fe856 526 /* Add Delay */
bcostm 6:e1d9da7fe856 527 AUDIO_IO_Delay(250);
bcostm 6:e1d9da7fe856 528
bcostm 6:e1d9da7fe856 529 /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate and output stages. Remove clamps */
bcostm 6:e1d9da7fe856 530 counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x00EE);
bcostm 6:e1d9da7fe856 531
bcostm 6:e1d9da7fe856 532 /* Unmutes */
bcostm 6:e1d9da7fe856 533
bcostm 6:e1d9da7fe856 534 /* Unmute DAC 1 (Left) */
bcostm 6:e1d9da7fe856 535 counter += CODEC_IO_Write(DeviceAddr, 0x610, 0x00C0);
bcostm 6:e1d9da7fe856 536
bcostm 6:e1d9da7fe856 537 /* Unmute DAC 1 (Right) */
bcostm 6:e1d9da7fe856 538 counter += CODEC_IO_Write(DeviceAddr, 0x611, 0x00C0);
bcostm 6:e1d9da7fe856 539
bcostm 6:e1d9da7fe856 540 /* Unmute the AIF1 Timeslot 0 DAC path */
bcostm 6:e1d9da7fe856 541 counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000);
bcostm 6:e1d9da7fe856 542
bcostm 6:e1d9da7fe856 543 /* Unmute DAC 2 (Left) */
bcostm 6:e1d9da7fe856 544 counter += CODEC_IO_Write(DeviceAddr, 0x612, 0x00C0);
bcostm 6:e1d9da7fe856 545
bcostm 6:e1d9da7fe856 546 /* Unmute DAC 2 (Right) */
bcostm 6:e1d9da7fe856 547 counter += CODEC_IO_Write(DeviceAddr, 0x613, 0x00C0);
bcostm 6:e1d9da7fe856 548
bcostm 6:e1d9da7fe856 549 /* Unmute the AIF1 Timeslot 1 DAC2 path */
bcostm 6:e1d9da7fe856 550 counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0000);
bcostm 6:e1d9da7fe856 551
bcostm 6:e1d9da7fe856 552 /* Volume Control */
bcostm 6:e1d9da7fe856 553 wm8994_SetVolume(DeviceAddr, Volume);
bcostm 6:e1d9da7fe856 554 }
bcostm 6:e1d9da7fe856 555
bcostm 6:e1d9da7fe856 556 if (input_device > 0) /* Audio input selected */
bcostm 6:e1d9da7fe856 557 {
bcostm 6:e1d9da7fe856 558 if ((input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_1) || (input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_2))
bcostm 6:e1d9da7fe856 559 {
bcostm 6:e1d9da7fe856 560 /* Enable Microphone bias 1 generator, Enable VMID */
bcostm 6:e1d9da7fe856 561 power_mgnt_reg_1 |= 0x0013;
bcostm 6:e1d9da7fe856 562 counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
bcostm 6:e1d9da7fe856 563
bcostm 6:e1d9da7fe856 564 /* ADC oversample enable */
bcostm 6:e1d9da7fe856 565 counter += CODEC_IO_Write(DeviceAddr, 0x620, 0x0002);
bcostm 6:e1d9da7fe856 566
bcostm 6:e1d9da7fe856 567 /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
bcostm 6:e1d9da7fe856 568 counter += CODEC_IO_Write(DeviceAddr, 0x411, 0x3800);
bcostm 6:e1d9da7fe856 569 }
bcostm 6:e1d9da7fe856 570 else if(input_device == INPUT_DEVICE_DIGITAL_MIC1_MIC2)
bcostm 6:e1d9da7fe856 571 {
bcostm 6:e1d9da7fe856 572 /* Enable Microphone bias 1 generator, Enable VMID */
bcostm 6:e1d9da7fe856 573 power_mgnt_reg_1 |= 0x0013;
bcostm 6:e1d9da7fe856 574 counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
bcostm 6:e1d9da7fe856 575
bcostm 6:e1d9da7fe856 576 /* ADC oversample enable */
bcostm 6:e1d9da7fe856 577 counter += CODEC_IO_Write(DeviceAddr, 0x620, 0x0002);
bcostm 6:e1d9da7fe856 578
bcostm 6:e1d9da7fe856 579 /* AIF ADC1 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
bcostm 6:e1d9da7fe856 580 counter += CODEC_IO_Write(DeviceAddr, 0x410, 0x1800);
bcostm 6:e1d9da7fe856 581
bcostm 6:e1d9da7fe856 582 /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
bcostm 6:e1d9da7fe856 583 counter += CODEC_IO_Write(DeviceAddr, 0x411, 0x1800);
bcostm 6:e1d9da7fe856 584 }
bcostm 6:e1d9da7fe856 585 else if ((input_device == INPUT_DEVICE_INPUT_LINE_1) || (input_device == INPUT_DEVICE_INPUT_LINE_2))
bcostm 6:e1d9da7fe856 586 {
bcostm 6:e1d9da7fe856 587
bcostm 6:e1d9da7fe856 588 /* Disable mute on IN1L, IN1L Volume = +0dB */
bcostm 6:e1d9da7fe856 589 counter += CODEC_IO_Write(DeviceAddr, 0x18, 0x000B);
bcostm 6:e1d9da7fe856 590
bcostm 6:e1d9da7fe856 591 /* Disable mute on IN1R, IN1R Volume = +0dB */
bcostm 6:e1d9da7fe856 592 counter += CODEC_IO_Write(DeviceAddr, 0x1A, 0x000B);
bcostm 6:e1d9da7fe856 593
bcostm 6:e1d9da7fe856 594 /* AIF ADC1 HPF enable, HPF cut = hifi mode fc=4Hz at fs=48kHz */
bcostm 6:e1d9da7fe856 595 counter += CODEC_IO_Write(DeviceAddr, 0x410, 0x1800);
bcostm 6:e1d9da7fe856 596 }
bcostm 6:e1d9da7fe856 597 /* Volume Control */
bcostm 6:e1d9da7fe856 598 wm8994_SetVolume(DeviceAddr, Volume);
bcostm 6:e1d9da7fe856 599 }
bcostm 6:e1d9da7fe856 600 /* Return communication control value */
bcostm 6:e1d9da7fe856 601 return counter;
bcostm 6:e1d9da7fe856 602 }
bcostm 6:e1d9da7fe856 603
bcostm 6:e1d9da7fe856 604 /**
bcostm 6:e1d9da7fe856 605 * @brief Deinitializes the audio codec.
bcostm 6:e1d9da7fe856 606 * @param None
bcostm 6:e1d9da7fe856 607 * @retval None
bcostm 6:e1d9da7fe856 608 */
bcostm 6:e1d9da7fe856 609 void wm8994_DeInit(void)
bcostm 6:e1d9da7fe856 610 {
bcostm 6:e1d9da7fe856 611 /* Deinitialize Audio Codec interface */
bcostm 6:e1d9da7fe856 612 AUDIO_IO_DeInit();
bcostm 6:e1d9da7fe856 613 }
bcostm 6:e1d9da7fe856 614
bcostm 6:e1d9da7fe856 615 /**
bcostm 6:e1d9da7fe856 616 * @brief Get the WM8994 ID.
bcostm 6:e1d9da7fe856 617 * @param DeviceAddr: Device address on communication Bus.
bcostm 6:e1d9da7fe856 618 * @retval The WM8994 ID
bcostm 6:e1d9da7fe856 619 */
bcostm 6:e1d9da7fe856 620 uint32_t wm8994_ReadID(uint16_t DeviceAddr)
bcostm 6:e1d9da7fe856 621 {
bcostm 6:e1d9da7fe856 622 /* Initialize the Control interface of the Audio Codec */
bcostm 6:e1d9da7fe856 623 AUDIO_IO_Init();
bcostm 6:e1d9da7fe856 624
bcostm 6:e1d9da7fe856 625 return ((uint32_t)AUDIO_IO_Read(DeviceAddr, WM8994_CHIPID_ADDR));
bcostm 6:e1d9da7fe856 626 }
bcostm 6:e1d9da7fe856 627
bcostm 6:e1d9da7fe856 628 /**
bcostm 6:e1d9da7fe856 629 * @brief Start the audio Codec play feature.
bcostm 6:e1d9da7fe856 630 * @note For this codec no Play options are required.
bcostm 6:e1d9da7fe856 631 * @param DeviceAddr: Device address on communication Bus.
bcostm 6:e1d9da7fe856 632 * @retval 0 if correct communication, else wrong communication
bcostm 6:e1d9da7fe856 633 */
bcostm 6:e1d9da7fe856 634 uint32_t wm8994_Play(uint16_t DeviceAddr, uint16_t* pBuffer, uint16_t Size)
bcostm 6:e1d9da7fe856 635 {
bcostm 6:e1d9da7fe856 636 uint32_t counter = 0;
bcostm 6:e1d9da7fe856 637
bcostm 6:e1d9da7fe856 638 /* Resumes the audio file playing */
bcostm 6:e1d9da7fe856 639 /* Unmute the output first */
bcostm 6:e1d9da7fe856 640 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
bcostm 6:e1d9da7fe856 641
bcostm 6:e1d9da7fe856 642 return counter;
bcostm 6:e1d9da7fe856 643 }
bcostm 6:e1d9da7fe856 644
bcostm 6:e1d9da7fe856 645 /**
bcostm 6:e1d9da7fe856 646 * @brief Pauses playing on the audio codec.
bcostm 6:e1d9da7fe856 647 * @param DeviceAddr: Device address on communication Bus.
bcostm 6:e1d9da7fe856 648 * @retval 0 if correct communication, else wrong communication
bcostm 6:e1d9da7fe856 649 */
bcostm 6:e1d9da7fe856 650 uint32_t wm8994_Pause(uint16_t DeviceAddr)
bcostm 6:e1d9da7fe856 651 {
bcostm 6:e1d9da7fe856 652 uint32_t counter = 0;
bcostm 6:e1d9da7fe856 653
bcostm 6:e1d9da7fe856 654 /* Pause the audio file playing */
bcostm 6:e1d9da7fe856 655 /* Mute the output first */
bcostm 6:e1d9da7fe856 656 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
bcostm 6:e1d9da7fe856 657
bcostm 6:e1d9da7fe856 658 /* Put the Codec in Power save mode */
bcostm 6:e1d9da7fe856 659 counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x01);
bcostm 6:e1d9da7fe856 660
bcostm 6:e1d9da7fe856 661 return counter;
bcostm 6:e1d9da7fe856 662 }
bcostm 6:e1d9da7fe856 663
bcostm 6:e1d9da7fe856 664 /**
bcostm 6:e1d9da7fe856 665 * @brief Resumes playing on the audio codec.
bcostm 6:e1d9da7fe856 666 * @param DeviceAddr: Device address on communication Bus.
bcostm 6:e1d9da7fe856 667 * @retval 0 if correct communication, else wrong communication
bcostm 6:e1d9da7fe856 668 */
bcostm 6:e1d9da7fe856 669 uint32_t wm8994_Resume(uint16_t DeviceAddr)
bcostm 6:e1d9da7fe856 670 {
bcostm 6:e1d9da7fe856 671 uint32_t counter = 0;
bcostm 6:e1d9da7fe856 672
bcostm 6:e1d9da7fe856 673 /* Resumes the audio file playing */
bcostm 6:e1d9da7fe856 674 /* Unmute the output first */
bcostm 6:e1d9da7fe856 675 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
bcostm 6:e1d9da7fe856 676
bcostm 6:e1d9da7fe856 677 return counter;
bcostm 6:e1d9da7fe856 678 }
bcostm 6:e1d9da7fe856 679
bcostm 6:e1d9da7fe856 680 /**
bcostm 6:e1d9da7fe856 681 * @brief Stops audio Codec playing. It powers down the codec.
bcostm 6:e1d9da7fe856 682 * @param DeviceAddr: Device address on communication Bus.
bcostm 6:e1d9da7fe856 683 * @param CodecPdwnMode: selects the power down mode.
bcostm 6:e1d9da7fe856 684 * - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this
bcostm 6:e1d9da7fe856 685 * mode the codec keeps the previous initialization
bcostm 6:e1d9da7fe856 686 * (no need to re-Initialize the codec registers).
bcostm 6:e1d9da7fe856 687 * - CODEC_PDWN_HW: Physically power down the codec. When resuming from this
bcostm 6:e1d9da7fe856 688 * mode, the codec is set to default configuration
bcostm 6:e1d9da7fe856 689 * (user should re-Initialize the codec in order to
bcostm 6:e1d9da7fe856 690 * play again the audio stream).
bcostm 6:e1d9da7fe856 691 * @retval 0 if correct communication, else wrong communication
bcostm 6:e1d9da7fe856 692 */
bcostm 6:e1d9da7fe856 693 uint32_t wm8994_Stop(uint16_t DeviceAddr, uint32_t CodecPdwnMode)
bcostm 6:e1d9da7fe856 694 {
bcostm 6:e1d9da7fe856 695 uint32_t counter = 0;
bcostm 6:e1d9da7fe856 696
bcostm 6:e1d9da7fe856 697 if (outputEnabled != 0)
bcostm 6:e1d9da7fe856 698 {
bcostm 6:e1d9da7fe856 699 /* Mute the output first */
bcostm 6:e1d9da7fe856 700 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
bcostm 6:e1d9da7fe856 701
bcostm 6:e1d9da7fe856 702 if (CodecPdwnMode == CODEC_PDWN_SW)
bcostm 6:e1d9da7fe856 703 {
bcostm 6:e1d9da7fe856 704 /* Only output mute required*/
bcostm 6:e1d9da7fe856 705 }
bcostm 6:e1d9da7fe856 706 else /* CODEC_PDWN_HW */
bcostm 6:e1d9da7fe856 707 {
bcostm 6:e1d9da7fe856 708 /* Mute the AIF1 Timeslot 0 DAC1 path */
bcostm 6:e1d9da7fe856 709 counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200);
bcostm 6:e1d9da7fe856 710
bcostm 6:e1d9da7fe856 711 /* Mute the AIF1 Timeslot 1 DAC2 path */
bcostm 6:e1d9da7fe856 712 counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200);
bcostm 6:e1d9da7fe856 713
bcostm 6:e1d9da7fe856 714 /* Disable DAC1L_TO_HPOUT1L */
bcostm 6:e1d9da7fe856 715 counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0000);
bcostm 6:e1d9da7fe856 716
bcostm 6:e1d9da7fe856 717 /* Disable DAC1R_TO_HPOUT1R */
bcostm 6:e1d9da7fe856 718 counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0000);
bcostm 6:e1d9da7fe856 719
bcostm 6:e1d9da7fe856 720 /* Disable DAC1 and DAC2 */
bcostm 6:e1d9da7fe856 721 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0000);
bcostm 6:e1d9da7fe856 722
bcostm 6:e1d9da7fe856 723 /* Reset Codec by writing in 0x0000 address register */
bcostm 6:e1d9da7fe856 724 counter += CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000);
bcostm 6:e1d9da7fe856 725
bcostm 6:e1d9da7fe856 726 outputEnabled = 0;
bcostm 6:e1d9da7fe856 727 }
bcostm 6:e1d9da7fe856 728 }
bcostm 6:e1d9da7fe856 729 return counter;
bcostm 6:e1d9da7fe856 730 }
bcostm 6:e1d9da7fe856 731
bcostm 6:e1d9da7fe856 732 /**
bcostm 6:e1d9da7fe856 733 * @brief Sets higher or lower the codec volume level.
bcostm 6:e1d9da7fe856 734 * @param DeviceAddr: Device address on communication Bus.
bcostm 6:e1d9da7fe856 735 * @param Volume: a byte value from 0 to 255 (refer to codec registers
bcostm 6:e1d9da7fe856 736 * description for more details).
bcostm 6:e1d9da7fe856 737 * @retval 0 if correct communication, else wrong communication
bcostm 6:e1d9da7fe856 738 */
bcostm 6:e1d9da7fe856 739 uint32_t wm8994_SetVolume(uint16_t DeviceAddr, uint8_t Volume)
bcostm 6:e1d9da7fe856 740 {
bcostm 6:e1d9da7fe856 741 uint32_t counter = 0;
bcostm 6:e1d9da7fe856 742 uint8_t convertedvol = VOLUME_CONVERT(Volume);
bcostm 6:e1d9da7fe856 743
bcostm 6:e1d9da7fe856 744 /* Output volume */
bcostm 6:e1d9da7fe856 745 if (outputEnabled != 0)
bcostm 6:e1d9da7fe856 746 {
bcostm 6:e1d9da7fe856 747 if(convertedvol > 0x3E)
bcostm 6:e1d9da7fe856 748 {
bcostm 6:e1d9da7fe856 749 /* Unmute audio codec */
bcostm 6:e1d9da7fe856 750 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
bcostm 6:e1d9da7fe856 751
bcostm 6:e1d9da7fe856 752 /* Left Headphone Volume */
bcostm 6:e1d9da7fe856 753 counter += CODEC_IO_Write(DeviceAddr, 0x1C, 0x3F | 0x140);
bcostm 6:e1d9da7fe856 754
bcostm 6:e1d9da7fe856 755 /* Right Headphone Volume */
bcostm 6:e1d9da7fe856 756 counter += CODEC_IO_Write(DeviceAddr, 0x1D, 0x3F | 0x140);
bcostm 6:e1d9da7fe856 757
bcostm 6:e1d9da7fe856 758 /* Left Speaker Volume */
bcostm 6:e1d9da7fe856 759 counter += CODEC_IO_Write(DeviceAddr, 0x26, 0x3F | 0x140);
bcostm 6:e1d9da7fe856 760
bcostm 6:e1d9da7fe856 761 /* Right Speaker Volume */
bcostm 6:e1d9da7fe856 762 counter += CODEC_IO_Write(DeviceAddr, 0x27, 0x3F | 0x140);
bcostm 6:e1d9da7fe856 763 }
bcostm 6:e1d9da7fe856 764 else if (Volume == 0)
bcostm 6:e1d9da7fe856 765 {
bcostm 6:e1d9da7fe856 766 /* Mute audio codec */
bcostm 6:e1d9da7fe856 767 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
bcostm 6:e1d9da7fe856 768 }
bcostm 6:e1d9da7fe856 769 else
bcostm 6:e1d9da7fe856 770 {
bcostm 6:e1d9da7fe856 771 /* Unmute audio codec */
bcostm 6:e1d9da7fe856 772 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
bcostm 6:e1d9da7fe856 773
bcostm 6:e1d9da7fe856 774 /* Left Headphone Volume */
bcostm 6:e1d9da7fe856 775 counter += CODEC_IO_Write(DeviceAddr, 0x1C, convertedvol | 0x140);
bcostm 6:e1d9da7fe856 776
bcostm 6:e1d9da7fe856 777 /* Right Headphone Volume */
bcostm 6:e1d9da7fe856 778 counter += CODEC_IO_Write(DeviceAddr, 0x1D, convertedvol | 0x140);
bcostm 6:e1d9da7fe856 779
bcostm 6:e1d9da7fe856 780 /* Left Speaker Volume */
bcostm 6:e1d9da7fe856 781 counter += CODEC_IO_Write(DeviceAddr, 0x26, convertedvol | 0x140);
bcostm 6:e1d9da7fe856 782
bcostm 6:e1d9da7fe856 783 /* Right Speaker Volume */
bcostm 6:e1d9da7fe856 784 counter += CODEC_IO_Write(DeviceAddr, 0x27, convertedvol | 0x140);
bcostm 6:e1d9da7fe856 785 }
bcostm 6:e1d9da7fe856 786 }
bcostm 6:e1d9da7fe856 787
bcostm 6:e1d9da7fe856 788 /* Input volume */
bcostm 6:e1d9da7fe856 789 if (inputEnabled != 0)
bcostm 6:e1d9da7fe856 790 {
bcostm 6:e1d9da7fe856 791 convertedvol = VOLUME_IN_CONVERT(Volume);
bcostm 6:e1d9da7fe856 792
bcostm 6:e1d9da7fe856 793 /* Left AIF1 ADC1 volume */
bcostm 6:e1d9da7fe856 794 counter += CODEC_IO_Write(DeviceAddr, 0x400, convertedvol | 0x100);
bcostm 6:e1d9da7fe856 795
bcostm 6:e1d9da7fe856 796 /* Right AIF1 ADC1 volume */
bcostm 6:e1d9da7fe856 797 counter += CODEC_IO_Write(DeviceAddr, 0x401, convertedvol | 0x100);
bcostm 6:e1d9da7fe856 798
bcostm 6:e1d9da7fe856 799 /* Left AIF1 ADC2 volume */
bcostm 6:e1d9da7fe856 800 counter += CODEC_IO_Write(DeviceAddr, 0x404, convertedvol | 0x100);
bcostm 6:e1d9da7fe856 801
bcostm 6:e1d9da7fe856 802 /* Right AIF1 ADC2 volume */
bcostm 6:e1d9da7fe856 803 counter += CODEC_IO_Write(DeviceAddr, 0x405, convertedvol | 0x100);
bcostm 6:e1d9da7fe856 804 }
bcostm 6:e1d9da7fe856 805 return counter;
bcostm 6:e1d9da7fe856 806 }
bcostm 6:e1d9da7fe856 807
bcostm 6:e1d9da7fe856 808 /**
bcostm 6:e1d9da7fe856 809 * @brief Enables or disables the mute feature on the audio codec.
bcostm 6:e1d9da7fe856 810 * @param DeviceAddr: Device address on communication Bus.
bcostm 6:e1d9da7fe856 811 * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
bcostm 6:e1d9da7fe856 812 * mute mode.
bcostm 6:e1d9da7fe856 813 * @retval 0 if correct communication, else wrong communication
bcostm 6:e1d9da7fe856 814 */
bcostm 6:e1d9da7fe856 815 uint32_t wm8994_SetMute(uint16_t DeviceAddr, uint32_t Cmd)
bcostm 6:e1d9da7fe856 816 {
bcostm 6:e1d9da7fe856 817 uint32_t counter = 0;
bcostm 6:e1d9da7fe856 818
bcostm 6:e1d9da7fe856 819 if (outputEnabled != 0)
bcostm 6:e1d9da7fe856 820 {
bcostm 6:e1d9da7fe856 821 /* Set the Mute mode */
bcostm 6:e1d9da7fe856 822 if(Cmd == AUDIO_MUTE_ON)
bcostm 6:e1d9da7fe856 823 {
bcostm 6:e1d9da7fe856 824 /* Soft Mute the AIF1 Timeslot 0 DAC1 path L&R */
bcostm 6:e1d9da7fe856 825 counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200);
bcostm 6:e1d9da7fe856 826
bcostm 6:e1d9da7fe856 827 /* Soft Mute the AIF1 Timeslot 1 DAC2 path L&R */
bcostm 6:e1d9da7fe856 828 counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200);
bcostm 6:e1d9da7fe856 829 }
bcostm 6:e1d9da7fe856 830 else /* AUDIO_MUTE_OFF Disable the Mute */
bcostm 6:e1d9da7fe856 831 {
bcostm 6:e1d9da7fe856 832 /* Unmute the AIF1 Timeslot 0 DAC1 path L&R */
bcostm 6:e1d9da7fe856 833 counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000);
bcostm 6:e1d9da7fe856 834
bcostm 6:e1d9da7fe856 835 /* Unmute the AIF1 Timeslot 1 DAC2 path L&R */
bcostm 6:e1d9da7fe856 836 counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0000);
bcostm 6:e1d9da7fe856 837 }
bcostm 6:e1d9da7fe856 838 }
bcostm 6:e1d9da7fe856 839 return counter;
bcostm 6:e1d9da7fe856 840 }
bcostm 6:e1d9da7fe856 841
bcostm 6:e1d9da7fe856 842 /**
bcostm 6:e1d9da7fe856 843 * @brief Switch dynamically (while audio file is played) the output target
bcostm 6:e1d9da7fe856 844 * (speaker or headphone).
bcostm 6:e1d9da7fe856 845 * @param DeviceAddr: Device address on communication Bus.
bcostm 6:e1d9da7fe856 846 * @param Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER,
bcostm 6:e1d9da7fe856 847 * OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO
bcostm 6:e1d9da7fe856 848 * @retval 0 if correct communication, else wrong communication
bcostm 6:e1d9da7fe856 849 */
bcostm 6:e1d9da7fe856 850 uint32_t wm8994_SetOutputMode(uint16_t DeviceAddr, uint8_t Output)
bcostm 6:e1d9da7fe856 851 {
bcostm 6:e1d9da7fe856 852 uint32_t counter = 0;
bcostm 6:e1d9da7fe856 853
bcostm 6:e1d9da7fe856 854 switch (Output)
bcostm 6:e1d9da7fe856 855 {
bcostm 6:e1d9da7fe856 856 case OUTPUT_DEVICE_SPEAKER:
bcostm 6:e1d9da7fe856 857 /* Enable DAC1 (Left), Enable DAC1 (Right),
bcostm 6:e1d9da7fe856 858 Disable DAC2 (Left), Disable DAC2 (Right)*/
bcostm 6:e1d9da7fe856 859 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C);
bcostm 6:e1d9da7fe856 860
bcostm 6:e1d9da7fe856 861 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 6:e1d9da7fe856 862 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000);
bcostm 6:e1d9da7fe856 863
bcostm 6:e1d9da7fe856 864 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 6:e1d9da7fe856 865 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000);
bcostm 6:e1d9da7fe856 866
bcostm 6:e1d9da7fe856 867 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 6:e1d9da7fe856 868 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
bcostm 6:e1d9da7fe856 869
bcostm 6:e1d9da7fe856 870 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 6:e1d9da7fe856 871 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
bcostm 6:e1d9da7fe856 872 break;
bcostm 6:e1d9da7fe856 873
bcostm 6:e1d9da7fe856 874 case OUTPUT_DEVICE_HEADPHONE:
bcostm 6:e1d9da7fe856 875 /* Disable DAC1 (Left), Disable DAC1 (Right),
bcostm 6:e1d9da7fe856 876 Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 6:e1d9da7fe856 877 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
bcostm 6:e1d9da7fe856 878
bcostm 6:e1d9da7fe856 879 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 6:e1d9da7fe856 880 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
bcostm 6:e1d9da7fe856 881
bcostm 6:e1d9da7fe856 882 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 6:e1d9da7fe856 883 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
bcostm 6:e1d9da7fe856 884
bcostm 6:e1d9da7fe856 885 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 6:e1d9da7fe856 886 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
bcostm 6:e1d9da7fe856 887
bcostm 6:e1d9da7fe856 888 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 6:e1d9da7fe856 889 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
bcostm 6:e1d9da7fe856 890 break;
bcostm 6:e1d9da7fe856 891
bcostm 6:e1d9da7fe856 892 case OUTPUT_DEVICE_BOTH:
bcostm 6:e1d9da7fe856 893 /* Enable DAC1 (Left), Enable DAC1 (Right),
bcostm 6:e1d9da7fe856 894 also Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 6:e1d9da7fe856 895 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
bcostm 6:e1d9da7fe856 896
bcostm 6:e1d9da7fe856 897 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 6:e1d9da7fe856 898 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
bcostm 6:e1d9da7fe856 899
bcostm 6:e1d9da7fe856 900 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 6:e1d9da7fe856 901 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
bcostm 6:e1d9da7fe856 902
bcostm 6:e1d9da7fe856 903 /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 6:e1d9da7fe856 904 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
bcostm 6:e1d9da7fe856 905
bcostm 6:e1d9da7fe856 906 /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 6:e1d9da7fe856 907 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
bcostm 6:e1d9da7fe856 908 break;
bcostm 6:e1d9da7fe856 909
bcostm 6:e1d9da7fe856 910 default:
bcostm 6:e1d9da7fe856 911 /* Disable DAC1 (Left), Disable DAC1 (Right),
bcostm 6:e1d9da7fe856 912 Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 6:e1d9da7fe856 913 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
bcostm 6:e1d9da7fe856 914
bcostm 6:e1d9da7fe856 915 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 6:e1d9da7fe856 916 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
bcostm 6:e1d9da7fe856 917
bcostm 6:e1d9da7fe856 918 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 6:e1d9da7fe856 919 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
bcostm 6:e1d9da7fe856 920
bcostm 6:e1d9da7fe856 921 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 6:e1d9da7fe856 922 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
bcostm 6:e1d9da7fe856 923
bcostm 6:e1d9da7fe856 924 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 6:e1d9da7fe856 925 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
bcostm 6:e1d9da7fe856 926 break;
bcostm 6:e1d9da7fe856 927 }
bcostm 6:e1d9da7fe856 928 return counter;
bcostm 6:e1d9da7fe856 929 }
bcostm 6:e1d9da7fe856 930
bcostm 6:e1d9da7fe856 931 /**
bcostm 6:e1d9da7fe856 932 * @brief Sets new frequency.
bcostm 6:e1d9da7fe856 933 * @param DeviceAddr: Device address on communication Bus.
bcostm 6:e1d9da7fe856 934 * @param AudioFreq: Audio frequency used to play the audio stream.
bcostm 6:e1d9da7fe856 935 * @retval 0 if correct communication, else wrong communication
bcostm 6:e1d9da7fe856 936 */
bcostm 6:e1d9da7fe856 937 uint32_t wm8994_SetFrequency(uint16_t DeviceAddr, uint32_t AudioFreq)
bcostm 6:e1d9da7fe856 938 {
bcostm 6:e1d9da7fe856 939 uint32_t counter = 0;
bcostm 6:e1d9da7fe856 940
bcostm 6:e1d9da7fe856 941 /* Clock Configurations */
bcostm 6:e1d9da7fe856 942 switch (AudioFreq)
bcostm 6:e1d9da7fe856 943 {
bcostm 6:e1d9da7fe856 944 case AUDIO_FREQUENCY_8K:
bcostm 6:e1d9da7fe856 945 /* AIF1 Sample Rate = 8 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 946 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003);
bcostm 6:e1d9da7fe856 947 break;
bcostm 6:e1d9da7fe856 948
bcostm 6:e1d9da7fe856 949 case AUDIO_FREQUENCY_16K:
bcostm 6:e1d9da7fe856 950 /* AIF1 Sample Rate = 16 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 951 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033);
bcostm 6:e1d9da7fe856 952 break;
bcostm 6:e1d9da7fe856 953
bcostm 6:e1d9da7fe856 954 case AUDIO_FREQUENCY_48K:
bcostm 6:e1d9da7fe856 955 /* AIF1 Sample Rate = 48 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 956 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
bcostm 6:e1d9da7fe856 957 break;
bcostm 6:e1d9da7fe856 958
bcostm 6:e1d9da7fe856 959 case AUDIO_FREQUENCY_96K:
bcostm 6:e1d9da7fe856 960 /* AIF1 Sample Rate = 96 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 961 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3);
bcostm 6:e1d9da7fe856 962 break;
bcostm 6:e1d9da7fe856 963
bcostm 6:e1d9da7fe856 964 case AUDIO_FREQUENCY_11K:
bcostm 6:e1d9da7fe856 965 /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 966 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013);
bcostm 6:e1d9da7fe856 967 break;
bcostm 6:e1d9da7fe856 968
bcostm 6:e1d9da7fe856 969 case AUDIO_FREQUENCY_22K:
bcostm 6:e1d9da7fe856 970 /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 971 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043);
bcostm 6:e1d9da7fe856 972 break;
bcostm 6:e1d9da7fe856 973
bcostm 6:e1d9da7fe856 974 case AUDIO_FREQUENCY_44K:
bcostm 6:e1d9da7fe856 975 /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 976 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073);
bcostm 6:e1d9da7fe856 977 break;
bcostm 6:e1d9da7fe856 978
bcostm 6:e1d9da7fe856 979 default:
bcostm 6:e1d9da7fe856 980 /* AIF1 Sample Rate = 48 (KHz), ratio=256 */
bcostm 6:e1d9da7fe856 981 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
bcostm 6:e1d9da7fe856 982 break;
bcostm 6:e1d9da7fe856 983 }
bcostm 6:e1d9da7fe856 984 return counter;
bcostm 6:e1d9da7fe856 985 }
bcostm 6:e1d9da7fe856 986
bcostm 6:e1d9da7fe856 987 /**
bcostm 6:e1d9da7fe856 988 * @brief Resets wm8994 registers.
bcostm 6:e1d9da7fe856 989 * @param DeviceAddr: Device address on communication Bus.
bcostm 6:e1d9da7fe856 990 * @retval 0 if correct communication, else wrong communication
bcostm 6:e1d9da7fe856 991 */
bcostm 6:e1d9da7fe856 992 uint32_t wm8994_Reset(uint16_t DeviceAddr)
bcostm 6:e1d9da7fe856 993 {
bcostm 6:e1d9da7fe856 994 uint32_t counter = 0;
bcostm 6:e1d9da7fe856 995
bcostm 6:e1d9da7fe856 996 /* Reset Codec by writing in 0x0000 address register */
bcostm 6:e1d9da7fe856 997 counter = CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000);
bcostm 6:e1d9da7fe856 998 outputEnabled = 0;
bcostm 6:e1d9da7fe856 999 inputEnabled=0;
bcostm 6:e1d9da7fe856 1000
bcostm 6:e1d9da7fe856 1001 return counter;
bcostm 6:e1d9da7fe856 1002 }
bcostm 6:e1d9da7fe856 1003
bcostm 6:e1d9da7fe856 1004 /**
bcostm 6:e1d9da7fe856 1005 * @brief Writes/Read a single data.
bcostm 6:e1d9da7fe856 1006 * @param Addr: I2C address
bcostm 6:e1d9da7fe856 1007 * @param Reg: Reg address
bcostm 6:e1d9da7fe856 1008 * @param Value: Data to be written
bcostm 6:e1d9da7fe856 1009 * @retval None
bcostm 6:e1d9da7fe856 1010 */
bcostm 6:e1d9da7fe856 1011 static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value)
bcostm 6:e1d9da7fe856 1012 {
bcostm 6:e1d9da7fe856 1013 uint32_t result = 0;
bcostm 6:e1d9da7fe856 1014
bcostm 6:e1d9da7fe856 1015 AUDIO_IO_Write(Addr, Reg, Value);
bcostm 6:e1d9da7fe856 1016
bcostm 6:e1d9da7fe856 1017 #ifdef VERIFY_WRITTENDATA
bcostm 6:e1d9da7fe856 1018 /* Verify that the data has been correctly written */
bcostm 6:e1d9da7fe856 1019 result = (AUDIO_IO_Read(Addr, Reg) == Value)? 0:1;
bcostm 6:e1d9da7fe856 1020 #endif /* VERIFY_WRITTENDATA */
bcostm 6:e1d9da7fe856 1021
bcostm 6:e1d9da7fe856 1022 return result;
bcostm 6:e1d9da7fe856 1023 }
bcostm 6:e1d9da7fe856 1024
bcostm 6:e1d9da7fe856 1025 /**
bcostm 6:e1d9da7fe856 1026 * @}
bcostm 6:e1d9da7fe856 1027 */
bcostm 6:e1d9da7fe856 1028
bcostm 6:e1d9da7fe856 1029 /**
bcostm 6:e1d9da7fe856 1030 * @}
bcostm 6:e1d9da7fe856 1031 */
bcostm 6:e1d9da7fe856 1032
bcostm 6:e1d9da7fe856 1033 /**
bcostm 6:e1d9da7fe856 1034 * @}
bcostm 6:e1d9da7fe856 1035 */
bcostm 6:e1d9da7fe856 1036
bcostm 6:e1d9da7fe856 1037 /**
bcostm 6:e1d9da7fe856 1038 * @}
bcostm 6:e1d9da7fe856 1039 */
bcostm 6:e1d9da7fe856 1040
bcostm 6:e1d9da7fe856 1041 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/