nguyen nam / Mbed 2 deprecated BSP-DISCO_F746NG

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Dependencies:   mbed

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Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_qspi.c@8:56384bddaba5, 2017-02-23 (annotated)

Committer:
Jerome Coutant
Date:
Thu Feb 23 14:14:09 2017 +0100
Revision:
8:56384bddaba5
Parent:
6:e1d9da7fe856 
STM32Cube_FW_F7_V1.6.0 BSP_DISCO_F746NG

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bcostm 6:e1d9da7fe856 1 /**
bcostm 6:e1d9da7fe856 2 ******************************************************************************
bcostm 6:e1d9da7fe856 3 * @file stm32746g_discovery_qspi.c
bcostm 6:e1d9da7fe856 4 * @author MCD Application Team
Jerome Coutant 8:56384bddaba5 5 * @version V2.0.0
Jerome Coutant 8:56384bddaba5 6 * @date 30-December-2016
bcostm 6:e1d9da7fe856 7 * @brief This file includes a standard driver for the N25Q128A QSPI
bcostm 6:e1d9da7fe856 8 * memory mounted on STM32746G-Discovery board.
bcostm 6:e1d9da7fe856 9 @verbatim
bcostm 6:e1d9da7fe856 10 ==============================================================================
bcostm 6:e1d9da7fe856 11 ##### How to use this driver #####
bcostm 6:e1d9da7fe856 12 ==============================================================================
bcostm 6:e1d9da7fe856 13 [..]
bcostm 6:e1d9da7fe856 14 (#) This driver is used to drive the N25Q128A QSPI external
bcostm 6:e1d9da7fe856 15 memory mounted on STM32746G-Discovery board.
bcostm 6:e1d9da7fe856 16
bcostm 6:e1d9da7fe856 17 (#) This driver need a specific component driver (N25Q128A) to be included with.
bcostm 6:e1d9da7fe856 18
bcostm 6:e1d9da7fe856 19 (#) Initialization steps:
bcostm 6:e1d9da7fe856 20 (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This
bcostm 6:e1d9da7fe856 21 function includes the MSP layer hardware resources initialization and the
bcostm 6:e1d9da7fe856 22 QSPI interface with the external memory.
bcostm 6:e1d9da7fe856 23
bcostm 6:e1d9da7fe856 24 (#) QSPI memory operations
bcostm 6:e1d9da7fe856 25 (++) QSPI memory can be accessed with read/write operations once it is
bcostm 6:e1d9da7fe856 26 initialized.
bcostm 6:e1d9da7fe856 27 Read/write operation can be performed with AHB access using the functions
bcostm 6:e1d9da7fe856 28 BSP_QSPI_Read()/BSP_QSPI_Write().
bcostm 6:e1d9da7fe856 29 (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory.
bcostm 6:e1d9da7fe856 30 (see the QSPI memory data sheet)
bcostm 6:e1d9da7fe856 31 (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by
bcostm 6:e1d9da7fe856 32 specifying the block address. You can perform an erase operation of the whole
bcostm 6:e1d9da7fe856 33 chip by calling the function BSP_QSPI_Erase_Chip().
bcostm 6:e1d9da7fe856 34 (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory.
bcostm 6:e1d9da7fe856 35 (see the QSPI memory data sheet)
bcostm 6:e1d9da7fe856 36 @endverbatim
bcostm 6:e1d9da7fe856 37 ******************************************************************************
bcostm 6:e1d9da7fe856 38 * @attention
bcostm 6:e1d9da7fe856 39 *
bcostm 6:e1d9da7fe856 40 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bcostm 6:e1d9da7fe856 41 *
bcostm 6:e1d9da7fe856 42 * Redistribution and use in source and binary forms, with or without modification,
bcostm 6:e1d9da7fe856 43 * are permitted provided that the following conditions are met:
bcostm 6:e1d9da7fe856 44 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 6:e1d9da7fe856 45 * this list of conditions and the following disclaimer.
bcostm 6:e1d9da7fe856 46 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 6:e1d9da7fe856 47 * this list of conditions and the following disclaimer in the documentation
bcostm 6:e1d9da7fe856 48 * and/or other materials provided with the distribution.
bcostm 6:e1d9da7fe856 49 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 6:e1d9da7fe856 50 * may be used to endorse or promote products derived from this software
bcostm 6:e1d9da7fe856 51 * without specific prior written permission.
bcostm 6:e1d9da7fe856 52 *
bcostm 6:e1d9da7fe856 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 6:e1d9da7fe856 54 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 6:e1d9da7fe856 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 6:e1d9da7fe856 56 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 6:e1d9da7fe856 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 6:e1d9da7fe856 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 6:e1d9da7fe856 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 6:e1d9da7fe856 60 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 6:e1d9da7fe856 61 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 6:e1d9da7fe856 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 6:e1d9da7fe856 63 *
bcostm 6:e1d9da7fe856 64 ******************************************************************************
bcostm 6:e1d9da7fe856 65 */
bcostm 6:e1d9da7fe856 66
bcostm 6:e1d9da7fe856 67 /* Includes ------------------------------------------------------------------*/
bcostm 6:e1d9da7fe856 68 #include "stm32746g_discovery_qspi.h"
bcostm 6:e1d9da7fe856 69
bcostm 6:e1d9da7fe856 70 /** @addtogroup BSP
bcostm 6:e1d9da7fe856 71 * @{
bcostm 6:e1d9da7fe856 72 */
bcostm 6:e1d9da7fe856 73
bcostm 6:e1d9da7fe856 74 /** @addtogroup STM32746G_DISCOVERY
bcostm 6:e1d9da7fe856 75 * @{
bcostm 6:e1d9da7fe856 76 */
bcostm 6:e1d9da7fe856 77
bcostm 6:e1d9da7fe856 78 /** @defgroup STM32746G_DISCOVERY_QSPI STM32746G-Discovery QSPI
bcostm 6:e1d9da7fe856 79 * @{
bcostm 6:e1d9da7fe856 80 */
bcostm 6:e1d9da7fe856 81
bcostm 6:e1d9da7fe856 82
bcostm 6:e1d9da7fe856 83 /* Private variables ---------------------------------------------------------*/
bcostm 6:e1d9da7fe856 84
bcostm 6:e1d9da7fe856 85 /** @defgroup STM32746G_DISCOVERY_QSPI_Private_Variables STM32746G_DISCOVERY QSPI Private Variables
bcostm 6:e1d9da7fe856 86 * @{
bcostm 6:e1d9da7fe856 87 */
bcostm 6:e1d9da7fe856 88 QSPI_HandleTypeDef QSPIHandle;
bcostm 6:e1d9da7fe856 89
bcostm 6:e1d9da7fe856 90 /**
bcostm 6:e1d9da7fe856 91 * @}
bcostm 6:e1d9da7fe856 92 */
bcostm 6:e1d9da7fe856 93
bcostm 6:e1d9da7fe856 94
bcostm 6:e1d9da7fe856 95
bcostm 6:e1d9da7fe856 96 /* Private functions ---------------------------------------------------------*/
bcostm 6:e1d9da7fe856 97
bcostm 6:e1d9da7fe856 98 /** @defgroup STM32746G_DISCOVERY_QSPI_Private_Functions STM32746G_DISCOVERY QSPI Private Functions
bcostm 6:e1d9da7fe856 99 * @{
bcostm 6:e1d9da7fe856 100 */
bcostm 6:e1d9da7fe856 101 static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi);
bcostm 6:e1d9da7fe856 102 static uint8_t QSPI_DummyCyclesCfg (QSPI_HandleTypeDef *hqspi);
bcostm 6:e1d9da7fe856 103 static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi);
bcostm 6:e1d9da7fe856 104 static uint8_t QSPI_AutoPollingMemReady (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
bcostm 6:e1d9da7fe856 105
bcostm 6:e1d9da7fe856 106 /**
bcostm 6:e1d9da7fe856 107 * @}
bcostm 6:e1d9da7fe856 108 */
bcostm 6:e1d9da7fe856 109
bcostm 6:e1d9da7fe856 110 /** @defgroup STM32746G_DISCOVERY_QSPI_Exported_Functions STM32746G_DISCOVERY QSPI Exported Functions
bcostm 6:e1d9da7fe856 111 * @{
bcostm 6:e1d9da7fe856 112 */
bcostm 6:e1d9da7fe856 113
bcostm 6:e1d9da7fe856 114 /**
bcostm 6:e1d9da7fe856 115 * @brief Initializes the QSPI interface.
bcostm 6:e1d9da7fe856 116 * @retval QSPI memory status
bcostm 6:e1d9da7fe856 117 */
bcostm 6:e1d9da7fe856 118 uint8_t BSP_QSPI_Init(void)
bcostm 6:e1d9da7fe856 119 {
bcostm 6:e1d9da7fe856 120 QSPIHandle.Instance = QUADSPI;
bcostm 6:e1d9da7fe856 121
bcostm 6:e1d9da7fe856 122 /* Call the DeInit function to reset the driver */
bcostm 6:e1d9da7fe856 123 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
bcostm 6:e1d9da7fe856 124 {
bcostm 6:e1d9da7fe856 125 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 126 }
bcostm 6:e1d9da7fe856 127
bcostm 6:e1d9da7fe856 128 /* System level initialization */
bcostm 6:e1d9da7fe856 129 BSP_QSPI_MspInit(&QSPIHandle, NULL);
bcostm 6:e1d9da7fe856 130
bcostm 6:e1d9da7fe856 131 /* QSPI initialization */
bcostm 6:e1d9da7fe856 132 QSPIHandle.Init.ClockPrescaler = 1; /* QSPI freq = 216 MHz/(1+1) = 108 Mhz */
bcostm 6:e1d9da7fe856 133 QSPIHandle.Init.FifoThreshold = 4;
bcostm 6:e1d9da7fe856 134 QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
bcostm 6:e1d9da7fe856 135 QSPIHandle.Init.FlashSize = POSITION_VAL(N25Q128A_FLASH_SIZE) - 1;
Jerome Coutant 8:56384bddaba5 136 QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_6_CYCLE; /* Min 50ns for nonRead */
bcostm 6:e1d9da7fe856 137 QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0;
bcostm 6:e1d9da7fe856 138 QSPIHandle.Init.FlashID = QSPI_FLASH_ID_1;
bcostm 6:e1d9da7fe856 139 QSPIHandle.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
bcostm 6:e1d9da7fe856 140
bcostm 6:e1d9da7fe856 141 if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)
bcostm 6:e1d9da7fe856 142 {
bcostm 6:e1d9da7fe856 143 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 144 }
bcostm 6:e1d9da7fe856 145
bcostm 6:e1d9da7fe856 146 /* QSPI memory reset */
bcostm 6:e1d9da7fe856 147 if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK)
bcostm 6:e1d9da7fe856 148 {
bcostm 6:e1d9da7fe856 149 return QSPI_NOT_SUPPORTED;
bcostm 6:e1d9da7fe856 150 }
bcostm 6:e1d9da7fe856 151
bcostm 6:e1d9da7fe856 152 /* Configuration of the dummy cycles on QSPI memory side */
bcostm 6:e1d9da7fe856 153 if (QSPI_DummyCyclesCfg(&QSPIHandle) != QSPI_OK)
bcostm 6:e1d9da7fe856 154 {
bcostm 6:e1d9da7fe856 155 return QSPI_NOT_SUPPORTED;
bcostm 6:e1d9da7fe856 156 }
bcostm 6:e1d9da7fe856 157
bcostm 6:e1d9da7fe856 158 return QSPI_OK;
bcostm 6:e1d9da7fe856 159 }
bcostm 6:e1d9da7fe856 160
bcostm 6:e1d9da7fe856 161 /**
bcostm 6:e1d9da7fe856 162 * @brief De-Initializes the QSPI interface.
bcostm 6:e1d9da7fe856 163 * @retval QSPI memory status
bcostm 6:e1d9da7fe856 164 */
bcostm 6:e1d9da7fe856 165 uint8_t BSP_QSPI_DeInit(void)
bcostm 6:e1d9da7fe856 166 {
bcostm 6:e1d9da7fe856 167 QSPIHandle.Instance = QUADSPI;
bcostm 6:e1d9da7fe856 168
bcostm 6:e1d9da7fe856 169 /* Call the DeInit function to reset the driver */
bcostm 6:e1d9da7fe856 170 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
bcostm 6:e1d9da7fe856 171 {
bcostm 6:e1d9da7fe856 172 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 173 }
bcostm 6:e1d9da7fe856 174
bcostm 6:e1d9da7fe856 175 /* System level De-initialization */
bcostm 6:e1d9da7fe856 176 BSP_QSPI_MspDeInit(&QSPIHandle, NULL);
bcostm 6:e1d9da7fe856 177
bcostm 6:e1d9da7fe856 178 return QSPI_OK;
bcostm 6:e1d9da7fe856 179 }
bcostm 6:e1d9da7fe856 180
bcostm 6:e1d9da7fe856 181 /**
bcostm 6:e1d9da7fe856 182 * @brief Reads an amount of data from the QSPI memory.
bcostm 6:e1d9da7fe856 183 * @param pData: Pointer to data to be read
bcostm 6:e1d9da7fe856 184 * @param ReadAddr: Read start address
bcostm 6:e1d9da7fe856 185 * @param Size: Size of data to read
bcostm 6:e1d9da7fe856 186 * @retval QSPI memory status
bcostm 6:e1d9da7fe856 187 */
bcostm 6:e1d9da7fe856 188 uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size)
bcostm 6:e1d9da7fe856 189 {
bcostm 6:e1d9da7fe856 190 QSPI_CommandTypeDef s_command;
bcostm 6:e1d9da7fe856 191
bcostm 6:e1d9da7fe856 192 /* Initialize the read command */
bcostm 6:e1d9da7fe856 193 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 6:e1d9da7fe856 194 s_command.Instruction = QUAD_INOUT_FAST_READ_CMD;
bcostm 6:e1d9da7fe856 195 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
bcostm 6:e1d9da7fe856 196 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 6:e1d9da7fe856 197 s_command.Address = ReadAddr;
bcostm 6:e1d9da7fe856 198 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 6:e1d9da7fe856 199 s_command.DataMode = QSPI_DATA_4_LINES;
bcostm 6:e1d9da7fe856 200 s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD;
bcostm 6:e1d9da7fe856 201 s_command.NbData = Size;
bcostm 6:e1d9da7fe856 202 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 6:e1d9da7fe856 203 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 6:e1d9da7fe856 204 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 6:e1d9da7fe856 205
bcostm 6:e1d9da7fe856 206 /* Configure the command */
bcostm 6:e1d9da7fe856 207 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 208 {
bcostm 6:e1d9da7fe856 209 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 210 }
bcostm 6:e1d9da7fe856 211
Jerome Coutant 8:56384bddaba5 212 /* Set S# timing for Read command */
Jerome Coutant 8:56384bddaba5 213 MODIFY_REG(QSPIHandle.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_3_CYCLE);
Jerome Coutant 8:56384bddaba5 214
bcostm 6:e1d9da7fe856 215 /* Reception of the data */
bcostm 6:e1d9da7fe856 216 if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 217 {
bcostm 6:e1d9da7fe856 218 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 219 }
Jerome Coutant 8:56384bddaba5 220
Jerome Coutant 8:56384bddaba5 221 /* Restore S# timing for nonRead commands */
Jerome Coutant 8:56384bddaba5 222 MODIFY_REG(QSPIHandle.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_6_CYCLE);
bcostm 6:e1d9da7fe856 223
bcostm 6:e1d9da7fe856 224 return QSPI_OK;
bcostm 6:e1d9da7fe856 225 }
bcostm 6:e1d9da7fe856 226
bcostm 6:e1d9da7fe856 227 /**
bcostm 6:e1d9da7fe856 228 * @brief Writes an amount of data to the QSPI memory.
bcostm 6:e1d9da7fe856 229 * @param pData: Pointer to data to be written
bcostm 6:e1d9da7fe856 230 * @param WriteAddr: Write start address
bcostm 6:e1d9da7fe856 231 * @param Size: Size of data to write
bcostm 6:e1d9da7fe856 232 * @retval QSPI memory status
bcostm 6:e1d9da7fe856 233 */
bcostm 6:e1d9da7fe856 234 uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)
bcostm 6:e1d9da7fe856 235 {
bcostm 6:e1d9da7fe856 236 QSPI_CommandTypeDef s_command;
bcostm 6:e1d9da7fe856 237 uint32_t end_addr, current_size, current_addr;
bcostm 6:e1d9da7fe856 238
bcostm 6:e1d9da7fe856 239 /* Calculation of the size between the write address and the end of the page */
Jerome Coutant 8:56384bddaba5 240 current_size = N25Q128A_PAGE_SIZE - (WriteAddr % N25Q128A_PAGE_SIZE);
bcostm 6:e1d9da7fe856 241
bcostm 6:e1d9da7fe856 242 /* Check if the size of the data is less than the remaining place in the page */
bcostm 6:e1d9da7fe856 243 if (current_size > Size)
bcostm 6:e1d9da7fe856 244 {
bcostm 6:e1d9da7fe856 245 current_size = Size;
bcostm 6:e1d9da7fe856 246 }
bcostm 6:e1d9da7fe856 247
bcostm 6:e1d9da7fe856 248 /* Initialize the adress variables */
bcostm 6:e1d9da7fe856 249 current_addr = WriteAddr;
bcostm 6:e1d9da7fe856 250 end_addr = WriteAddr + Size;
bcostm 6:e1d9da7fe856 251
bcostm 6:e1d9da7fe856 252 /* Initialize the program command */
bcostm 6:e1d9da7fe856 253 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 6:e1d9da7fe856 254 s_command.Instruction = EXT_QUAD_IN_FAST_PROG_CMD;
bcostm 6:e1d9da7fe856 255 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
bcostm 6:e1d9da7fe856 256 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 6:e1d9da7fe856 257 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 6:e1d9da7fe856 258 s_command.DataMode = QSPI_DATA_4_LINES;
bcostm 6:e1d9da7fe856 259 s_command.DummyCycles = 0;
bcostm 6:e1d9da7fe856 260 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 6:e1d9da7fe856 261 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 6:e1d9da7fe856 262 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 6:e1d9da7fe856 263
bcostm 6:e1d9da7fe856 264 /* Perform the write page by page */
bcostm 6:e1d9da7fe856 265 do
bcostm 6:e1d9da7fe856 266 {
bcostm 6:e1d9da7fe856 267 s_command.Address = current_addr;
bcostm 6:e1d9da7fe856 268 s_command.NbData = current_size;
bcostm 6:e1d9da7fe856 269
bcostm 6:e1d9da7fe856 270 /* Enable write operations */
bcostm 6:e1d9da7fe856 271 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 6:e1d9da7fe856 272 {
bcostm 6:e1d9da7fe856 273 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 274 }
bcostm 6:e1d9da7fe856 275
bcostm 6:e1d9da7fe856 276 /* Configure the command */
bcostm 6:e1d9da7fe856 277 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 278 {
bcostm 6:e1d9da7fe856 279 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 280 }
bcostm 6:e1d9da7fe856 281
bcostm 6:e1d9da7fe856 282 /* Transmission of the data */
bcostm 6:e1d9da7fe856 283 if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 284 {
bcostm 6:e1d9da7fe856 285 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 286 }
bcostm 6:e1d9da7fe856 287
bcostm 6:e1d9da7fe856 288 /* Configure automatic polling mode to wait for end of program */
bcostm 6:e1d9da7fe856 289 if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
bcostm 6:e1d9da7fe856 290 {
bcostm 6:e1d9da7fe856 291 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 292 }
bcostm 6:e1d9da7fe856 293
bcostm 6:e1d9da7fe856 294 /* Update the address and size variables for next page programming */
bcostm 6:e1d9da7fe856 295 current_addr += current_size;
bcostm 6:e1d9da7fe856 296 pData += current_size;
bcostm 6:e1d9da7fe856 297 current_size = ((current_addr + N25Q128A_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : N25Q128A_PAGE_SIZE;
bcostm 6:e1d9da7fe856 298 } while (current_addr < end_addr);
bcostm 6:e1d9da7fe856 299
bcostm 6:e1d9da7fe856 300 return QSPI_OK;
bcostm 6:e1d9da7fe856 301 }
bcostm 6:e1d9da7fe856 302
bcostm 6:e1d9da7fe856 303 /**
bcostm 6:e1d9da7fe856 304 * @brief Erases the specified block of the QSPI memory.
bcostm 6:e1d9da7fe856 305 * @param BlockAddress: Block address to erase
bcostm 6:e1d9da7fe856 306 * @retval QSPI memory status
bcostm 6:e1d9da7fe856 307 */
bcostm 6:e1d9da7fe856 308 uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress)
bcostm 6:e1d9da7fe856 309 {
bcostm 6:e1d9da7fe856 310 QSPI_CommandTypeDef s_command;
bcostm 6:e1d9da7fe856 311
bcostm 6:e1d9da7fe856 312 /* Initialize the erase command */
bcostm 6:e1d9da7fe856 313 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 6:e1d9da7fe856 314 s_command.Instruction = SUBSECTOR_ERASE_CMD;
bcostm 6:e1d9da7fe856 315 s_command.AddressMode = QSPI_ADDRESS_1_LINE;
bcostm 6:e1d9da7fe856 316 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 6:e1d9da7fe856 317 s_command.Address = BlockAddress;
bcostm 6:e1d9da7fe856 318 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 6:e1d9da7fe856 319 s_command.DataMode = QSPI_DATA_NONE;
bcostm 6:e1d9da7fe856 320 s_command.DummyCycles = 0;
bcostm 6:e1d9da7fe856 321 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 6:e1d9da7fe856 322 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 6:e1d9da7fe856 323 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 6:e1d9da7fe856 324
bcostm 6:e1d9da7fe856 325 /* Enable write operations */
bcostm 6:e1d9da7fe856 326 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 6:e1d9da7fe856 327 {
bcostm 6:e1d9da7fe856 328 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 329 }
bcostm 6:e1d9da7fe856 330
bcostm 6:e1d9da7fe856 331 /* Send the command */
bcostm 6:e1d9da7fe856 332 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 333 {
bcostm 6:e1d9da7fe856 334 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 335 }
bcostm 6:e1d9da7fe856 336
bcostm 6:e1d9da7fe856 337 /* Configure automatic polling mode to wait for end of erase */
bcostm 6:e1d9da7fe856 338 if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_SUBSECTOR_ERASE_MAX_TIME) != QSPI_OK)
bcostm 6:e1d9da7fe856 339 {
bcostm 6:e1d9da7fe856 340 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 341 }
bcostm 6:e1d9da7fe856 342
bcostm 6:e1d9da7fe856 343 return QSPI_OK;
bcostm 6:e1d9da7fe856 344 }
bcostm 6:e1d9da7fe856 345
bcostm 6:e1d9da7fe856 346 /**
bcostm 6:e1d9da7fe856 347 * @brief Erases the entire QSPI memory.
bcostm 6:e1d9da7fe856 348 * @retval QSPI memory status
bcostm 6:e1d9da7fe856 349 */
bcostm 6:e1d9da7fe856 350 uint8_t BSP_QSPI_Erase_Chip(void)
bcostm 6:e1d9da7fe856 351 {
bcostm 6:e1d9da7fe856 352 QSPI_CommandTypeDef s_command;
bcostm 6:e1d9da7fe856 353
bcostm 6:e1d9da7fe856 354 /* Initialize the erase command */
bcostm 6:e1d9da7fe856 355 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 6:e1d9da7fe856 356 s_command.Instruction = BULK_ERASE_CMD;
bcostm 6:e1d9da7fe856 357 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 6:e1d9da7fe856 358 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 6:e1d9da7fe856 359 s_command.DataMode = QSPI_DATA_NONE;
bcostm 6:e1d9da7fe856 360 s_command.DummyCycles = 0;
bcostm 6:e1d9da7fe856 361 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 6:e1d9da7fe856 362 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 6:e1d9da7fe856 363 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 6:e1d9da7fe856 364
bcostm 6:e1d9da7fe856 365 /* Enable write operations */
bcostm 6:e1d9da7fe856 366 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 6:e1d9da7fe856 367 {
bcostm 6:e1d9da7fe856 368 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 369 }
bcostm 6:e1d9da7fe856 370
bcostm 6:e1d9da7fe856 371 /* Send the command */
bcostm 6:e1d9da7fe856 372 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 373 {
bcostm 6:e1d9da7fe856 374 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 375 }
bcostm 6:e1d9da7fe856 376
bcostm 6:e1d9da7fe856 377 /* Configure automatic polling mode to wait for end of erase */
bcostm 6:e1d9da7fe856 378 if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_BULK_ERASE_MAX_TIME) != QSPI_OK)
bcostm 6:e1d9da7fe856 379 {
bcostm 6:e1d9da7fe856 380 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 381 }
bcostm 6:e1d9da7fe856 382
bcostm 6:e1d9da7fe856 383 return QSPI_OK;
bcostm 6:e1d9da7fe856 384 }
bcostm 6:e1d9da7fe856 385
bcostm 6:e1d9da7fe856 386 /**
bcostm 6:e1d9da7fe856 387 * @brief Reads current status of the QSPI memory.
bcostm 6:e1d9da7fe856 388 * @retval QSPI memory status
bcostm 6:e1d9da7fe856 389 */
bcostm 6:e1d9da7fe856 390 uint8_t BSP_QSPI_GetStatus(void)
bcostm 6:e1d9da7fe856 391 {
bcostm 6:e1d9da7fe856 392 QSPI_CommandTypeDef s_command;
bcostm 6:e1d9da7fe856 393 uint8_t reg;
bcostm 6:e1d9da7fe856 394
bcostm 6:e1d9da7fe856 395 /* Initialize the read flag status register command */
bcostm 6:e1d9da7fe856 396 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 6:e1d9da7fe856 397 s_command.Instruction = READ_FLAG_STATUS_REG_CMD;
bcostm 6:e1d9da7fe856 398 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 6:e1d9da7fe856 399 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 6:e1d9da7fe856 400 s_command.DataMode = QSPI_DATA_1_LINE;
bcostm 6:e1d9da7fe856 401 s_command.DummyCycles = 0;
bcostm 6:e1d9da7fe856 402 s_command.NbData = 1;
bcostm 6:e1d9da7fe856 403 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 6:e1d9da7fe856 404 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 6:e1d9da7fe856 405 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 6:e1d9da7fe856 406
bcostm 6:e1d9da7fe856 407 /* Configure the command */
bcostm 6:e1d9da7fe856 408 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 409 {
bcostm 6:e1d9da7fe856 410 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 411 }
bcostm 6:e1d9da7fe856 412
bcostm 6:e1d9da7fe856 413 /* Reception of the data */
bcostm 6:e1d9da7fe856 414 if (HAL_QSPI_Receive(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 415 {
bcostm 6:e1d9da7fe856 416 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 417 }
bcostm 6:e1d9da7fe856 418
bcostm 6:e1d9da7fe856 419 /* Check the value of the register */
bcostm 6:e1d9da7fe856 420 if ((reg & (N25Q128A_FSR_PRERR | N25Q128A_FSR_VPPERR | N25Q128A_FSR_PGERR | N25Q128A_FSR_ERERR)) != 0)
bcostm 6:e1d9da7fe856 421 {
bcostm 6:e1d9da7fe856 422 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 423 }
bcostm 6:e1d9da7fe856 424 else if ((reg & (N25Q128A_FSR_PGSUS | N25Q128A_FSR_ERSUS)) != 0)
bcostm 6:e1d9da7fe856 425 {
bcostm 6:e1d9da7fe856 426 return QSPI_SUSPENDED;
bcostm 6:e1d9da7fe856 427 }
bcostm 6:e1d9da7fe856 428 else if ((reg & N25Q128A_FSR_READY) != 0)
bcostm 6:e1d9da7fe856 429 {
bcostm 6:e1d9da7fe856 430 return QSPI_OK;
bcostm 6:e1d9da7fe856 431 }
bcostm 6:e1d9da7fe856 432 else
bcostm 6:e1d9da7fe856 433 {
bcostm 6:e1d9da7fe856 434 return QSPI_BUSY;
bcostm 6:e1d9da7fe856 435 }
bcostm 6:e1d9da7fe856 436 }
bcostm 6:e1d9da7fe856 437
bcostm 6:e1d9da7fe856 438 /**
bcostm 6:e1d9da7fe856 439 * @brief Return the configuration of the QSPI memory.
bcostm 6:e1d9da7fe856 440 * @param pInfo: pointer on the configuration structure
bcostm 6:e1d9da7fe856 441 * @retval QSPI memory status
bcostm 6:e1d9da7fe856 442 */
bcostm 6:e1d9da7fe856 443 uint8_t BSP_QSPI_GetInfo(QSPI_Info* pInfo)
bcostm 6:e1d9da7fe856 444 {
bcostm 6:e1d9da7fe856 445 /* Configure the structure with the memory configuration */
bcostm 6:e1d9da7fe856 446 pInfo->FlashSize = N25Q128A_FLASH_SIZE;
bcostm 6:e1d9da7fe856 447 pInfo->EraseSectorSize = N25Q128A_SUBSECTOR_SIZE;
bcostm 6:e1d9da7fe856 448 pInfo->EraseSectorsNumber = (N25Q128A_FLASH_SIZE/N25Q128A_SUBSECTOR_SIZE);
bcostm 6:e1d9da7fe856 449 pInfo->ProgPageSize = N25Q128A_PAGE_SIZE;
bcostm 6:e1d9da7fe856 450 pInfo->ProgPagesNumber = (N25Q128A_FLASH_SIZE/N25Q128A_PAGE_SIZE);
bcostm 6:e1d9da7fe856 451
bcostm 6:e1d9da7fe856 452 return QSPI_OK;
bcostm 6:e1d9da7fe856 453 }
bcostm 6:e1d9da7fe856 454
bcostm 6:e1d9da7fe856 455 /**
bcostm 6:e1d9da7fe856 456 * @brief Configure the QSPI in memory-mapped mode
bcostm 6:e1d9da7fe856 457 * @retval QSPI memory status
bcostm 6:e1d9da7fe856 458 */
bcostm 6:e1d9da7fe856 459 uint8_t BSP_QSPI_EnableMemoryMappedMode(void)
bcostm 6:e1d9da7fe856 460 {
bcostm 6:e1d9da7fe856 461 QSPI_CommandTypeDef s_command;
bcostm 6:e1d9da7fe856 462 QSPI_MemoryMappedTypeDef s_mem_mapped_cfg;
bcostm 6:e1d9da7fe856 463
bcostm 6:e1d9da7fe856 464 /* Configure the command for the read instruction */
bcostm 6:e1d9da7fe856 465 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 6:e1d9da7fe856 466 s_command.Instruction = QUAD_INOUT_FAST_READ_CMD;
bcostm 6:e1d9da7fe856 467 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
bcostm 6:e1d9da7fe856 468 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 6:e1d9da7fe856 469 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 6:e1d9da7fe856 470 s_command.DataMode = QSPI_DATA_4_LINES;
bcostm 6:e1d9da7fe856 471 s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD;
bcostm 6:e1d9da7fe856 472 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 6:e1d9da7fe856 473 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 6:e1d9da7fe856 474 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 6:e1d9da7fe856 475
bcostm 6:e1d9da7fe856 476 /* Configure the memory mapped mode */
bcostm 6:e1d9da7fe856 477 s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;
bcostm 6:e1d9da7fe856 478 s_mem_mapped_cfg.TimeOutPeriod = 0;
bcostm 6:e1d9da7fe856 479
bcostm 6:e1d9da7fe856 480 if (HAL_QSPI_MemoryMapped(&QSPIHandle, &s_command, &s_mem_mapped_cfg) != HAL_OK)
bcostm 6:e1d9da7fe856 481 {
bcostm 6:e1d9da7fe856 482 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 483 }
bcostm 6:e1d9da7fe856 484
bcostm 6:e1d9da7fe856 485 return QSPI_OK;
bcostm 6:e1d9da7fe856 486 }
bcostm 6:e1d9da7fe856 487
bcostm 6:e1d9da7fe856 488 /**
bcostm 6:e1d9da7fe856 489 * @}
bcostm 6:e1d9da7fe856 490 */
bcostm 6:e1d9da7fe856 491
bcostm 6:e1d9da7fe856 492 /** @addtogroup STM32746G_DISCOVERY_QSPI_Private_Functions
bcostm 6:e1d9da7fe856 493 * @{
bcostm 6:e1d9da7fe856 494 */
bcostm 6:e1d9da7fe856 495
bcostm 6:e1d9da7fe856 496 /**
bcostm 6:e1d9da7fe856 497 * @brief QSPI MSP Initialization
bcostm 6:e1d9da7fe856 498 * This function configures the hardware resources used in this example:
bcostm 6:e1d9da7fe856 499 * - Peripheral's clock enable
bcostm 6:e1d9da7fe856 500 * - Peripheral's GPIO Configuration
bcostm 6:e1d9da7fe856 501 * - NVIC configuration for QSPI interrupt
bcostm 6:e1d9da7fe856 502 * @retval None
bcostm 6:e1d9da7fe856 503 */
bcostm 6:e1d9da7fe856 504 __weak void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params)
bcostm 6:e1d9da7fe856 505 {
bcostm 6:e1d9da7fe856 506 GPIO_InitTypeDef gpio_init_structure;
bcostm 6:e1d9da7fe856 507
bcostm 6:e1d9da7fe856 508 /*##-1- Enable peripherals and GPIO Clocks #################################*/
bcostm 6:e1d9da7fe856 509 /* Enable the QuadSPI memory interface clock */
bcostm 6:e1d9da7fe856 510 QSPI_CLK_ENABLE();
bcostm 6:e1d9da7fe856 511 /* Reset the QuadSPI memory interface */
bcostm 6:e1d9da7fe856 512 QSPI_FORCE_RESET();
bcostm 6:e1d9da7fe856 513 QSPI_RELEASE_RESET();
bcostm 6:e1d9da7fe856 514 /* Enable GPIO clocks */
bcostm 6:e1d9da7fe856 515 QSPI_CS_GPIO_CLK_ENABLE();
bcostm 6:e1d9da7fe856 516 QSPI_CLK_GPIO_CLK_ENABLE();
bcostm 6:e1d9da7fe856 517 QSPI_D0_GPIO_CLK_ENABLE();
bcostm 6:e1d9da7fe856 518 QSPI_D1_GPIO_CLK_ENABLE();
bcostm 6:e1d9da7fe856 519 QSPI_D2_GPIO_CLK_ENABLE();
bcostm 6:e1d9da7fe856 520 QSPI_D3_GPIO_CLK_ENABLE();
bcostm 6:e1d9da7fe856 521
bcostm 6:e1d9da7fe856 522 /*##-2- Configure peripheral GPIO ##########################################*/
bcostm 6:e1d9da7fe856 523 /* QSPI CS GPIO pin configuration */
bcostm 6:e1d9da7fe856 524 gpio_init_structure.Pin = QSPI_CS_PIN;
bcostm 6:e1d9da7fe856 525 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
bcostm 6:e1d9da7fe856 526 gpio_init_structure.Pull = GPIO_PULLUP;
bcostm 6:e1d9da7fe856 527 gpio_init_structure.Speed = GPIO_SPEED_HIGH;
bcostm 6:e1d9da7fe856 528 gpio_init_structure.Alternate = GPIO_AF10_QUADSPI;
bcostm 6:e1d9da7fe856 529 HAL_GPIO_Init(QSPI_CS_GPIO_PORT, &gpio_init_structure);
bcostm 6:e1d9da7fe856 530
bcostm 6:e1d9da7fe856 531 /* QSPI CLK GPIO pin configuration */
bcostm 6:e1d9da7fe856 532 gpio_init_structure.Pin = QSPI_CLK_PIN;
bcostm 6:e1d9da7fe856 533 gpio_init_structure.Pull = GPIO_NOPULL;
bcostm 6:e1d9da7fe856 534 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
bcostm 6:e1d9da7fe856 535 HAL_GPIO_Init(QSPI_CLK_GPIO_PORT, &gpio_init_structure);
bcostm 6:e1d9da7fe856 536
bcostm 6:e1d9da7fe856 537 /* QSPI D0 GPIO pin configuration */
bcostm 6:e1d9da7fe856 538 gpio_init_structure.Pin = QSPI_D0_PIN;
bcostm 6:e1d9da7fe856 539 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
bcostm 6:e1d9da7fe856 540 HAL_GPIO_Init(QSPI_D0_GPIO_PORT, &gpio_init_structure);
bcostm 6:e1d9da7fe856 541
bcostm 6:e1d9da7fe856 542 /* QSPI D1 GPIO pin configuration */
bcostm 6:e1d9da7fe856 543 gpio_init_structure.Pin = QSPI_D1_PIN;
bcostm 6:e1d9da7fe856 544 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
bcostm 6:e1d9da7fe856 545 HAL_GPIO_Init(QSPI_D1_GPIO_PORT, &gpio_init_structure);
bcostm 6:e1d9da7fe856 546
bcostm 6:e1d9da7fe856 547 /* QSPI D2 GPIO pin configuration */
bcostm 6:e1d9da7fe856 548 gpio_init_structure.Pin = QSPI_D2_PIN;
bcostm 6:e1d9da7fe856 549 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
bcostm 6:e1d9da7fe856 550 HAL_GPIO_Init(QSPI_D2_GPIO_PORT, &gpio_init_structure);
bcostm 6:e1d9da7fe856 551
bcostm 6:e1d9da7fe856 552 /* QSPI D3 GPIO pin configuration */
bcostm 6:e1d9da7fe856 553 gpio_init_structure.Pin = QSPI_D3_PIN;
bcostm 6:e1d9da7fe856 554 gpio_init_structure.Alternate = GPIO_AF9_QUADSPI;
bcostm 6:e1d9da7fe856 555 HAL_GPIO_Init(QSPI_D3_GPIO_PORT, &gpio_init_structure);
bcostm 6:e1d9da7fe856 556
bcostm 6:e1d9da7fe856 557 /*##-3- Configure the NVIC for QSPI #########################################*/
bcostm 6:e1d9da7fe856 558 /* NVIC configuration for QSPI interrupt */
bcostm 6:e1d9da7fe856 559 HAL_NVIC_SetPriority(QUADSPI_IRQn, 0x0F, 0);
bcostm 6:e1d9da7fe856 560 HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
bcostm 6:e1d9da7fe856 561 }
bcostm 6:e1d9da7fe856 562
bcostm 6:e1d9da7fe856 563 /**
bcostm 6:e1d9da7fe856 564 * @brief QSPI MSP De-Initialization
bcostm 6:e1d9da7fe856 565 * This function frees the hardware resources used in this example:
bcostm 6:e1d9da7fe856 566 * - Disable the Peripheral's clock
bcostm 6:e1d9da7fe856 567 * - Revert GPIO and NVIC configuration to their default state
bcostm 6:e1d9da7fe856 568 * @retval None
bcostm 6:e1d9da7fe856 569 */
bcostm 6:e1d9da7fe856 570 __weak void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params)
bcostm 6:e1d9da7fe856 571 {
bcostm 6:e1d9da7fe856 572 /*##-1- Disable the NVIC for QSPI ###########################################*/
bcostm 6:e1d9da7fe856 573 HAL_NVIC_DisableIRQ(QUADSPI_IRQn);
bcostm 6:e1d9da7fe856 574
bcostm 6:e1d9da7fe856 575 /*##-2- Disable peripherals and GPIO Clocks ################################*/
bcostm 6:e1d9da7fe856 576 /* De-Configure QSPI pins */
bcostm 6:e1d9da7fe856 577 HAL_GPIO_DeInit(QSPI_CS_GPIO_PORT, QSPI_CS_PIN);
bcostm 6:e1d9da7fe856 578 HAL_GPIO_DeInit(QSPI_CLK_GPIO_PORT, QSPI_CLK_PIN);
bcostm 6:e1d9da7fe856 579 HAL_GPIO_DeInit(QSPI_D0_GPIO_PORT, QSPI_D0_PIN);
bcostm 6:e1d9da7fe856 580 HAL_GPIO_DeInit(QSPI_D1_GPIO_PORT, QSPI_D1_PIN);
bcostm 6:e1d9da7fe856 581 HAL_GPIO_DeInit(QSPI_D2_GPIO_PORT, QSPI_D2_PIN);
bcostm 6:e1d9da7fe856 582 HAL_GPIO_DeInit(QSPI_D3_GPIO_PORT, QSPI_D3_PIN);
bcostm 6:e1d9da7fe856 583
bcostm 6:e1d9da7fe856 584 /*##-3- Reset peripherals ##################################################*/
bcostm 6:e1d9da7fe856 585 /* Reset the QuadSPI memory interface */
bcostm 6:e1d9da7fe856 586 QSPI_FORCE_RESET();
bcostm 6:e1d9da7fe856 587 QSPI_RELEASE_RESET();
bcostm 6:e1d9da7fe856 588
bcostm 6:e1d9da7fe856 589 /* Disable the QuadSPI memory interface clock */
bcostm 6:e1d9da7fe856 590 QSPI_CLK_DISABLE();
bcostm 6:e1d9da7fe856 591 }
bcostm 6:e1d9da7fe856 592
bcostm 6:e1d9da7fe856 593 /**
bcostm 6:e1d9da7fe856 594 * @brief This function reset the QSPI memory.
bcostm 6:e1d9da7fe856 595 * @param hqspi: QSPI handle
bcostm 6:e1d9da7fe856 596 * @retval None
bcostm 6:e1d9da7fe856 597 */
bcostm 6:e1d9da7fe856 598 static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi)
bcostm 6:e1d9da7fe856 599 {
bcostm 6:e1d9da7fe856 600 QSPI_CommandTypeDef s_command;
bcostm 6:e1d9da7fe856 601
bcostm 6:e1d9da7fe856 602 /* Initialize the reset enable command */
bcostm 6:e1d9da7fe856 603 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 6:e1d9da7fe856 604 s_command.Instruction = RESET_ENABLE_CMD;
bcostm 6:e1d9da7fe856 605 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 6:e1d9da7fe856 606 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 6:e1d9da7fe856 607 s_command.DataMode = QSPI_DATA_NONE;
bcostm 6:e1d9da7fe856 608 s_command.DummyCycles = 0;
bcostm 6:e1d9da7fe856 609 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 6:e1d9da7fe856 610 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 6:e1d9da7fe856 611 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 6:e1d9da7fe856 612
bcostm 6:e1d9da7fe856 613 /* Send the command */
bcostm 6:e1d9da7fe856 614 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 615 {
bcostm 6:e1d9da7fe856 616 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 617 }
bcostm 6:e1d9da7fe856 618
bcostm 6:e1d9da7fe856 619 /* Send the reset memory command */
bcostm 6:e1d9da7fe856 620 s_command.Instruction = RESET_MEMORY_CMD;
bcostm 6:e1d9da7fe856 621 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 622 {
bcostm 6:e1d9da7fe856 623 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 624 }
bcostm 6:e1d9da7fe856 625
bcostm 6:e1d9da7fe856 626 /* Configure automatic polling mode to wait the memory is ready */
bcostm 6:e1d9da7fe856 627 if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
bcostm 6:e1d9da7fe856 628 {
bcostm 6:e1d9da7fe856 629 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 630 }
bcostm 6:e1d9da7fe856 631
bcostm 6:e1d9da7fe856 632 return QSPI_OK;
bcostm 6:e1d9da7fe856 633 }
bcostm 6:e1d9da7fe856 634
bcostm 6:e1d9da7fe856 635 /**
bcostm 6:e1d9da7fe856 636 * @brief This function configure the dummy cycles on memory side.
bcostm 6:e1d9da7fe856 637 * @param hqspi: QSPI handle
bcostm 6:e1d9da7fe856 638 * @retval None
bcostm 6:e1d9da7fe856 639 */
bcostm 6:e1d9da7fe856 640 static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi)
bcostm 6:e1d9da7fe856 641 {
bcostm 6:e1d9da7fe856 642 QSPI_CommandTypeDef s_command;
bcostm 6:e1d9da7fe856 643 uint8_t reg;
bcostm 6:e1d9da7fe856 644
bcostm 6:e1d9da7fe856 645 /* Initialize the read volatile configuration register command */
bcostm 6:e1d9da7fe856 646 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 6:e1d9da7fe856 647 s_command.Instruction = READ_VOL_CFG_REG_CMD;
bcostm 6:e1d9da7fe856 648 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 6:e1d9da7fe856 649 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 6:e1d9da7fe856 650 s_command.DataMode = QSPI_DATA_1_LINE;
bcostm 6:e1d9da7fe856 651 s_command.DummyCycles = 0;
bcostm 6:e1d9da7fe856 652 s_command.NbData = 1;
bcostm 6:e1d9da7fe856 653 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 6:e1d9da7fe856 654 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 6:e1d9da7fe856 655 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 6:e1d9da7fe856 656
bcostm 6:e1d9da7fe856 657 /* Configure the command */
bcostm 6:e1d9da7fe856 658 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 659 {
bcostm 6:e1d9da7fe856 660 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 661 }
bcostm 6:e1d9da7fe856 662
bcostm 6:e1d9da7fe856 663 /* Reception of the data */
bcostm 6:e1d9da7fe856 664 if (HAL_QSPI_Receive(hqspi, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 665 {
bcostm 6:e1d9da7fe856 666 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 667 }
bcostm 6:e1d9da7fe856 668
bcostm 6:e1d9da7fe856 669 /* Enable write operations */
bcostm 6:e1d9da7fe856 670 if (QSPI_WriteEnable(hqspi) != QSPI_OK)
bcostm 6:e1d9da7fe856 671 {
bcostm 6:e1d9da7fe856 672 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 673 }
bcostm 6:e1d9da7fe856 674
bcostm 6:e1d9da7fe856 675 /* Update volatile configuration register (with new dummy cycles) */
bcostm 6:e1d9da7fe856 676 s_command.Instruction = WRITE_VOL_CFG_REG_CMD;
bcostm 6:e1d9da7fe856 677 MODIFY_REG(reg, N25Q128A_VCR_NB_DUMMY, (N25Q128A_DUMMY_CYCLES_READ_QUAD << POSITION_VAL(N25Q128A_VCR_NB_DUMMY)));
bcostm 6:e1d9da7fe856 678
bcostm 6:e1d9da7fe856 679 /* Configure the write volatile configuration register command */
bcostm 6:e1d9da7fe856 680 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 681 {
bcostm 6:e1d9da7fe856 682 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 683 }
bcostm 6:e1d9da7fe856 684
bcostm 6:e1d9da7fe856 685 /* Transmission of the data */
bcostm 6:e1d9da7fe856 686 if (HAL_QSPI_Transmit(hqspi, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 687 {
bcostm 6:e1d9da7fe856 688 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 689 }
bcostm 6:e1d9da7fe856 690
bcostm 6:e1d9da7fe856 691 return QSPI_OK;
bcostm 6:e1d9da7fe856 692 }
bcostm 6:e1d9da7fe856 693
bcostm 6:e1d9da7fe856 694 /**
bcostm 6:e1d9da7fe856 695 * @brief This function send a Write Enable and wait it is effective.
bcostm 6:e1d9da7fe856 696 * @param hqspi: QSPI handle
bcostm 6:e1d9da7fe856 697 * @retval None
bcostm 6:e1d9da7fe856 698 */
bcostm 6:e1d9da7fe856 699 static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi)
bcostm 6:e1d9da7fe856 700 {
bcostm 6:e1d9da7fe856 701 QSPI_CommandTypeDef s_command;
bcostm 6:e1d9da7fe856 702 QSPI_AutoPollingTypeDef s_config;
bcostm 6:e1d9da7fe856 703
bcostm 6:e1d9da7fe856 704 /* Enable write operations */
bcostm 6:e1d9da7fe856 705 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 6:e1d9da7fe856 706 s_command.Instruction = WRITE_ENABLE_CMD;
bcostm 6:e1d9da7fe856 707 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 6:e1d9da7fe856 708 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 6:e1d9da7fe856 709 s_command.DataMode = QSPI_DATA_NONE;
bcostm 6:e1d9da7fe856 710 s_command.DummyCycles = 0;
bcostm 6:e1d9da7fe856 711 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 6:e1d9da7fe856 712 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 6:e1d9da7fe856 713 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 6:e1d9da7fe856 714
bcostm 6:e1d9da7fe856 715 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 716 {
bcostm 6:e1d9da7fe856 717 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 718 }
bcostm 6:e1d9da7fe856 719
bcostm 6:e1d9da7fe856 720 /* Configure automatic polling mode to wait for write enabling */
bcostm 6:e1d9da7fe856 721 s_config.Match = N25Q128A_SR_WREN;
bcostm 6:e1d9da7fe856 722 s_config.Mask = N25Q128A_SR_WREN;
bcostm 6:e1d9da7fe856 723 s_config.MatchMode = QSPI_MATCH_MODE_AND;
bcostm 6:e1d9da7fe856 724 s_config.StatusBytesSize = 1;
bcostm 6:e1d9da7fe856 725 s_config.Interval = 0x10;
bcostm 6:e1d9da7fe856 726 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
bcostm 6:e1d9da7fe856 727
bcostm 6:e1d9da7fe856 728 s_command.Instruction = READ_STATUS_REG_CMD;
bcostm 6:e1d9da7fe856 729 s_command.DataMode = QSPI_DATA_1_LINE;
bcostm 6:e1d9da7fe856 730
bcostm 6:e1d9da7fe856 731 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 6:e1d9da7fe856 732 {
bcostm 6:e1d9da7fe856 733 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 734 }
bcostm 6:e1d9da7fe856 735
bcostm 6:e1d9da7fe856 736 return QSPI_OK;
bcostm 6:e1d9da7fe856 737 }
bcostm 6:e1d9da7fe856 738
bcostm 6:e1d9da7fe856 739 /**
bcostm 6:e1d9da7fe856 740 * @brief This function read the SR of the memory and wait the EOP.
bcostm 6:e1d9da7fe856 741 * @param hqspi: QSPI handle
bcostm 6:e1d9da7fe856 742 * @param Timeout
bcostm 6:e1d9da7fe856 743 * @retval None
bcostm 6:e1d9da7fe856 744 */
bcostm 6:e1d9da7fe856 745 static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
bcostm 6:e1d9da7fe856 746 {
bcostm 6:e1d9da7fe856 747 QSPI_CommandTypeDef s_command;
bcostm 6:e1d9da7fe856 748 QSPI_AutoPollingTypeDef s_config;
bcostm 6:e1d9da7fe856 749
bcostm 6:e1d9da7fe856 750 /* Configure automatic polling mode to wait for memory ready */
bcostm 6:e1d9da7fe856 751 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 6:e1d9da7fe856 752 s_command.Instruction = READ_STATUS_REG_CMD;
bcostm 6:e1d9da7fe856 753 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 6:e1d9da7fe856 754 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 6:e1d9da7fe856 755 s_command.DataMode = QSPI_DATA_1_LINE;
bcostm 6:e1d9da7fe856 756 s_command.DummyCycles = 0;
bcostm 6:e1d9da7fe856 757 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 6:e1d9da7fe856 758 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 6:e1d9da7fe856 759 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 6:e1d9da7fe856 760
bcostm 6:e1d9da7fe856 761 s_config.Match = 0;
bcostm 6:e1d9da7fe856 762 s_config.Mask = N25Q128A_SR_WIP;
bcostm 6:e1d9da7fe856 763 s_config.MatchMode = QSPI_MATCH_MODE_AND;
bcostm 6:e1d9da7fe856 764 s_config.StatusBytesSize = 1;
bcostm 6:e1d9da7fe856 765 s_config.Interval = 0x10;
bcostm 6:e1d9da7fe856 766 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
bcostm 6:e1d9da7fe856 767
bcostm 6:e1d9da7fe856 768 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK)
bcostm 6:e1d9da7fe856 769 {
bcostm 6:e1d9da7fe856 770 return QSPI_ERROR;
bcostm 6:e1d9da7fe856 771 }
bcostm 6:e1d9da7fe856 772
bcostm 6:e1d9da7fe856 773 return QSPI_OK;
bcostm 6:e1d9da7fe856 774 }
bcostm 6:e1d9da7fe856 775 /**
bcostm 6:e1d9da7fe856 776 * @}
bcostm 6:e1d9da7fe856 777 */
bcostm 6:e1d9da7fe856 778
bcostm 6:e1d9da7fe856 779 /**
bcostm 6:e1d9da7fe856 780 * @}
bcostm 6:e1d9da7fe856 781 */
bcostm 6:e1d9da7fe856 782
bcostm 6:e1d9da7fe856 783 /**
bcostm 6:e1d9da7fe856 784 * @}
bcostm 6:e1d9da7fe856 785 */
bcostm 6:e1d9da7fe856 786
bcostm 6:e1d9da7fe856 787 /**
bcostm 6:e1d9da7fe856 788 * @}
bcostm 6:e1d9da7fe856 789 */
bcostm 6:e1d9da7fe856 790
bcostm 6:e1d9da7fe856 791 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bcostm 6:e1d9da7fe856 792