Maxim nexpaq / nexpaq_dev

Preliminary main mbed library for nexpaq development

hal/common/mbed_critical.c@1:d96dbedaebdb, 2016-11-04 (annotated)

Committer:
nexpaq
Date:
Fri Nov 04 20:54:50 2016 +0000
Revision:
1:d96dbedaebdb
Parent:
0:6c56fb4bc5f0 
Removed extra directories for other platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nexpaq 0:6c56fb4bc5f0 1 /*
nexpaq 0:6c56fb4bc5f0 2 * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
nexpaq 0:6c56fb4bc5f0 3 * SPDX-License-Identifier: Apache-2.0
nexpaq 0:6c56fb4bc5f0 4 *
nexpaq 0:6c56fb4bc5f0 5 * Licensed under the Apache License, Version 2.0 (the "License"); you may
nexpaq 0:6c56fb4bc5f0 6 * not use this file except in compliance with the License.
nexpaq 0:6c56fb4bc5f0 7 * You may obtain a copy of the License at
nexpaq 0:6c56fb4bc5f0 8 *
nexpaq 0:6c56fb4bc5f0 9 * http://www.apache.org/licenses/LICENSE-2.0
nexpaq 0:6c56fb4bc5f0 10 *
nexpaq 0:6c56fb4bc5f0 11 * Unless required by applicable law or agreed to in writing, software
nexpaq 0:6c56fb4bc5f0 12 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
nexpaq 0:6c56fb4bc5f0 13 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
nexpaq 0:6c56fb4bc5f0 14 * See the License for the specific language governing permissions and
nexpaq 0:6c56fb4bc5f0 15 * limitations under the License.
nexpaq 0:6c56fb4bc5f0 16 */
nexpaq 0:6c56fb4bc5f0 17
nexpaq 0:6c56fb4bc5f0 18 #include "critical.h"
nexpaq 0:6c56fb4bc5f0 19
nexpaq 0:6c56fb4bc5f0 20 #include "cmsis.h"
nexpaq 0:6c56fb4bc5f0 21 #include "mbed_assert.h"
nexpaq 0:6c56fb4bc5f0 22
nexpaq 0:6c56fb4bc5f0 23 #define EXCLUSIVE_ACCESS (!defined (__CORTEX_M0) && !defined (__CORTEX_M0PLUS))
nexpaq 0:6c56fb4bc5f0 24
nexpaq 0:6c56fb4bc5f0 25 static volatile uint32_t interrupt_enable_counter = 0;
nexpaq 0:6c56fb4bc5f0 26 static volatile bool critical_interrupts_disabled = false;
nexpaq 0:6c56fb4bc5f0 27
nexpaq 0:6c56fb4bc5f0 28 bool core_util_are_interrupts_enabled(void)
nexpaq 0:6c56fb4bc5f0 29 {
nexpaq 0:6c56fb4bc5f0 30 #if defined(__CORTEX_A9)
nexpaq 0:6c56fb4bc5f0 31 return ((__get_CPSR() & 0x80) == 0);
nexpaq 0:6c56fb4bc5f0 32 #else
nexpaq 0:6c56fb4bc5f0 33 return ((__get_PRIMASK() & 0x1) == 0);
nexpaq 0:6c56fb4bc5f0 34 #endif
nexpaq 0:6c56fb4bc5f0 35 }
nexpaq 0:6c56fb4bc5f0 36
nexpaq 0:6c56fb4bc5f0 37 void core_util_critical_section_enter(void)
nexpaq 0:6c56fb4bc5f0 38 {
nexpaq 0:6c56fb4bc5f0 39 bool interrupts_disabled = !core_util_are_interrupts_enabled();
nexpaq 0:6c56fb4bc5f0 40 __disable_irq();
nexpaq 0:6c56fb4bc5f0 41
nexpaq 0:6c56fb4bc5f0 42 /* Save the interrupt disabled state as it was prior to any nested critical section lock use */
nexpaq 0:6c56fb4bc5f0 43 if (!interrupt_enable_counter) {
nexpaq 0:6c56fb4bc5f0 44 critical_interrupts_disabled = interrupts_disabled;
nexpaq 0:6c56fb4bc5f0 45 }
nexpaq 0:6c56fb4bc5f0 46
nexpaq 0:6c56fb4bc5f0 47 /* If the interrupt_enable_counter overflows or we are in a nested critical section and interrupts
nexpaq 0:6c56fb4bc5f0 48 are enabled, then something has gone badly wrong thus assert an error.
nexpaq 0:6c56fb4bc5f0 49 */
nexpaq 0:6c56fb4bc5f0 50 MBED_ASSERT(interrupt_enable_counter < UINT32_MAX);
nexpaq 0:6c56fb4bc5f0 51 // FIXME
nexpaq 0:6c56fb4bc5f0 52 #ifndef FEATURE_UVISOR
nexpaq 0:6c56fb4bc5f0 53 if (interrupt_enable_counter > 0) {
nexpaq 0:6c56fb4bc5f0 54 MBED_ASSERT(interrupts_disabled);
nexpaq 0:6c56fb4bc5f0 55 }
nexpaq 0:6c56fb4bc5f0 56 #else
nexpaq 0:6c56fb4bc5f0 57 #warning "core_util_critical_section_enter needs fixing to work from unprivileged code"
nexpaq 0:6c56fb4bc5f0 58 #endif /* FEATURE_UVISOR */
nexpaq 0:6c56fb4bc5f0 59 interrupt_enable_counter++;
nexpaq 0:6c56fb4bc5f0 60 }
nexpaq 0:6c56fb4bc5f0 61
nexpaq 0:6c56fb4bc5f0 62 void core_util_critical_section_exit(void)
nexpaq 0:6c56fb4bc5f0 63 {
nexpaq 0:6c56fb4bc5f0 64 /* If critical_section_enter has not previously been called, do nothing */
nexpaq 0:6c56fb4bc5f0 65 if (interrupt_enable_counter) {
nexpaq 0:6c56fb4bc5f0 66
nexpaq 0:6c56fb4bc5f0 67 // FIXME
nexpaq 0:6c56fb4bc5f0 68 #ifndef FEATURE_UVISOR
nexpaq 0:6c56fb4bc5f0 69 bool interrupts_disabled = !core_util_are_interrupts_enabled(); /* get the current interrupt disabled state */
nexpaq 0:6c56fb4bc5f0 70
nexpaq 0:6c56fb4bc5f0 71 MBED_ASSERT(interrupts_disabled); /* Interrupts must be disabled on invoking an exit from a critical section */
nexpaq 0:6c56fb4bc5f0 72 #else
nexpaq 0:6c56fb4bc5f0 73 #warning "core_util_critical_section_exit needs fixing to work from unprivileged code"
nexpaq 0:6c56fb4bc5f0 74 #endif /* FEATURE_UVISOR */
nexpaq 0:6c56fb4bc5f0 75
nexpaq 0:6c56fb4bc5f0 76 interrupt_enable_counter--;
nexpaq 0:6c56fb4bc5f0 77
nexpaq 0:6c56fb4bc5f0 78 /* Only re-enable interrupts if we are exiting the last of the nested critical sections and
nexpaq 0:6c56fb4bc5f0 79 interrupts were enabled on entry to the first critical section.
nexpaq 0:6c56fb4bc5f0 80 */
nexpaq 0:6c56fb4bc5f0 81 if (!interrupt_enable_counter && !critical_interrupts_disabled) {
nexpaq 0:6c56fb4bc5f0 82 __enable_irq();
nexpaq 0:6c56fb4bc5f0 83 }
nexpaq 0:6c56fb4bc5f0 84 }
nexpaq 0:6c56fb4bc5f0 85 }
nexpaq 0:6c56fb4bc5f0 86
nexpaq 0:6c56fb4bc5f0 87 #if EXCLUSIVE_ACCESS
nexpaq 0:6c56fb4bc5f0 88
nexpaq 0:6c56fb4bc5f0 89 /* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
nexpaq 0:6c56fb4bc5f0 90 #if defined (__CC_ARM)
nexpaq 0:6c56fb4bc5f0 91 #pragma diag_suppress 3731
nexpaq 0:6c56fb4bc5f0 92 #endif
nexpaq 0:6c56fb4bc5f0 93
nexpaq 0:6c56fb4bc5f0 94 bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
nexpaq 0:6c56fb4bc5f0 95 {
nexpaq 0:6c56fb4bc5f0 96 uint8_t currentValue = __LDREXB((volatile uint8_t*)ptr);
nexpaq 0:6c56fb4bc5f0 97 if (currentValue != *expectedCurrentValue) {
nexpaq 0:6c56fb4bc5f0 98 *expectedCurrentValue = currentValue;
nexpaq 0:6c56fb4bc5f0 99 __CLREX();
nexpaq 0:6c56fb4bc5f0 100 return false;
nexpaq 0:6c56fb4bc5f0 101 }
nexpaq 0:6c56fb4bc5f0 102
nexpaq 0:6c56fb4bc5f0 103 return !__STREXB(desiredValue, (volatile uint8_t*)ptr);
nexpaq 0:6c56fb4bc5f0 104 }
nexpaq 0:6c56fb4bc5f0 105
nexpaq 0:6c56fb4bc5f0 106 bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
nexpaq 0:6c56fb4bc5f0 107 {
nexpaq 0:6c56fb4bc5f0 108 uint16_t currentValue = __LDREXH((volatile uint16_t*)ptr);
nexpaq 0:6c56fb4bc5f0 109 if (currentValue != *expectedCurrentValue) {
nexpaq 0:6c56fb4bc5f0 110 *expectedCurrentValue = currentValue;
nexpaq 0:6c56fb4bc5f0 111 __CLREX();
nexpaq 0:6c56fb4bc5f0 112 return false;
nexpaq 0:6c56fb4bc5f0 113 }
nexpaq 0:6c56fb4bc5f0 114
nexpaq 0:6c56fb4bc5f0 115 return !__STREXH(desiredValue, (volatile uint16_t*)ptr);
nexpaq 0:6c56fb4bc5f0 116 }
nexpaq 0:6c56fb4bc5f0 117
nexpaq 0:6c56fb4bc5f0 118
nexpaq 0:6c56fb4bc5f0 119 bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
nexpaq 0:6c56fb4bc5f0 120 {
nexpaq 0:6c56fb4bc5f0 121 uint32_t currentValue = __LDREXW((volatile uint32_t*)ptr);
nexpaq 0:6c56fb4bc5f0 122 if (currentValue != *expectedCurrentValue) {
nexpaq 0:6c56fb4bc5f0 123 *expectedCurrentValue = currentValue;
nexpaq 0:6c56fb4bc5f0 124 __CLREX();
nexpaq 0:6c56fb4bc5f0 125 return false;
nexpaq 0:6c56fb4bc5f0 126 }
nexpaq 0:6c56fb4bc5f0 127
nexpaq 0:6c56fb4bc5f0 128 return !__STREXW(desiredValue, (volatile uint32_t*)ptr);
nexpaq 0:6c56fb4bc5f0 129 }
nexpaq 0:6c56fb4bc5f0 130
nexpaq 0:6c56fb4bc5f0 131 uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
nexpaq 0:6c56fb4bc5f0 132 {
nexpaq 0:6c56fb4bc5f0 133 uint8_t newValue;
nexpaq 0:6c56fb4bc5f0 134 do {
nexpaq 0:6c56fb4bc5f0 135 newValue = __LDREXB((volatile uint8_t*)valuePtr) + delta;
nexpaq 0:6c56fb4bc5f0 136 } while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
nexpaq 0:6c56fb4bc5f0 137 return newValue;
nexpaq 0:6c56fb4bc5f0 138 }
nexpaq 0:6c56fb4bc5f0 139
nexpaq 0:6c56fb4bc5f0 140 uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
nexpaq 0:6c56fb4bc5f0 141 {
nexpaq 0:6c56fb4bc5f0 142 uint16_t newValue;
nexpaq 0:6c56fb4bc5f0 143 do {
nexpaq 0:6c56fb4bc5f0 144 newValue = __LDREXH((volatile uint16_t*)valuePtr) + delta;
nexpaq 0:6c56fb4bc5f0 145 } while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
nexpaq 0:6c56fb4bc5f0 146 return newValue;
nexpaq 0:6c56fb4bc5f0 147 }
nexpaq 0:6c56fb4bc5f0 148
nexpaq 0:6c56fb4bc5f0 149 uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
nexpaq 0:6c56fb4bc5f0 150 {
nexpaq 0:6c56fb4bc5f0 151 uint32_t newValue;
nexpaq 0:6c56fb4bc5f0 152 do {
nexpaq 0:6c56fb4bc5f0 153 newValue = __LDREXW((volatile uint32_t*)valuePtr) + delta;
nexpaq 0:6c56fb4bc5f0 154 } while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
nexpaq 0:6c56fb4bc5f0 155 return newValue;
nexpaq 0:6c56fb4bc5f0 156 }
nexpaq 0:6c56fb4bc5f0 157
nexpaq 0:6c56fb4bc5f0 158
nexpaq 0:6c56fb4bc5f0 159 uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
nexpaq 0:6c56fb4bc5f0 160 {
nexpaq 0:6c56fb4bc5f0 161 uint8_t newValue;
nexpaq 0:6c56fb4bc5f0 162 do {
nexpaq 0:6c56fb4bc5f0 163 newValue = __LDREXB((volatile uint8_t*)valuePtr) - delta;
nexpaq 0:6c56fb4bc5f0 164 } while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
nexpaq 0:6c56fb4bc5f0 165 return newValue;
nexpaq 0:6c56fb4bc5f0 166 }
nexpaq 0:6c56fb4bc5f0 167
nexpaq 0:6c56fb4bc5f0 168 uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
nexpaq 0:6c56fb4bc5f0 169 {
nexpaq 0:6c56fb4bc5f0 170 uint16_t newValue;
nexpaq 0:6c56fb4bc5f0 171 do {
nexpaq 0:6c56fb4bc5f0 172 newValue = __LDREXH((volatile uint16_t*)valuePtr) - delta;
nexpaq 0:6c56fb4bc5f0 173 } while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
nexpaq 0:6c56fb4bc5f0 174 return newValue;
nexpaq 0:6c56fb4bc5f0 175 }
nexpaq 0:6c56fb4bc5f0 176
nexpaq 0:6c56fb4bc5f0 177 uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
nexpaq 0:6c56fb4bc5f0 178 {
nexpaq 0:6c56fb4bc5f0 179 uint32_t newValue;
nexpaq 0:6c56fb4bc5f0 180 do {
nexpaq 0:6c56fb4bc5f0 181 newValue = __LDREXW((volatile uint32_t*)valuePtr) - delta;
nexpaq 0:6c56fb4bc5f0 182 } while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
nexpaq 0:6c56fb4bc5f0 183 return newValue;
nexpaq 0:6c56fb4bc5f0 184 }
nexpaq 0:6c56fb4bc5f0 185
nexpaq 0:6c56fb4bc5f0 186 #else
nexpaq 0:6c56fb4bc5f0 187
nexpaq 0:6c56fb4bc5f0 188 bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
nexpaq 0:6c56fb4bc5f0 189 {
nexpaq 0:6c56fb4bc5f0 190 bool success;
nexpaq 0:6c56fb4bc5f0 191 uint8_t currentValue;
nexpaq 0:6c56fb4bc5f0 192 core_util_critical_section_enter();
nexpaq 0:6c56fb4bc5f0 193 currentValue = *ptr;
nexpaq 0:6c56fb4bc5f0 194 if (currentValue == *expectedCurrentValue) {
nexpaq 0:6c56fb4bc5f0 195 *ptr = desiredValue;
nexpaq 0:6c56fb4bc5f0 196 success = true;
nexpaq 0:6c56fb4bc5f0 197 } else {
nexpaq 0:6c56fb4bc5f0 198 *expectedCurrentValue = currentValue;
nexpaq 0:6c56fb4bc5f0 199 success = false;
nexpaq 0:6c56fb4bc5f0 200 }
nexpaq 0:6c56fb4bc5f0 201 core_util_critical_section_exit();
nexpaq 0:6c56fb4bc5f0 202 return success;
nexpaq 0:6c56fb4bc5f0 203 }
nexpaq 0:6c56fb4bc5f0 204
nexpaq 0:6c56fb4bc5f0 205 bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
nexpaq 0:6c56fb4bc5f0 206 {
nexpaq 0:6c56fb4bc5f0 207 bool success;
nexpaq 0:6c56fb4bc5f0 208 uint16_t currentValue;
nexpaq 0:6c56fb4bc5f0 209 core_util_critical_section_enter();
nexpaq 0:6c56fb4bc5f0 210 currentValue = *ptr;
nexpaq 0:6c56fb4bc5f0 211 if (currentValue == *expectedCurrentValue) {
nexpaq 0:6c56fb4bc5f0 212 *ptr = desiredValue;
nexpaq 0:6c56fb4bc5f0 213 success = true;
nexpaq 0:6c56fb4bc5f0 214 } else {
nexpaq 0:6c56fb4bc5f0 215 *expectedCurrentValue = currentValue;
nexpaq 0:6c56fb4bc5f0 216 success = false;
nexpaq 0:6c56fb4bc5f0 217 }
nexpaq 0:6c56fb4bc5f0 218 core_util_critical_section_exit();
nexpaq 0:6c56fb4bc5f0 219 return success;
nexpaq 0:6c56fb4bc5f0 220 }
nexpaq 0:6c56fb4bc5f0 221
nexpaq 0:6c56fb4bc5f0 222
nexpaq 0:6c56fb4bc5f0 223 bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
nexpaq 0:6c56fb4bc5f0 224 {
nexpaq 0:6c56fb4bc5f0 225 bool success;
nexpaq 0:6c56fb4bc5f0 226 uint32_t currentValue;
nexpaq 0:6c56fb4bc5f0 227 core_util_critical_section_enter();
nexpaq 0:6c56fb4bc5f0 228 currentValue = *ptr;
nexpaq 0:6c56fb4bc5f0 229 if (currentValue == *expectedCurrentValue) {
nexpaq 0:6c56fb4bc5f0 230 *ptr = desiredValue;
nexpaq 0:6c56fb4bc5f0 231 success = true;
nexpaq 0:6c56fb4bc5f0 232 } else {
nexpaq 0:6c56fb4bc5f0 233 *expectedCurrentValue = currentValue;
nexpaq 0:6c56fb4bc5f0 234 success = false;
nexpaq 0:6c56fb4bc5f0 235 }
nexpaq 0:6c56fb4bc5f0 236 core_util_critical_section_exit();
nexpaq 0:6c56fb4bc5f0 237 return success;
nexpaq 0:6c56fb4bc5f0 238 }
nexpaq 0:6c56fb4bc5f0 239
nexpaq 0:6c56fb4bc5f0 240
nexpaq 0:6c56fb4bc5f0 241 uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
nexpaq 0:6c56fb4bc5f0 242 {
nexpaq 0:6c56fb4bc5f0 243 uint8_t newValue;
nexpaq 0:6c56fb4bc5f0 244 core_util_critical_section_enter();
nexpaq 0:6c56fb4bc5f0 245 newValue = *valuePtr + delta;
nexpaq 0:6c56fb4bc5f0 246 *valuePtr = newValue;
nexpaq 0:6c56fb4bc5f0 247 core_util_critical_section_exit();
nexpaq 0:6c56fb4bc5f0 248 return newValue;
nexpaq 0:6c56fb4bc5f0 249 }
nexpaq 0:6c56fb4bc5f0 250
nexpaq 0:6c56fb4bc5f0 251 uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
nexpaq 0:6c56fb4bc5f0 252 {
nexpaq 0:6c56fb4bc5f0 253 uint16_t newValue;
nexpaq 0:6c56fb4bc5f0 254 core_util_critical_section_enter();
nexpaq 0:6c56fb4bc5f0 255 newValue = *valuePtr + delta;
nexpaq 0:6c56fb4bc5f0 256 *valuePtr = newValue;
nexpaq 0:6c56fb4bc5f0 257 core_util_critical_section_exit();
nexpaq 0:6c56fb4bc5f0 258 return newValue;
nexpaq 0:6c56fb4bc5f0 259 }
nexpaq 0:6c56fb4bc5f0 260
nexpaq 0:6c56fb4bc5f0 261 uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
nexpaq 0:6c56fb4bc5f0 262 {
nexpaq 0:6c56fb4bc5f0 263 uint32_t newValue;
nexpaq 0:6c56fb4bc5f0 264 core_util_critical_section_enter();
nexpaq 0:6c56fb4bc5f0 265 newValue = *valuePtr + delta;
nexpaq 0:6c56fb4bc5f0 266 *valuePtr = newValue;
nexpaq 0:6c56fb4bc5f0 267 core_util_critical_section_exit();
nexpaq 0:6c56fb4bc5f0 268 return newValue;
nexpaq 0:6c56fb4bc5f0 269 }
nexpaq 0:6c56fb4bc5f0 270
nexpaq 0:6c56fb4bc5f0 271
nexpaq 0:6c56fb4bc5f0 272 uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
nexpaq 0:6c56fb4bc5f0 273 {
nexpaq 0:6c56fb4bc5f0 274 uint8_t newValue;
nexpaq 0:6c56fb4bc5f0 275 core_util_critical_section_enter();
nexpaq 0:6c56fb4bc5f0 276 newValue = *valuePtr - delta;
nexpaq 0:6c56fb4bc5f0 277 *valuePtr = newValue;
nexpaq 0:6c56fb4bc5f0 278 core_util_critical_section_exit();
nexpaq 0:6c56fb4bc5f0 279 return newValue;
nexpaq 0:6c56fb4bc5f0 280 }
nexpaq 0:6c56fb4bc5f0 281
nexpaq 0:6c56fb4bc5f0 282 uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
nexpaq 0:6c56fb4bc5f0 283 {
nexpaq 0:6c56fb4bc5f0 284 uint16_t newValue;
nexpaq 0:6c56fb4bc5f0 285 core_util_critical_section_enter();
nexpaq 0:6c56fb4bc5f0 286 newValue = *valuePtr - delta;
nexpaq 0:6c56fb4bc5f0 287 *valuePtr = newValue;
nexpaq 0:6c56fb4bc5f0 288 core_util_critical_section_exit();
nexpaq 0:6c56fb4bc5f0 289 return newValue;
nexpaq 0:6c56fb4bc5f0 290 }
nexpaq 0:6c56fb4bc5f0 291
nexpaq 0:6c56fb4bc5f0 292 uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
nexpaq 0:6c56fb4bc5f0 293 {
nexpaq 0:6c56fb4bc5f0 294 uint32_t newValue;
nexpaq 0:6c56fb4bc5f0 295 core_util_critical_section_enter();
nexpaq 0:6c56fb4bc5f0 296 newValue = *valuePtr - delta;
nexpaq 0:6c56fb4bc5f0 297 *valuePtr = newValue;
nexpaq 0:6c56fb4bc5f0 298 core_util_critical_section_exit();
nexpaq 0:6c56fb4bc5f0 299 return newValue;
nexpaq 0:6c56fb4bc5f0 300 }
nexpaq 0:6c56fb4bc5f0 301
nexpaq 0:6c56fb4bc5f0 302 #endif
nexpaq 0:6c56fb4bc5f0 303
nexpaq 0:6c56fb4bc5f0 304
nexpaq 0:6c56fb4bc5f0 305 bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue) {
nexpaq 0:6c56fb4bc5f0 306 return core_util_atomic_cas_u32(
nexpaq 0:6c56fb4bc5f0 307 (uint32_t *)ptr,
nexpaq 0:6c56fb4bc5f0 308 (uint32_t *)expectedCurrentValue,
nexpaq 0:6c56fb4bc5f0 309 (uint32_t)desiredValue);
nexpaq 0:6c56fb4bc5f0 310 }
nexpaq 0:6c56fb4bc5f0 311
nexpaq 0:6c56fb4bc5f0 312 void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta) {
nexpaq 0:6c56fb4bc5f0 313 return (void *)core_util_atomic_incr_u32((uint32_t *)valuePtr, (uint32_t)delta);
nexpaq 0:6c56fb4bc5f0 314 }
nexpaq 0:6c56fb4bc5f0 315
nexpaq 0:6c56fb4bc5f0 316 void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta) {
nexpaq 0:6c56fb4bc5f0 317 return (void *)core_util_atomic_decr_u32((uint32_t *)valuePtr, (uint32_t)delta);
nexpaq 0:6c56fb4bc5f0 318 }
nexpaq 0:6c56fb4bc5f0 319