Maxim nexpaq / nexpaq_dev

Preliminary main mbed library for nexpaq development

hal/common/SPI.cpp@1:d96dbedaebdb, 2016-11-04 (annotated)

Committer:
nexpaq
Date:
Fri Nov 04 20:54:50 2016 +0000
Revision:
1:d96dbedaebdb
Parent:
0:6c56fb4bc5f0 
Removed extra directories for other platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nexpaq 0:6c56fb4bc5f0 1 /* mbed Microcontroller Library
nexpaq 0:6c56fb4bc5f0 2 * Copyright (c) 2006-2013 ARM Limited
nexpaq 0:6c56fb4bc5f0 3 *
nexpaq 0:6c56fb4bc5f0 4 * Licensed under the Apache License, Version 2.0 (the "License");
nexpaq 0:6c56fb4bc5f0 5 * you may not use this file except in compliance with the License.
nexpaq 0:6c56fb4bc5f0 6 * You may obtain a copy of the License at
nexpaq 0:6c56fb4bc5f0 7 *
nexpaq 0:6c56fb4bc5f0 8 * http://www.apache.org/licenses/LICENSE-2.0
nexpaq 0:6c56fb4bc5f0 9 *
nexpaq 0:6c56fb4bc5f0 10 * Unless required by applicable law or agreed to in writing, software
nexpaq 0:6c56fb4bc5f0 11 * distributed under the License is distributed on an "AS IS" BASIS,
nexpaq 0:6c56fb4bc5f0 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
nexpaq 0:6c56fb4bc5f0 13 * See the License for the specific language governing permissions and
nexpaq 0:6c56fb4bc5f0 14 * limitations under the License.
nexpaq 0:6c56fb4bc5f0 15 */
nexpaq 0:6c56fb4bc5f0 16 #include "SPI.h"
nexpaq 0:6c56fb4bc5f0 17 #include "critical.h"
nexpaq 0:6c56fb4bc5f0 18
nexpaq 0:6c56fb4bc5f0 19 #if DEVICE_SPI
nexpaq 0:6c56fb4bc5f0 20
nexpaq 0:6c56fb4bc5f0 21 namespace mbed {
nexpaq 0:6c56fb4bc5f0 22
nexpaq 0:6c56fb4bc5f0 23 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
nexpaq 0:6c56fb4bc5f0 24 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
nexpaq 0:6c56fb4bc5f0 25 #endif
nexpaq 0:6c56fb4bc5f0 26
nexpaq 0:6c56fb4bc5f0 27 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
nexpaq 0:6c56fb4bc5f0 28 _spi(),
nexpaq 0:6c56fb4bc5f0 29 #if DEVICE_SPI_ASYNCH
nexpaq 0:6c56fb4bc5f0 30 _irq(this),
nexpaq 0:6c56fb4bc5f0 31 _usage(DMA_USAGE_NEVER),
nexpaq 0:6c56fb4bc5f0 32 #endif
nexpaq 0:6c56fb4bc5f0 33 _bits(8),
nexpaq 0:6c56fb4bc5f0 34 _mode(0),
nexpaq 0:6c56fb4bc5f0 35 _hz(1000000) {
nexpaq 0:6c56fb4bc5f0 36 // No lock needed in the constructor
nexpaq 0:6c56fb4bc5f0 37
nexpaq 0:6c56fb4bc5f0 38 spi_init(&_spi, mosi, miso, sclk, ssel);
nexpaq 0:6c56fb4bc5f0 39 aquire();
nexpaq 0:6c56fb4bc5f0 40 }
nexpaq 0:6c56fb4bc5f0 41
nexpaq 0:6c56fb4bc5f0 42 void SPI::format(int bits, int mode) {
nexpaq 0:6c56fb4bc5f0 43 lock();
nexpaq 0:6c56fb4bc5f0 44 _bits = bits;
nexpaq 0:6c56fb4bc5f0 45 _mode = mode;
nexpaq 0:6c56fb4bc5f0 46 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
nexpaq 0:6c56fb4bc5f0 47 aquire();
nexpaq 0:6c56fb4bc5f0 48 unlock();
nexpaq 0:6c56fb4bc5f0 49 }
nexpaq 0:6c56fb4bc5f0 50
nexpaq 0:6c56fb4bc5f0 51 void SPI::frequency(int hz) {
nexpaq 0:6c56fb4bc5f0 52 lock();
nexpaq 0:6c56fb4bc5f0 53 _hz = hz;
nexpaq 0:6c56fb4bc5f0 54 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
nexpaq 0:6c56fb4bc5f0 55 aquire();
nexpaq 0:6c56fb4bc5f0 56 unlock();
nexpaq 0:6c56fb4bc5f0 57 }
nexpaq 0:6c56fb4bc5f0 58
nexpaq 0:6c56fb4bc5f0 59 SPI* SPI::_owner = NULL;
nexpaq 0:6c56fb4bc5f0 60 SingletonPtr<PlatformMutex> SPI::_mutex;
nexpaq 0:6c56fb4bc5f0 61
nexpaq 0:6c56fb4bc5f0 62 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
nexpaq 0:6c56fb4bc5f0 63 void SPI::aquire() {
nexpaq 0:6c56fb4bc5f0 64 lock();
nexpaq 0:6c56fb4bc5f0 65 if (_owner != this) {
nexpaq 0:6c56fb4bc5f0 66 spi_format(&_spi, _bits, _mode, 0);
nexpaq 0:6c56fb4bc5f0 67 spi_frequency(&_spi, _hz);
nexpaq 0:6c56fb4bc5f0 68 _owner = this;
nexpaq 0:6c56fb4bc5f0 69 }
nexpaq 0:6c56fb4bc5f0 70 unlock();
nexpaq 0:6c56fb4bc5f0 71 }
nexpaq 0:6c56fb4bc5f0 72
nexpaq 0:6c56fb4bc5f0 73 int SPI::write(int value) {
nexpaq 0:6c56fb4bc5f0 74 lock();
nexpaq 0:6c56fb4bc5f0 75 aquire();
nexpaq 0:6c56fb4bc5f0 76 int ret = spi_master_write(&_spi, value);
nexpaq 0:6c56fb4bc5f0 77 unlock();
nexpaq 0:6c56fb4bc5f0 78 return ret;
nexpaq 0:6c56fb4bc5f0 79 }
nexpaq 0:6c56fb4bc5f0 80
nexpaq 0:6c56fb4bc5f0 81 void SPI::lock() {
nexpaq 0:6c56fb4bc5f0 82 _mutex->lock();
nexpaq 0:6c56fb4bc5f0 83 }
nexpaq 0:6c56fb4bc5f0 84
nexpaq 0:6c56fb4bc5f0 85 void SPI::unlock() {
nexpaq 0:6c56fb4bc5f0 86 _mutex->unlock();
nexpaq 0:6c56fb4bc5f0 87 }
nexpaq 0:6c56fb4bc5f0 88
nexpaq 0:6c56fb4bc5f0 89 #if DEVICE_SPI_ASYNCH
nexpaq 0:6c56fb4bc5f0 90
nexpaq 0:6c56fb4bc5f0 91 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
nexpaq 0:6c56fb4bc5f0 92 {
nexpaq 0:6c56fb4bc5f0 93 if (spi_active(&_spi)) {
nexpaq 0:6c56fb4bc5f0 94 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
nexpaq 0:6c56fb4bc5f0 95 }
nexpaq 0:6c56fb4bc5f0 96 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
nexpaq 0:6c56fb4bc5f0 97 return 0;
nexpaq 0:6c56fb4bc5f0 98 }
nexpaq 0:6c56fb4bc5f0 99
nexpaq 0:6c56fb4bc5f0 100 void SPI::abort_transfer()
nexpaq 0:6c56fb4bc5f0 101 {
nexpaq 0:6c56fb4bc5f0 102 spi_abort_asynch(&_spi);
nexpaq 0:6c56fb4bc5f0 103 #if TRANSACTION_QUEUE_SIZE_SPI
nexpaq 0:6c56fb4bc5f0 104 dequeue_transaction();
nexpaq 0:6c56fb4bc5f0 105 #endif
nexpaq 0:6c56fb4bc5f0 106 }
nexpaq 0:6c56fb4bc5f0 107
nexpaq 0:6c56fb4bc5f0 108
nexpaq 0:6c56fb4bc5f0 109 void SPI::clear_transfer_buffer()
nexpaq 0:6c56fb4bc5f0 110 {
nexpaq 0:6c56fb4bc5f0 111 #if TRANSACTION_QUEUE_SIZE_SPI
nexpaq 0:6c56fb4bc5f0 112 _transaction_buffer.reset();
nexpaq 0:6c56fb4bc5f0 113 #endif
nexpaq 0:6c56fb4bc5f0 114 }
nexpaq 0:6c56fb4bc5f0 115
nexpaq 0:6c56fb4bc5f0 116 void SPI::abort_all_transfers()
nexpaq 0:6c56fb4bc5f0 117 {
nexpaq 0:6c56fb4bc5f0 118 clear_transfer_buffer();
nexpaq 0:6c56fb4bc5f0 119 abort_transfer();
nexpaq 0:6c56fb4bc5f0 120 }
nexpaq 0:6c56fb4bc5f0 121
nexpaq 0:6c56fb4bc5f0 122 int SPI::set_dma_usage(DMAUsage usage)
nexpaq 0:6c56fb4bc5f0 123 {
nexpaq 0:6c56fb4bc5f0 124 if (spi_active(&_spi)) {
nexpaq 0:6c56fb4bc5f0 125 return -1;
nexpaq 0:6c56fb4bc5f0 126 }
nexpaq 0:6c56fb4bc5f0 127 _usage = usage;
nexpaq 0:6c56fb4bc5f0 128 return 0;
nexpaq 0:6c56fb4bc5f0 129 }
nexpaq 0:6c56fb4bc5f0 130
nexpaq 0:6c56fb4bc5f0 131 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
nexpaq 0:6c56fb4bc5f0 132 {
nexpaq 0:6c56fb4bc5f0 133 #if TRANSACTION_QUEUE_SIZE_SPI
nexpaq 0:6c56fb4bc5f0 134 transaction_t t;
nexpaq 0:6c56fb4bc5f0 135
nexpaq 0:6c56fb4bc5f0 136 t.tx_buffer = const_cast<void *>(tx_buffer);
nexpaq 0:6c56fb4bc5f0 137 t.tx_length = tx_length;
nexpaq 0:6c56fb4bc5f0 138 t.rx_buffer = rx_buffer;
nexpaq 0:6c56fb4bc5f0 139 t.rx_length = rx_length;
nexpaq 0:6c56fb4bc5f0 140 t.event = event;
nexpaq 0:6c56fb4bc5f0 141 t.callback = callback;
nexpaq 0:6c56fb4bc5f0 142 t.width = bit_width;
nexpaq 0:6c56fb4bc5f0 143 Transaction<SPI> transaction(this, t);
nexpaq 0:6c56fb4bc5f0 144 if (_transaction_buffer.full()) {
nexpaq 0:6c56fb4bc5f0 145 return -1; // the buffer is full
nexpaq 0:6c56fb4bc5f0 146 } else {
nexpaq 0:6c56fb4bc5f0 147 core_util_critical_section_enter();
nexpaq 0:6c56fb4bc5f0 148 _transaction_buffer.push(transaction);
nexpaq 0:6c56fb4bc5f0 149 if (!spi_active(&_spi)) {
nexpaq 0:6c56fb4bc5f0 150 dequeue_transaction();
nexpaq 0:6c56fb4bc5f0 151 }
nexpaq 0:6c56fb4bc5f0 152 core_util_critical_section_exit();
nexpaq 0:6c56fb4bc5f0 153 return 0;
nexpaq 0:6c56fb4bc5f0 154 }
nexpaq 0:6c56fb4bc5f0 155 #else
nexpaq 0:6c56fb4bc5f0 156 return -1;
nexpaq 0:6c56fb4bc5f0 157 #endif
nexpaq 0:6c56fb4bc5f0 158 }
nexpaq 0:6c56fb4bc5f0 159
nexpaq 0:6c56fb4bc5f0 160 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
nexpaq 0:6c56fb4bc5f0 161 {
nexpaq 0:6c56fb4bc5f0 162 aquire();
nexpaq 0:6c56fb4bc5f0 163 _callback = callback;
nexpaq 0:6c56fb4bc5f0 164 _irq.callback(&SPI::irq_handler_asynch);
nexpaq 0:6c56fb4bc5f0 165 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
nexpaq 0:6c56fb4bc5f0 166 }
nexpaq 0:6c56fb4bc5f0 167
nexpaq 0:6c56fb4bc5f0 168 #if TRANSACTION_QUEUE_SIZE_SPI
nexpaq 0:6c56fb4bc5f0 169
nexpaq 0:6c56fb4bc5f0 170 void SPI::start_transaction(transaction_t *data)
nexpaq 0:6c56fb4bc5f0 171 {
nexpaq 0:6c56fb4bc5f0 172 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
nexpaq 0:6c56fb4bc5f0 173 }
nexpaq 0:6c56fb4bc5f0 174
nexpaq 0:6c56fb4bc5f0 175 void SPI::dequeue_transaction()
nexpaq 0:6c56fb4bc5f0 176 {
nexpaq 0:6c56fb4bc5f0 177 Transaction<SPI> t;
nexpaq 0:6c56fb4bc5f0 178 if (_transaction_buffer.pop(t)) {
nexpaq 0:6c56fb4bc5f0 179 SPI* obj = t.get_object();
nexpaq 0:6c56fb4bc5f0 180 transaction_t* data = t.get_transaction();
nexpaq 0:6c56fb4bc5f0 181 obj->start_transaction(data);
nexpaq 0:6c56fb4bc5f0 182 }
nexpaq 0:6c56fb4bc5f0 183 }
nexpaq 0:6c56fb4bc5f0 184
nexpaq 0:6c56fb4bc5f0 185 #endif
nexpaq 0:6c56fb4bc5f0 186
nexpaq 0:6c56fb4bc5f0 187 void SPI::irq_handler_asynch(void)
nexpaq 0:6c56fb4bc5f0 188 {
nexpaq 0:6c56fb4bc5f0 189 int event = spi_irq_handler_asynch(&_spi);
nexpaq 0:6c56fb4bc5f0 190 if (_callback && (event & SPI_EVENT_ALL)) {
nexpaq 0:6c56fb4bc5f0 191 _callback.call(event & SPI_EVENT_ALL);
nexpaq 0:6c56fb4bc5f0 192 }
nexpaq 0:6c56fb4bc5f0 193 #if TRANSACTION_QUEUE_SIZE_SPI
nexpaq 0:6c56fb4bc5f0 194 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
nexpaq 0:6c56fb4bc5f0 195 // SPI peripheral is free (event happend), dequeue transaction
nexpaq 0:6c56fb4bc5f0 196 dequeue_transaction();
nexpaq 0:6c56fb4bc5f0 197 }
nexpaq 0:6c56fb4bc5f0 198 #endif
nexpaq 0:6c56fb4bc5f0 199 }
nexpaq 0:6c56fb4bc5f0 200
nexpaq 0:6c56fb4bc5f0 201 #endif
nexpaq 0:6c56fb4bc5f0 202
nexpaq 0:6c56fb4bc5f0 203 } // namespace mbed
nexpaq 0:6c56fb4bc5f0 204
nexpaq 0:6c56fb4bc5f0 205 #endif