philippe s. / mbed-dev

mbed library sources. Supersedes mbed-src. Fixes analogIn and analogOut problems for TARGET_STM32F3. Tested on NUCLEO-F303K8, using 3 analogout and 7 analogin channels simultaneously. Added ability for STM32F334R8 and STM32F303K8 to use all three channels of DAC simultaneously. https://developer.mbed.org/users/StevieWray/code/mbed-dev/ Added ability for TARGET_STM32F3 to use more than one ADC simultaneously. https://developer.mbed.org/questions/67997/NUCLEO-F303K8ADC/

Fork of mbed-dev by mbed official

targets/cmsis/core_cm0plus.h@70:b3a5af880266, 2016-02-23 (annotated)

Committer:
neurofun
Date:
Tue Feb 23 21:59:35 2016 +0000
Revision:
70:b3a5af880266
Parent:
19:112740acecfa 
Edited DAC routines to allow for the simultaneous use of three channels from two DACs as seen on the STM32F334R8 and STM32F303K8. Edited ADC routines to allow for the simultaneous use of more than one ADC.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file core_cm0plus.h
bogdanm 0:9b334a45a8ff 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
mbed_official 19:112740acecfa 4 * @version V4.10
mbed_official 19:112740acecfa 5 * @date 18. March 2015
bogdanm 0:9b334a45a8ff 6 *
bogdanm 0:9b334a45a8ff 7 * @note
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 ******************************************************************************/
mbed_official 19:112740acecfa 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
bogdanm 0:9b334a45a8ff 11
bogdanm 0:9b334a45a8ff 12 All rights reserved.
bogdanm 0:9b334a45a8ff 13 Redistribution and use in source and binary forms, with or without
bogdanm 0:9b334a45a8ff 14 modification, are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 - Redistributions of source code must retain the above copyright
bogdanm 0:9b334a45a8ff 16 notice, this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 0:9b334a45a8ff 18 notice, this list of conditions and the following disclaimer in the
bogdanm 0:9b334a45a8ff 19 documentation and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 0:9b334a45a8ff 21 to endorse or promote products derived from this software without
bogdanm 0:9b334a45a8ff 22 specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 0:9b334a45a8ff 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 0:9b334a45a8ff 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 0:9b334a45a8ff 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 0:9b334a45a8ff 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 0:9b334a45a8ff 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 0:9b334a45a8ff 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 0:9b334a45a8ff 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 0:9b334a45a8ff 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 35 ---------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 #if defined ( __ICCARM__ )
bogdanm 0:9b334a45a8ff 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 0:9b334a45a8ff 40 #endif
bogdanm 0:9b334a45a8ff 41
mbed_official 19:112740acecfa 42 #ifndef __CORE_CM0PLUS_H_GENERIC
mbed_official 19:112740acecfa 43 #define __CORE_CM0PLUS_H_GENERIC
mbed_official 19:112740acecfa 44
bogdanm 0:9b334a45a8ff 45 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 46 extern "C" {
bogdanm 0:9b334a45a8ff 47 #endif
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 0:9b334a45a8ff 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 0:9b334a45a8ff 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 0:9b334a45a8ff 56 Unions are used for effective representation of core registers.
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 0:9b334a45a8ff 59 Function-like macros are used to allow more efficient code.
bogdanm 0:9b334a45a8ff 60 */
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /*******************************************************************************
bogdanm 0:9b334a45a8ff 64 * CMSIS definitions
bogdanm 0:9b334a45a8ff 65 ******************************************************************************/
bogdanm 0:9b334a45a8ff 66 /** \ingroup Cortex-M0+
bogdanm 0:9b334a45a8ff 67 @{
bogdanm 0:9b334a45a8ff 68 */
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /* CMSIS CM0P definitions */
mbed_official 19:112740acecfa 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
mbed_official 19:112740acecfa 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
bogdanm 0:9b334a45a8ff 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
bogdanm 0:9b334a45a8ff 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 0:9b334a45a8ff 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 0:9b334a45a8ff 82 #define __STATIC_INLINE static __inline
bogdanm 0:9b334a45a8ff 83
mbed_official 19:112740acecfa 84 #elif defined ( __GNUC__ )
mbed_official 19:112740acecfa 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mbed_official 19:112740acecfa 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mbed_official 19:112740acecfa 87 #define __STATIC_INLINE static inline
mbed_official 19:112740acecfa 88
bogdanm 0:9b334a45a8ff 89 #elif defined ( __ICCARM__ )
bogdanm 0:9b334a45a8ff 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 0:9b334a45a8ff 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 0:9b334a45a8ff 92 #define __STATIC_INLINE static inline
bogdanm 0:9b334a45a8ff 93
mbed_official 19:112740acecfa 94 #elif defined ( __TMS470__ )
mbed_official 19:112740acecfa 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 0:9b334a45a8ff 96 #define __STATIC_INLINE static inline
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 #elif defined ( __TASKING__ )
bogdanm 0:9b334a45a8ff 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 0:9b334a45a8ff 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 0:9b334a45a8ff 101 #define __STATIC_INLINE static inline
bogdanm 0:9b334a45a8ff 102
mbed_official 19:112740acecfa 103 #elif defined ( __CSMC__ )
mbed_official 19:112740acecfa 104 #define __packed
mbed_official 19:112740acecfa 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
mbed_official 19:112740acecfa 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
mbed_official 19:112740acecfa 107 #define __STATIC_INLINE static inline
mbed_official 19:112740acecfa 108
bogdanm 0:9b334a45a8ff 109 #endif
bogdanm 0:9b334a45a8ff 110
mbed_official 19:112740acecfa 111 /** __FPU_USED indicates whether an FPU is used or not.
mbed_official 19:112740acecfa 112 This core does not support an FPU at all
bogdanm 0:9b334a45a8ff 113 */
bogdanm 0:9b334a45a8ff 114 #define __FPU_USED 0
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 117 #if defined __TARGET_FPU_VFP
bogdanm 0:9b334a45a8ff 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 119 #endif
bogdanm 0:9b334a45a8ff 120
mbed_official 19:112740acecfa 121 #elif defined ( __GNUC__ )
mbed_official 19:112740acecfa 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbed_official 19:112740acecfa 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 19:112740acecfa 124 #endif
mbed_official 19:112740acecfa 125
bogdanm 0:9b334a45a8ff 126 #elif defined ( __ICCARM__ )
bogdanm 0:9b334a45a8ff 127 #if defined __ARMVFP__
bogdanm 0:9b334a45a8ff 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 129 #endif
bogdanm 0:9b334a45a8ff 130
mbed_official 19:112740acecfa 131 #elif defined ( __TMS470__ )
mbed_official 19:112740acecfa 132 #if defined __TI__VFP_SUPPORT____
bogdanm 0:9b334a45a8ff 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 134 #endif
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 #elif defined ( __TASKING__ )
bogdanm 0:9b334a45a8ff 137 #if defined __FPU_VFP__
bogdanm 0:9b334a45a8ff 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 139 #endif
mbed_official 19:112740acecfa 140
mbed_official 19:112740acecfa 141 #elif defined ( __CSMC__ ) /* Cosmic */
mbed_official 19:112740acecfa 142 #if ( __CSMC__ & 0x400) // FPU present for parser
mbed_official 19:112740acecfa 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 19:112740acecfa 144 #endif
bogdanm 0:9b334a45a8ff 145 #endif
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 #include <stdint.h> /* standard types definitions */
bogdanm 0:9b334a45a8ff 148 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 0:9b334a45a8ff 149 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 0:9b334a45a8ff 150
mbed_official 19:112740acecfa 151 #ifdef __cplusplus
mbed_official 19:112740acecfa 152 }
mbed_official 19:112740acecfa 153 #endif
mbed_official 19:112740acecfa 154
bogdanm 0:9b334a45a8ff 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 #ifndef __CMSIS_GENERIC
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
bogdanm 0:9b334a45a8ff 160 #define __CORE_CM0PLUS_H_DEPENDANT
bogdanm 0:9b334a45a8ff 161
mbed_official 19:112740acecfa 162 #ifdef __cplusplus
mbed_official 19:112740acecfa 163 extern "C" {
mbed_official 19:112740acecfa 164 #endif
mbed_official 19:112740acecfa 165
bogdanm 0:9b334a45a8ff 166 /* check device defines and use defaults */
bogdanm 0:9b334a45a8ff 167 #if defined __CHECK_DEVICE_DEFINES
bogdanm 0:9b334a45a8ff 168 #ifndef __CM0PLUS_REV
bogdanm 0:9b334a45a8ff 169 #define __CM0PLUS_REV 0x0000
bogdanm 0:9b334a45a8ff 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 171 #endif
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 #ifndef __MPU_PRESENT
bogdanm 0:9b334a45a8ff 174 #define __MPU_PRESENT 0
bogdanm 0:9b334a45a8ff 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 176 #endif
bogdanm 0:9b334a45a8ff 177
bogdanm 0:9b334a45a8ff 178 #ifndef __VTOR_PRESENT
bogdanm 0:9b334a45a8ff 179 #define __VTOR_PRESENT 0
bogdanm 0:9b334a45a8ff 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 181 #endif
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 #ifndef __NVIC_PRIO_BITS
bogdanm 0:9b334a45a8ff 184 #define __NVIC_PRIO_BITS 2
bogdanm 0:9b334a45a8ff 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 186 #endif
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 #ifndef __Vendor_SysTickConfig
bogdanm 0:9b334a45a8ff 189 #define __Vendor_SysTickConfig 0
bogdanm 0:9b334a45a8ff 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 191 #endif
bogdanm 0:9b334a45a8ff 192 #endif
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 0:9b334a45a8ff 195 /**
bogdanm 0:9b334a45a8ff 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 <strong>IO Type Qualifiers</strong> are used
bogdanm 0:9b334a45a8ff 199 \li to specify the access to peripheral variables.
bogdanm 0:9b334a45a8ff 200 \li for automatic generation of peripheral register debug information.
bogdanm 0:9b334a45a8ff 201 */
bogdanm 0:9b334a45a8ff 202 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 203 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 0:9b334a45a8ff 204 #else
bogdanm 0:9b334a45a8ff 205 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 0:9b334a45a8ff 206 #endif
bogdanm 0:9b334a45a8ff 207 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 0:9b334a45a8ff 208 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /*@} end of group Cortex-M0+ */
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 /*******************************************************************************
bogdanm 0:9b334a45a8ff 215 * Register Abstraction
bogdanm 0:9b334a45a8ff 216 Core Register contain:
bogdanm 0:9b334a45a8ff 217 - Core Register
bogdanm 0:9b334a45a8ff 218 - Core NVIC Register
bogdanm 0:9b334a45a8ff 219 - Core SCB Register
bogdanm 0:9b334a45a8ff 220 - Core SysTick Register
bogdanm 0:9b334a45a8ff 221 - Core MPU Register
bogdanm 0:9b334a45a8ff 222 ******************************************************************************/
bogdanm 0:9b334a45a8ff 223 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 0:9b334a45a8ff 224 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 0:9b334a45a8ff 225 */
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 228 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 0:9b334a45a8ff 229 \brief Core Register type definitions.
bogdanm 0:9b334a45a8ff 230 @{
bogdanm 0:9b334a45a8ff 231 */
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 0:9b334a45a8ff 234 */
bogdanm 0:9b334a45a8ff 235 typedef union
bogdanm 0:9b334a45a8ff 236 {
bogdanm 0:9b334a45a8ff 237 struct
bogdanm 0:9b334a45a8ff 238 {
mbed_official 19:112740acecfa 239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
bogdanm 0:9b334a45a8ff 240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 0:9b334a45a8ff 241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 0:9b334a45a8ff 242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 0:9b334a45a8ff 243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 0:9b334a45a8ff 244 } b; /*!< Structure used for bit access */
bogdanm 0:9b334a45a8ff 245 uint32_t w; /*!< Type used for word access */
bogdanm 0:9b334a45a8ff 246 } APSR_Type;
bogdanm 0:9b334a45a8ff 247
mbed_official 19:112740acecfa 248 /* APSR Register Definitions */
mbed_official 19:112740acecfa 249 #define APSR_N_Pos 31 /*!< APSR: N Position */
mbed_official 19:112740acecfa 250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mbed_official 19:112740acecfa 251
mbed_official 19:112740acecfa 252 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
mbed_official 19:112740acecfa 253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mbed_official 19:112740acecfa 254
mbed_official 19:112740acecfa 255 #define APSR_C_Pos 29 /*!< APSR: C Position */
mbed_official 19:112740acecfa 256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mbed_official 19:112740acecfa 257
mbed_official 19:112740acecfa 258 #define APSR_V_Pos 28 /*!< APSR: V Position */
mbed_official 19:112740acecfa 259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mbed_official 19:112740acecfa 260
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 0:9b334a45a8ff 263 */
bogdanm 0:9b334a45a8ff 264 typedef union
bogdanm 0:9b334a45a8ff 265 {
bogdanm 0:9b334a45a8ff 266 struct
bogdanm 0:9b334a45a8ff 267 {
bogdanm 0:9b334a45a8ff 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 0:9b334a45a8ff 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 0:9b334a45a8ff 270 } b; /*!< Structure used for bit access */
bogdanm 0:9b334a45a8ff 271 uint32_t w; /*!< Type used for word access */
bogdanm 0:9b334a45a8ff 272 } IPSR_Type;
bogdanm 0:9b334a45a8ff 273
mbed_official 19:112740acecfa 274 /* IPSR Register Definitions */
mbed_official 19:112740acecfa 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
mbed_official 19:112740acecfa 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mbed_official 19:112740acecfa 277
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 0:9b334a45a8ff 280 */
bogdanm 0:9b334a45a8ff 281 typedef union
bogdanm 0:9b334a45a8ff 282 {
bogdanm 0:9b334a45a8ff 283 struct
bogdanm 0:9b334a45a8ff 284 {
bogdanm 0:9b334a45a8ff 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 0:9b334a45a8ff 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 0:9b334a45a8ff 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mbed_official 19:112740acecfa 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
bogdanm 0:9b334a45a8ff 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 0:9b334a45a8ff 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 0:9b334a45a8ff 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 0:9b334a45a8ff 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 0:9b334a45a8ff 293 } b; /*!< Structure used for bit access */
bogdanm 0:9b334a45a8ff 294 uint32_t w; /*!< Type used for word access */
bogdanm 0:9b334a45a8ff 295 } xPSR_Type;
bogdanm 0:9b334a45a8ff 296
mbed_official 19:112740acecfa 297 /* xPSR Register Definitions */
mbed_official 19:112740acecfa 298 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
mbed_official 19:112740acecfa 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mbed_official 19:112740acecfa 300
mbed_official 19:112740acecfa 301 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
mbed_official 19:112740acecfa 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mbed_official 19:112740acecfa 303
mbed_official 19:112740acecfa 304 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
mbed_official 19:112740acecfa 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mbed_official 19:112740acecfa 306
mbed_official 19:112740acecfa 307 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
mbed_official 19:112740acecfa 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mbed_official 19:112740acecfa 309
mbed_official 19:112740acecfa 310 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
mbed_official 19:112740acecfa 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mbed_official 19:112740acecfa 312
mbed_official 19:112740acecfa 313 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
mbed_official 19:112740acecfa 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mbed_official 19:112740acecfa 315
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 0:9b334a45a8ff 318 */
bogdanm 0:9b334a45a8ff 319 typedef union
bogdanm 0:9b334a45a8ff 320 {
bogdanm 0:9b334a45a8ff 321 struct
bogdanm 0:9b334a45a8ff 322 {
bogdanm 0:9b334a45a8ff 323 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 0:9b334a45a8ff 324 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mbed_official 19:112740acecfa 325 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
bogdanm 0:9b334a45a8ff 326 } b; /*!< Structure used for bit access */
bogdanm 0:9b334a45a8ff 327 uint32_t w; /*!< Type used for word access */
bogdanm 0:9b334a45a8ff 328 } CONTROL_Type;
bogdanm 0:9b334a45a8ff 329
mbed_official 19:112740acecfa 330 /* CONTROL Register Definitions */
mbed_official 19:112740acecfa 331 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
mbed_official 19:112740acecfa 332 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mbed_official 19:112740acecfa 333
mbed_official 19:112740acecfa 334 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
mbed_official 19:112740acecfa 335 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
mbed_official 19:112740acecfa 336
bogdanm 0:9b334a45a8ff 337 /*@} end of group CMSIS_CORE */
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 0:9b334a45a8ff 342 \brief Type definitions for the NVIC Registers
bogdanm 0:9b334a45a8ff 343 @{
bogdanm 0:9b334a45a8ff 344 */
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 0:9b334a45a8ff 347 */
bogdanm 0:9b334a45a8ff 348 typedef struct
bogdanm 0:9b334a45a8ff 349 {
bogdanm 0:9b334a45a8ff 350 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 0:9b334a45a8ff 351 uint32_t RESERVED0[31];
bogdanm 0:9b334a45a8ff 352 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 0:9b334a45a8ff 353 uint32_t RSERVED1[31];
bogdanm 0:9b334a45a8ff 354 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 0:9b334a45a8ff 355 uint32_t RESERVED2[31];
bogdanm 0:9b334a45a8ff 356 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 0:9b334a45a8ff 357 uint32_t RESERVED3[31];
bogdanm 0:9b334a45a8ff 358 uint32_t RESERVED4[64];
bogdanm 0:9b334a45a8ff 359 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 0:9b334a45a8ff 360 } NVIC_Type;
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 /*@} end of group CMSIS_NVIC */
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 366 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 0:9b334a45a8ff 367 \brief Type definitions for the System Control Block Registers
bogdanm 0:9b334a45a8ff 368 @{
bogdanm 0:9b334a45a8ff 369 */
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 0:9b334a45a8ff 372 */
bogdanm 0:9b334a45a8ff 373 typedef struct
bogdanm 0:9b334a45a8ff 374 {
bogdanm 0:9b334a45a8ff 375 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 0:9b334a45a8ff 376 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 0:9b334a45a8ff 377 #if (__VTOR_PRESENT == 1)
bogdanm 0:9b334a45a8ff 378 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 0:9b334a45a8ff 379 #else
bogdanm 0:9b334a45a8ff 380 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 381 #endif
bogdanm 0:9b334a45a8ff 382 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 0:9b334a45a8ff 383 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 0:9b334a45a8ff 384 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 0:9b334a45a8ff 385 uint32_t RESERVED1;
bogdanm 0:9b334a45a8ff 386 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 0:9b334a45a8ff 387 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 0:9b334a45a8ff 388 } SCB_Type;
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 /* SCB CPUID Register Definitions */
bogdanm 0:9b334a45a8ff 391 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 0:9b334a45a8ff 392 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 0:9b334a45a8ff 395 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 0:9b334a45a8ff 398 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 0:9b334a45a8ff 399
bogdanm 0:9b334a45a8ff 400 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 0:9b334a45a8ff 401 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mbed_official 19:112740acecfa 404 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 /* SCB Interrupt Control State Register Definitions */
bogdanm 0:9b334a45a8ff 407 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 0:9b334a45a8ff 408 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 0:9b334a45a8ff 411 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 0:9b334a45a8ff 414 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 0:9b334a45a8ff 417 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 0:9b334a45a8ff 420 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 0:9b334a45a8ff 423 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 0:9b334a45a8ff 426 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 0:9b334a45a8ff 429 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 0:9b334a45a8ff 430
bogdanm 0:9b334a45a8ff 431 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mbed_official 19:112740acecfa 432 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 #if (__VTOR_PRESENT == 1)
bogdanm 0:9b334a45a8ff 435 /* SCB Interrupt Control State Register Definitions */
bogdanm 0:9b334a45a8ff 436 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
bogdanm 0:9b334a45a8ff 437 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 0:9b334a45a8ff 438 #endif
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 0:9b334a45a8ff 441 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 0:9b334a45a8ff 442 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 0:9b334a45a8ff 445 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 0:9b334a45a8ff 448 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 0:9b334a45a8ff 451 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 0:9b334a45a8ff 454 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 /* SCB System Control Register Definitions */
bogdanm 0:9b334a45a8ff 457 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 0:9b334a45a8ff 458 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 0:9b334a45a8ff 461 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 0:9b334a45a8ff 464 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /* SCB Configuration Control Register Definitions */
bogdanm 0:9b334a45a8ff 467 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 0:9b334a45a8ff 468 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 0:9b334a45a8ff 471 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /* SCB System Handler Control and State Register Definitions */
bogdanm 0:9b334a45a8ff 474 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 0:9b334a45a8ff 475 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 /*@} end of group CMSIS_SCB */
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 481 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 0:9b334a45a8ff 482 \brief Type definitions for the System Timer Registers.
bogdanm 0:9b334a45a8ff 483 @{
bogdanm 0:9b334a45a8ff 484 */
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 0:9b334a45a8ff 487 */
bogdanm 0:9b334a45a8ff 488 typedef struct
bogdanm 0:9b334a45a8ff 489 {
bogdanm 0:9b334a45a8ff 490 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 0:9b334a45a8ff 491 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 0:9b334a45a8ff 492 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 0:9b334a45a8ff 493 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 0:9b334a45a8ff 494 } SysTick_Type;
bogdanm 0:9b334a45a8ff 495
bogdanm 0:9b334a45a8ff 496 /* SysTick Control / Status Register Definitions */
bogdanm 0:9b334a45a8ff 497 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 0:9b334a45a8ff 498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 0:9b334a45a8ff 501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 0:9b334a45a8ff 502
bogdanm 0:9b334a45a8ff 503 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 0:9b334a45a8ff 504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mbed_official 19:112740acecfa 507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 0:9b334a45a8ff 508
bogdanm 0:9b334a45a8ff 509 /* SysTick Reload Register Definitions */
bogdanm 0:9b334a45a8ff 510 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mbed_official 19:112740acecfa 511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 /* SysTick Current Register Definitions */
bogdanm 0:9b334a45a8ff 514 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mbed_official 19:112740acecfa 515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /* SysTick Calibration Register Definitions */
bogdanm 0:9b334a45a8ff 518 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 0:9b334a45a8ff 519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 0:9b334a45a8ff 520
bogdanm 0:9b334a45a8ff 521 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 0:9b334a45a8ff 522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mbed_official 19:112740acecfa 525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
bogdanm 0:9b334a45a8ff 526
bogdanm 0:9b334a45a8ff 527 /*@} end of group CMSIS_SysTick */
bogdanm 0:9b334a45a8ff 528
bogdanm 0:9b334a45a8ff 529 #if (__MPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 530 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 531 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 0:9b334a45a8ff 532 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 0:9b334a45a8ff 533 @{
bogdanm 0:9b334a45a8ff 534 */
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 0:9b334a45a8ff 537 */
bogdanm 0:9b334a45a8ff 538 typedef struct
bogdanm 0:9b334a45a8ff 539 {
bogdanm 0:9b334a45a8ff 540 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 0:9b334a45a8ff 541 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 0:9b334a45a8ff 542 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 0:9b334a45a8ff 543 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 0:9b334a45a8ff 544 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 0:9b334a45a8ff 545 } MPU_Type;
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 /* MPU Type Register */
bogdanm 0:9b334a45a8ff 548 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 0:9b334a45a8ff 549 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 0:9b334a45a8ff 552 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 0:9b334a45a8ff 553
bogdanm 0:9b334a45a8ff 554 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mbed_official 19:112740acecfa 555 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 /* MPU Control Register */
bogdanm 0:9b334a45a8ff 558 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 0:9b334a45a8ff 559 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 0:9b334a45a8ff 560
bogdanm 0:9b334a45a8ff 561 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 0:9b334a45a8ff 562 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mbed_official 19:112740acecfa 565 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
bogdanm 0:9b334a45a8ff 566
bogdanm 0:9b334a45a8ff 567 /* MPU Region Number Register */
bogdanm 0:9b334a45a8ff 568 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mbed_official 19:112740acecfa 569 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571 /* MPU Region Base Address Register */
bogdanm 0:9b334a45a8ff 572 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
bogdanm 0:9b334a45a8ff 573 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 0:9b334a45a8ff 576 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 0:9b334a45a8ff 577
bogdanm 0:9b334a45a8ff 578 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mbed_official 19:112740acecfa 579 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
bogdanm 0:9b334a45a8ff 580
bogdanm 0:9b334a45a8ff 581 /* MPU Region Attribute and Size Register */
bogdanm 0:9b334a45a8ff 582 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 0:9b334a45a8ff 583 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 0:9b334a45a8ff 586 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 0:9b334a45a8ff 587
bogdanm 0:9b334a45a8ff 588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 0:9b334a45a8ff 589 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 0:9b334a45a8ff 592 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 0:9b334a45a8ff 593
bogdanm 0:9b334a45a8ff 594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 0:9b334a45a8ff 595 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 0:9b334a45a8ff 598 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 0:9b334a45a8ff 601 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 0:9b334a45a8ff 602
bogdanm 0:9b334a45a8ff 603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 0:9b334a45a8ff 604 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 0:9b334a45a8ff 605
bogdanm 0:9b334a45a8ff 606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 0:9b334a45a8ff 607 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 0:9b334a45a8ff 608
bogdanm 0:9b334a45a8ff 609 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mbed_official 19:112740acecfa 610 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 0:9b334a45a8ff 611
bogdanm 0:9b334a45a8ff 612 /*@} end of group CMSIS_MPU */
bogdanm 0:9b334a45a8ff 613 #endif
bogdanm 0:9b334a45a8ff 614
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 0:9b334a45a8ff 618 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 0:9b334a45a8ff 619 are only accessible over DAP and not via processor. Therefore
bogdanm 0:9b334a45a8ff 620 they are not covered by the Cortex-M0 header file.
bogdanm 0:9b334a45a8ff 621 @{
bogdanm 0:9b334a45a8ff 622 */
bogdanm 0:9b334a45a8ff 623 /*@} end of group CMSIS_CoreDebug */
bogdanm 0:9b334a45a8ff 624
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 627 \defgroup CMSIS_core_base Core Definitions
bogdanm 0:9b334a45a8ff 628 \brief Definitions for base addresses, unions, and structures.
bogdanm 0:9b334a45a8ff 629 @{
bogdanm 0:9b334a45a8ff 630 */
bogdanm 0:9b334a45a8ff 631
bogdanm 0:9b334a45a8ff 632 /* Memory mapping of Cortex-M0+ Hardware */
bogdanm 0:9b334a45a8ff 633 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 0:9b334a45a8ff 634 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 0:9b334a45a8ff 635 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 0:9b334a45a8ff 636 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 0:9b334a45a8ff 639 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 0:9b334a45a8ff 640 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 0:9b334a45a8ff 641
bogdanm 0:9b334a45a8ff 642 #if (__MPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 643 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 0:9b334a45a8ff 644 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 0:9b334a45a8ff 645 #endif
bogdanm 0:9b334a45a8ff 646
bogdanm 0:9b334a45a8ff 647 /*@} */
bogdanm 0:9b334a45a8ff 648
bogdanm 0:9b334a45a8ff 649
bogdanm 0:9b334a45a8ff 650
bogdanm 0:9b334a45a8ff 651 /*******************************************************************************
bogdanm 0:9b334a45a8ff 652 * Hardware Abstraction Layer
bogdanm 0:9b334a45a8ff 653 Core Function Interface contains:
bogdanm 0:9b334a45a8ff 654 - Core NVIC Functions
bogdanm 0:9b334a45a8ff 655 - Core SysTick Functions
bogdanm 0:9b334a45a8ff 656 - Core Register Access Functions
bogdanm 0:9b334a45a8ff 657 ******************************************************************************/
bogdanm 0:9b334a45a8ff 658 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 0:9b334a45a8ff 659 */
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661
bogdanm 0:9b334a45a8ff 662
bogdanm 0:9b334a45a8ff 663 /* ########################## NVIC functions #################################### */
bogdanm 0:9b334a45a8ff 664 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 0:9b334a45a8ff 665 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 0:9b334a45a8ff 666 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 0:9b334a45a8ff 667 @{
bogdanm 0:9b334a45a8ff 668 */
bogdanm 0:9b334a45a8ff 669
bogdanm 0:9b334a45a8ff 670 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 0:9b334a45a8ff 671 /* The following MACROS handle generation of the register offset and byte masks */
mbed_official 19:112740acecfa 672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
mbed_official 19:112740acecfa 673 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
mbed_official 19:112740acecfa 674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 /** \brief Enable External Interrupt
bogdanm 0:9b334a45a8ff 678
bogdanm 0:9b334a45a8ff 679 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 0:9b334a45a8ff 680
bogdanm 0:9b334a45a8ff 681 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 0:9b334a45a8ff 682 */
bogdanm 0:9b334a45a8ff 683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 684 {
mbed_official 19:112740acecfa 685 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 0:9b334a45a8ff 686 }
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688
bogdanm 0:9b334a45a8ff 689 /** \brief Disable External Interrupt
bogdanm 0:9b334a45a8ff 690
bogdanm 0:9b334a45a8ff 691 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 0:9b334a45a8ff 692
bogdanm 0:9b334a45a8ff 693 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 0:9b334a45a8ff 694 */
bogdanm 0:9b334a45a8ff 695 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 696 {
mbed_official 19:112740acecfa 697 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 0:9b334a45a8ff 698 }
bogdanm 0:9b334a45a8ff 699
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 /** \brief Get Pending Interrupt
bogdanm 0:9b334a45a8ff 702
bogdanm 0:9b334a45a8ff 703 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 0:9b334a45a8ff 704 for the specified interrupt.
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 707
bogdanm 0:9b334a45a8ff 708 \return 0 Interrupt status is not pending.
bogdanm 0:9b334a45a8ff 709 \return 1 Interrupt status is pending.
bogdanm 0:9b334a45a8ff 710 */
bogdanm 0:9b334a45a8ff 711 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 712 {
mbed_official 19:112740acecfa 713 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 0:9b334a45a8ff 714 }
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716
bogdanm 0:9b334a45a8ff 717 /** \brief Set Pending Interrupt
bogdanm 0:9b334a45a8ff 718
bogdanm 0:9b334a45a8ff 719 The function sets the pending bit of an external interrupt.
bogdanm 0:9b334a45a8ff 720
bogdanm 0:9b334a45a8ff 721 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 0:9b334a45a8ff 722 */
bogdanm 0:9b334a45a8ff 723 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 724 {
mbed_official 19:112740acecfa 725 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 0:9b334a45a8ff 726 }
bogdanm 0:9b334a45a8ff 727
bogdanm 0:9b334a45a8ff 728
bogdanm 0:9b334a45a8ff 729 /** \brief Clear Pending Interrupt
bogdanm 0:9b334a45a8ff 730
bogdanm 0:9b334a45a8ff 731 The function clears the pending bit of an external interrupt.
bogdanm 0:9b334a45a8ff 732
bogdanm 0:9b334a45a8ff 733 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 0:9b334a45a8ff 734 */
bogdanm 0:9b334a45a8ff 735 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 736 {
mbed_official 19:112740acecfa 737 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 0:9b334a45a8ff 738 }
bogdanm 0:9b334a45a8ff 739
bogdanm 0:9b334a45a8ff 740
bogdanm 0:9b334a45a8ff 741 /** \brief Set Interrupt Priority
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743 The function sets the priority of an interrupt.
bogdanm 0:9b334a45a8ff 744
bogdanm 0:9b334a45a8ff 745 \note The priority cannot be set for every core interrupt.
bogdanm 0:9b334a45a8ff 746
bogdanm 0:9b334a45a8ff 747 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 748 \param [in] priority Priority to set.
bogdanm 0:9b334a45a8ff 749 */
bogdanm 0:9b334a45a8ff 750 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 0:9b334a45a8ff 751 {
mbed_official 19:112740acecfa 752 if((int32_t)(IRQn) < 0) {
mbed_official 19:112740acecfa 753 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mbed_official 19:112740acecfa 754 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official 19:112740acecfa 755 }
bogdanm 0:9b334a45a8ff 756 else {
mbed_official 19:112740acecfa 757 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mbed_official 19:112740acecfa 758 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official 19:112740acecfa 759 }
bogdanm 0:9b334a45a8ff 760 }
bogdanm 0:9b334a45a8ff 761
bogdanm 0:9b334a45a8ff 762
bogdanm 0:9b334a45a8ff 763 /** \brief Get Interrupt Priority
bogdanm 0:9b334a45a8ff 764
bogdanm 0:9b334a45a8ff 765 The function reads the priority of an interrupt. The interrupt
bogdanm 0:9b334a45a8ff 766 number can be positive to specify an external (device specific)
bogdanm 0:9b334a45a8ff 767 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 0:9b334a45a8ff 768
bogdanm 0:9b334a45a8ff 769
bogdanm 0:9b334a45a8ff 770 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 771 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 0:9b334a45a8ff 772 priority bits of the microcontroller.
bogdanm 0:9b334a45a8ff 773 */
bogdanm 0:9b334a45a8ff 774 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 775 {
bogdanm 0:9b334a45a8ff 776
mbed_official 19:112740acecfa 777 if((int32_t)(IRQn) < 0) {
mbed_official 19:112740acecfa 778 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
mbed_official 19:112740acecfa 779 }
bogdanm 0:9b334a45a8ff 780 else {
mbed_official 19:112740acecfa 781 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
mbed_official 19:112740acecfa 782 }
bogdanm 0:9b334a45a8ff 783 }
bogdanm 0:9b334a45a8ff 784
bogdanm 0:9b334a45a8ff 785
bogdanm 0:9b334a45a8ff 786 /** \brief System Reset
bogdanm 0:9b334a45a8ff 787
bogdanm 0:9b334a45a8ff 788 The function initiates a system reset request to reset the MCU.
bogdanm 0:9b334a45a8ff 789 */
bogdanm 0:9b334a45a8ff 790 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 0:9b334a45a8ff 791 {
bogdanm 0:9b334a45a8ff 792 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 0:9b334a45a8ff 793 buffered write are completed before reset */
mbed_official 19:112740acecfa 794 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 0:9b334a45a8ff 795 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 0:9b334a45a8ff 796 __DSB(); /* Ensure completion of memory access */
mbed_official 19:112740acecfa 797 while(1) { __NOP(); } /* wait until reset */
bogdanm 0:9b334a45a8ff 798 }
bogdanm 0:9b334a45a8ff 799
bogdanm 0:9b334a45a8ff 800 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 0:9b334a45a8ff 801
bogdanm 0:9b334a45a8ff 802
bogdanm 0:9b334a45a8ff 803
bogdanm 0:9b334a45a8ff 804 /* ################################## SysTick function ############################################ */
bogdanm 0:9b334a45a8ff 805 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 0:9b334a45a8ff 806 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 0:9b334a45a8ff 807 \brief Functions that configure the System.
bogdanm 0:9b334a45a8ff 808 @{
bogdanm 0:9b334a45a8ff 809 */
bogdanm 0:9b334a45a8ff 810
bogdanm 0:9b334a45a8ff 811 #if (__Vendor_SysTickConfig == 0)
bogdanm 0:9b334a45a8ff 812
bogdanm 0:9b334a45a8ff 813 /** \brief System Tick Configuration
bogdanm 0:9b334a45a8ff 814
bogdanm 0:9b334a45a8ff 815 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 0:9b334a45a8ff 816 Counter is in free running mode to generate periodic interrupts.
bogdanm 0:9b334a45a8ff 817
bogdanm 0:9b334a45a8ff 818 \param [in] ticks Number of ticks between two interrupts.
bogdanm 0:9b334a45a8ff 819
bogdanm 0:9b334a45a8ff 820 \return 0 Function succeeded.
bogdanm 0:9b334a45a8ff 821 \return 1 Function failed.
bogdanm 0:9b334a45a8ff 822
bogdanm 0:9b334a45a8ff 823 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 0:9b334a45a8ff 824 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 0:9b334a45a8ff 825 must contain a vendor-specific implementation of this function.
bogdanm 0:9b334a45a8ff 826
bogdanm 0:9b334a45a8ff 827 */
bogdanm 0:9b334a45a8ff 828 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 0:9b334a45a8ff 829 {
mbed_official 19:112740acecfa 830 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
bogdanm 0:9b334a45a8ff 831
mbed_official 19:112740acecfa 832 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official 19:112740acecfa 833 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official 19:112740acecfa 834 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm 0:9b334a45a8ff 835 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 0:9b334a45a8ff 836 SysTick_CTRL_TICKINT_Msk |
mbed_official 19:112740acecfa 837 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official 19:112740acecfa 838 return (0UL); /* Function successful */
bogdanm 0:9b334a45a8ff 839 }
bogdanm 0:9b334a45a8ff 840
bogdanm 0:9b334a45a8ff 841 #endif
bogdanm 0:9b334a45a8ff 842
bogdanm 0:9b334a45a8ff 843 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 0:9b334a45a8ff 844
bogdanm 0:9b334a45a8ff 845
bogdanm 0:9b334a45a8ff 846
bogdanm 0:9b334a45a8ff 847
mbed_official 19:112740acecfa 848 #ifdef __cplusplus
mbed_official 19:112740acecfa 849 }
mbed_official 19:112740acecfa 850 #endif
mbed_official 19:112740acecfa 851
bogdanm 0:9b334a45a8ff 852 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
bogdanm 0:9b334a45a8ff 853
bogdanm 0:9b334a45a8ff 854 #endif /* __CMSIS_GENERIC */