philippe s. / mbed-dev

mbed library sources. Supersedes mbed-src. Fixes analogIn and analogOut problems for TARGET_STM32F3. Tested on NUCLEO-F303K8, using 3 analogout and 7 analogin channels simultaneously. Added ability for STM32F334R8 and STM32F303K8 to use all three channels of DAC simultaneously. https://developer.mbed.org/users/StevieWray/code/mbed-dev/ Added ability for TARGET_STM32F3 to use more than one ADC simultaneously. https://developer.mbed.org/questions/67997/NUCLEO-F303K8ADC/

Fork of mbed-dev by mbed official

targets/cmsis/core_sc000.h@70:b3a5af880266, 2016-02-23 (annotated)

Committer:
neurofun
Date:
Tue Feb 23 21:59:35 2016 +0000
Revision:
70:b3a5af880266
Parent:
25:ac5b0a371348 
Edited DAC routines to allow for the simultaneous use of three channels from two DACs as seen on the STM32F334R8 and STM32F303K8. Edited ADC routines to allow for the simultaneous use of more than one ADC.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 25:ac5b0a371348 1 /**************************************************************************//**
mbed_official 25:ac5b0a371348 2 * @file core_sc000.h
mbed_official 25:ac5b0a371348 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
mbed_official 25:ac5b0a371348 4 * @version V4.10
mbed_official 25:ac5b0a371348 5 * @date 18. March 2015
mbed_official 25:ac5b0a371348 6 *
mbed_official 25:ac5b0a371348 7 * @note
mbed_official 25:ac5b0a371348 8 *
mbed_official 25:ac5b0a371348 9 ******************************************************************************/
mbed_official 25:ac5b0a371348 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
mbed_official 25:ac5b0a371348 11
mbed_official 25:ac5b0a371348 12 All rights reserved.
mbed_official 25:ac5b0a371348 13 Redistribution and use in source and binary forms, with or without
mbed_official 25:ac5b0a371348 14 modification, are permitted provided that the following conditions are met:
mbed_official 25:ac5b0a371348 15 - Redistributions of source code must retain the above copyright
mbed_official 25:ac5b0a371348 16 notice, this list of conditions and the following disclaimer.
mbed_official 25:ac5b0a371348 17 - Redistributions in binary form must reproduce the above copyright
mbed_official 25:ac5b0a371348 18 notice, this list of conditions and the following disclaimer in the
mbed_official 25:ac5b0a371348 19 documentation and/or other materials provided with the distribution.
mbed_official 25:ac5b0a371348 20 - Neither the name of ARM nor the names of its contributors may be used
mbed_official 25:ac5b0a371348 21 to endorse or promote products derived from this software without
mbed_official 25:ac5b0a371348 22 specific prior written permission.
mbed_official 25:ac5b0a371348 23 *
mbed_official 25:ac5b0a371348 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 25:ac5b0a371348 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 25:ac5b0a371348 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 25:ac5b0a371348 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 25:ac5b0a371348 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 25:ac5b0a371348 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 25:ac5b0a371348 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 25:ac5b0a371348 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 25:ac5b0a371348 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 25:ac5b0a371348 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 25:ac5b0a371348 34 POSSIBILITY OF SUCH DAMAGE.
mbed_official 25:ac5b0a371348 35 ---------------------------------------------------------------------------*/
mbed_official 25:ac5b0a371348 36
mbed_official 25:ac5b0a371348 37
mbed_official 25:ac5b0a371348 38 #if defined ( __ICCARM__ )
mbed_official 25:ac5b0a371348 39 #pragma system_include /* treat file as system include file for MISRA check */
mbed_official 25:ac5b0a371348 40 #endif
mbed_official 25:ac5b0a371348 41
mbed_official 25:ac5b0a371348 42 #ifndef __CORE_SC000_H_GENERIC
mbed_official 25:ac5b0a371348 43 #define __CORE_SC000_H_GENERIC
mbed_official 25:ac5b0a371348 44
mbed_official 25:ac5b0a371348 45 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 46 extern "C" {
mbed_official 25:ac5b0a371348 47 #endif
mbed_official 25:ac5b0a371348 48
mbed_official 25:ac5b0a371348 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mbed_official 25:ac5b0a371348 50 CMSIS violates the following MISRA-C:2004 rules:
mbed_official 25:ac5b0a371348 51
mbed_official 25:ac5b0a371348 52 \li Required Rule 8.5, object/function definition in header file.<br>
mbed_official 25:ac5b0a371348 53 Function definitions in header files are used to allow 'inlining'.
mbed_official 25:ac5b0a371348 54
mbed_official 25:ac5b0a371348 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mbed_official 25:ac5b0a371348 56 Unions are used for effective representation of core registers.
mbed_official 25:ac5b0a371348 57
mbed_official 25:ac5b0a371348 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mbed_official 25:ac5b0a371348 59 Function-like macros are used to allow more efficient code.
mbed_official 25:ac5b0a371348 60 */
mbed_official 25:ac5b0a371348 61
mbed_official 25:ac5b0a371348 62
mbed_official 25:ac5b0a371348 63 /*******************************************************************************
mbed_official 25:ac5b0a371348 64 * CMSIS definitions
mbed_official 25:ac5b0a371348 65 ******************************************************************************/
mbed_official 25:ac5b0a371348 66 /** \ingroup SC000
mbed_official 25:ac5b0a371348 67 @{
mbed_official 25:ac5b0a371348 68 */
mbed_official 25:ac5b0a371348 69
mbed_official 25:ac5b0a371348 70 /* CMSIS SC000 definitions */
mbed_official 25:ac5b0a371348 71 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
mbed_official 25:ac5b0a371348 72 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
mbed_official 25:ac5b0a371348 73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
mbed_official 25:ac5b0a371348 74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mbed_official 25:ac5b0a371348 75
mbed_official 25:ac5b0a371348 76 #define __CORTEX_SC (000) /*!< Cortex secure core */
mbed_official 25:ac5b0a371348 77
mbed_official 25:ac5b0a371348 78
mbed_official 25:ac5b0a371348 79 #if defined ( __CC_ARM )
mbed_official 25:ac5b0a371348 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mbed_official 25:ac5b0a371348 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mbed_official 25:ac5b0a371348 82 #define __STATIC_INLINE static __inline
mbed_official 25:ac5b0a371348 83
mbed_official 25:ac5b0a371348 84 #elif defined ( __GNUC__ )
mbed_official 25:ac5b0a371348 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mbed_official 25:ac5b0a371348 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mbed_official 25:ac5b0a371348 87 #define __STATIC_INLINE static inline
mbed_official 25:ac5b0a371348 88
mbed_official 25:ac5b0a371348 89 #elif defined ( __ICCARM__ )
mbed_official 25:ac5b0a371348 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mbed_official 25:ac5b0a371348 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mbed_official 25:ac5b0a371348 92 #define __STATIC_INLINE static inline
mbed_official 25:ac5b0a371348 93
mbed_official 25:ac5b0a371348 94 #elif defined ( __TMS470__ )
mbed_official 25:ac5b0a371348 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
mbed_official 25:ac5b0a371348 96 #define __STATIC_INLINE static inline
mbed_official 25:ac5b0a371348 97
mbed_official 25:ac5b0a371348 98 #elif defined ( __TASKING__ )
mbed_official 25:ac5b0a371348 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mbed_official 25:ac5b0a371348 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mbed_official 25:ac5b0a371348 101 #define __STATIC_INLINE static inline
mbed_official 25:ac5b0a371348 102
mbed_official 25:ac5b0a371348 103 #elif defined ( __CSMC__ )
mbed_official 25:ac5b0a371348 104 #define __packed
mbed_official 25:ac5b0a371348 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
mbed_official 25:ac5b0a371348 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
mbed_official 25:ac5b0a371348 107 #define __STATIC_INLINE static inline
mbed_official 25:ac5b0a371348 108
mbed_official 25:ac5b0a371348 109 #endif
mbed_official 25:ac5b0a371348 110
mbed_official 25:ac5b0a371348 111 /** __FPU_USED indicates whether an FPU is used or not.
mbed_official 25:ac5b0a371348 112 This core does not support an FPU at all
mbed_official 25:ac5b0a371348 113 */
mbed_official 25:ac5b0a371348 114 #define __FPU_USED 0
mbed_official 25:ac5b0a371348 115
mbed_official 25:ac5b0a371348 116 #if defined ( __CC_ARM )
mbed_official 25:ac5b0a371348 117 #if defined __TARGET_FPU_VFP
mbed_official 25:ac5b0a371348 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 119 #endif
mbed_official 25:ac5b0a371348 120
mbed_official 25:ac5b0a371348 121 #elif defined ( __GNUC__ )
mbed_official 25:ac5b0a371348 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbed_official 25:ac5b0a371348 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 124 #endif
mbed_official 25:ac5b0a371348 125
mbed_official 25:ac5b0a371348 126 #elif defined ( __ICCARM__ )
mbed_official 25:ac5b0a371348 127 #if defined __ARMVFP__
mbed_official 25:ac5b0a371348 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 129 #endif
mbed_official 25:ac5b0a371348 130
mbed_official 25:ac5b0a371348 131 #elif defined ( __TMS470__ )
mbed_official 25:ac5b0a371348 132 #if defined __TI__VFP_SUPPORT____
mbed_official 25:ac5b0a371348 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 134 #endif
mbed_official 25:ac5b0a371348 135
mbed_official 25:ac5b0a371348 136 #elif defined ( __TASKING__ )
mbed_official 25:ac5b0a371348 137 #if defined __FPU_VFP__
mbed_official 25:ac5b0a371348 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 139 #endif
mbed_official 25:ac5b0a371348 140
mbed_official 25:ac5b0a371348 141 #elif defined ( __CSMC__ ) /* Cosmic */
mbed_official 25:ac5b0a371348 142 #if ( __CSMC__ & 0x400) // FPU present for parser
mbed_official 25:ac5b0a371348 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 144 #endif
mbed_official 25:ac5b0a371348 145 #endif
mbed_official 25:ac5b0a371348 146
mbed_official 25:ac5b0a371348 147 #include <stdint.h> /* standard types definitions */
mbed_official 25:ac5b0a371348 148 #include <core_cmInstr.h> /* Core Instruction Access */
mbed_official 25:ac5b0a371348 149 #include <core_cmFunc.h> /* Core Function Access */
mbed_official 25:ac5b0a371348 150
mbed_official 25:ac5b0a371348 151 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 152 }
mbed_official 25:ac5b0a371348 153 #endif
mbed_official 25:ac5b0a371348 154
mbed_official 25:ac5b0a371348 155 #endif /* __CORE_SC000_H_GENERIC */
mbed_official 25:ac5b0a371348 156
mbed_official 25:ac5b0a371348 157 #ifndef __CMSIS_GENERIC
mbed_official 25:ac5b0a371348 158
mbed_official 25:ac5b0a371348 159 #ifndef __CORE_SC000_H_DEPENDANT
mbed_official 25:ac5b0a371348 160 #define __CORE_SC000_H_DEPENDANT
mbed_official 25:ac5b0a371348 161
mbed_official 25:ac5b0a371348 162 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 163 extern "C" {
mbed_official 25:ac5b0a371348 164 #endif
mbed_official 25:ac5b0a371348 165
mbed_official 25:ac5b0a371348 166 /* check device defines and use defaults */
mbed_official 25:ac5b0a371348 167 #if defined __CHECK_DEVICE_DEFINES
mbed_official 25:ac5b0a371348 168 #ifndef __SC000_REV
mbed_official 25:ac5b0a371348 169 #define __SC000_REV 0x0000
mbed_official 25:ac5b0a371348 170 #warning "__SC000_REV not defined in device header file; using default!"
mbed_official 25:ac5b0a371348 171 #endif
mbed_official 25:ac5b0a371348 172
mbed_official 25:ac5b0a371348 173 #ifndef __MPU_PRESENT
mbed_official 25:ac5b0a371348 174 #define __MPU_PRESENT 0
mbed_official 25:ac5b0a371348 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
mbed_official 25:ac5b0a371348 176 #endif
mbed_official 25:ac5b0a371348 177
mbed_official 25:ac5b0a371348 178 #ifndef __NVIC_PRIO_BITS
mbed_official 25:ac5b0a371348 179 #define __NVIC_PRIO_BITS 2
mbed_official 25:ac5b0a371348 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mbed_official 25:ac5b0a371348 181 #endif
mbed_official 25:ac5b0a371348 182
mbed_official 25:ac5b0a371348 183 #ifndef __Vendor_SysTickConfig
mbed_official 25:ac5b0a371348 184 #define __Vendor_SysTickConfig 0
mbed_official 25:ac5b0a371348 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mbed_official 25:ac5b0a371348 186 #endif
mbed_official 25:ac5b0a371348 187 #endif
mbed_official 25:ac5b0a371348 188
mbed_official 25:ac5b0a371348 189 /* IO definitions (access restrictions to peripheral registers) */
mbed_official 25:ac5b0a371348 190 /**
mbed_official 25:ac5b0a371348 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
mbed_official 25:ac5b0a371348 192
mbed_official 25:ac5b0a371348 193 <strong>IO Type Qualifiers</strong> are used
mbed_official 25:ac5b0a371348 194 \li to specify the access to peripheral variables.
mbed_official 25:ac5b0a371348 195 \li for automatic generation of peripheral register debug information.
mbed_official 25:ac5b0a371348 196 */
mbed_official 25:ac5b0a371348 197 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 198 #define __I volatile /*!< Defines 'read only' permissions */
mbed_official 25:ac5b0a371348 199 #else
mbed_official 25:ac5b0a371348 200 #define __I volatile const /*!< Defines 'read only' permissions */
mbed_official 25:ac5b0a371348 201 #endif
mbed_official 25:ac5b0a371348 202 #define __O volatile /*!< Defines 'write only' permissions */
mbed_official 25:ac5b0a371348 203 #define __IO volatile /*!< Defines 'read / write' permissions */
mbed_official 25:ac5b0a371348 204
mbed_official 25:ac5b0a371348 205 /*@} end of group SC000 */
mbed_official 25:ac5b0a371348 206
mbed_official 25:ac5b0a371348 207
mbed_official 25:ac5b0a371348 208
mbed_official 25:ac5b0a371348 209 /*******************************************************************************
mbed_official 25:ac5b0a371348 210 * Register Abstraction
mbed_official 25:ac5b0a371348 211 Core Register contain:
mbed_official 25:ac5b0a371348 212 - Core Register
mbed_official 25:ac5b0a371348 213 - Core NVIC Register
mbed_official 25:ac5b0a371348 214 - Core SCB Register
mbed_official 25:ac5b0a371348 215 - Core SysTick Register
mbed_official 25:ac5b0a371348 216 - Core MPU Register
mbed_official 25:ac5b0a371348 217 ******************************************************************************/
mbed_official 25:ac5b0a371348 218 /** \defgroup CMSIS_core_register Defines and Type Definitions
mbed_official 25:ac5b0a371348 219 \brief Type definitions and defines for Cortex-M processor based devices.
mbed_official 25:ac5b0a371348 220 */
mbed_official 25:ac5b0a371348 221
mbed_official 25:ac5b0a371348 222 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 223 \defgroup CMSIS_CORE Status and Control Registers
mbed_official 25:ac5b0a371348 224 \brief Core Register type definitions.
mbed_official 25:ac5b0a371348 225 @{
mbed_official 25:ac5b0a371348 226 */
mbed_official 25:ac5b0a371348 227
mbed_official 25:ac5b0a371348 228 /** \brief Union type to access the Application Program Status Register (APSR).
mbed_official 25:ac5b0a371348 229 */
mbed_official 25:ac5b0a371348 230 typedef union
mbed_official 25:ac5b0a371348 231 {
mbed_official 25:ac5b0a371348 232 struct
mbed_official 25:ac5b0a371348 233 {
mbed_official 25:ac5b0a371348 234 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
mbed_official 25:ac5b0a371348 235 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbed_official 25:ac5b0a371348 236 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbed_official 25:ac5b0a371348 237 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbed_official 25:ac5b0a371348 238 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbed_official 25:ac5b0a371348 239 } b; /*!< Structure used for bit access */
mbed_official 25:ac5b0a371348 240 uint32_t w; /*!< Type used for word access */
mbed_official 25:ac5b0a371348 241 } APSR_Type;
mbed_official 25:ac5b0a371348 242
mbed_official 25:ac5b0a371348 243 /* APSR Register Definitions */
mbed_official 25:ac5b0a371348 244 #define APSR_N_Pos 31 /*!< APSR: N Position */
mbed_official 25:ac5b0a371348 245 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mbed_official 25:ac5b0a371348 246
mbed_official 25:ac5b0a371348 247 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
mbed_official 25:ac5b0a371348 248 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mbed_official 25:ac5b0a371348 249
mbed_official 25:ac5b0a371348 250 #define APSR_C_Pos 29 /*!< APSR: C Position */
mbed_official 25:ac5b0a371348 251 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mbed_official 25:ac5b0a371348 252
mbed_official 25:ac5b0a371348 253 #define APSR_V_Pos 28 /*!< APSR: V Position */
mbed_official 25:ac5b0a371348 254 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mbed_official 25:ac5b0a371348 255
mbed_official 25:ac5b0a371348 256
mbed_official 25:ac5b0a371348 257 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mbed_official 25:ac5b0a371348 258 */
mbed_official 25:ac5b0a371348 259 typedef union
mbed_official 25:ac5b0a371348 260 {
mbed_official 25:ac5b0a371348 261 struct
mbed_official 25:ac5b0a371348 262 {
mbed_official 25:ac5b0a371348 263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbed_official 25:ac5b0a371348 264 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mbed_official 25:ac5b0a371348 265 } b; /*!< Structure used for bit access */
mbed_official 25:ac5b0a371348 266 uint32_t w; /*!< Type used for word access */
mbed_official 25:ac5b0a371348 267 } IPSR_Type;
mbed_official 25:ac5b0a371348 268
mbed_official 25:ac5b0a371348 269 /* IPSR Register Definitions */
mbed_official 25:ac5b0a371348 270 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
mbed_official 25:ac5b0a371348 271 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mbed_official 25:ac5b0a371348 272
mbed_official 25:ac5b0a371348 273
mbed_official 25:ac5b0a371348 274 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mbed_official 25:ac5b0a371348 275 */
mbed_official 25:ac5b0a371348 276 typedef union
mbed_official 25:ac5b0a371348 277 {
mbed_official 25:ac5b0a371348 278 struct
mbed_official 25:ac5b0a371348 279 {
mbed_official 25:ac5b0a371348 280 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbed_official 25:ac5b0a371348 281 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mbed_official 25:ac5b0a371348 282 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mbed_official 25:ac5b0a371348 283 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
mbed_official 25:ac5b0a371348 284 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbed_official 25:ac5b0a371348 285 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbed_official 25:ac5b0a371348 286 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbed_official 25:ac5b0a371348 287 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbed_official 25:ac5b0a371348 288 } b; /*!< Structure used for bit access */
mbed_official 25:ac5b0a371348 289 uint32_t w; /*!< Type used for word access */
mbed_official 25:ac5b0a371348 290 } xPSR_Type;
mbed_official 25:ac5b0a371348 291
mbed_official 25:ac5b0a371348 292 /* xPSR Register Definitions */
mbed_official 25:ac5b0a371348 293 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
mbed_official 25:ac5b0a371348 294 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mbed_official 25:ac5b0a371348 295
mbed_official 25:ac5b0a371348 296 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
mbed_official 25:ac5b0a371348 297 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mbed_official 25:ac5b0a371348 298
mbed_official 25:ac5b0a371348 299 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
mbed_official 25:ac5b0a371348 300 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mbed_official 25:ac5b0a371348 301
mbed_official 25:ac5b0a371348 302 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
mbed_official 25:ac5b0a371348 303 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mbed_official 25:ac5b0a371348 304
mbed_official 25:ac5b0a371348 305 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
mbed_official 25:ac5b0a371348 306 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mbed_official 25:ac5b0a371348 307
mbed_official 25:ac5b0a371348 308 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
mbed_official 25:ac5b0a371348 309 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mbed_official 25:ac5b0a371348 310
mbed_official 25:ac5b0a371348 311
mbed_official 25:ac5b0a371348 312 /** \brief Union type to access the Control Registers (CONTROL).
mbed_official 25:ac5b0a371348 313 */
mbed_official 25:ac5b0a371348 314 typedef union
mbed_official 25:ac5b0a371348 315 {
mbed_official 25:ac5b0a371348 316 struct
mbed_official 25:ac5b0a371348 317 {
mbed_official 25:ac5b0a371348 318 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
mbed_official 25:ac5b0a371348 319 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mbed_official 25:ac5b0a371348 320 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
mbed_official 25:ac5b0a371348 321 } b; /*!< Structure used for bit access */
mbed_official 25:ac5b0a371348 322 uint32_t w; /*!< Type used for word access */
mbed_official 25:ac5b0a371348 323 } CONTROL_Type;
mbed_official 25:ac5b0a371348 324
mbed_official 25:ac5b0a371348 325 /* CONTROL Register Definitions */
mbed_official 25:ac5b0a371348 326 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
mbed_official 25:ac5b0a371348 327 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mbed_official 25:ac5b0a371348 328
mbed_official 25:ac5b0a371348 329 /*@} end of group CMSIS_CORE */
mbed_official 25:ac5b0a371348 330
mbed_official 25:ac5b0a371348 331
mbed_official 25:ac5b0a371348 332 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 333 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mbed_official 25:ac5b0a371348 334 \brief Type definitions for the NVIC Registers
mbed_official 25:ac5b0a371348 335 @{
mbed_official 25:ac5b0a371348 336 */
mbed_official 25:ac5b0a371348 337
mbed_official 25:ac5b0a371348 338 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mbed_official 25:ac5b0a371348 339 */
mbed_official 25:ac5b0a371348 340 typedef struct
mbed_official 25:ac5b0a371348 341 {
mbed_official 25:ac5b0a371348 342 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mbed_official 25:ac5b0a371348 343 uint32_t RESERVED0[31];
mbed_official 25:ac5b0a371348 344 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mbed_official 25:ac5b0a371348 345 uint32_t RSERVED1[31];
mbed_official 25:ac5b0a371348 346 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mbed_official 25:ac5b0a371348 347 uint32_t RESERVED2[31];
mbed_official 25:ac5b0a371348 348 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mbed_official 25:ac5b0a371348 349 uint32_t RESERVED3[31];
mbed_official 25:ac5b0a371348 350 uint32_t RESERVED4[64];
mbed_official 25:ac5b0a371348 351 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mbed_official 25:ac5b0a371348 352 } NVIC_Type;
mbed_official 25:ac5b0a371348 353
mbed_official 25:ac5b0a371348 354 /*@} end of group CMSIS_NVIC */
mbed_official 25:ac5b0a371348 355
mbed_official 25:ac5b0a371348 356
mbed_official 25:ac5b0a371348 357 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 358 \defgroup CMSIS_SCB System Control Block (SCB)
mbed_official 25:ac5b0a371348 359 \brief Type definitions for the System Control Block Registers
mbed_official 25:ac5b0a371348 360 @{
mbed_official 25:ac5b0a371348 361 */
mbed_official 25:ac5b0a371348 362
mbed_official 25:ac5b0a371348 363 /** \brief Structure type to access the System Control Block (SCB).
mbed_official 25:ac5b0a371348 364 */
mbed_official 25:ac5b0a371348 365 typedef struct
mbed_official 25:ac5b0a371348 366 {
mbed_official 25:ac5b0a371348 367 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mbed_official 25:ac5b0a371348 368 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mbed_official 25:ac5b0a371348 369 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mbed_official 25:ac5b0a371348 370 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mbed_official 25:ac5b0a371348 371 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mbed_official 25:ac5b0a371348 372 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mbed_official 25:ac5b0a371348 373 uint32_t RESERVED0[1];
mbed_official 25:ac5b0a371348 374 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
mbed_official 25:ac5b0a371348 375 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mbed_official 25:ac5b0a371348 376 uint32_t RESERVED1[154];
mbed_official 25:ac5b0a371348 377 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
mbed_official 25:ac5b0a371348 378 } SCB_Type;
mbed_official 25:ac5b0a371348 379
mbed_official 25:ac5b0a371348 380 /* SCB CPUID Register Definitions */
mbed_official 25:ac5b0a371348 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mbed_official 25:ac5b0a371348 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mbed_official 25:ac5b0a371348 383
mbed_official 25:ac5b0a371348 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mbed_official 25:ac5b0a371348 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mbed_official 25:ac5b0a371348 386
mbed_official 25:ac5b0a371348 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mbed_official 25:ac5b0a371348 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mbed_official 25:ac5b0a371348 389
mbed_official 25:ac5b0a371348 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mbed_official 25:ac5b0a371348 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mbed_official 25:ac5b0a371348 392
mbed_official 25:ac5b0a371348 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mbed_official 25:ac5b0a371348 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
mbed_official 25:ac5b0a371348 395
mbed_official 25:ac5b0a371348 396 /* SCB Interrupt Control State Register Definitions */
mbed_official 25:ac5b0a371348 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mbed_official 25:ac5b0a371348 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mbed_official 25:ac5b0a371348 399
mbed_official 25:ac5b0a371348 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mbed_official 25:ac5b0a371348 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mbed_official 25:ac5b0a371348 402
mbed_official 25:ac5b0a371348 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mbed_official 25:ac5b0a371348 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mbed_official 25:ac5b0a371348 405
mbed_official 25:ac5b0a371348 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mbed_official 25:ac5b0a371348 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mbed_official 25:ac5b0a371348 408
mbed_official 25:ac5b0a371348 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mbed_official 25:ac5b0a371348 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mbed_official 25:ac5b0a371348 411
mbed_official 25:ac5b0a371348 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mbed_official 25:ac5b0a371348 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mbed_official 25:ac5b0a371348 414
mbed_official 25:ac5b0a371348 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mbed_official 25:ac5b0a371348 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mbed_official 25:ac5b0a371348 417
mbed_official 25:ac5b0a371348 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mbed_official 25:ac5b0a371348 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mbed_official 25:ac5b0a371348 420
mbed_official 25:ac5b0a371348 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mbed_official 25:ac5b0a371348 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
mbed_official 25:ac5b0a371348 423
mbed_official 25:ac5b0a371348 424 /* SCB Interrupt Control State Register Definitions */
mbed_official 25:ac5b0a371348 425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
mbed_official 25:ac5b0a371348 426 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mbed_official 25:ac5b0a371348 427
mbed_official 25:ac5b0a371348 428 /* SCB Application Interrupt and Reset Control Register Definitions */
mbed_official 25:ac5b0a371348 429 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mbed_official 25:ac5b0a371348 430 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mbed_official 25:ac5b0a371348 431
mbed_official 25:ac5b0a371348 432 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mbed_official 25:ac5b0a371348 433 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mbed_official 25:ac5b0a371348 434
mbed_official 25:ac5b0a371348 435 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mbed_official 25:ac5b0a371348 436 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mbed_official 25:ac5b0a371348 437
mbed_official 25:ac5b0a371348 438 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mbed_official 25:ac5b0a371348 439 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mbed_official 25:ac5b0a371348 440
mbed_official 25:ac5b0a371348 441 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mbed_official 25:ac5b0a371348 442 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mbed_official 25:ac5b0a371348 443
mbed_official 25:ac5b0a371348 444 /* SCB System Control Register Definitions */
mbed_official 25:ac5b0a371348 445 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mbed_official 25:ac5b0a371348 446 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mbed_official 25:ac5b0a371348 447
mbed_official 25:ac5b0a371348 448 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mbed_official 25:ac5b0a371348 449 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mbed_official 25:ac5b0a371348 450
mbed_official 25:ac5b0a371348 451 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mbed_official 25:ac5b0a371348 452 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mbed_official 25:ac5b0a371348 453
mbed_official 25:ac5b0a371348 454 /* SCB Configuration Control Register Definitions */
mbed_official 25:ac5b0a371348 455 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mbed_official 25:ac5b0a371348 456 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mbed_official 25:ac5b0a371348 457
mbed_official 25:ac5b0a371348 458 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mbed_official 25:ac5b0a371348 459 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mbed_official 25:ac5b0a371348 460
mbed_official 25:ac5b0a371348 461 /* SCB System Handler Control and State Register Definitions */
mbed_official 25:ac5b0a371348 462 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mbed_official 25:ac5b0a371348 463 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mbed_official 25:ac5b0a371348 464
mbed_official 25:ac5b0a371348 465 /*@} end of group CMSIS_SCB */
mbed_official 25:ac5b0a371348 466
mbed_official 25:ac5b0a371348 467
mbed_official 25:ac5b0a371348 468 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 469 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mbed_official 25:ac5b0a371348 470 \brief Type definitions for the System Control and ID Register not in the SCB
mbed_official 25:ac5b0a371348 471 @{
mbed_official 25:ac5b0a371348 472 */
mbed_official 25:ac5b0a371348 473
mbed_official 25:ac5b0a371348 474 /** \brief Structure type to access the System Control and ID Register not in the SCB.
mbed_official 25:ac5b0a371348 475 */
mbed_official 25:ac5b0a371348 476 typedef struct
mbed_official 25:ac5b0a371348 477 {
mbed_official 25:ac5b0a371348 478 uint32_t RESERVED0[2];
mbed_official 25:ac5b0a371348 479 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
mbed_official 25:ac5b0a371348 480 } SCnSCB_Type;
mbed_official 25:ac5b0a371348 481
mbed_official 25:ac5b0a371348 482 /* Auxiliary Control Register Definitions */
mbed_official 25:ac5b0a371348 483 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
mbed_official 25:ac5b0a371348 484 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
mbed_official 25:ac5b0a371348 485
mbed_official 25:ac5b0a371348 486 /*@} end of group CMSIS_SCnotSCB */
mbed_official 25:ac5b0a371348 487
mbed_official 25:ac5b0a371348 488
mbed_official 25:ac5b0a371348 489 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 490 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mbed_official 25:ac5b0a371348 491 \brief Type definitions for the System Timer Registers.
mbed_official 25:ac5b0a371348 492 @{
mbed_official 25:ac5b0a371348 493 */
mbed_official 25:ac5b0a371348 494
mbed_official 25:ac5b0a371348 495 /** \brief Structure type to access the System Timer (SysTick).
mbed_official 25:ac5b0a371348 496 */
mbed_official 25:ac5b0a371348 497 typedef struct
mbed_official 25:ac5b0a371348 498 {
mbed_official 25:ac5b0a371348 499 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mbed_official 25:ac5b0a371348 500 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mbed_official 25:ac5b0a371348 501 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mbed_official 25:ac5b0a371348 502 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mbed_official 25:ac5b0a371348 503 } SysTick_Type;
mbed_official 25:ac5b0a371348 504
mbed_official 25:ac5b0a371348 505 /* SysTick Control / Status Register Definitions */
mbed_official 25:ac5b0a371348 506 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mbed_official 25:ac5b0a371348 507 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mbed_official 25:ac5b0a371348 508
mbed_official 25:ac5b0a371348 509 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mbed_official 25:ac5b0a371348 510 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mbed_official 25:ac5b0a371348 511
mbed_official 25:ac5b0a371348 512 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mbed_official 25:ac5b0a371348 513 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mbed_official 25:ac5b0a371348 514
mbed_official 25:ac5b0a371348 515 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mbed_official 25:ac5b0a371348 516 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
mbed_official 25:ac5b0a371348 517
mbed_official 25:ac5b0a371348 518 /* SysTick Reload Register Definitions */
mbed_official 25:ac5b0a371348 519 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mbed_official 25:ac5b0a371348 520 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
mbed_official 25:ac5b0a371348 521
mbed_official 25:ac5b0a371348 522 /* SysTick Current Register Definitions */
mbed_official 25:ac5b0a371348 523 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mbed_official 25:ac5b0a371348 524 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
mbed_official 25:ac5b0a371348 525
mbed_official 25:ac5b0a371348 526 /* SysTick Calibration Register Definitions */
mbed_official 25:ac5b0a371348 527 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mbed_official 25:ac5b0a371348 528 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mbed_official 25:ac5b0a371348 529
mbed_official 25:ac5b0a371348 530 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mbed_official 25:ac5b0a371348 531 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mbed_official 25:ac5b0a371348 532
mbed_official 25:ac5b0a371348 533 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mbed_official 25:ac5b0a371348 534 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
mbed_official 25:ac5b0a371348 535
mbed_official 25:ac5b0a371348 536 /*@} end of group CMSIS_SysTick */
mbed_official 25:ac5b0a371348 537
mbed_official 25:ac5b0a371348 538 #if (__MPU_PRESENT == 1)
mbed_official 25:ac5b0a371348 539 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 540 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mbed_official 25:ac5b0a371348 541 \brief Type definitions for the Memory Protection Unit (MPU)
mbed_official 25:ac5b0a371348 542 @{
mbed_official 25:ac5b0a371348 543 */
mbed_official 25:ac5b0a371348 544
mbed_official 25:ac5b0a371348 545 /** \brief Structure type to access the Memory Protection Unit (MPU).
mbed_official 25:ac5b0a371348 546 */
mbed_official 25:ac5b0a371348 547 typedef struct
mbed_official 25:ac5b0a371348 548 {
mbed_official 25:ac5b0a371348 549 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mbed_official 25:ac5b0a371348 550 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mbed_official 25:ac5b0a371348 551 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mbed_official 25:ac5b0a371348 552 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mbed_official 25:ac5b0a371348 553 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mbed_official 25:ac5b0a371348 554 } MPU_Type;
mbed_official 25:ac5b0a371348 555
mbed_official 25:ac5b0a371348 556 /* MPU Type Register */
mbed_official 25:ac5b0a371348 557 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
mbed_official 25:ac5b0a371348 558 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mbed_official 25:ac5b0a371348 559
mbed_official 25:ac5b0a371348 560 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
mbed_official 25:ac5b0a371348 561 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mbed_official 25:ac5b0a371348 562
mbed_official 25:ac5b0a371348 563 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mbed_official 25:ac5b0a371348 564 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
mbed_official 25:ac5b0a371348 565
mbed_official 25:ac5b0a371348 566 /* MPU Control Register */
mbed_official 25:ac5b0a371348 567 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
mbed_official 25:ac5b0a371348 568 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mbed_official 25:ac5b0a371348 569
mbed_official 25:ac5b0a371348 570 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
mbed_official 25:ac5b0a371348 571 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mbed_official 25:ac5b0a371348 572
mbed_official 25:ac5b0a371348 573 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mbed_official 25:ac5b0a371348 574 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
mbed_official 25:ac5b0a371348 575
mbed_official 25:ac5b0a371348 576 /* MPU Region Number Register */
mbed_official 25:ac5b0a371348 577 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mbed_official 25:ac5b0a371348 578 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
mbed_official 25:ac5b0a371348 579
mbed_official 25:ac5b0a371348 580 /* MPU Region Base Address Register */
mbed_official 25:ac5b0a371348 581 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
mbed_official 25:ac5b0a371348 582 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mbed_official 25:ac5b0a371348 583
mbed_official 25:ac5b0a371348 584 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
mbed_official 25:ac5b0a371348 585 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mbed_official 25:ac5b0a371348 586
mbed_official 25:ac5b0a371348 587 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mbed_official 25:ac5b0a371348 588 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
mbed_official 25:ac5b0a371348 589
mbed_official 25:ac5b0a371348 590 /* MPU Region Attribute and Size Register */
mbed_official 25:ac5b0a371348 591 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
mbed_official 25:ac5b0a371348 592 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mbed_official 25:ac5b0a371348 593
mbed_official 25:ac5b0a371348 594 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
mbed_official 25:ac5b0a371348 595 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mbed_official 25:ac5b0a371348 596
mbed_official 25:ac5b0a371348 597 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
mbed_official 25:ac5b0a371348 598 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mbed_official 25:ac5b0a371348 599
mbed_official 25:ac5b0a371348 600 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
mbed_official 25:ac5b0a371348 601 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mbed_official 25:ac5b0a371348 602
mbed_official 25:ac5b0a371348 603 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
mbed_official 25:ac5b0a371348 604 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mbed_official 25:ac5b0a371348 605
mbed_official 25:ac5b0a371348 606 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
mbed_official 25:ac5b0a371348 607 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mbed_official 25:ac5b0a371348 608
mbed_official 25:ac5b0a371348 609 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
mbed_official 25:ac5b0a371348 610 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mbed_official 25:ac5b0a371348 611
mbed_official 25:ac5b0a371348 612 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
mbed_official 25:ac5b0a371348 613 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mbed_official 25:ac5b0a371348 614
mbed_official 25:ac5b0a371348 615 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
mbed_official 25:ac5b0a371348 616 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mbed_official 25:ac5b0a371348 617
mbed_official 25:ac5b0a371348 618 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mbed_official 25:ac5b0a371348 619 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
mbed_official 25:ac5b0a371348 620
mbed_official 25:ac5b0a371348 621 /*@} end of group CMSIS_MPU */
mbed_official 25:ac5b0a371348 622 #endif
mbed_official 25:ac5b0a371348 623
mbed_official 25:ac5b0a371348 624
mbed_official 25:ac5b0a371348 625 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 626 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mbed_official 25:ac5b0a371348 627 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
mbed_official 25:ac5b0a371348 628 are only accessible over DAP and not via processor. Therefore
mbed_official 25:ac5b0a371348 629 they are not covered by the Cortex-M0 header file.
mbed_official 25:ac5b0a371348 630 @{
mbed_official 25:ac5b0a371348 631 */
mbed_official 25:ac5b0a371348 632 /*@} end of group CMSIS_CoreDebug */
mbed_official 25:ac5b0a371348 633
mbed_official 25:ac5b0a371348 634
mbed_official 25:ac5b0a371348 635 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 636 \defgroup CMSIS_core_base Core Definitions
mbed_official 25:ac5b0a371348 637 \brief Definitions for base addresses, unions, and structures.
mbed_official 25:ac5b0a371348 638 @{
mbed_official 25:ac5b0a371348 639 */
mbed_official 25:ac5b0a371348 640
mbed_official 25:ac5b0a371348 641 /* Memory mapping of SC000 Hardware */
mbed_official 25:ac5b0a371348 642 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mbed_official 25:ac5b0a371348 643 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mbed_official 25:ac5b0a371348 644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mbed_official 25:ac5b0a371348 645 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mbed_official 25:ac5b0a371348 646
mbed_official 25:ac5b0a371348 647 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
mbed_official 25:ac5b0a371348 648 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mbed_official 25:ac5b0a371348 649 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mbed_official 25:ac5b0a371348 650 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mbed_official 25:ac5b0a371348 651
mbed_official 25:ac5b0a371348 652 #if (__MPU_PRESENT == 1)
mbed_official 25:ac5b0a371348 653 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mbed_official 25:ac5b0a371348 654 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mbed_official 25:ac5b0a371348 655 #endif
mbed_official 25:ac5b0a371348 656
mbed_official 25:ac5b0a371348 657 /*@} */
mbed_official 25:ac5b0a371348 658
mbed_official 25:ac5b0a371348 659
mbed_official 25:ac5b0a371348 660
mbed_official 25:ac5b0a371348 661 /*******************************************************************************
mbed_official 25:ac5b0a371348 662 * Hardware Abstraction Layer
mbed_official 25:ac5b0a371348 663 Core Function Interface contains:
mbed_official 25:ac5b0a371348 664 - Core NVIC Functions
mbed_official 25:ac5b0a371348 665 - Core SysTick Functions
mbed_official 25:ac5b0a371348 666 - Core Register Access Functions
mbed_official 25:ac5b0a371348 667 ******************************************************************************/
mbed_official 25:ac5b0a371348 668 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mbed_official 25:ac5b0a371348 669 */
mbed_official 25:ac5b0a371348 670
mbed_official 25:ac5b0a371348 671
mbed_official 25:ac5b0a371348 672
mbed_official 25:ac5b0a371348 673 /* ########################## NVIC functions #################################### */
mbed_official 25:ac5b0a371348 674 /** \ingroup CMSIS_Core_FunctionInterface
mbed_official 25:ac5b0a371348 675 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mbed_official 25:ac5b0a371348 676 \brief Functions that manage interrupts and exceptions via the NVIC.
mbed_official 25:ac5b0a371348 677 @{
mbed_official 25:ac5b0a371348 678 */
mbed_official 25:ac5b0a371348 679
mbed_official 25:ac5b0a371348 680 /* Interrupt Priorities are WORD accessible only under ARMv6M */
mbed_official 25:ac5b0a371348 681 /* The following MACROS handle generation of the register offset and byte masks */
mbed_official 25:ac5b0a371348 682 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
mbed_official 25:ac5b0a371348 683 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
mbed_official 25:ac5b0a371348 684 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
mbed_official 25:ac5b0a371348 685
mbed_official 25:ac5b0a371348 686
mbed_official 25:ac5b0a371348 687 /** \brief Enable External Interrupt
mbed_official 25:ac5b0a371348 688
mbed_official 25:ac5b0a371348 689 The function enables a device-specific interrupt in the NVIC interrupt controller.
mbed_official 25:ac5b0a371348 690
mbed_official 25:ac5b0a371348 691 \param [in] IRQn External interrupt number. Value cannot be negative.
mbed_official 25:ac5b0a371348 692 */
mbed_official 25:ac5b0a371348 693 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 694 {
mbed_official 25:ac5b0a371348 695 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 25:ac5b0a371348 696 }
mbed_official 25:ac5b0a371348 697
mbed_official 25:ac5b0a371348 698
mbed_official 25:ac5b0a371348 699 /** \brief Disable External Interrupt
mbed_official 25:ac5b0a371348 700
mbed_official 25:ac5b0a371348 701 The function disables a device-specific interrupt in the NVIC interrupt controller.
mbed_official 25:ac5b0a371348 702
mbed_official 25:ac5b0a371348 703 \param [in] IRQn External interrupt number. Value cannot be negative.
mbed_official 25:ac5b0a371348 704 */
mbed_official 25:ac5b0a371348 705 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 706 {
mbed_official 25:ac5b0a371348 707 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 25:ac5b0a371348 708 }
mbed_official 25:ac5b0a371348 709
mbed_official 25:ac5b0a371348 710
mbed_official 25:ac5b0a371348 711 /** \brief Get Pending Interrupt
mbed_official 25:ac5b0a371348 712
mbed_official 25:ac5b0a371348 713 The function reads the pending register in the NVIC and returns the pending bit
mbed_official 25:ac5b0a371348 714 for the specified interrupt.
mbed_official 25:ac5b0a371348 715
mbed_official 25:ac5b0a371348 716 \param [in] IRQn Interrupt number.
mbed_official 25:ac5b0a371348 717
mbed_official 25:ac5b0a371348 718 \return 0 Interrupt status is not pending.
mbed_official 25:ac5b0a371348 719 \return 1 Interrupt status is pending.
mbed_official 25:ac5b0a371348 720 */
mbed_official 25:ac5b0a371348 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 722 {
mbed_official 25:ac5b0a371348 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 25:ac5b0a371348 724 }
mbed_official 25:ac5b0a371348 725
mbed_official 25:ac5b0a371348 726
mbed_official 25:ac5b0a371348 727 /** \brief Set Pending Interrupt
mbed_official 25:ac5b0a371348 728
mbed_official 25:ac5b0a371348 729 The function sets the pending bit of an external interrupt.
mbed_official 25:ac5b0a371348 730
mbed_official 25:ac5b0a371348 731 \param [in] IRQn Interrupt number. Value cannot be negative.
mbed_official 25:ac5b0a371348 732 */
mbed_official 25:ac5b0a371348 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 734 {
mbed_official 25:ac5b0a371348 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 25:ac5b0a371348 736 }
mbed_official 25:ac5b0a371348 737
mbed_official 25:ac5b0a371348 738
mbed_official 25:ac5b0a371348 739 /** \brief Clear Pending Interrupt
mbed_official 25:ac5b0a371348 740
mbed_official 25:ac5b0a371348 741 The function clears the pending bit of an external interrupt.
mbed_official 25:ac5b0a371348 742
mbed_official 25:ac5b0a371348 743 \param [in] IRQn External interrupt number. Value cannot be negative.
mbed_official 25:ac5b0a371348 744 */
mbed_official 25:ac5b0a371348 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 746 {
mbed_official 25:ac5b0a371348 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 25:ac5b0a371348 748 }
mbed_official 25:ac5b0a371348 749
mbed_official 25:ac5b0a371348 750
mbed_official 25:ac5b0a371348 751 /** \brief Set Interrupt Priority
mbed_official 25:ac5b0a371348 752
mbed_official 25:ac5b0a371348 753 The function sets the priority of an interrupt.
mbed_official 25:ac5b0a371348 754
mbed_official 25:ac5b0a371348 755 \note The priority cannot be set for every core interrupt.
mbed_official 25:ac5b0a371348 756
mbed_official 25:ac5b0a371348 757 \param [in] IRQn Interrupt number.
mbed_official 25:ac5b0a371348 758 \param [in] priority Priority to set.
mbed_official 25:ac5b0a371348 759 */
mbed_official 25:ac5b0a371348 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mbed_official 25:ac5b0a371348 761 {
mbed_official 25:ac5b0a371348 762 if((int32_t)(IRQn) < 0) {
mbed_official 25:ac5b0a371348 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mbed_official 25:ac5b0a371348 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official 25:ac5b0a371348 765 }
mbed_official 25:ac5b0a371348 766 else {
mbed_official 25:ac5b0a371348 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mbed_official 25:ac5b0a371348 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mbed_official 25:ac5b0a371348 769 }
mbed_official 25:ac5b0a371348 770 }
mbed_official 25:ac5b0a371348 771
mbed_official 25:ac5b0a371348 772
mbed_official 25:ac5b0a371348 773 /** \brief Get Interrupt Priority
mbed_official 25:ac5b0a371348 774
mbed_official 25:ac5b0a371348 775 The function reads the priority of an interrupt. The interrupt
mbed_official 25:ac5b0a371348 776 number can be positive to specify an external (device specific)
mbed_official 25:ac5b0a371348 777 interrupt, or negative to specify an internal (core) interrupt.
mbed_official 25:ac5b0a371348 778
mbed_official 25:ac5b0a371348 779
mbed_official 25:ac5b0a371348 780 \param [in] IRQn Interrupt number.
mbed_official 25:ac5b0a371348 781 \return Interrupt Priority. Value is aligned automatically to the implemented
mbed_official 25:ac5b0a371348 782 priority bits of the microcontroller.
mbed_official 25:ac5b0a371348 783 */
mbed_official 25:ac5b0a371348 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 785 {
mbed_official 25:ac5b0a371348 786
mbed_official 25:ac5b0a371348 787 if((int32_t)(IRQn) < 0) {
mbed_official 25:ac5b0a371348 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
mbed_official 25:ac5b0a371348 789 }
mbed_official 25:ac5b0a371348 790 else {
mbed_official 25:ac5b0a371348 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
mbed_official 25:ac5b0a371348 792 }
mbed_official 25:ac5b0a371348 793 }
mbed_official 25:ac5b0a371348 794
mbed_official 25:ac5b0a371348 795
mbed_official 25:ac5b0a371348 796 /** \brief System Reset
mbed_official 25:ac5b0a371348 797
mbed_official 25:ac5b0a371348 798 The function initiates a system reset request to reset the MCU.
mbed_official 25:ac5b0a371348 799 */
mbed_official 25:ac5b0a371348 800 __STATIC_INLINE void NVIC_SystemReset(void)
mbed_official 25:ac5b0a371348 801 {
mbed_official 25:ac5b0a371348 802 __DSB(); /* Ensure all outstanding memory accesses included
mbed_official 25:ac5b0a371348 803 buffered write are completed before reset */
mbed_official 25:ac5b0a371348 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 25:ac5b0a371348 805 SCB_AIRCR_SYSRESETREQ_Msk);
mbed_official 25:ac5b0a371348 806 __DSB(); /* Ensure completion of memory access */
mbed_official 25:ac5b0a371348 807 while(1) { __NOP(); } /* wait until reset */
mbed_official 25:ac5b0a371348 808 }
mbed_official 25:ac5b0a371348 809
mbed_official 25:ac5b0a371348 810 /*@} end of CMSIS_Core_NVICFunctions */
mbed_official 25:ac5b0a371348 811
mbed_official 25:ac5b0a371348 812
mbed_official 25:ac5b0a371348 813
mbed_official 25:ac5b0a371348 814 /* ################################## SysTick function ############################################ */
mbed_official 25:ac5b0a371348 815 /** \ingroup CMSIS_Core_FunctionInterface
mbed_official 25:ac5b0a371348 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mbed_official 25:ac5b0a371348 817 \brief Functions that configure the System.
mbed_official 25:ac5b0a371348 818 @{
mbed_official 25:ac5b0a371348 819 */
mbed_official 25:ac5b0a371348 820
mbed_official 25:ac5b0a371348 821 #if (__Vendor_SysTickConfig == 0)
mbed_official 25:ac5b0a371348 822
mbed_official 25:ac5b0a371348 823 /** \brief System Tick Configuration
mbed_official 25:ac5b0a371348 824
mbed_official 25:ac5b0a371348 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mbed_official 25:ac5b0a371348 826 Counter is in free running mode to generate periodic interrupts.
mbed_official 25:ac5b0a371348 827
mbed_official 25:ac5b0a371348 828 \param [in] ticks Number of ticks between two interrupts.
mbed_official 25:ac5b0a371348 829
mbed_official 25:ac5b0a371348 830 \return 0 Function succeeded.
mbed_official 25:ac5b0a371348 831 \return 1 Function failed.
mbed_official 25:ac5b0a371348 832
mbed_official 25:ac5b0a371348 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mbed_official 25:ac5b0a371348 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mbed_official 25:ac5b0a371348 835 must contain a vendor-specific implementation of this function.
mbed_official 25:ac5b0a371348 836
mbed_official 25:ac5b0a371348 837 */
mbed_official 25:ac5b0a371348 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mbed_official 25:ac5b0a371348 839 {
mbed_official 25:ac5b0a371348 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
mbed_official 25:ac5b0a371348 841
mbed_official 25:ac5b0a371348 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official 25:ac5b0a371348 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official 25:ac5b0a371348 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mbed_official 25:ac5b0a371348 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mbed_official 25:ac5b0a371348 846 SysTick_CTRL_TICKINT_Msk |
mbed_official 25:ac5b0a371348 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official 25:ac5b0a371348 848 return (0UL); /* Function successful */
mbed_official 25:ac5b0a371348 849 }
mbed_official 25:ac5b0a371348 850
mbed_official 25:ac5b0a371348 851 #endif
mbed_official 25:ac5b0a371348 852
mbed_official 25:ac5b0a371348 853 /*@} end of CMSIS_Core_SysTickFunctions */
mbed_official 25:ac5b0a371348 854
mbed_official 25:ac5b0a371348 855
mbed_official 25:ac5b0a371348 856
mbed_official 25:ac5b0a371348 857
mbed_official 25:ac5b0a371348 858 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 859 }
mbed_official 25:ac5b0a371348 860 #endif
mbed_official 25:ac5b0a371348 861
mbed_official 25:ac5b0a371348 862 #endif /* __CORE_SC000_H_DEPENDANT */
mbed_official 25:ac5b0a371348 863
mbed_official 25:ac5b0a371348 864 #endif /* __CMSIS_GENERIC */