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targets/cmsis/TARGET_STM/TARGET_STM32F4XX/stm32f4xx.h@70:b3a5af880266, 2016-02-23 (annotated)

Committer:
neurofun
Date:
Tue Feb 23 21:59:35 2016 +0000
Revision:
70:b3a5af880266
Parent:
0:9b334a45a8ff 
Edited DAC routines to allow for the simultaneous use of three channels from two DACs as seen on the STM32F334R8 and STM32F303K8. Edited ADC routines to allow for the simultaneous use of more than one ADC.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.1.0
bogdanm 0:9b334a45a8ff 6 * @date 11-January-2013
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
bogdanm 0:9b334a45a8ff 8 * This file contains all the peripheral register's definitions, bits
bogdanm 0:9b334a45a8ff 9 * definitions and memory mapping for STM32F4xx devices.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * The file is the unique include file that the application programmer
bogdanm 0:9b334a45a8ff 12 * is using in the C source code, usually in main.c. This file contains:
bogdanm 0:9b334a45a8ff 13 * - Configuration section that allows to select:
bogdanm 0:9b334a45a8ff 14 * - The device used in the target application
bogdanm 0:9b334a45a8ff 15 * - To use or not the peripheral's drivers in application code(i.e.
bogdanm 0:9b334a45a8ff 16 * code will be based on direct access to peripheral's registers
bogdanm 0:9b334a45a8ff 17 * rather than drivers API), this option is controlled by
bogdanm 0:9b334a45a8ff 18 * "#define USE_STDPERIPH_DRIVER"
bogdanm 0:9b334a45a8ff 19 * - To change few application-specific parameters such as the HSE
bogdanm 0:9b334a45a8ff 20 * crystal frequency
bogdanm 0:9b334a45a8ff 21 * - Data structures and the address mapping for all peripherals
bogdanm 0:9b334a45a8ff 22 * - Peripheral's registers declarations and bits definition
bogdanm 0:9b334a45a8ff 23 * - Macros to access peripheral's registers hardware
bogdanm 0:9b334a45a8ff 24 *
bogdanm 0:9b334a45a8ff 25 ******************************************************************************
bogdanm 0:9b334a45a8ff 26 * @attention
bogdanm 0:9b334a45a8ff 27 *
bogdanm 0:9b334a45a8ff 28 * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 29 *
bogdanm 0:9b334a45a8ff 30 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
bogdanm 0:9b334a45a8ff 31 * You may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 32 * You may obtain a copy of the License at:
bogdanm 0:9b334a45a8ff 33 *
bogdanm 0:9b334a45a8ff 34 * http://www.st.com/software_license_agreement_liberty_v2
bogdanm 0:9b334a45a8ff 35 *
bogdanm 0:9b334a45a8ff 36 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 37 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 38 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 39 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 40 * limitations under the License.
bogdanm 0:9b334a45a8ff 41 *
bogdanm 0:9b334a45a8ff 42 ******************************************************************************
bogdanm 0:9b334a45a8ff 43 */
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45 /** @addtogroup CMSIS
bogdanm 0:9b334a45a8ff 46 * @{
bogdanm 0:9b334a45a8ff 47 */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup stm32f4xx
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 #ifndef __STM32F4xx_H
bogdanm 0:9b334a45a8ff 54 #define __STM32F4xx_H
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 57 extern "C" {
bogdanm 0:9b334a45a8ff 58 #endif /* __cplusplus */
bogdanm 0:9b334a45a8ff 59
bogdanm 0:9b334a45a8ff 60 /** @addtogroup Library_configuration_section
bogdanm 0:9b334a45a8ff 61 * @{
bogdanm 0:9b334a45a8ff 62 */
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 /* Uncomment the line below according to the target STM32 device used in your
bogdanm 0:9b334a45a8ff 65 application
bogdanm 0:9b334a45a8ff 66 */
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 #if !defined (STM32F4XX) && !defined (STM32F40XX) && !defined (STM32F427X)
bogdanm 0:9b334a45a8ff 69 #define STM32F40XX /*!< STM32F40xx/41xx Devices */
bogdanm 0:9b334a45a8ff 70 /* #define STM32F427X */ /*!< STM32F427x/437x Devices*/
bogdanm 0:9b334a45a8ff 71 #endif
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 /* Tip: To avoid modifying this file each time you need to switch between these
bogdanm 0:9b334a45a8ff 75 devices, you can define the device in your toolchain compiler preprocessor.
bogdanm 0:9b334a45a8ff 76 */
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 #if !defined (STM32F4XX) && !defined (STM32F40XX) && !defined (STM32F427X)
bogdanm 0:9b334a45a8ff 79 #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
bogdanm 0:9b334a45a8ff 80 #endif
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 #if !defined (USE_STDPERIPH_DRIVER)
bogdanm 0:9b334a45a8ff 83 /**
bogdanm 0:9b334a45a8ff 84 * @brief Comment the line below if you will not use the peripherals drivers.
bogdanm 0:9b334a45a8ff 85 In this case, these drivers will not be included and the application code will
bogdanm 0:9b334a45a8ff 86 be based on direct access to peripherals registers
bogdanm 0:9b334a45a8ff 87 */
bogdanm 0:9b334a45a8ff 88 /*#define USE_STDPERIPH_DRIVER */
bogdanm 0:9b334a45a8ff 89 #endif /* USE_STDPERIPH_DRIVER */
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 /**
bogdanm 0:9b334a45a8ff 92 * @brief In the following line adjust the value of External High Speed oscillator (HSE)
bogdanm 0:9b334a45a8ff 93 used in your application
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 Tip: To avoid modifying this file each time you need to use different HSE, you
bogdanm 0:9b334a45a8ff 96 can define the HSE value in your toolchain compiler preprocessor.
bogdanm 0:9b334a45a8ff 97 */
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 #if !defined (HSE_VALUE)
bogdanm 0:9b334a45a8ff 100 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
bogdanm 0:9b334a45a8ff 101 #endif /* HSE_VALUE */
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 /**
bogdanm 0:9b334a45a8ff 104 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
bogdanm 0:9b334a45a8ff 105 Timeout value
bogdanm 0:9b334a45a8ff 106 */
bogdanm 0:9b334a45a8ff 107 #if !defined (HSE_STARTUP_TIMEOUT)
bogdanm 0:9b334a45a8ff 108 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
bogdanm 0:9b334a45a8ff 109 #endif /* HSE_STARTUP_TIMEOUT */
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 #if !defined (HSI_VALUE)
bogdanm 0:9b334a45a8ff 112 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
bogdanm 0:9b334a45a8ff 113 #endif /* HSI_VALUE */
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 /**
bogdanm 0:9b334a45a8ff 116 * @brief STM32F4XX Standard Peripherals Library version number V1.1.0
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118 #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
bogdanm 0:9b334a45a8ff 119 #define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
bogdanm 0:9b334a45a8ff 120 #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
bogdanm 0:9b334a45a8ff 121 #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
bogdanm 0:9b334a45a8ff 122 #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
bogdanm 0:9b334a45a8ff 123 |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
bogdanm 0:9b334a45a8ff 124 |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
bogdanm 0:9b334a45a8ff 125 |(__STM32F4XX_STDPERIPH_VERSION_RC))
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 /**
bogdanm 0:9b334a45a8ff 128 * @}
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /** @addtogroup Configuration_section_for_CMSIS
bogdanm 0:9b334a45a8ff 132 * @{
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /**
bogdanm 0:9b334a45a8ff 136 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
bogdanm 0:9b334a45a8ff 137 */
bogdanm 0:9b334a45a8ff 138 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
bogdanm 0:9b334a45a8ff 139 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
bogdanm 0:9b334a45a8ff 140 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
bogdanm 0:9b334a45a8ff 141 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 142 #define __FPU_PRESENT 1 /*!< FPU present */
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 /**
bogdanm 0:9b334a45a8ff 145 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
bogdanm 0:9b334a45a8ff 146 * in @ref Library_configuration_section
bogdanm 0:9b334a45a8ff 147 */
bogdanm 0:9b334a45a8ff 148 typedef enum IRQn
bogdanm 0:9b334a45a8ff 149 {
bogdanm 0:9b334a45a8ff 150 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
bogdanm 0:9b334a45a8ff 151 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 0:9b334a45a8ff 152 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
bogdanm 0:9b334a45a8ff 153 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
bogdanm 0:9b334a45a8ff 154 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
bogdanm 0:9b334a45a8ff 155 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
bogdanm 0:9b334a45a8ff 156 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
bogdanm 0:9b334a45a8ff 157 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
bogdanm 0:9b334a45a8ff 158 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
bogdanm 0:9b334a45a8ff 159 /****** STM32 specific Interrupt Numbers **********************************************************************/
bogdanm 0:9b334a45a8ff 160 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 0:9b334a45a8ff 161 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
bogdanm 0:9b334a45a8ff 162 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
bogdanm 0:9b334a45a8ff 163 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
bogdanm 0:9b334a45a8ff 164 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
bogdanm 0:9b334a45a8ff 165 RCC_IRQn = 5, /*!< RCC global Interrupt */
bogdanm 0:9b334a45a8ff 166 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
bogdanm 0:9b334a45a8ff 167 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
bogdanm 0:9b334a45a8ff 168 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
bogdanm 0:9b334a45a8ff 169 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
bogdanm 0:9b334a45a8ff 170 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
bogdanm 0:9b334a45a8ff 171 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
bogdanm 0:9b334a45a8ff 172 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
bogdanm 0:9b334a45a8ff 173 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
bogdanm 0:9b334a45a8ff 174 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
bogdanm 0:9b334a45a8ff 175 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
bogdanm 0:9b334a45a8ff 176 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
bogdanm 0:9b334a45a8ff 177 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
bogdanm 0:9b334a45a8ff 178 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
bogdanm 0:9b334a45a8ff 179 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
bogdanm 0:9b334a45a8ff 180 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
bogdanm 0:9b334a45a8ff 181 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
bogdanm 0:9b334a45a8ff 182 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
bogdanm 0:9b334a45a8ff 183 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 0:9b334a45a8ff 184 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
bogdanm 0:9b334a45a8ff 185 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
bogdanm 0:9b334a45a8ff 186 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
bogdanm 0:9b334a45a8ff 187 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 0:9b334a45a8ff 188 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 0:9b334a45a8ff 189 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 0:9b334a45a8ff 190 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
bogdanm 0:9b334a45a8ff 191 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 0:9b334a45a8ff 192 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 0:9b334a45a8ff 193 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 0:9b334a45a8ff 194 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 0:9b334a45a8ff 195 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 0:9b334a45a8ff 196 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 0:9b334a45a8ff 197 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 0:9b334a45a8ff 198 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 0:9b334a45a8ff 199 USART3_IRQn = 39, /*!< USART3 global Interrupt */
bogdanm 0:9b334a45a8ff 200 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 0:9b334a45a8ff 201 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
bogdanm 0:9b334a45a8ff 202 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
bogdanm 0:9b334a45a8ff 203 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
bogdanm 0:9b334a45a8ff 204 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
bogdanm 0:9b334a45a8ff 205 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
bogdanm 0:9b334a45a8ff 206 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
bogdanm 0:9b334a45a8ff 207 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
bogdanm 0:9b334a45a8ff 208 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
bogdanm 0:9b334a45a8ff 209 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
bogdanm 0:9b334a45a8ff 210 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
bogdanm 0:9b334a45a8ff 211 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
bogdanm 0:9b334a45a8ff 212 UART4_IRQn = 52, /*!< UART4 global Interrupt */
bogdanm 0:9b334a45a8ff 213 UART5_IRQn = 53, /*!< UART5 global Interrupt */
bogdanm 0:9b334a45a8ff 214 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
bogdanm 0:9b334a45a8ff 215 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
bogdanm 0:9b334a45a8ff 216 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
bogdanm 0:9b334a45a8ff 217 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
bogdanm 0:9b334a45a8ff 218 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
bogdanm 0:9b334a45a8ff 219 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
bogdanm 0:9b334a45a8ff 220 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
bogdanm 0:9b334a45a8ff 221 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
bogdanm 0:9b334a45a8ff 222 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
bogdanm 0:9b334a45a8ff 223 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
bogdanm 0:9b334a45a8ff 224 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
bogdanm 0:9b334a45a8ff 225 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
bogdanm 0:9b334a45a8ff 226 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
bogdanm 0:9b334a45a8ff 227 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
bogdanm 0:9b334a45a8ff 228 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
bogdanm 0:9b334a45a8ff 229 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
bogdanm 0:9b334a45a8ff 230 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
bogdanm 0:9b334a45a8ff 231 USART6_IRQn = 71, /*!< USART6 global interrupt */
bogdanm 0:9b334a45a8ff 232 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
bogdanm 0:9b334a45a8ff 233 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
bogdanm 0:9b334a45a8ff 234 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
bogdanm 0:9b334a45a8ff 235 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
bogdanm 0:9b334a45a8ff 236 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
bogdanm 0:9b334a45a8ff 237 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
bogdanm 0:9b334a45a8ff 238 DCMI_IRQn = 78, /*!< DCMI global interrupt */
bogdanm 0:9b334a45a8ff 239 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
bogdanm 0:9b334a45a8ff 240 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 #ifdef STM32F40XX
bogdanm 0:9b334a45a8ff 243 FPU_IRQn = 81 /*!< FPU global interrupt */
bogdanm 0:9b334a45a8ff 244 #endif /* STM32F40XX */
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 #ifdef STM32F427X
bogdanm 0:9b334a45a8ff 247 FPU_IRQn = 81, /*!< FPU global interrupt */
bogdanm 0:9b334a45a8ff 248 UART7_IRQn = 82, /*!< UART7 global interrupt */
bogdanm 0:9b334a45a8ff 249 UART8_IRQn = 83, /*!< UART8 global interrupt */
bogdanm 0:9b334a45a8ff 250 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
bogdanm 0:9b334a45a8ff 251 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
bogdanm 0:9b334a45a8ff 252 SPI6_IRQn = 86 /*!< SPI6 global Interrupt */
bogdanm 0:9b334a45a8ff 253 #endif /* STM32F427X */
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 } IRQn_Type;
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /**
bogdanm 0:9b334a45a8ff 258 * @}
bogdanm 0:9b334a45a8ff 259 */
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm 0:9b334a45a8ff 262 #include "system_stm32f4xx.h"
bogdanm 0:9b334a45a8ff 263 #include <stdint.h>
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 /** @addtogroup Exported_types
bogdanm 0:9b334a45a8ff 266 * @{
bogdanm 0:9b334a45a8ff 267 */
bogdanm 0:9b334a45a8ff 268 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
bogdanm 0:9b334a45a8ff 269 typedef int32_t s32;
bogdanm 0:9b334a45a8ff 270 typedef int16_t s16;
bogdanm 0:9b334a45a8ff 271 typedef int8_t s8;
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 typedef const int32_t sc32; /*!< Read Only */
bogdanm 0:9b334a45a8ff 274 typedef const int16_t sc16; /*!< Read Only */
bogdanm 0:9b334a45a8ff 275 typedef const int8_t sc8; /*!< Read Only */
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 typedef __IO int32_t vs32;
bogdanm 0:9b334a45a8ff 278 typedef __IO int16_t vs16;
bogdanm 0:9b334a45a8ff 279 typedef __IO int8_t vs8;
bogdanm 0:9b334a45a8ff 280
bogdanm 0:9b334a45a8ff 281 typedef __I int32_t vsc32; /*!< Read Only */
bogdanm 0:9b334a45a8ff 282 typedef __I int16_t vsc16; /*!< Read Only */
bogdanm 0:9b334a45a8ff 283 typedef __I int8_t vsc8; /*!< Read Only */
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 typedef uint32_t u32;
bogdanm 0:9b334a45a8ff 286 typedef uint16_t u16;
bogdanm 0:9b334a45a8ff 287 typedef uint8_t u8;
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 typedef const uint32_t uc32; /*!< Read Only */
bogdanm 0:9b334a45a8ff 290 typedef const uint16_t uc16; /*!< Read Only */
bogdanm 0:9b334a45a8ff 291 typedef const uint8_t uc8; /*!< Read Only */
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 typedef __IO uint32_t vu32;
bogdanm 0:9b334a45a8ff 294 typedef __IO uint16_t vu16;
bogdanm 0:9b334a45a8ff 295 typedef __IO uint8_t vu8;
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 typedef __I uint32_t vuc32; /*!< Read Only */
bogdanm 0:9b334a45a8ff 298 typedef __I uint16_t vuc16; /*!< Read Only */
bogdanm 0:9b334a45a8ff 299 typedef __I uint8_t vuc8; /*!< Read Only */
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
bogdanm 0:9b334a45a8ff 304 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
bogdanm 0:9b334a45a8ff 305
bogdanm 0:9b334a45a8ff 306 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /**
bogdanm 0:9b334a45a8ff 309 * @}
bogdanm 0:9b334a45a8ff 310 */
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 /** @addtogroup Peripheral_registers_structures
bogdanm 0:9b334a45a8ff 313 * @{
bogdanm 0:9b334a45a8ff 314 */
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 /**
bogdanm 0:9b334a45a8ff 317 * @brief Analog to Digital Converter
bogdanm 0:9b334a45a8ff 318 */
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 typedef struct
bogdanm 0:9b334a45a8ff 321 {
bogdanm 0:9b334a45a8ff 322 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 323 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 324 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 325 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 326 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 327 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 328 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 329 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 330 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 331 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 332 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 333 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 334 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 335 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 336 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
bogdanm 0:9b334a45a8ff 337 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 338 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 339 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 340 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 341 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
bogdanm 0:9b334a45a8ff 342 } ADC_TypeDef;
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 typedef struct
bogdanm 0:9b334a45a8ff 345 {
bogdanm 0:9b334a45a8ff 346 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
bogdanm 0:9b334a45a8ff 347 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
bogdanm 0:9b334a45a8ff 348 __IO uint32_t CDR; /*!< ADC common regular data register for dual
bogdanm 0:9b334a45a8ff 349 AND triple modes, Address offset: ADC1 base address + 0x308 */
bogdanm 0:9b334a45a8ff 350 } ADC_Common_TypeDef;
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 /**
bogdanm 0:9b334a45a8ff 354 * @brief Controller Area Network TxMailBox
bogdanm 0:9b334a45a8ff 355 */
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 typedef struct
bogdanm 0:9b334a45a8ff 358 {
bogdanm 0:9b334a45a8ff 359 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
bogdanm 0:9b334a45a8ff 360 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
bogdanm 0:9b334a45a8ff 361 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
bogdanm 0:9b334a45a8ff 362 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
bogdanm 0:9b334a45a8ff 363 } CAN_TxMailBox_TypeDef;
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /**
bogdanm 0:9b334a45a8ff 366 * @brief Controller Area Network FIFOMailBox
bogdanm 0:9b334a45a8ff 367 */
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 typedef struct
bogdanm 0:9b334a45a8ff 370 {
bogdanm 0:9b334a45a8ff 371 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
bogdanm 0:9b334a45a8ff 372 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
bogdanm 0:9b334a45a8ff 373 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
bogdanm 0:9b334a45a8ff 374 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
bogdanm 0:9b334a45a8ff 375 } CAN_FIFOMailBox_TypeDef;
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 /**
bogdanm 0:9b334a45a8ff 378 * @brief Controller Area Network FilterRegister
bogdanm 0:9b334a45a8ff 379 */
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 typedef struct
bogdanm 0:9b334a45a8ff 382 {
bogdanm 0:9b334a45a8ff 383 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
bogdanm 0:9b334a45a8ff 384 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
bogdanm 0:9b334a45a8ff 385 } CAN_FilterRegister_TypeDef;
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 /**
bogdanm 0:9b334a45a8ff 388 * @brief Controller Area Network
bogdanm 0:9b334a45a8ff 389 */
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 typedef struct
bogdanm 0:9b334a45a8ff 392 {
bogdanm 0:9b334a45a8ff 393 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 394 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 395 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 396 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 397 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 398 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 399 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 400 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 401 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
bogdanm 0:9b334a45a8ff 402 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
bogdanm 0:9b334a45a8ff 403 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
bogdanm 0:9b334a45a8ff 404 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
bogdanm 0:9b334a45a8ff 405 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
bogdanm 0:9b334a45a8ff 406 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
bogdanm 0:9b334a45a8ff 407 uint32_t RESERVED2; /*!< Reserved, 0x208 */
bogdanm 0:9b334a45a8ff 408 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
bogdanm 0:9b334a45a8ff 409 uint32_t RESERVED3; /*!< Reserved, 0x210 */
bogdanm 0:9b334a45a8ff 410 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
bogdanm 0:9b334a45a8ff 411 uint32_t RESERVED4; /*!< Reserved, 0x218 */
bogdanm 0:9b334a45a8ff 412 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
bogdanm 0:9b334a45a8ff 413 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
bogdanm 0:9b334a45a8ff 414 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
bogdanm 0:9b334a45a8ff 415 } CAN_TypeDef;
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /**
bogdanm 0:9b334a45a8ff 418 * @brief CRC calculation unit
bogdanm 0:9b334a45a8ff 419 */
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 typedef struct
bogdanm 0:9b334a45a8ff 422 {
bogdanm 0:9b334a45a8ff 423 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 424 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 425 uint8_t RESERVED0; /*!< Reserved, 0x05 */
bogdanm 0:9b334a45a8ff 426 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 0:9b334a45a8ff 427 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 428 } CRC_TypeDef;
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 /**
bogdanm 0:9b334a45a8ff 431 * @brief Digital to Analog Converter
bogdanm 0:9b334a45a8ff 432 */
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 typedef struct
bogdanm 0:9b334a45a8ff 435 {
bogdanm 0:9b334a45a8ff 436 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 437 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 438 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 439 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 440 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 441 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 442 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 443 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 444 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 445 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 446 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 447 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 448 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 449 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 450 } DAC_TypeDef;
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 /**
bogdanm 0:9b334a45a8ff 453 * @brief Debug MCU
bogdanm 0:9b334a45a8ff 454 */
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 typedef struct
bogdanm 0:9b334a45a8ff 457 {
bogdanm 0:9b334a45a8ff 458 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 459 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 460 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 461 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 462 }DBGMCU_TypeDef;
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /**
bogdanm 0:9b334a45a8ff 465 * @brief DCMI
bogdanm 0:9b334a45a8ff 466 */
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 typedef struct
bogdanm 0:9b334a45a8ff 469 {
bogdanm 0:9b334a45a8ff 470 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 471 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 472 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 473 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 474 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 475 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 476 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 477 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 478 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 479 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 480 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 481 } DCMI_TypeDef;
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /**
bogdanm 0:9b334a45a8ff 484 * @brief DMA Controller
bogdanm 0:9b334a45a8ff 485 */
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 typedef struct
bogdanm 0:9b334a45a8ff 488 {
bogdanm 0:9b334a45a8ff 489 __IO uint32_t CR; /*!< DMA stream x configuration register */
bogdanm 0:9b334a45a8ff 490 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
bogdanm 0:9b334a45a8ff 491 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
bogdanm 0:9b334a45a8ff 492 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
bogdanm 0:9b334a45a8ff 493 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
bogdanm 0:9b334a45a8ff 494 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
bogdanm 0:9b334a45a8ff 495 } DMA_Stream_TypeDef;
bogdanm 0:9b334a45a8ff 496
bogdanm 0:9b334a45a8ff 497 typedef struct
bogdanm 0:9b334a45a8ff 498 {
bogdanm 0:9b334a45a8ff 499 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 500 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 501 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 502 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 503 } DMA_TypeDef;
bogdanm 0:9b334a45a8ff 504
bogdanm 0:9b334a45a8ff 505 /**
bogdanm 0:9b334a45a8ff 506 * @brief Ethernet MAC
bogdanm 0:9b334a45a8ff 507 */
bogdanm 0:9b334a45a8ff 508
bogdanm 0:9b334a45a8ff 509 typedef struct
bogdanm 0:9b334a45a8ff 510 {
bogdanm 0:9b334a45a8ff 511 __IO uint32_t MACCR;
bogdanm 0:9b334a45a8ff 512 __IO uint32_t MACFFR;
bogdanm 0:9b334a45a8ff 513 __IO uint32_t MACHTHR;
bogdanm 0:9b334a45a8ff 514 __IO uint32_t MACHTLR;
bogdanm 0:9b334a45a8ff 515 __IO uint32_t MACMIIAR;
bogdanm 0:9b334a45a8ff 516 __IO uint32_t MACMIIDR;
bogdanm 0:9b334a45a8ff 517 __IO uint32_t MACFCR;
bogdanm 0:9b334a45a8ff 518 __IO uint32_t MACVLANTR; /* 8 */
bogdanm 0:9b334a45a8ff 519 uint32_t RESERVED0[2];
bogdanm 0:9b334a45a8ff 520 __IO uint32_t MACRWUFFR; /* 11 */
bogdanm 0:9b334a45a8ff 521 __IO uint32_t MACPMTCSR;
bogdanm 0:9b334a45a8ff 522 uint32_t RESERVED1[2];
bogdanm 0:9b334a45a8ff 523 __IO uint32_t MACSR; /* 15 */
bogdanm 0:9b334a45a8ff 524 __IO uint32_t MACIMR;
bogdanm 0:9b334a45a8ff 525 __IO uint32_t MACA0HR;
bogdanm 0:9b334a45a8ff 526 __IO uint32_t MACA0LR;
bogdanm 0:9b334a45a8ff 527 __IO uint32_t MACA1HR;
bogdanm 0:9b334a45a8ff 528 __IO uint32_t MACA1LR;
bogdanm 0:9b334a45a8ff 529 __IO uint32_t MACA2HR;
bogdanm 0:9b334a45a8ff 530 __IO uint32_t MACA2LR;
bogdanm 0:9b334a45a8ff 531 __IO uint32_t MACA3HR;
bogdanm 0:9b334a45a8ff 532 __IO uint32_t MACA3LR; /* 24 */
bogdanm 0:9b334a45a8ff 533 uint32_t RESERVED2[40];
bogdanm 0:9b334a45a8ff 534 __IO uint32_t MMCCR; /* 65 */
bogdanm 0:9b334a45a8ff 535 __IO uint32_t MMCRIR;
bogdanm 0:9b334a45a8ff 536 __IO uint32_t MMCTIR;
bogdanm 0:9b334a45a8ff 537 __IO uint32_t MMCRIMR;
bogdanm 0:9b334a45a8ff 538 __IO uint32_t MMCTIMR; /* 69 */
bogdanm 0:9b334a45a8ff 539 uint32_t RESERVED3[14];
bogdanm 0:9b334a45a8ff 540 __IO uint32_t MMCTGFSCCR; /* 84 */
bogdanm 0:9b334a45a8ff 541 __IO uint32_t MMCTGFMSCCR;
bogdanm 0:9b334a45a8ff 542 uint32_t RESERVED4[5];
bogdanm 0:9b334a45a8ff 543 __IO uint32_t MMCTGFCR;
bogdanm 0:9b334a45a8ff 544 uint32_t RESERVED5[10];
bogdanm 0:9b334a45a8ff 545 __IO uint32_t MMCRFCECR;
bogdanm 0:9b334a45a8ff 546 __IO uint32_t MMCRFAECR;
bogdanm 0:9b334a45a8ff 547 uint32_t RESERVED6[10];
bogdanm 0:9b334a45a8ff 548 __IO uint32_t MMCRGUFCR;
bogdanm 0:9b334a45a8ff 549 uint32_t RESERVED7[334];
bogdanm 0:9b334a45a8ff 550 __IO uint32_t PTPTSCR;
bogdanm 0:9b334a45a8ff 551 __IO uint32_t PTPSSIR;
bogdanm 0:9b334a45a8ff 552 __IO uint32_t PTPTSHR;
bogdanm 0:9b334a45a8ff 553 __IO uint32_t PTPTSLR;
bogdanm 0:9b334a45a8ff 554 __IO uint32_t PTPTSHUR;
bogdanm 0:9b334a45a8ff 555 __IO uint32_t PTPTSLUR;
bogdanm 0:9b334a45a8ff 556 __IO uint32_t PTPTSAR;
bogdanm 0:9b334a45a8ff 557 __IO uint32_t PTPTTHR;
bogdanm 0:9b334a45a8ff 558 __IO uint32_t PTPTTLR;
bogdanm 0:9b334a45a8ff 559 __IO uint32_t RESERVED8;
bogdanm 0:9b334a45a8ff 560 __IO uint32_t PTPTSSR;
bogdanm 0:9b334a45a8ff 561 uint32_t RESERVED9[565];
bogdanm 0:9b334a45a8ff 562 __IO uint32_t DMABMR;
bogdanm 0:9b334a45a8ff 563 __IO uint32_t DMATPDR;
bogdanm 0:9b334a45a8ff 564 __IO uint32_t DMARPDR;
bogdanm 0:9b334a45a8ff 565 __IO uint32_t DMARDLAR;
bogdanm 0:9b334a45a8ff 566 __IO uint32_t DMATDLAR;
bogdanm 0:9b334a45a8ff 567 __IO uint32_t DMASR;
bogdanm 0:9b334a45a8ff 568 __IO uint32_t DMAOMR;
bogdanm 0:9b334a45a8ff 569 __IO uint32_t DMAIER;
bogdanm 0:9b334a45a8ff 570 __IO uint32_t DMAMFBOCR;
bogdanm 0:9b334a45a8ff 571 __IO uint32_t DMARSWTR;
bogdanm 0:9b334a45a8ff 572 uint32_t RESERVED10[8];
bogdanm 0:9b334a45a8ff 573 __IO uint32_t DMACHTDR;
bogdanm 0:9b334a45a8ff 574 __IO uint32_t DMACHRDR;
bogdanm 0:9b334a45a8ff 575 __IO uint32_t DMACHTBAR;
bogdanm 0:9b334a45a8ff 576 __IO uint32_t DMACHRBAR;
bogdanm 0:9b334a45a8ff 577 } ETH_TypeDef;
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /**
bogdanm 0:9b334a45a8ff 580 * @brief External Interrupt/Event Controller
bogdanm 0:9b334a45a8ff 581 */
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 typedef struct
bogdanm 0:9b334a45a8ff 584 {
bogdanm 0:9b334a45a8ff 585 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 586 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 587 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 588 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 589 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 590 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 591 } EXTI_TypeDef;
bogdanm 0:9b334a45a8ff 592
bogdanm 0:9b334a45a8ff 593 /**
bogdanm 0:9b334a45a8ff 594 * @brief FLASH Registers
bogdanm 0:9b334a45a8ff 595 */
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 typedef struct
bogdanm 0:9b334a45a8ff 598 {
bogdanm 0:9b334a45a8ff 599 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 600 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 601 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 602 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 603 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 604 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 605 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 606 } FLASH_TypeDef;
bogdanm 0:9b334a45a8ff 607
bogdanm 0:9b334a45a8ff 608 /**
bogdanm 0:9b334a45a8ff 609 * @brief Flexible Static Memory Controller
bogdanm 0:9b334a45a8ff 610 */
bogdanm 0:9b334a45a8ff 611
bogdanm 0:9b334a45a8ff 612 typedef struct
bogdanm 0:9b334a45a8ff 613 {
bogdanm 0:9b334a45a8ff 614 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
bogdanm 0:9b334a45a8ff 615 } FSMC_Bank1_TypeDef;
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617 /**
bogdanm 0:9b334a45a8ff 618 * @brief Flexible Static Memory Controller Bank1E
bogdanm 0:9b334a45a8ff 619 */
bogdanm 0:9b334a45a8ff 620
bogdanm 0:9b334a45a8ff 621 typedef struct
bogdanm 0:9b334a45a8ff 622 {
bogdanm 0:9b334a45a8ff 623 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
bogdanm 0:9b334a45a8ff 624 } FSMC_Bank1E_TypeDef;
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 /**
bogdanm 0:9b334a45a8ff 627 * @brief Flexible Static Memory Controller Bank2
bogdanm 0:9b334a45a8ff 628 */
bogdanm 0:9b334a45a8ff 629
bogdanm 0:9b334a45a8ff 630 typedef struct
bogdanm 0:9b334a45a8ff 631 {
bogdanm 0:9b334a45a8ff 632 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
bogdanm 0:9b334a45a8ff 633 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
bogdanm 0:9b334a45a8ff 634 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
bogdanm 0:9b334a45a8ff 635 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
bogdanm 0:9b334a45a8ff 636 uint32_t RESERVED0; /*!< Reserved, 0x70 */
bogdanm 0:9b334a45a8ff 637 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
bogdanm 0:9b334a45a8ff 638 } FSMC_Bank2_TypeDef;
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 /**
bogdanm 0:9b334a45a8ff 641 * @brief Flexible Static Memory Controller Bank3
bogdanm 0:9b334a45a8ff 642 */
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 typedef struct
bogdanm 0:9b334a45a8ff 645 {
bogdanm 0:9b334a45a8ff 646 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
bogdanm 0:9b334a45a8ff 647 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
bogdanm 0:9b334a45a8ff 648 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
bogdanm 0:9b334a45a8ff 649 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
bogdanm 0:9b334a45a8ff 650 uint32_t RESERVED0; /*!< Reserved, 0x90 */
bogdanm 0:9b334a45a8ff 651 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
bogdanm 0:9b334a45a8ff 652 } FSMC_Bank3_TypeDef;
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 /**
bogdanm 0:9b334a45a8ff 655 * @brief Flexible Static Memory Controller Bank4
bogdanm 0:9b334a45a8ff 656 */
bogdanm 0:9b334a45a8ff 657
bogdanm 0:9b334a45a8ff 658 typedef struct
bogdanm 0:9b334a45a8ff 659 {
bogdanm 0:9b334a45a8ff 660 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
bogdanm 0:9b334a45a8ff 661 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
bogdanm 0:9b334a45a8ff 662 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
bogdanm 0:9b334a45a8ff 663 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
bogdanm 0:9b334a45a8ff 664 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
bogdanm 0:9b334a45a8ff 665 } FSMC_Bank4_TypeDef;
bogdanm 0:9b334a45a8ff 666
bogdanm 0:9b334a45a8ff 667 /**
bogdanm 0:9b334a45a8ff 668 * @brief General Purpose I/O
bogdanm 0:9b334a45a8ff 669 */
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 typedef struct
bogdanm 0:9b334a45a8ff 672 {
bogdanm 0:9b334a45a8ff 673 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 674 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 675 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 676 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 677 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 678 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 679 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 680 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
bogdanm 0:9b334a45a8ff 681 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 682 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
bogdanm 0:9b334a45a8ff 683 } GPIO_TypeDef;
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 /**
bogdanm 0:9b334a45a8ff 686 * @brief System configuration controller
bogdanm 0:9b334a45a8ff 687 */
bogdanm 0:9b334a45a8ff 688
bogdanm 0:9b334a45a8ff 689 typedef struct
bogdanm 0:9b334a45a8ff 690 {
bogdanm 0:9b334a45a8ff 691 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 692 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 693 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
bogdanm 0:9b334a45a8ff 694 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
bogdanm 0:9b334a45a8ff 695 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 696 } SYSCFG_TypeDef;
bogdanm 0:9b334a45a8ff 697
bogdanm 0:9b334a45a8ff 698 /**
bogdanm 0:9b334a45a8ff 699 * @brief Inter-integrated Circuit Interface
bogdanm 0:9b334a45a8ff 700 */
bogdanm 0:9b334a45a8ff 701
bogdanm 0:9b334a45a8ff 702 typedef struct
bogdanm 0:9b334a45a8ff 703 {
bogdanm 0:9b334a45a8ff 704 __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 705 uint16_t RESERVED0; /*!< Reserved, 0x02 */
bogdanm 0:9b334a45a8ff 706 __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 707 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 0:9b334a45a8ff 708 __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 709 uint16_t RESERVED2; /*!< Reserved, 0x0A */
bogdanm 0:9b334a45a8ff 710 __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 711 uint16_t RESERVED3; /*!< Reserved, 0x0E */
bogdanm 0:9b334a45a8ff 712 __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 713 uint16_t RESERVED4; /*!< Reserved, 0x12 */
bogdanm 0:9b334a45a8ff 714 __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 715 uint16_t RESERVED5; /*!< Reserved, 0x16 */
bogdanm 0:9b334a45a8ff 716 __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 717 uint16_t RESERVED6; /*!< Reserved, 0x1A */
bogdanm 0:9b334a45a8ff 718 __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 719 uint16_t RESERVED7; /*!< Reserved, 0x1E */
bogdanm 0:9b334a45a8ff 720 __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 721 uint16_t RESERVED8; /*!< Reserved, 0x22 */
bogdanm 0:9b334a45a8ff 722 __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 723 uint16_t RESERVED9; /*!< Reserved, 0x26 */
bogdanm 0:9b334a45a8ff 724 } I2C_TypeDef;
bogdanm 0:9b334a45a8ff 725
bogdanm 0:9b334a45a8ff 726 /**
bogdanm 0:9b334a45a8ff 727 * @brief Independent WATCHDOG
bogdanm 0:9b334a45a8ff 728 */
bogdanm 0:9b334a45a8ff 729
bogdanm 0:9b334a45a8ff 730 typedef struct
bogdanm 0:9b334a45a8ff 731 {
bogdanm 0:9b334a45a8ff 732 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 733 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 734 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 735 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 736 } IWDG_TypeDef;
bogdanm 0:9b334a45a8ff 737
bogdanm 0:9b334a45a8ff 738 /**
bogdanm 0:9b334a45a8ff 739 * @brief Power Control
bogdanm 0:9b334a45a8ff 740 */
bogdanm 0:9b334a45a8ff 741
bogdanm 0:9b334a45a8ff 742 typedef struct
bogdanm 0:9b334a45a8ff 743 {
bogdanm 0:9b334a45a8ff 744 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 745 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 746 } PWR_TypeDef;
bogdanm 0:9b334a45a8ff 747
bogdanm 0:9b334a45a8ff 748 /**
bogdanm 0:9b334a45a8ff 749 * @brief Reset and Clock Control
bogdanm 0:9b334a45a8ff 750 */
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 typedef struct
bogdanm 0:9b334a45a8ff 753 {
bogdanm 0:9b334a45a8ff 754 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 755 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 756 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 757 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 758 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 759 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 760 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 761 uint32_t RESERVED0; /*!< Reserved, 0x1C */
bogdanm 0:9b334a45a8ff 762 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 763 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 764 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
bogdanm 0:9b334a45a8ff 765 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 766 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 767 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 768 uint32_t RESERVED2; /*!< Reserved, 0x3C */
bogdanm 0:9b334a45a8ff 769 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 770 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 771 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
bogdanm 0:9b334a45a8ff 772 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 773 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
bogdanm 0:9b334a45a8ff 774 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
bogdanm 0:9b334a45a8ff 775 uint32_t RESERVED4; /*!< Reserved, 0x5C */
bogdanm 0:9b334a45a8ff 776 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
bogdanm 0:9b334a45a8ff 777 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
bogdanm 0:9b334a45a8ff 778 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
bogdanm 0:9b334a45a8ff 779 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
bogdanm 0:9b334a45a8ff 780 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
bogdanm 0:9b334a45a8ff 781 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
bogdanm 0:9b334a45a8ff 782 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
bogdanm 0:9b334a45a8ff 783 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
bogdanm 0:9b334a45a8ff 784
bogdanm 0:9b334a45a8ff 785 #ifdef STM32F427X
bogdanm 0:9b334a45a8ff 786 uint32_t RESERVED7; /*!< Reserved, 0x88 */
bogdanm 0:9b334a45a8ff 787 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
bogdanm 0:9b334a45a8ff 788 #endif /* STM32F427X */
bogdanm 0:9b334a45a8ff 789
bogdanm 0:9b334a45a8ff 790 } RCC_TypeDef;
bogdanm 0:9b334a45a8ff 791
bogdanm 0:9b334a45a8ff 792 /**
bogdanm 0:9b334a45a8ff 793 * @brief Real-Time Clock
bogdanm 0:9b334a45a8ff 794 */
bogdanm 0:9b334a45a8ff 795
bogdanm 0:9b334a45a8ff 796 typedef struct
bogdanm 0:9b334a45a8ff 797 {
bogdanm 0:9b334a45a8ff 798 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 799 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 800 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 801 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 802 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 803 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 804 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 805 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 806 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 807 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 808 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 809 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 810 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 811 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 812 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 813 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 814 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 815 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 816 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 817 uint32_t RESERVED7; /*!< Reserved, 0x4C */
bogdanm 0:9b334a45a8ff 818 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 819 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
bogdanm 0:9b334a45a8ff 820 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
bogdanm 0:9b334a45a8ff 821 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
bogdanm 0:9b334a45a8ff 822 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
bogdanm 0:9b334a45a8ff 823 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
bogdanm 0:9b334a45a8ff 824 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
bogdanm 0:9b334a45a8ff 825 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
bogdanm 0:9b334a45a8ff 826 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
bogdanm 0:9b334a45a8ff 827 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
bogdanm 0:9b334a45a8ff 828 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
bogdanm 0:9b334a45a8ff 829 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
bogdanm 0:9b334a45a8ff 830 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
bogdanm 0:9b334a45a8ff 831 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
bogdanm 0:9b334a45a8ff 832 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
bogdanm 0:9b334a45a8ff 833 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
bogdanm 0:9b334a45a8ff 834 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
bogdanm 0:9b334a45a8ff 835 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
bogdanm 0:9b334a45a8ff 836 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
bogdanm 0:9b334a45a8ff 837 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
bogdanm 0:9b334a45a8ff 838 } RTC_TypeDef;
bogdanm 0:9b334a45a8ff 839
bogdanm 0:9b334a45a8ff 840 /**
bogdanm 0:9b334a45a8ff 841 * @brief SD host Interface
bogdanm 0:9b334a45a8ff 842 */
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 typedef struct
bogdanm 0:9b334a45a8ff 845 {
bogdanm 0:9b334a45a8ff 846 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 847 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 848 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 849 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 850 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 851 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 852 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 853 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 854 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 855 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 856 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 857 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 858 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 859 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 860 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 861 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 862 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
bogdanm 0:9b334a45a8ff 863 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 864 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
bogdanm 0:9b334a45a8ff 865 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
bogdanm 0:9b334a45a8ff 866 } SDIO_TypeDef;
bogdanm 0:9b334a45a8ff 867
bogdanm 0:9b334a45a8ff 868 /**
bogdanm 0:9b334a45a8ff 869 * @brief Serial Peripheral Interface
bogdanm 0:9b334a45a8ff 870 */
bogdanm 0:9b334a45a8ff 871
bogdanm 0:9b334a45a8ff 872 typedef struct
bogdanm 0:9b334a45a8ff 873 {
bogdanm 0:9b334a45a8ff 874 __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 875 uint16_t RESERVED0; /*!< Reserved, 0x02 */
bogdanm 0:9b334a45a8ff 876 __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 877 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 0:9b334a45a8ff 878 __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 879 uint16_t RESERVED2; /*!< Reserved, 0x0A */
bogdanm 0:9b334a45a8ff 880 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 881 uint16_t RESERVED3; /*!< Reserved, 0x0E */
bogdanm 0:9b334a45a8ff 882 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 883 uint16_t RESERVED4; /*!< Reserved, 0x12 */
bogdanm 0:9b334a45a8ff 884 __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 885 uint16_t RESERVED5; /*!< Reserved, 0x16 */
bogdanm 0:9b334a45a8ff 886 __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 887 uint16_t RESERVED6; /*!< Reserved, 0x1A */
bogdanm 0:9b334a45a8ff 888 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 889 uint16_t RESERVED7; /*!< Reserved, 0x1E */
bogdanm 0:9b334a45a8ff 890 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 891 uint16_t RESERVED8; /*!< Reserved, 0x22 */
bogdanm 0:9b334a45a8ff 892 } SPI_TypeDef;
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 /**
bogdanm 0:9b334a45a8ff 895 * @brief TIM
bogdanm 0:9b334a45a8ff 896 */
bogdanm 0:9b334a45a8ff 897
bogdanm 0:9b334a45a8ff 898 typedef struct
bogdanm 0:9b334a45a8ff 899 {
bogdanm 0:9b334a45a8ff 900 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 901 uint16_t RESERVED0; /*!< Reserved, 0x02 */
bogdanm 0:9b334a45a8ff 902 __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 903 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 0:9b334a45a8ff 904 __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 905 uint16_t RESERVED2; /*!< Reserved, 0x0A */
bogdanm 0:9b334a45a8ff 906 __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 907 uint16_t RESERVED3; /*!< Reserved, 0x0E */
bogdanm 0:9b334a45a8ff 908 __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 909 uint16_t RESERVED4; /*!< Reserved, 0x12 */
bogdanm 0:9b334a45a8ff 910 __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 911 uint16_t RESERVED5; /*!< Reserved, 0x16 */
bogdanm 0:9b334a45a8ff 912 __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 913 uint16_t RESERVED6; /*!< Reserved, 0x1A */
bogdanm 0:9b334a45a8ff 914 __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 915 uint16_t RESERVED7; /*!< Reserved, 0x1E */
bogdanm 0:9b334a45a8ff 916 __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 917 uint16_t RESERVED8; /*!< Reserved, 0x22 */
bogdanm 0:9b334a45a8ff 918 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 919 __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 920 uint16_t RESERVED9; /*!< Reserved, 0x2A */
bogdanm 0:9b334a45a8ff 921 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 922 __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 923 uint16_t RESERVED10; /*!< Reserved, 0x32 */
bogdanm 0:9b334a45a8ff 924 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 925 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 926 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 927 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 928 __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 929 uint16_t RESERVED11; /*!< Reserved, 0x46 */
bogdanm 0:9b334a45a8ff 930 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 931 uint16_t RESERVED12; /*!< Reserved, 0x4A */
bogdanm 0:9b334a45a8ff 932 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
bogdanm 0:9b334a45a8ff 933 uint16_t RESERVED13; /*!< Reserved, 0x4E */
bogdanm 0:9b334a45a8ff 934 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 935 uint16_t RESERVED14; /*!< Reserved, 0x52 */
bogdanm 0:9b334a45a8ff 936 } TIM_TypeDef;
bogdanm 0:9b334a45a8ff 937
bogdanm 0:9b334a45a8ff 938 /**
bogdanm 0:9b334a45a8ff 939 * @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm 0:9b334a45a8ff 940 */
bogdanm 0:9b334a45a8ff 941
bogdanm 0:9b334a45a8ff 942 typedef struct
bogdanm 0:9b334a45a8ff 943 {
bogdanm 0:9b334a45a8ff 944 __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 945 uint16_t RESERVED0; /*!< Reserved, 0x02 */
bogdanm 0:9b334a45a8ff 946 __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 947 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 0:9b334a45a8ff 948 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 949 uint16_t RESERVED2; /*!< Reserved, 0x0A */
bogdanm 0:9b334a45a8ff 950 __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 951 uint16_t RESERVED3; /*!< Reserved, 0x0E */
bogdanm 0:9b334a45a8ff 952 __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 953 uint16_t RESERVED4; /*!< Reserved, 0x12 */
bogdanm 0:9b334a45a8ff 954 __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 955 uint16_t RESERVED5; /*!< Reserved, 0x16 */
bogdanm 0:9b334a45a8ff 956 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 957 uint16_t RESERVED6; /*!< Reserved, 0x1A */
bogdanm 0:9b334a45a8ff 958 } USART_TypeDef;
bogdanm 0:9b334a45a8ff 959
bogdanm 0:9b334a45a8ff 960 /**
bogdanm 0:9b334a45a8ff 961 * @brief Window WATCHDOG
bogdanm 0:9b334a45a8ff 962 */
bogdanm 0:9b334a45a8ff 963
bogdanm 0:9b334a45a8ff 964 typedef struct
bogdanm 0:9b334a45a8ff 965 {
bogdanm 0:9b334a45a8ff 966 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 967 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 968 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 969 } WWDG_TypeDef;
bogdanm 0:9b334a45a8ff 970
bogdanm 0:9b334a45a8ff 971 /**
bogdanm 0:9b334a45a8ff 972 * @brief Crypto Processor
bogdanm 0:9b334a45a8ff 973 */
bogdanm 0:9b334a45a8ff 974
bogdanm 0:9b334a45a8ff 975 typedef struct
bogdanm 0:9b334a45a8ff 976 {
bogdanm 0:9b334a45a8ff 977 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 978 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 979 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 980 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 981 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 982 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 983 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 984 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 985 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 986 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 987 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 988 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 989 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 990 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 991 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 992 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 993 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 994 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 995 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 996 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
bogdanm 0:9b334a45a8ff 997 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 998 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
bogdanm 0:9b334a45a8ff 999 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
bogdanm 0:9b334a45a8ff 1000 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
bogdanm 0:9b334a45a8ff 1001 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
bogdanm 0:9b334a45a8ff 1002 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
bogdanm 0:9b334a45a8ff 1003 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
bogdanm 0:9b334a45a8ff 1004 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
bogdanm 0:9b334a45a8ff 1005 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
bogdanm 0:9b334a45a8ff 1006 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
bogdanm 0:9b334a45a8ff 1007 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
bogdanm 0:9b334a45a8ff 1008 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
bogdanm 0:9b334a45a8ff 1009 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
bogdanm 0:9b334a45a8ff 1010 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
bogdanm 0:9b334a45a8ff 1011 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
bogdanm 0:9b334a45a8ff 1012 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
bogdanm 0:9b334a45a8ff 1013 } CRYP_TypeDef;
bogdanm 0:9b334a45a8ff 1014
bogdanm 0:9b334a45a8ff 1015 /**
bogdanm 0:9b334a45a8ff 1016 * @brief HASH
bogdanm 0:9b334a45a8ff 1017 */
bogdanm 0:9b334a45a8ff 1018
bogdanm 0:9b334a45a8ff 1019 typedef struct
bogdanm 0:9b334a45a8ff 1020 {
bogdanm 0:9b334a45a8ff 1021 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 1022 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 1023 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 1024 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
bogdanm 0:9b334a45a8ff 1025 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 1026 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 1027 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
bogdanm 0:9b334a45a8ff 1028 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
bogdanm 0:9b334a45a8ff 1029 } HASH_TypeDef;
bogdanm 0:9b334a45a8ff 1030
bogdanm 0:9b334a45a8ff 1031 /**
bogdanm 0:9b334a45a8ff 1032 * @brief HASH_DIGEST
bogdanm 0:9b334a45a8ff 1033 */
bogdanm 0:9b334a45a8ff 1034
bogdanm 0:9b334a45a8ff 1035 typedef struct
bogdanm 0:9b334a45a8ff 1036 {
bogdanm 0:9b334a45a8ff 1037 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
bogdanm 0:9b334a45a8ff 1038 } HASH_DIGEST_TypeDef;
bogdanm 0:9b334a45a8ff 1039
bogdanm 0:9b334a45a8ff 1040 /**
bogdanm 0:9b334a45a8ff 1041 * @brief RNG
bogdanm 0:9b334a45a8ff 1042 */
bogdanm 0:9b334a45a8ff 1043
bogdanm 0:9b334a45a8ff 1044 typedef struct
bogdanm 0:9b334a45a8ff 1045 {
bogdanm 0:9b334a45a8ff 1046 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 1047 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 1048 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 1049 } RNG_TypeDef;
bogdanm 0:9b334a45a8ff 1050
bogdanm 0:9b334a45a8ff 1051 /**
bogdanm 0:9b334a45a8ff 1052 * @}
bogdanm 0:9b334a45a8ff 1053 */
bogdanm 0:9b334a45a8ff 1054
bogdanm 0:9b334a45a8ff 1055 /** @addtogroup Peripheral_memory_map
bogdanm 0:9b334a45a8ff 1056 * @{
bogdanm 0:9b334a45a8ff 1057 */
bogdanm 0:9b334a45a8ff 1058 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
bogdanm 0:9b334a45a8ff 1059 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
bogdanm 0:9b334a45a8ff 1060 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
bogdanm 0:9b334a45a8ff 1061 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
bogdanm 0:9b334a45a8ff 1062 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
bogdanm 0:9b334a45a8ff 1063 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
bogdanm 0:9b334a45a8ff 1064 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
bogdanm 0:9b334a45a8ff 1065 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
bogdanm 0:9b334a45a8ff 1066
bogdanm 0:9b334a45a8ff 1067 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
bogdanm 0:9b334a45a8ff 1068 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
bogdanm 0:9b334a45a8ff 1069 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
bogdanm 0:9b334a45a8ff 1070 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
bogdanm 0:9b334a45a8ff 1071 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
bogdanm 0:9b334a45a8ff 1072 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
bogdanm 0:9b334a45a8ff 1073
bogdanm 0:9b334a45a8ff 1074 /* Legacy defines */
bogdanm 0:9b334a45a8ff 1075 #define SRAM_BASE SRAM1_BASE
bogdanm 0:9b334a45a8ff 1076 #define SRAM_BB_BASE SRAM1_BB_BASE
bogdanm 0:9b334a45a8ff 1077
bogdanm 0:9b334a45a8ff 1078 /*!< Peripheral memory map */
bogdanm 0:9b334a45a8ff 1079 #define APB1PERIPH_BASE PERIPH_BASE
bogdanm 0:9b334a45a8ff 1080 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
bogdanm 0:9b334a45a8ff 1081 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm 0:9b334a45a8ff 1082 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
bogdanm 0:9b334a45a8ff 1083
bogdanm 0:9b334a45a8ff 1084 /*!< APB1 peripherals */
bogdanm 0:9b334a45a8ff 1085 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
bogdanm 0:9b334a45a8ff 1086 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
bogdanm 0:9b334a45a8ff 1087 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
bogdanm 0:9b334a45a8ff 1088 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
bogdanm 0:9b334a45a8ff 1089 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
bogdanm 0:9b334a45a8ff 1090 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
bogdanm 0:9b334a45a8ff 1091 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
bogdanm 0:9b334a45a8ff 1092 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
bogdanm 0:9b334a45a8ff 1093 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
bogdanm 0:9b334a45a8ff 1094 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
bogdanm 0:9b334a45a8ff 1095 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
bogdanm 0:9b334a45a8ff 1096 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
bogdanm 0:9b334a45a8ff 1097 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
bogdanm 0:9b334a45a8ff 1098 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
bogdanm 0:9b334a45a8ff 1099 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
bogdanm 0:9b334a45a8ff 1100 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
bogdanm 0:9b334a45a8ff 1101 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
bogdanm 0:9b334a45a8ff 1102 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
bogdanm 0:9b334a45a8ff 1103 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
bogdanm 0:9b334a45a8ff 1104 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
bogdanm 0:9b334a45a8ff 1105 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
bogdanm 0:9b334a45a8ff 1106 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
bogdanm 0:9b334a45a8ff 1107 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
bogdanm 0:9b334a45a8ff 1108 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
bogdanm 0:9b334a45a8ff 1109 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
bogdanm 0:9b334a45a8ff 1110 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
bogdanm 0:9b334a45a8ff 1111 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
bogdanm 0:9b334a45a8ff 1112 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
bogdanm 0:9b334a45a8ff 1113 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
bogdanm 0:9b334a45a8ff 1114
bogdanm 0:9b334a45a8ff 1115 /*!< APB2 peripherals */
bogdanm 0:9b334a45a8ff 1116 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
bogdanm 0:9b334a45a8ff 1117 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
bogdanm 0:9b334a45a8ff 1118 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
bogdanm 0:9b334a45a8ff 1119 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
bogdanm 0:9b334a45a8ff 1120 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
bogdanm 0:9b334a45a8ff 1121 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
bogdanm 0:9b334a45a8ff 1122 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
bogdanm 0:9b334a45a8ff 1123 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
bogdanm 0:9b334a45a8ff 1124 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
bogdanm 0:9b334a45a8ff 1125 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
bogdanm 0:9b334a45a8ff 1126 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
bogdanm 0:9b334a45a8ff 1127 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
bogdanm 0:9b334a45a8ff 1128 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
bogdanm 0:9b334a45a8ff 1129 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
bogdanm 0:9b334a45a8ff 1130 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
bogdanm 0:9b334a45a8ff 1131 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
bogdanm 0:9b334a45a8ff 1132 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
bogdanm 0:9b334a45a8ff 1133 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
bogdanm 0:9b334a45a8ff 1134
bogdanm 0:9b334a45a8ff 1135 /*!< AHB1 peripherals */
bogdanm 0:9b334a45a8ff 1136 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
bogdanm 0:9b334a45a8ff 1137 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
bogdanm 0:9b334a45a8ff 1138 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
bogdanm 0:9b334a45a8ff 1139 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
bogdanm 0:9b334a45a8ff 1140 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
bogdanm 0:9b334a45a8ff 1141 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
bogdanm 0:9b334a45a8ff 1142 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
bogdanm 0:9b334a45a8ff 1143 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
bogdanm 0:9b334a45a8ff 1144 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
bogdanm 0:9b334a45a8ff 1145
bogdanm 0:9b334a45a8ff 1146 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
bogdanm 0:9b334a45a8ff 1147 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
bogdanm 0:9b334a45a8ff 1148 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
bogdanm 0:9b334a45a8ff 1149 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
bogdanm 0:9b334a45a8ff 1150 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
bogdanm 0:9b334a45a8ff 1151 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
bogdanm 0:9b334a45a8ff 1152 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
bogdanm 0:9b334a45a8ff 1153 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
bogdanm 0:9b334a45a8ff 1154 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
bogdanm 0:9b334a45a8ff 1155 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
bogdanm 0:9b334a45a8ff 1156 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
bogdanm 0:9b334a45a8ff 1157 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
bogdanm 0:9b334a45a8ff 1158 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
bogdanm 0:9b334a45a8ff 1159 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
bogdanm 0:9b334a45a8ff 1160 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
bogdanm 0:9b334a45a8ff 1161 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
bogdanm 0:9b334a45a8ff 1162 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
bogdanm 0:9b334a45a8ff 1163 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
bogdanm 0:9b334a45a8ff 1164 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
bogdanm 0:9b334a45a8ff 1165 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
bogdanm 0:9b334a45a8ff 1166 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
bogdanm 0:9b334a45a8ff 1167 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
bogdanm 0:9b334a45a8ff 1168 #define ETH_MAC_BASE (ETH_BASE)
bogdanm 0:9b334a45a8ff 1169 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
bogdanm 0:9b334a45a8ff 1170 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
bogdanm 0:9b334a45a8ff 1171 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
bogdanm 0:9b334a45a8ff 1172
bogdanm 0:9b334a45a8ff 1173 /*!< AHB2 peripherals */
bogdanm 0:9b334a45a8ff 1174 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
bogdanm 0:9b334a45a8ff 1175 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
bogdanm 0:9b334a45a8ff 1176 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
bogdanm 0:9b334a45a8ff 1177 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
bogdanm 0:9b334a45a8ff 1178 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
bogdanm 0:9b334a45a8ff 1179
bogdanm 0:9b334a45a8ff 1180 /*!< FSMC Bankx registers base address */
bogdanm 0:9b334a45a8ff 1181 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
bogdanm 0:9b334a45a8ff 1182 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
bogdanm 0:9b334a45a8ff 1183 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
bogdanm 0:9b334a45a8ff 1184 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
bogdanm 0:9b334a45a8ff 1185 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
bogdanm 0:9b334a45a8ff 1186
bogdanm 0:9b334a45a8ff 1187 /* Debug MCU registers base address */
bogdanm 0:9b334a45a8ff 1188 #define DBGMCU_BASE ((uint32_t )0xE0042000)
bogdanm 0:9b334a45a8ff 1189
bogdanm 0:9b334a45a8ff 1190 /**
bogdanm 0:9b334a45a8ff 1191 * @}
bogdanm 0:9b334a45a8ff 1192 */
bogdanm 0:9b334a45a8ff 1193
bogdanm 0:9b334a45a8ff 1194 /** @addtogroup Peripheral_declaration
bogdanm 0:9b334a45a8ff 1195 * @{
bogdanm 0:9b334a45a8ff 1196 */
bogdanm 0:9b334a45a8ff 1197 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm 0:9b334a45a8ff 1198 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm 0:9b334a45a8ff 1199 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
bogdanm 0:9b334a45a8ff 1200 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
bogdanm 0:9b334a45a8ff 1201 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm 0:9b334a45a8ff 1202 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm 0:9b334a45a8ff 1203 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
bogdanm 0:9b334a45a8ff 1204 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
bogdanm 0:9b334a45a8ff 1205 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
bogdanm 0:9b334a45a8ff 1206 #define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm 0:9b334a45a8ff 1207 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm 0:9b334a45a8ff 1208 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm 0:9b334a45a8ff 1209 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
bogdanm 0:9b334a45a8ff 1210 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm 0:9b334a45a8ff 1211 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
bogdanm 0:9b334a45a8ff 1212 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
bogdanm 0:9b334a45a8ff 1213 #define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm 0:9b334a45a8ff 1214 #define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm 0:9b334a45a8ff 1215 #define UART4 ((USART_TypeDef *) UART4_BASE)
bogdanm 0:9b334a45a8ff 1216 #define UART5 ((USART_TypeDef *) UART5_BASE)
bogdanm 0:9b334a45a8ff 1217 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm 0:9b334a45a8ff 1218 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm 0:9b334a45a8ff 1219 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
bogdanm 0:9b334a45a8ff 1220 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
bogdanm 0:9b334a45a8ff 1221 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
bogdanm 0:9b334a45a8ff 1222 #define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm 0:9b334a45a8ff 1223 #define DAC ((DAC_TypeDef *) DAC_BASE)
bogdanm 0:9b334a45a8ff 1224 #define UART7 ((USART_TypeDef *) UART7_BASE)
bogdanm 0:9b334a45a8ff 1225 #define UART8 ((USART_TypeDef *) UART8_BASE)
bogdanm 0:9b334a45a8ff 1226 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm 0:9b334a45a8ff 1227 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
bogdanm 0:9b334a45a8ff 1228 #define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm 0:9b334a45a8ff 1229 #define USART6 ((USART_TypeDef *) USART6_BASE)
bogdanm 0:9b334a45a8ff 1230 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
bogdanm 0:9b334a45a8ff 1231 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm 0:9b334a45a8ff 1232 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
bogdanm 0:9b334a45a8ff 1233 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
bogdanm 0:9b334a45a8ff 1234 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
bogdanm 0:9b334a45a8ff 1235 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm 0:9b334a45a8ff 1236 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
bogdanm 0:9b334a45a8ff 1237 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm 0:9b334a45a8ff 1238 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm 0:9b334a45a8ff 1239 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
bogdanm 0:9b334a45a8ff 1240 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
bogdanm 0:9b334a45a8ff 1241 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
bogdanm 0:9b334a45a8ff 1242 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
bogdanm 0:9b334a45a8ff 1243 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
bogdanm 0:9b334a45a8ff 1244
bogdanm 0:9b334a45a8ff 1245 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm 0:9b334a45a8ff 1246 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm 0:9b334a45a8ff 1247 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm 0:9b334a45a8ff 1248 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm 0:9b334a45a8ff 1249 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm 0:9b334a45a8ff 1250 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm 0:9b334a45a8ff 1251 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
bogdanm 0:9b334a45a8ff 1252 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
bogdanm 0:9b334a45a8ff 1253 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
bogdanm 0:9b334a45a8ff 1254
bogdanm 0:9b334a45a8ff 1255 #define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm 0:9b334a45a8ff 1256 #define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm 0:9b334a45a8ff 1257 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm 0:9b334a45a8ff 1258 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm 0:9b334a45a8ff 1259 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
bogdanm 0:9b334a45a8ff 1260 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
bogdanm 0:9b334a45a8ff 1261 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
bogdanm 0:9b334a45a8ff 1262 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
bogdanm 0:9b334a45a8ff 1263 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
bogdanm 0:9b334a45a8ff 1264 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
bogdanm 0:9b334a45a8ff 1265 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
bogdanm 0:9b334a45a8ff 1266 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
bogdanm 0:9b334a45a8ff 1267 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
bogdanm 0:9b334a45a8ff 1268 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
bogdanm 0:9b334a45a8ff 1269 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
bogdanm 0:9b334a45a8ff 1270 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
bogdanm 0:9b334a45a8ff 1271 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
bogdanm 0:9b334a45a8ff 1272 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
bogdanm 0:9b334a45a8ff 1273 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
bogdanm 0:9b334a45a8ff 1274 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
bogdanm 0:9b334a45a8ff 1275 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
bogdanm 0:9b334a45a8ff 1276 #define ETH ((ETH_TypeDef *) ETH_BASE)
bogdanm 0:9b334a45a8ff 1277 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
bogdanm 0:9b334a45a8ff 1278 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
bogdanm 0:9b334a45a8ff 1279 #define HASH ((HASH_TypeDef *) HASH_BASE)
bogdanm 0:9b334a45a8ff 1280 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
bogdanm 0:9b334a45a8ff 1281 #define RNG ((RNG_TypeDef *) RNG_BASE)
bogdanm 0:9b334a45a8ff 1282 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
bogdanm 0:9b334a45a8ff 1283 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
bogdanm 0:9b334a45a8ff 1284 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
bogdanm 0:9b334a45a8ff 1285 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
bogdanm 0:9b334a45a8ff 1286 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
bogdanm 0:9b334a45a8ff 1287 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm 0:9b334a45a8ff 1288
bogdanm 0:9b334a45a8ff 1289 /**
bogdanm 0:9b334a45a8ff 1290 * @}
bogdanm 0:9b334a45a8ff 1291 */
bogdanm 0:9b334a45a8ff 1292
bogdanm 0:9b334a45a8ff 1293 /** @addtogroup Exported_constants
bogdanm 0:9b334a45a8ff 1294 * @{
bogdanm 0:9b334a45a8ff 1295 */
bogdanm 0:9b334a45a8ff 1296
bogdanm 0:9b334a45a8ff 1297 /** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm 0:9b334a45a8ff 1298 * @{
bogdanm 0:9b334a45a8ff 1299 */
bogdanm 0:9b334a45a8ff 1300
bogdanm 0:9b334a45a8ff 1301 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1302 /* Peripheral Registers_Bits_Definition */
bogdanm 0:9b334a45a8ff 1303 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1304
bogdanm 0:9b334a45a8ff 1305 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1306 /* */
bogdanm 0:9b334a45a8ff 1307 /* Analog to Digital Converter */
bogdanm 0:9b334a45a8ff 1308 /* */
bogdanm 0:9b334a45a8ff 1309 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1310 /******************** Bit definition for ADC_SR register ********************/
bogdanm 0:9b334a45a8ff 1311 #define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
bogdanm 0:9b334a45a8ff 1312 #define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
bogdanm 0:9b334a45a8ff 1313 #define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
bogdanm 0:9b334a45a8ff 1314 #define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
bogdanm 0:9b334a45a8ff 1315 #define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
bogdanm 0:9b334a45a8ff 1316 #define ADC_SR_OVR ((uint8_t)0x20) /*!<Overrun flag */
bogdanm 0:9b334a45a8ff 1317
bogdanm 0:9b334a45a8ff 1318 /******************* Bit definition for ADC_CR1 register ********************/
bogdanm 0:9b334a45a8ff 1319 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
bogdanm 0:9b334a45a8ff 1320 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1321 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1322 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1323 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1324 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1325 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
bogdanm 0:9b334a45a8ff 1326 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
bogdanm 0:9b334a45a8ff 1327 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
bogdanm 0:9b334a45a8ff 1328 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
bogdanm 0:9b334a45a8ff 1329 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
bogdanm 0:9b334a45a8ff 1330 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
bogdanm 0:9b334a45a8ff 1331 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
bogdanm 0:9b334a45a8ff 1332 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
bogdanm 0:9b334a45a8ff 1333 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
bogdanm 0:9b334a45a8ff 1334 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1335 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1336 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1337 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
bogdanm 0:9b334a45a8ff 1338 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
bogdanm 0:9b334a45a8ff 1339 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
bogdanm 0:9b334a45a8ff 1340 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1341 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1342 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
bogdanm 0:9b334a45a8ff 1343
bogdanm 0:9b334a45a8ff 1344 /******************* Bit definition for ADC_CR2 register ********************/
bogdanm 0:9b334a45a8ff 1345 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
bogdanm 0:9b334a45a8ff 1346 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
bogdanm 0:9b334a45a8ff 1347 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
bogdanm 0:9b334a45a8ff 1348 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
bogdanm 0:9b334a45a8ff 1349 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
bogdanm 0:9b334a45a8ff 1350 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
bogdanm 0:9b334a45a8ff 1351 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
bogdanm 0:9b334a45a8ff 1352 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1353 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1354 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1355 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1356 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
bogdanm 0:9b334a45a8ff 1357 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1358 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1359 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
bogdanm 0:9b334a45a8ff 1360 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
bogdanm 0:9b334a45a8ff 1361 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1362 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1363 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1364 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1365 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
bogdanm 0:9b334a45a8ff 1366 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1367 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1368 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
bogdanm 0:9b334a45a8ff 1369
bogdanm 0:9b334a45a8ff 1370 /****************** Bit definition for ADC_SMPR1 register *******************/
bogdanm 0:9b334a45a8ff 1371 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
bogdanm 0:9b334a45a8ff 1372 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1373 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1374 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1375 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
bogdanm 0:9b334a45a8ff 1376 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1377 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1378 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1379 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
bogdanm 0:9b334a45a8ff 1380 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1381 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1382 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1383 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
bogdanm 0:9b334a45a8ff 1384 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1385 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1386 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1387 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
bogdanm 0:9b334a45a8ff 1388 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1389 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1390 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1391 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
bogdanm 0:9b334a45a8ff 1392 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1393 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1394 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1395 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
bogdanm 0:9b334a45a8ff 1396 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1397 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1398 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1399 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
bogdanm 0:9b334a45a8ff 1400 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1401 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1402 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1403 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
bogdanm 0:9b334a45a8ff 1404 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1405 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1406 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1407
bogdanm 0:9b334a45a8ff 1408 /****************** Bit definition for ADC_SMPR2 register *******************/
bogdanm 0:9b334a45a8ff 1409 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
bogdanm 0:9b334a45a8ff 1410 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1411 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1412 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1413 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
bogdanm 0:9b334a45a8ff 1414 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1415 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1416 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1417 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
bogdanm 0:9b334a45a8ff 1418 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1419 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1420 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1421 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
bogdanm 0:9b334a45a8ff 1422 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1423 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1424 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1425 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
bogdanm 0:9b334a45a8ff 1426 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1427 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1428 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1429 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
bogdanm 0:9b334a45a8ff 1430 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1431 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1432 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1433 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
bogdanm 0:9b334a45a8ff 1434 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1435 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1436 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1437 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
bogdanm 0:9b334a45a8ff 1438 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1439 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1440 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1441 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
bogdanm 0:9b334a45a8ff 1442 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1443 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1444 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1445 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
bogdanm 0:9b334a45a8ff 1446 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1447 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1448 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1449
bogdanm 0:9b334a45a8ff 1450 /****************** Bit definition for ADC_JOFR1 register *******************/
bogdanm 0:9b334a45a8ff 1451 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
bogdanm 0:9b334a45a8ff 1452
bogdanm 0:9b334a45a8ff 1453 /****************** Bit definition for ADC_JOFR2 register *******************/
bogdanm 0:9b334a45a8ff 1454 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
bogdanm 0:9b334a45a8ff 1455
bogdanm 0:9b334a45a8ff 1456 /****************** Bit definition for ADC_JOFR3 register *******************/
bogdanm 0:9b334a45a8ff 1457 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
bogdanm 0:9b334a45a8ff 1458
bogdanm 0:9b334a45a8ff 1459 /****************** Bit definition for ADC_JOFR4 register *******************/
bogdanm 0:9b334a45a8ff 1460 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
bogdanm 0:9b334a45a8ff 1461
bogdanm 0:9b334a45a8ff 1462 /******************* Bit definition for ADC_HTR register ********************/
bogdanm 0:9b334a45a8ff 1463 #define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
bogdanm 0:9b334a45a8ff 1464
bogdanm 0:9b334a45a8ff 1465 /******************* Bit definition for ADC_LTR register ********************/
bogdanm 0:9b334a45a8ff 1466 #define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
bogdanm 0:9b334a45a8ff 1467
bogdanm 0:9b334a45a8ff 1468 /******************* Bit definition for ADC_SQR1 register *******************/
bogdanm 0:9b334a45a8ff 1469 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1470 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1471 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1472 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1473 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1474 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1475 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1476 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1477 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1478 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1479 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1480 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1481 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1482 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1483 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1484 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1485 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1486 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1487 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1488 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1489 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1490 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1491 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1492 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1493 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
bogdanm 0:9b334a45a8ff 1494 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1495 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1496 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1497 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1498
bogdanm 0:9b334a45a8ff 1499 /******************* Bit definition for ADC_SQR2 register *******************/
bogdanm 0:9b334a45a8ff 1500 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1501 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1502 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1503 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1504 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1505 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1506 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1507 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1508 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1509 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1510 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1511 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1512 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1513 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1514 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1515 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1516 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1517 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1518 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1519 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1520 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1521 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1522 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1523 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1524 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1525 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1526 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1527 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1528 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1529 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1530 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1531 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1532 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1533 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1534 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1535 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1536
bogdanm 0:9b334a45a8ff 1537 /******************* Bit definition for ADC_SQR3 register *******************/
bogdanm 0:9b334a45a8ff 1538 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1539 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1540 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1541 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1542 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1543 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1544 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1545 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1546 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1547 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1548 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1549 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1550 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1551 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1552 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1553 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1554 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1555 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1556 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1557 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1558 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1559 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1560 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1561 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1562 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1563 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1564 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1565 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1566 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1567 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1568 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
bogdanm 0:9b334a45a8ff 1569 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1570 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1571 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1572 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1573 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1574
bogdanm 0:9b334a45a8ff 1575 /******************* Bit definition for ADC_JSQR register *******************/
bogdanm 0:9b334a45a8ff 1576 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
bogdanm 0:9b334a45a8ff 1577 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1578 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1579 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1580 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1581 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1582 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
bogdanm 0:9b334a45a8ff 1583 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1584 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1585 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1586 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1587 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1588 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
bogdanm 0:9b334a45a8ff 1589 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1590 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1591 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1592 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1593 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1594 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
bogdanm 0:9b334a45a8ff 1595 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1596 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1597 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1598 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1599 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1600 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
bogdanm 0:9b334a45a8ff 1601 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1602 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1603
bogdanm 0:9b334a45a8ff 1604 /******************* Bit definition for ADC_JDR1 register *******************/
bogdanm 0:9b334a45a8ff 1605 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
bogdanm 0:9b334a45a8ff 1606
bogdanm 0:9b334a45a8ff 1607 /******************* Bit definition for ADC_JDR2 register *******************/
bogdanm 0:9b334a45a8ff 1608 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
bogdanm 0:9b334a45a8ff 1609
bogdanm 0:9b334a45a8ff 1610 /******************* Bit definition for ADC_JDR3 register *******************/
bogdanm 0:9b334a45a8ff 1611 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
bogdanm 0:9b334a45a8ff 1612
bogdanm 0:9b334a45a8ff 1613 /******************* Bit definition for ADC_JDR4 register *******************/
bogdanm 0:9b334a45a8ff 1614 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
bogdanm 0:9b334a45a8ff 1615
bogdanm 0:9b334a45a8ff 1616 /******************** Bit definition for ADC_DR register ********************/
bogdanm 0:9b334a45a8ff 1617 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
bogdanm 0:9b334a45a8ff 1618 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
bogdanm 0:9b334a45a8ff 1619
bogdanm 0:9b334a45a8ff 1620 /******************* Bit definition for ADC_CSR register ********************/
bogdanm 0:9b334a45a8ff 1621 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
bogdanm 0:9b334a45a8ff 1622 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
bogdanm 0:9b334a45a8ff 1623 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
bogdanm 0:9b334a45a8ff 1624 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
bogdanm 0:9b334a45a8ff 1625 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
bogdanm 0:9b334a45a8ff 1626 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
bogdanm 0:9b334a45a8ff 1627 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
bogdanm 0:9b334a45a8ff 1628 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
bogdanm 0:9b334a45a8ff 1629 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
bogdanm 0:9b334a45a8ff 1630 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
bogdanm 0:9b334a45a8ff 1631 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
bogdanm 0:9b334a45a8ff 1632 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
bogdanm 0:9b334a45a8ff 1633 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
bogdanm 0:9b334a45a8ff 1634 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
bogdanm 0:9b334a45a8ff 1635 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
bogdanm 0:9b334a45a8ff 1636 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
bogdanm 0:9b334a45a8ff 1637 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
bogdanm 0:9b334a45a8ff 1638 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
bogdanm 0:9b334a45a8ff 1639
bogdanm 0:9b334a45a8ff 1640 /******************* Bit definition for ADC_CCR register ********************/
bogdanm 0:9b334a45a8ff 1641 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
bogdanm 0:9b334a45a8ff 1642 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1643 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1644 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1645 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1646 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 1647 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
bogdanm 0:9b334a45a8ff 1648 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1649 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1650 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1651 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 1652 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
bogdanm 0:9b334a45a8ff 1653 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
bogdanm 0:9b334a45a8ff 1654 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1655 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1656 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
bogdanm 0:9b334a45a8ff 1657 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1658 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1659 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
bogdanm 0:9b334a45a8ff 1660 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
bogdanm 0:9b334a45a8ff 1661
bogdanm 0:9b334a45a8ff 1662 /******************* Bit definition for ADC_CDR register ********************/
bogdanm 0:9b334a45a8ff 1663 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
bogdanm 0:9b334a45a8ff 1664 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
bogdanm 0:9b334a45a8ff 1665
bogdanm 0:9b334a45a8ff 1666 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1667 /* */
bogdanm 0:9b334a45a8ff 1668 /* Controller Area Network */
bogdanm 0:9b334a45a8ff 1669 /* */
bogdanm 0:9b334a45a8ff 1670 /******************************************************************************/
bogdanm 0:9b334a45a8ff 1671 /*!<CAN control and status registers */
bogdanm 0:9b334a45a8ff 1672 /******************* Bit definition for CAN_MCR register ********************/
bogdanm 0:9b334a45a8ff 1673 #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
bogdanm 0:9b334a45a8ff 1674 #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
bogdanm 0:9b334a45a8ff 1675 #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
bogdanm 0:9b334a45a8ff 1676 #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
bogdanm 0:9b334a45a8ff 1677 #define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
bogdanm 0:9b334a45a8ff 1678 #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
bogdanm 0:9b334a45a8ff 1679 #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
bogdanm 0:9b334a45a8ff 1680 #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
bogdanm 0:9b334a45a8ff 1681 #define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
bogdanm 0:9b334a45a8ff 1682
bogdanm 0:9b334a45a8ff 1683 /******************* Bit definition for CAN_MSR register ********************/
bogdanm 0:9b334a45a8ff 1684 #define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
bogdanm 0:9b334a45a8ff 1685 #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
bogdanm 0:9b334a45a8ff 1686 #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
bogdanm 0:9b334a45a8ff 1687 #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
bogdanm 0:9b334a45a8ff 1688 #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
bogdanm 0:9b334a45a8ff 1689 #define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
bogdanm 0:9b334a45a8ff 1690 #define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
bogdanm 0:9b334a45a8ff 1691 #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
bogdanm 0:9b334a45a8ff 1692 #define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
bogdanm 0:9b334a45a8ff 1693
bogdanm 0:9b334a45a8ff 1694 /******************* Bit definition for CAN_TSR register ********************/
bogdanm 0:9b334a45a8ff 1695 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
bogdanm 0:9b334a45a8ff 1696 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
bogdanm 0:9b334a45a8ff 1697 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
bogdanm 0:9b334a45a8ff 1698 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
bogdanm 0:9b334a45a8ff 1699 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
bogdanm 0:9b334a45a8ff 1700 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
bogdanm 0:9b334a45a8ff 1701 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
bogdanm 0:9b334a45a8ff 1702 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
bogdanm 0:9b334a45a8ff 1703 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
bogdanm 0:9b334a45a8ff 1704 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
bogdanm 0:9b334a45a8ff 1705 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
bogdanm 0:9b334a45a8ff 1706 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
bogdanm 0:9b334a45a8ff 1707 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
bogdanm 0:9b334a45a8ff 1708 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
bogdanm 0:9b334a45a8ff 1709 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
bogdanm 0:9b334a45a8ff 1710 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
bogdanm 0:9b334a45a8ff 1711
bogdanm 0:9b334a45a8ff 1712 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
bogdanm 0:9b334a45a8ff 1713 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
bogdanm 0:9b334a45a8ff 1714 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
bogdanm 0:9b334a45a8ff 1715 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
bogdanm 0:9b334a45a8ff 1716
bogdanm 0:9b334a45a8ff 1717 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
bogdanm 0:9b334a45a8ff 1718 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
bogdanm 0:9b334a45a8ff 1719 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
bogdanm 0:9b334a45a8ff 1720 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
bogdanm 0:9b334a45a8ff 1721
bogdanm 0:9b334a45a8ff 1722 /******************* Bit definition for CAN_RF0R register *******************/
bogdanm 0:9b334a45a8ff 1723 #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
bogdanm 0:9b334a45a8ff 1724 #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
bogdanm 0:9b334a45a8ff 1725 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
bogdanm 0:9b334a45a8ff 1726 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
bogdanm 0:9b334a45a8ff 1727
bogdanm 0:9b334a45a8ff 1728 /******************* Bit definition for CAN_RF1R register *******************/
bogdanm 0:9b334a45a8ff 1729 #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
bogdanm 0:9b334a45a8ff 1730 #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
bogdanm 0:9b334a45a8ff 1731 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
bogdanm 0:9b334a45a8ff 1732 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
bogdanm 0:9b334a45a8ff 1733
bogdanm 0:9b334a45a8ff 1734 /******************** Bit definition for CAN_IER register *******************/
bogdanm 0:9b334a45a8ff 1735 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
bogdanm 0:9b334a45a8ff 1736 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
bogdanm 0:9b334a45a8ff 1737 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
bogdanm 0:9b334a45a8ff 1738 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
bogdanm 0:9b334a45a8ff 1739 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
bogdanm 0:9b334a45a8ff 1740 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
bogdanm 0:9b334a45a8ff 1741 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
bogdanm 0:9b334a45a8ff 1742 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
bogdanm 0:9b334a45a8ff 1743 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
bogdanm 0:9b334a45a8ff 1744 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
bogdanm 0:9b334a45a8ff 1745 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
bogdanm 0:9b334a45a8ff 1746 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 1747 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
bogdanm 0:9b334a45a8ff 1748 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
bogdanm 0:9b334a45a8ff 1749
bogdanm 0:9b334a45a8ff 1750 /******************** Bit definition for CAN_ESR register *******************/
bogdanm 0:9b334a45a8ff 1751 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
bogdanm 0:9b334a45a8ff 1752 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
bogdanm 0:9b334a45a8ff 1753 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
bogdanm 0:9b334a45a8ff 1754
bogdanm 0:9b334a45a8ff 1755 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
bogdanm 0:9b334a45a8ff 1756 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1757 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1758 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1759
bogdanm 0:9b334a45a8ff 1760 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
bogdanm 0:9b334a45a8ff 1761 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
bogdanm 0:9b334a45a8ff 1762
bogdanm 0:9b334a45a8ff 1763 /******************* Bit definition for CAN_BTR register ********************/
bogdanm 0:9b334a45a8ff 1764 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
bogdanm 0:9b334a45a8ff 1765 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
bogdanm 0:9b334a45a8ff 1766 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
bogdanm 0:9b334a45a8ff 1767 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
bogdanm 0:9b334a45a8ff 1768 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
bogdanm 0:9b334a45a8ff 1769 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
bogdanm 0:9b334a45a8ff 1770
bogdanm 0:9b334a45a8ff 1771 /*!<Mailbox registers */
bogdanm 0:9b334a45a8ff 1772 /****************** Bit definition for CAN_TI0R register ********************/
bogdanm 0:9b334a45a8ff 1773 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 0:9b334a45a8ff 1774 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 1775 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 1776 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 0:9b334a45a8ff 1777 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 1778
bogdanm 0:9b334a45a8ff 1779 /****************** Bit definition for CAN_TDT0R register *******************/
bogdanm 0:9b334a45a8ff 1780 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 1781 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 0:9b334a45a8ff 1782 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 1783
bogdanm 0:9b334a45a8ff 1784 /****************** Bit definition for CAN_TDL0R register *******************/
bogdanm 0:9b334a45a8ff 1785 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 1786 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 1787 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 1788 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 1789
bogdanm 0:9b334a45a8ff 1790 /****************** Bit definition for CAN_TDH0R register *******************/
bogdanm 0:9b334a45a8ff 1791 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 1792 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 1793 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 1794 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 1795
bogdanm 0:9b334a45a8ff 1796 /******************* Bit definition for CAN_TI1R register *******************/
bogdanm 0:9b334a45a8ff 1797 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 0:9b334a45a8ff 1798 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 1799 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 1800 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 0:9b334a45a8ff 1801 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 1802
bogdanm 0:9b334a45a8ff 1803 /******************* Bit definition for CAN_TDT1R register ******************/
bogdanm 0:9b334a45a8ff 1804 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 1805 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 0:9b334a45a8ff 1806 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 1807
bogdanm 0:9b334a45a8ff 1808 /******************* Bit definition for CAN_TDL1R register ******************/
bogdanm 0:9b334a45a8ff 1809 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 1810 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 1811 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 1812 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 1813
bogdanm 0:9b334a45a8ff 1814 /******************* Bit definition for CAN_TDH1R register ******************/
bogdanm 0:9b334a45a8ff 1815 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 1816 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 1817 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 1818 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 1819
bogdanm 0:9b334a45a8ff 1820 /******************* Bit definition for CAN_TI2R register *******************/
bogdanm 0:9b334a45a8ff 1821 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 0:9b334a45a8ff 1822 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 1823 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 1824 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
bogdanm 0:9b334a45a8ff 1825 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 1826
bogdanm 0:9b334a45a8ff 1827 /******************* Bit definition for CAN_TDT2R register ******************/
bogdanm 0:9b334a45a8ff 1828 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 1829 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 0:9b334a45a8ff 1830 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 1831
bogdanm 0:9b334a45a8ff 1832 /******************* Bit definition for CAN_TDL2R register ******************/
bogdanm 0:9b334a45a8ff 1833 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 1834 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 1835 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 1836 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 1837
bogdanm 0:9b334a45a8ff 1838 /******************* Bit definition for CAN_TDH2R register ******************/
bogdanm 0:9b334a45a8ff 1839 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 1840 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 1841 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 1842 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 1843
bogdanm 0:9b334a45a8ff 1844 /******************* Bit definition for CAN_RI0R register *******************/
bogdanm 0:9b334a45a8ff 1845 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 1846 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 1847 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 0:9b334a45a8ff 1848 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 1849
bogdanm 0:9b334a45a8ff 1850 /******************* Bit definition for CAN_RDT0R register ******************/
bogdanm 0:9b334a45a8ff 1851 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 1852 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
bogdanm 0:9b334a45a8ff 1853 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 1854
bogdanm 0:9b334a45a8ff 1855 /******************* Bit definition for CAN_RDL0R register ******************/
bogdanm 0:9b334a45a8ff 1856 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 1857 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 1858 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 1859 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 1860
bogdanm 0:9b334a45a8ff 1861 /******************* Bit definition for CAN_RDH0R register ******************/
bogdanm 0:9b334a45a8ff 1862 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 1863 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 1864 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 1865 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 1866
bogdanm 0:9b334a45a8ff 1867 /******************* Bit definition for CAN_RI1R register *******************/
bogdanm 0:9b334a45a8ff 1868 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 1869 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 1870 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
bogdanm 0:9b334a45a8ff 1871 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 1872
bogdanm 0:9b334a45a8ff 1873 /******************* Bit definition for CAN_RDT1R register ******************/
bogdanm 0:9b334a45a8ff 1874 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 1875 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
bogdanm 0:9b334a45a8ff 1876 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 1877
bogdanm 0:9b334a45a8ff 1878 /******************* Bit definition for CAN_RDL1R register ******************/
bogdanm 0:9b334a45a8ff 1879 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 1880 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 1881 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 1882 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 1883
bogdanm 0:9b334a45a8ff 1884 /******************* Bit definition for CAN_RDH1R register ******************/
bogdanm 0:9b334a45a8ff 1885 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 1886 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 1887 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 1888 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 1889
bogdanm 0:9b334a45a8ff 1890 /*!<CAN filter registers */
bogdanm 0:9b334a45a8ff 1891 /******************* Bit definition for CAN_FMR register ********************/
bogdanm 0:9b334a45a8ff 1892 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
bogdanm 0:9b334a45a8ff 1893
bogdanm 0:9b334a45a8ff 1894 /******************* Bit definition for CAN_FM1R register *******************/
bogdanm 0:9b334a45a8ff 1895 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
bogdanm 0:9b334a45a8ff 1896 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
bogdanm 0:9b334a45a8ff 1897 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
bogdanm 0:9b334a45a8ff 1898 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
bogdanm 0:9b334a45a8ff 1899 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
bogdanm 0:9b334a45a8ff 1900 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
bogdanm 0:9b334a45a8ff 1901 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
bogdanm 0:9b334a45a8ff 1902 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
bogdanm 0:9b334a45a8ff 1903 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
bogdanm 0:9b334a45a8ff 1904 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
bogdanm 0:9b334a45a8ff 1905 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
bogdanm 0:9b334a45a8ff 1906 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
bogdanm 0:9b334a45a8ff 1907 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
bogdanm 0:9b334a45a8ff 1908 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
bogdanm 0:9b334a45a8ff 1909 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
bogdanm 0:9b334a45a8ff 1910
bogdanm 0:9b334a45a8ff 1911 /******************* Bit definition for CAN_FS1R register *******************/
bogdanm 0:9b334a45a8ff 1912 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
bogdanm 0:9b334a45a8ff 1913 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
bogdanm 0:9b334a45a8ff 1914 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
bogdanm 0:9b334a45a8ff 1915 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
bogdanm 0:9b334a45a8ff 1916 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
bogdanm 0:9b334a45a8ff 1917 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
bogdanm 0:9b334a45a8ff 1918 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
bogdanm 0:9b334a45a8ff 1919 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
bogdanm 0:9b334a45a8ff 1920 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
bogdanm 0:9b334a45a8ff 1921 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
bogdanm 0:9b334a45a8ff 1922 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
bogdanm 0:9b334a45a8ff 1923 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
bogdanm 0:9b334a45a8ff 1924 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
bogdanm 0:9b334a45a8ff 1925 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
bogdanm 0:9b334a45a8ff 1926 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
bogdanm 0:9b334a45a8ff 1927
bogdanm 0:9b334a45a8ff 1928 /****************** Bit definition for CAN_FFA1R register *******************/
bogdanm 0:9b334a45a8ff 1929 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
bogdanm 0:9b334a45a8ff 1930 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
bogdanm 0:9b334a45a8ff 1931 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
bogdanm 0:9b334a45a8ff 1932 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
bogdanm 0:9b334a45a8ff 1933 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
bogdanm 0:9b334a45a8ff 1934 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
bogdanm 0:9b334a45a8ff 1935 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
bogdanm 0:9b334a45a8ff 1936 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
bogdanm 0:9b334a45a8ff 1937 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
bogdanm 0:9b334a45a8ff 1938 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
bogdanm 0:9b334a45a8ff 1939 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
bogdanm 0:9b334a45a8ff 1940 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
bogdanm 0:9b334a45a8ff 1941 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
bogdanm 0:9b334a45a8ff 1942 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
bogdanm 0:9b334a45a8ff 1943 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
bogdanm 0:9b334a45a8ff 1944
bogdanm 0:9b334a45a8ff 1945 /******************* Bit definition for CAN_FA1R register *******************/
bogdanm 0:9b334a45a8ff 1946 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
bogdanm 0:9b334a45a8ff 1947 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
bogdanm 0:9b334a45a8ff 1948 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
bogdanm 0:9b334a45a8ff 1949 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
bogdanm 0:9b334a45a8ff 1950 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
bogdanm 0:9b334a45a8ff 1951 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
bogdanm 0:9b334a45a8ff 1952 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
bogdanm 0:9b334a45a8ff 1953 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
bogdanm 0:9b334a45a8ff 1954 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
bogdanm 0:9b334a45a8ff 1955 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
bogdanm 0:9b334a45a8ff 1956 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
bogdanm 0:9b334a45a8ff 1957 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
bogdanm 0:9b334a45a8ff 1958 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
bogdanm 0:9b334a45a8ff 1959 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
bogdanm 0:9b334a45a8ff 1960 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
bogdanm 0:9b334a45a8ff 1961
bogdanm 0:9b334a45a8ff 1962 /******************* Bit definition for CAN_F0R1 register *******************/
bogdanm 0:9b334a45a8ff 1963 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1964 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1965 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1966 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1967 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1968 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1969 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1970 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1971 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1972 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1973 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1974 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1975 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1976 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1977 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1978 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1979 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1980 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1981 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1982 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1983 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1984 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1985 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1986 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1987 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1988 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1989 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1990 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1991 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1992 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1993 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1994 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1995
bogdanm 0:9b334a45a8ff 1996 /******************* Bit definition for CAN_F1R1 register *******************/
bogdanm 0:9b334a45a8ff 1997 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1998 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1999 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2000 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2001 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2002 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2003 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2004 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2005 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2006 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2007 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2008 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2009 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2010 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2011 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2012 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2013 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2014 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2015 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2016 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2017 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2018 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2019 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2020 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2021 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2022 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2023 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2024 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2025 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2026 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2027 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2028 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2029
bogdanm 0:9b334a45a8ff 2030 /******************* Bit definition for CAN_F2R1 register *******************/
bogdanm 0:9b334a45a8ff 2031 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2032 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2033 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2034 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2035 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2036 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2037 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2038 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2039 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2040 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2041 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2042 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2043 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2044 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2045 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2046 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2047 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2048 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2049 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2050 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2051 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2052 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2053 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2054 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2055 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2056 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2057 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2058 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2059 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2060 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2061 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2062 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2063
bogdanm 0:9b334a45a8ff 2064 /******************* Bit definition for CAN_F3R1 register *******************/
bogdanm 0:9b334a45a8ff 2065 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2066 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2067 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2068 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2069 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2070 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2071 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2072 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2073 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2074 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2075 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2076 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2077 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2078 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2079 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2080 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2081 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2082 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2083 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2084 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2085 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2086 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2087 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2088 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2089 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2090 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2091 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2092 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2093 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2094 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2095 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2096 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2097
bogdanm 0:9b334a45a8ff 2098 /******************* Bit definition for CAN_F4R1 register *******************/
bogdanm 0:9b334a45a8ff 2099 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2100 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2101 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2102 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2103 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2104 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2105 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2106 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2107 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2108 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2109 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2110 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2111 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2112 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2113 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2114 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2115 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2116 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2117 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2118 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2119 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2120 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2121 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2122 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2123 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2124 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2125 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2126 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2127 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2128 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2129 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2130 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2131
bogdanm 0:9b334a45a8ff 2132 /******************* Bit definition for CAN_F5R1 register *******************/
bogdanm 0:9b334a45a8ff 2133 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2134 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2135 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2136 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2137 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2138 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2139 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2140 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2141 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2142 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2143 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2144 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2145 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2146 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2147 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2148 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2149 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2150 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2151 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2152 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2153 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2154 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2155 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2156 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2157 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2158 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2159 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2160 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2161 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2162 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2163 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2164 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2165
bogdanm 0:9b334a45a8ff 2166 /******************* Bit definition for CAN_F6R1 register *******************/
bogdanm 0:9b334a45a8ff 2167 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2168 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2169 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2170 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2171 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2172 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2173 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2174 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2175 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2176 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2177 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2178 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2179 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2180 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2181 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2182 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2183 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2184 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2185 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2186 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2187 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2188 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2189 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2190 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2191 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2192 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2193 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2194 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2195 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2196 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2197 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2198 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2199
bogdanm 0:9b334a45a8ff 2200 /******************* Bit definition for CAN_F7R1 register *******************/
bogdanm 0:9b334a45a8ff 2201 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2202 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2203 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2204 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2205 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2206 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2207 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2208 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2209 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2210 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2211 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2212 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2213 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2214 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2215 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2216 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2217 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2218 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2219 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2220 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2221 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2222 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2223 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2224 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2225 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2226 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2227 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2228 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2229 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2230 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2231 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2232 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2233
bogdanm 0:9b334a45a8ff 2234 /******************* Bit definition for CAN_F8R1 register *******************/
bogdanm 0:9b334a45a8ff 2235 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2236 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2237 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2238 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2239 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2240 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2241 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2242 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2243 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2244 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2245 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2246 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2247 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2248 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2249 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2250 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2251 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2252 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2253 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2254 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2255 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2256 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2257 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2258 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2259 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2260 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2261 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2262 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2263 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2264 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2265 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2266 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2267
bogdanm 0:9b334a45a8ff 2268 /******************* Bit definition for CAN_F9R1 register *******************/
bogdanm 0:9b334a45a8ff 2269 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2270 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2271 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2272 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2273 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2274 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2275 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2276 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2277 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2278 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2279 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2280 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2281 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2282 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2283 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2284 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2285 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2286 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2287 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2288 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2289 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2290 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2291 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2292 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2293 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2294 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2295 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2296 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2297 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2298 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2299 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2300 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2301
bogdanm 0:9b334a45a8ff 2302 /******************* Bit definition for CAN_F10R1 register ******************/
bogdanm 0:9b334a45a8ff 2303 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2304 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2305 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2306 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2307 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2308 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2309 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2310 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2311 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2312 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2313 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2314 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2315 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2316 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2317 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2318 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2319 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2320 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2321 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2322 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2323 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2324 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2325 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2326 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2327 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2328 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2329 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2330 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2331 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2332 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2333 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2334 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2335
bogdanm 0:9b334a45a8ff 2336 /******************* Bit definition for CAN_F11R1 register ******************/
bogdanm 0:9b334a45a8ff 2337 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2338 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2339 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2340 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2341 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2342 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2343 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2344 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2345 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2346 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2347 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2348 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2349 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2350 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2351 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2352 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2353 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2354 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2355 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2356 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2357 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2358 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2359 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2360 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2361 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2362 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2363 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2364 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2365 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2366 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2367 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2368 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2369
bogdanm 0:9b334a45a8ff 2370 /******************* Bit definition for CAN_F12R1 register ******************/
bogdanm 0:9b334a45a8ff 2371 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2372 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2373 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2374 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2375 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2376 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2377 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2378 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2379 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2380 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2381 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2382 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2383 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2384 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2385 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2386 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2387 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2388 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2389 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2390 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2391 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2392 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2393 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2394 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2395 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2396 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2397 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2398 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2399 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2400 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2401 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2402 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2403
bogdanm 0:9b334a45a8ff 2404 /******************* Bit definition for CAN_F13R1 register ******************/
bogdanm 0:9b334a45a8ff 2405 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2406 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2407 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2408 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2409 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2410 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2411 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2412 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2413 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2414 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2415 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2416 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2417 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2418 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2419 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2420 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2421 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2422 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2423 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2424 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2425 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2426 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2427 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2428 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2429 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2430 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2431 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2432 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2433 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2434 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2435 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2436 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2437
bogdanm 0:9b334a45a8ff 2438 /******************* Bit definition for CAN_F0R2 register *******************/
bogdanm 0:9b334a45a8ff 2439 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2440 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2441 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2442 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2443 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2444 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2445 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2446 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2447 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2448 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2449 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2450 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2451 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2452 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2453 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2454 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2455 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2456 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2457 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2458 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2459 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2460 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2461 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2462 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2463 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2464 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2465 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2466 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2467 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2468 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2469 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2470 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2471
bogdanm 0:9b334a45a8ff 2472 /******************* Bit definition for CAN_F1R2 register *******************/
bogdanm 0:9b334a45a8ff 2473 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2474 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2475 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2476 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2477 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2478 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2479 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2480 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2481 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2482 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2483 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2484 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2485 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2486 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2487 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2488 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2489 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2490 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2491 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2492 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2493 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2494 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2495 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2496 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2497 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2498 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2499 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2500 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2501 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2502 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2503 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2504 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2505
bogdanm 0:9b334a45a8ff 2506 /******************* Bit definition for CAN_F2R2 register *******************/
bogdanm 0:9b334a45a8ff 2507 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2508 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2509 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2510 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2511 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2512 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2513 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2514 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2515 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2516 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2517 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2518 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2519 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2520 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2521 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2522 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2523 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2524 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2525 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2526 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2527 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2528 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2529 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2530 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2531 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2532 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2533 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2534 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2535 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2536 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2537 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2538 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2539
bogdanm 0:9b334a45a8ff 2540 /******************* Bit definition for CAN_F3R2 register *******************/
bogdanm 0:9b334a45a8ff 2541 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2542 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2543 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2544 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2545 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2546 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2547 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2548 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2549 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2550 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2551 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2552 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2553 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2554 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2555 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2556 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2557 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2558 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2559 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2560 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2561 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2562 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2563 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2564 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2565 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2566 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2567 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2568 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2569 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2570 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2571 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2572 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2573
bogdanm 0:9b334a45a8ff 2574 /******************* Bit definition for CAN_F4R2 register *******************/
bogdanm 0:9b334a45a8ff 2575 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2576 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2577 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2578 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2579 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2580 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2581 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2582 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2583 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2584 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2585 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2586 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2587 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2588 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2589 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2590 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2591 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2592 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2593 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2594 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2595 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2596 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2597 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2598 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2599 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2600 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2601 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2602 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2603 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2604 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2605 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2606 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2607
bogdanm 0:9b334a45a8ff 2608 /******************* Bit definition for CAN_F5R2 register *******************/
bogdanm 0:9b334a45a8ff 2609 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2610 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2611 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2612 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2613 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2614 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2615 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2616 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2617 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2618 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2619 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2620 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2621 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2622 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2623 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2624 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2625 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2626 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2627 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2628 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2629 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2630 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2631 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2632 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2633 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2634 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2635 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2636 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2637 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2638 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2639 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2640 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2641
bogdanm 0:9b334a45a8ff 2642 /******************* Bit definition for CAN_F6R2 register *******************/
bogdanm 0:9b334a45a8ff 2643 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2644 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2645 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2646 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2647 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2648 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2649 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2650 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2651 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2652 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2653 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2654 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2655 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2656 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2657 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2658 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2659 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2660 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2661 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2662 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2663 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2664 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2665 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2666 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2667 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2668 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2669 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2670 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2671 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2672 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2673 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2674 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2675
bogdanm 0:9b334a45a8ff 2676 /******************* Bit definition for CAN_F7R2 register *******************/
bogdanm 0:9b334a45a8ff 2677 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2678 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2679 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2680 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2681 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2682 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2683 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2684 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2685 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2686 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2687 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2688 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2689 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2690 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2691 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2692 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2693 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2694 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2695 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2696 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2697 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2698 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2699 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2700 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2701 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2702 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2703 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2704 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2705 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2706 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2707 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2708 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2709
bogdanm 0:9b334a45a8ff 2710 /******************* Bit definition for CAN_F8R2 register *******************/
bogdanm 0:9b334a45a8ff 2711 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2712 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2713 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2714 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2715 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2716 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2717 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2718 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2719 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2720 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2721 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2722 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2723 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2724 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2725 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2726 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2727 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2728 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2729 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2730 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2731 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2732 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2733 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2734 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2735 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2736 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2737 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2738 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2739 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2740 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2741 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2742 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2743
bogdanm 0:9b334a45a8ff 2744 /******************* Bit definition for CAN_F9R2 register *******************/
bogdanm 0:9b334a45a8ff 2745 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2746 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2747 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2748 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2749 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2750 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2751 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2752 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2753 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2754 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2755 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2756 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2757 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2758 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2759 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2760 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2761 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2762 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2763 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2764 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2765 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2766 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2767 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2768 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2769 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2770 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2771 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2772 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2773 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2774 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2775 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2776 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2777
bogdanm 0:9b334a45a8ff 2778 /******************* Bit definition for CAN_F10R2 register ******************/
bogdanm 0:9b334a45a8ff 2779 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2780 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2781 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2782 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2783 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2784 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2785 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2786 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2787 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2788 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2789 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2790 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2791 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2792 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2793 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2794 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2795 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2796 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2797 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2798 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2799 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2800 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2801 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2802 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2803 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2804 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2805 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2806 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2807 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2808 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2809 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2810 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2811
bogdanm 0:9b334a45a8ff 2812 /******************* Bit definition for CAN_F11R2 register ******************/
bogdanm 0:9b334a45a8ff 2813 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2814 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2815 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2816 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2817 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2818 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2819 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2820 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2821 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2822 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2823 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2824 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2825 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2826 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2827 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2828 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2829 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2830 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2831 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2832 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2833 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2834 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2835 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2836 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2837 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2838 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2839 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2840 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2841 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2842 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2843 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2844 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2845
bogdanm 0:9b334a45a8ff 2846 /******************* Bit definition for CAN_F12R2 register ******************/
bogdanm 0:9b334a45a8ff 2847 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2848 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2849 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2850 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2851 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2852 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2853 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2854 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2855 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2856 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2857 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2858 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2859 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2860 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2861 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2862 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2863 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2864 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2865 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2866 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2867 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2868 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2869 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2870 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2871 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2872 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2873 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2874 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2875 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2876 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2877 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2878 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2879
bogdanm 0:9b334a45a8ff 2880 /******************* Bit definition for CAN_F13R2 register ******************/
bogdanm 0:9b334a45a8ff 2881 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2882 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2883 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2884 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2885 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2886 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2887 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2888 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2889 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2890 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2891 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2892 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2893 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2894 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2895 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2896 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2897 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2898 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2899 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2900 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2901 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2902 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2903 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2904 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2905 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2906 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2907 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2908 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2909 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2910 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2911 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2912 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2913
bogdanm 0:9b334a45a8ff 2914 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2915 /* */
bogdanm 0:9b334a45a8ff 2916 /* CRC calculation unit */
bogdanm 0:9b334a45a8ff 2917 /* */
bogdanm 0:9b334a45a8ff 2918 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2919 /******************* Bit definition for CRC_DR register *********************/
bogdanm 0:9b334a45a8ff 2920 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
bogdanm 0:9b334a45a8ff 2921
bogdanm 0:9b334a45a8ff 2922
bogdanm 0:9b334a45a8ff 2923 /******************* Bit definition for CRC_IDR register ********************/
bogdanm 0:9b334a45a8ff 2924 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
bogdanm 0:9b334a45a8ff 2925
bogdanm 0:9b334a45a8ff 2926
bogdanm 0:9b334a45a8ff 2927 /******************** Bit definition for CRC_CR register ********************/
bogdanm 0:9b334a45a8ff 2928 #define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
bogdanm 0:9b334a45a8ff 2929
bogdanm 0:9b334a45a8ff 2930 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2931 /* */
bogdanm 0:9b334a45a8ff 2932 /* Crypto Processor */
bogdanm 0:9b334a45a8ff 2933 /* */
bogdanm 0:9b334a45a8ff 2934 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2935 /******************* Bits definition for CRYP_CR register ********************/
bogdanm 0:9b334a45a8ff 2936 #define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 2937
bogdanm 0:9b334a45a8ff 2938 #define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)
bogdanm 0:9b334a45a8ff 2939 #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 2940 #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 2941 #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 2942 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 2943 #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 2944 #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 2945 #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
bogdanm 0:9b334a45a8ff 2946 #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 2947 #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
bogdanm 0:9b334a45a8ff 2948 #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 2949 #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
bogdanm 0:9b334a45a8ff 2950
bogdanm 0:9b334a45a8ff 2951 #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 2952 #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 2953 #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 2954 #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
bogdanm 0:9b334a45a8ff 2955 #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 2956 #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 2957 #define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 2958 #define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 2959
bogdanm 0:9b334a45a8ff 2960 #define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)
bogdanm 0:9b334a45a8ff 2961 #define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 2962 #define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 2963 #define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 2964
bogdanm 0:9b334a45a8ff 2965 /****************** Bits definition for CRYP_SR register *********************/
bogdanm 0:9b334a45a8ff 2966 #define CRYP_SR_IFEM ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 2967 #define CRYP_SR_IFNF ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 2968 #define CRYP_SR_OFNE ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 2969 #define CRYP_SR_OFFU ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 2970 #define CRYP_SR_BUSY ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 2971 /****************** Bits definition for CRYP_DMACR register ******************/
bogdanm 0:9b334a45a8ff 2972 #define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 2973 #define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 2974 /***************** Bits definition for CRYP_IMSCR register ******************/
bogdanm 0:9b334a45a8ff 2975 #define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 2976 #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 2977 /****************** Bits definition for CRYP_RISR register *******************/
bogdanm 0:9b334a45a8ff 2978 #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 2979 #define CRYP_RISR_INRIS ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 2980 /****************** Bits definition for CRYP_MISR register *******************/
bogdanm 0:9b334a45a8ff 2981 #define CRYP_MISR_INMIS ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 2982 #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 2983
bogdanm 0:9b334a45a8ff 2984 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2985 /* */
bogdanm 0:9b334a45a8ff 2986 /* Digital to Analog Converter */
bogdanm 0:9b334a45a8ff 2987 /* */
bogdanm 0:9b334a45a8ff 2988 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2989 /******************** Bit definition for DAC_CR register ********************/
bogdanm 0:9b334a45a8ff 2990 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
bogdanm 0:9b334a45a8ff 2991 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
bogdanm 0:9b334a45a8ff 2992 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
bogdanm 0:9b334a45a8ff 2993
bogdanm 0:9b334a45a8ff 2994 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
bogdanm 0:9b334a45a8ff 2995 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 2996 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 2997 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 2998
bogdanm 0:9b334a45a8ff 2999 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
bogdanm 0:9b334a45a8ff 3000 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3001 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3002
bogdanm 0:9b334a45a8ff 3003 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
bogdanm 0:9b334a45a8ff 3004 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3005 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3006 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3007 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3008
bogdanm 0:9b334a45a8ff 3009 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
bogdanm 0:9b334a45a8ff 3010 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
bogdanm 0:9b334a45a8ff 3011 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
bogdanm 0:9b334a45a8ff 3012 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
bogdanm 0:9b334a45a8ff 3013
bogdanm 0:9b334a45a8ff 3014 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
bogdanm 0:9b334a45a8ff 3015 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3016 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3017 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3018
bogdanm 0:9b334a45a8ff 3019 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
bogdanm 0:9b334a45a8ff 3020 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3021 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3022
bogdanm 0:9b334a45a8ff 3023 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
bogdanm 0:9b334a45a8ff 3024 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3025 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3026 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3027 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3028
bogdanm 0:9b334a45a8ff 3029 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
bogdanm 0:9b334a45a8ff 3030
bogdanm 0:9b334a45a8ff 3031 /***************** Bit definition for DAC_SWTRIGR register ******************/
bogdanm 0:9b334a45a8ff 3032 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
bogdanm 0:9b334a45a8ff 3033 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
bogdanm 0:9b334a45a8ff 3034
bogdanm 0:9b334a45a8ff 3035 /***************** Bit definition for DAC_DHR12R1 register ******************/
bogdanm 0:9b334a45a8ff 3036 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3037
bogdanm 0:9b334a45a8ff 3038 /***************** Bit definition for DAC_DHR12L1 register ******************/
bogdanm 0:9b334a45a8ff 3039 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 3040
bogdanm 0:9b334a45a8ff 3041 /****************** Bit definition for DAC_DHR8R1 register ******************/
bogdanm 0:9b334a45a8ff 3042 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3043
bogdanm 0:9b334a45a8ff 3044 /***************** Bit definition for DAC_DHR12R2 register ******************/
bogdanm 0:9b334a45a8ff 3045 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3046
bogdanm 0:9b334a45a8ff 3047 /***************** Bit definition for DAC_DHR12L2 register ******************/
bogdanm 0:9b334a45a8ff 3048 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 3049
bogdanm 0:9b334a45a8ff 3050 /****************** Bit definition for DAC_DHR8R2 register ******************/
bogdanm 0:9b334a45a8ff 3051 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3052
bogdanm 0:9b334a45a8ff 3053 /***************** Bit definition for DAC_DHR12RD register ******************/
bogdanm 0:9b334a45a8ff 3054 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3055 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3056
bogdanm 0:9b334a45a8ff 3057 /***************** Bit definition for DAC_DHR12LD register ******************/
bogdanm 0:9b334a45a8ff 3058 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 3059 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 3060
bogdanm 0:9b334a45a8ff 3061 /****************** Bit definition for DAC_DHR8RD register ******************/
bogdanm 0:9b334a45a8ff 3062 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3063 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 3064
bogdanm 0:9b334a45a8ff 3065 /******************* Bit definition for DAC_DOR1 register *******************/
bogdanm 0:9b334a45a8ff 3066 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
bogdanm 0:9b334a45a8ff 3067
bogdanm 0:9b334a45a8ff 3068 /******************* Bit definition for DAC_DOR2 register *******************/
bogdanm 0:9b334a45a8ff 3069 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
bogdanm 0:9b334a45a8ff 3070
bogdanm 0:9b334a45a8ff 3071 /******************** Bit definition for DAC_SR register ********************/
bogdanm 0:9b334a45a8ff 3072 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
bogdanm 0:9b334a45a8ff 3073 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
bogdanm 0:9b334a45a8ff 3074
bogdanm 0:9b334a45a8ff 3075 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3076 /* */
bogdanm 0:9b334a45a8ff 3077 /* Debug MCU */
bogdanm 0:9b334a45a8ff 3078 /* */
bogdanm 0:9b334a45a8ff 3079 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3080
bogdanm 0:9b334a45a8ff 3081 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3082 /* */
bogdanm 0:9b334a45a8ff 3083 /* DCMI */
bogdanm 0:9b334a45a8ff 3084 /* */
bogdanm 0:9b334a45a8ff 3085 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3086 /******************** Bits definition for DCMI_CR register ******************/
bogdanm 0:9b334a45a8ff 3087 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3088 #define DCMI_CR_CM ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3089 #define DCMI_CR_CROP ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3090 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3091 #define DCMI_CR_ESS ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3092 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3093 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3094 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3095 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3096 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3097 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3098 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3099 #define DCMI_CR_CRE ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3100 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3101
bogdanm 0:9b334a45a8ff 3102 /******************** Bits definition for DCMI_SR register ******************/
bogdanm 0:9b334a45a8ff 3103 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3104 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3105 #define DCMI_SR_FNE ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3106
bogdanm 0:9b334a45a8ff 3107 /******************** Bits definition for DCMI_RISR register ****************/
bogdanm 0:9b334a45a8ff 3108 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3109 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3110 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3111 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3112 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3113
bogdanm 0:9b334a45a8ff 3114 /******************** Bits definition for DCMI_IER register *****************/
bogdanm 0:9b334a45a8ff 3115 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3116 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3117 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3118 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3119 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3120
bogdanm 0:9b334a45a8ff 3121 /******************** Bits definition for DCMI_MISR register ****************/
bogdanm 0:9b334a45a8ff 3122 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3123 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3124 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3125 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3126 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3127
bogdanm 0:9b334a45a8ff 3128 /******************** Bits definition for DCMI_ICR register *****************/
bogdanm 0:9b334a45a8ff 3129 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3130 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3131 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3132 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3133 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3134
bogdanm 0:9b334a45a8ff 3135 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3136 /* */
bogdanm 0:9b334a45a8ff 3137 /* DMA Controller */
bogdanm 0:9b334a45a8ff 3138 /* */
bogdanm 0:9b334a45a8ff 3139 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3140 /******************** Bits definition for DMA_SxCR register *****************/
bogdanm 0:9b334a45a8ff 3141 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
bogdanm 0:9b334a45a8ff 3142 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3143 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3144 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3145 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
bogdanm 0:9b334a45a8ff 3146 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3147 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3148 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
bogdanm 0:9b334a45a8ff 3149 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3150 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3151 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3152 #define DMA_SxCR_CT ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3153 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3154 #define DMA_SxCR_PL ((uint32_t)0x00030000)
bogdanm 0:9b334a45a8ff 3155 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3156 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3157 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3158 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
bogdanm 0:9b334a45a8ff 3159 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3160 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3161 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
bogdanm 0:9b334a45a8ff 3162 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3163 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3164 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3165 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3166 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3167 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 3168 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3169 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3170 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3171 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3172 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3173 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3174 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3175 #define DMA_SxCR_EN ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3176
bogdanm 0:9b334a45a8ff 3177 /******************** Bits definition for DMA_SxCNDTR register **************/
bogdanm 0:9b334a45a8ff 3178 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
bogdanm 0:9b334a45a8ff 3179 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3180 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3181 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3182 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3183 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3184 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3185 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3186 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3187 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3188 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3189 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3190 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3191 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3192 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3193 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3194 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3195
bogdanm 0:9b334a45a8ff 3196 /******************** Bits definition for DMA_SxFCR register ****************/
bogdanm 0:9b334a45a8ff 3197 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3198 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
bogdanm 0:9b334a45a8ff 3199 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3200 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3201 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3202 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3203 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 3204 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3205 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3206
bogdanm 0:9b334a45a8ff 3207 /******************** Bits definition for DMA_LISR register *****************/
bogdanm 0:9b334a45a8ff 3208 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3209 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3210 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3211 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3212 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3213 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3214 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3215 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3216 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3217 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3218 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3219 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3220 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3221 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3222 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3223 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3224 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3225 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3226 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3227 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3228
bogdanm 0:9b334a45a8ff 3229 /******************** Bits definition for DMA_HISR register *****************/
bogdanm 0:9b334a45a8ff 3230 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3231 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3232 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3233 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3234 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3235 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3236 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3237 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3238 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3239 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3240 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3241 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3242 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3243 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3244 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3245 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3246 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3247 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3248 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3249 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3250
bogdanm 0:9b334a45a8ff 3251 /******************** Bits definition for DMA_LIFCR register ****************/
bogdanm 0:9b334a45a8ff 3252 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3253 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3254 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3255 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3256 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3257 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3258 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3259 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3260 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3261 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3262 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3263 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3264 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3265 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3266 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3267 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3268 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3269 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3270 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3271 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3272
bogdanm 0:9b334a45a8ff 3273 /******************** Bits definition for DMA_HIFCR register ****************/
bogdanm 0:9b334a45a8ff 3274 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3275 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3276 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3277 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3278 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3279 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3280 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3281 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3282 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3283 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3284 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3285 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3286 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3287 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3288 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3289 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3290 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3291 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3292 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3293 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3294
bogdanm 0:9b334a45a8ff 3295
bogdanm 0:9b334a45a8ff 3296 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3297 /* */
bogdanm 0:9b334a45a8ff 3298 /* External Interrupt/Event Controller */
bogdanm 0:9b334a45a8ff 3299 /* */
bogdanm 0:9b334a45a8ff 3300 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3301 /******************* Bit definition for EXTI_IMR register *******************/
bogdanm 0:9b334a45a8ff 3302 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
bogdanm 0:9b334a45a8ff 3303 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
bogdanm 0:9b334a45a8ff 3304 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
bogdanm 0:9b334a45a8ff 3305 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
bogdanm 0:9b334a45a8ff 3306 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
bogdanm 0:9b334a45a8ff 3307 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
bogdanm 0:9b334a45a8ff 3308 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
bogdanm 0:9b334a45a8ff 3309 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
bogdanm 0:9b334a45a8ff 3310 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
bogdanm 0:9b334a45a8ff 3311 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
bogdanm 0:9b334a45a8ff 3312 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
bogdanm 0:9b334a45a8ff 3313 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
bogdanm 0:9b334a45a8ff 3314 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
bogdanm 0:9b334a45a8ff 3315 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
bogdanm 0:9b334a45a8ff 3316 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
bogdanm 0:9b334a45a8ff 3317 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
bogdanm 0:9b334a45a8ff 3318 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
bogdanm 0:9b334a45a8ff 3319 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
bogdanm 0:9b334a45a8ff 3320 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
bogdanm 0:9b334a45a8ff 3321 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
bogdanm 0:9b334a45a8ff 3322
bogdanm 0:9b334a45a8ff 3323 /******************* Bit definition for EXTI_EMR register *******************/
bogdanm 0:9b334a45a8ff 3324 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
bogdanm 0:9b334a45a8ff 3325 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
bogdanm 0:9b334a45a8ff 3326 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
bogdanm 0:9b334a45a8ff 3327 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
bogdanm 0:9b334a45a8ff 3328 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
bogdanm 0:9b334a45a8ff 3329 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
bogdanm 0:9b334a45a8ff 3330 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
bogdanm 0:9b334a45a8ff 3331 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
bogdanm 0:9b334a45a8ff 3332 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
bogdanm 0:9b334a45a8ff 3333 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
bogdanm 0:9b334a45a8ff 3334 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
bogdanm 0:9b334a45a8ff 3335 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
bogdanm 0:9b334a45a8ff 3336 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
bogdanm 0:9b334a45a8ff 3337 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
bogdanm 0:9b334a45a8ff 3338 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
bogdanm 0:9b334a45a8ff 3339 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
bogdanm 0:9b334a45a8ff 3340 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
bogdanm 0:9b334a45a8ff 3341 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
bogdanm 0:9b334a45a8ff 3342 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
bogdanm 0:9b334a45a8ff 3343 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
bogdanm 0:9b334a45a8ff 3344
bogdanm 0:9b334a45a8ff 3345 /****************** Bit definition for EXTI_RTSR register *******************/
bogdanm 0:9b334a45a8ff 3346 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
bogdanm 0:9b334a45a8ff 3347 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
bogdanm 0:9b334a45a8ff 3348 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
bogdanm 0:9b334a45a8ff 3349 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
bogdanm 0:9b334a45a8ff 3350 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
bogdanm 0:9b334a45a8ff 3351 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
bogdanm 0:9b334a45a8ff 3352 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
bogdanm 0:9b334a45a8ff 3353 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
bogdanm 0:9b334a45a8ff 3354 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
bogdanm 0:9b334a45a8ff 3355 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
bogdanm 0:9b334a45a8ff 3356 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
bogdanm 0:9b334a45a8ff 3357 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
bogdanm 0:9b334a45a8ff 3358 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
bogdanm 0:9b334a45a8ff 3359 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
bogdanm 0:9b334a45a8ff 3360 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
bogdanm 0:9b334a45a8ff 3361 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
bogdanm 0:9b334a45a8ff 3362 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
bogdanm 0:9b334a45a8ff 3363 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
bogdanm 0:9b334a45a8ff 3364 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
bogdanm 0:9b334a45a8ff 3365 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
bogdanm 0:9b334a45a8ff 3366
bogdanm 0:9b334a45a8ff 3367 /****************** Bit definition for EXTI_FTSR register *******************/
bogdanm 0:9b334a45a8ff 3368 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
bogdanm 0:9b334a45a8ff 3369 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
bogdanm 0:9b334a45a8ff 3370 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
bogdanm 0:9b334a45a8ff 3371 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
bogdanm 0:9b334a45a8ff 3372 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
bogdanm 0:9b334a45a8ff 3373 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
bogdanm 0:9b334a45a8ff 3374 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
bogdanm 0:9b334a45a8ff 3375 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
bogdanm 0:9b334a45a8ff 3376 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
bogdanm 0:9b334a45a8ff 3377 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
bogdanm 0:9b334a45a8ff 3378 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
bogdanm 0:9b334a45a8ff 3379 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
bogdanm 0:9b334a45a8ff 3380 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
bogdanm 0:9b334a45a8ff 3381 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
bogdanm 0:9b334a45a8ff 3382 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
bogdanm 0:9b334a45a8ff 3383 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
bogdanm 0:9b334a45a8ff 3384 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
bogdanm 0:9b334a45a8ff 3385 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
bogdanm 0:9b334a45a8ff 3386 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
bogdanm 0:9b334a45a8ff 3387 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
bogdanm 0:9b334a45a8ff 3388
bogdanm 0:9b334a45a8ff 3389 /****************** Bit definition for EXTI_SWIER register ******************/
bogdanm 0:9b334a45a8ff 3390 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
bogdanm 0:9b334a45a8ff 3391 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
bogdanm 0:9b334a45a8ff 3392 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
bogdanm 0:9b334a45a8ff 3393 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
bogdanm 0:9b334a45a8ff 3394 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
bogdanm 0:9b334a45a8ff 3395 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
bogdanm 0:9b334a45a8ff 3396 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
bogdanm 0:9b334a45a8ff 3397 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
bogdanm 0:9b334a45a8ff 3398 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
bogdanm 0:9b334a45a8ff 3399 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
bogdanm 0:9b334a45a8ff 3400 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
bogdanm 0:9b334a45a8ff 3401 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
bogdanm 0:9b334a45a8ff 3402 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
bogdanm 0:9b334a45a8ff 3403 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
bogdanm 0:9b334a45a8ff 3404 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
bogdanm 0:9b334a45a8ff 3405 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
bogdanm 0:9b334a45a8ff 3406 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
bogdanm 0:9b334a45a8ff 3407 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
bogdanm 0:9b334a45a8ff 3408 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
bogdanm 0:9b334a45a8ff 3409 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
bogdanm 0:9b334a45a8ff 3410
bogdanm 0:9b334a45a8ff 3411 /******************* Bit definition for EXTI_PR register ********************/
bogdanm 0:9b334a45a8ff 3412 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
bogdanm 0:9b334a45a8ff 3413 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
bogdanm 0:9b334a45a8ff 3414 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
bogdanm 0:9b334a45a8ff 3415 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
bogdanm 0:9b334a45a8ff 3416 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
bogdanm 0:9b334a45a8ff 3417 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
bogdanm 0:9b334a45a8ff 3418 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
bogdanm 0:9b334a45a8ff 3419 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
bogdanm 0:9b334a45a8ff 3420 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
bogdanm 0:9b334a45a8ff 3421 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
bogdanm 0:9b334a45a8ff 3422 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
bogdanm 0:9b334a45a8ff 3423 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
bogdanm 0:9b334a45a8ff 3424 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
bogdanm 0:9b334a45a8ff 3425 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
bogdanm 0:9b334a45a8ff 3426 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
bogdanm 0:9b334a45a8ff 3427 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
bogdanm 0:9b334a45a8ff 3428 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
bogdanm 0:9b334a45a8ff 3429 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
bogdanm 0:9b334a45a8ff 3430 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
bogdanm 0:9b334a45a8ff 3431 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
bogdanm 0:9b334a45a8ff 3432
bogdanm 0:9b334a45a8ff 3433 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3434 /* */
bogdanm 0:9b334a45a8ff 3435 /* FLASH */
bogdanm 0:9b334a45a8ff 3436 /* */
bogdanm 0:9b334a45a8ff 3437 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3438 /******************* Bits definition for FLASH_ACR register *****************/
bogdanm 0:9b334a45a8ff 3439 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 3440 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 3441 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3442 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3443 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 3444 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3445 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
bogdanm 0:9b334a45a8ff 3446 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
bogdanm 0:9b334a45a8ff 3447 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
bogdanm 0:9b334a45a8ff 3448
bogdanm 0:9b334a45a8ff 3449 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3450 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3451 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3452 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3453 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3454 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
bogdanm 0:9b334a45a8ff 3455 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
bogdanm 0:9b334a45a8ff 3456
bogdanm 0:9b334a45a8ff 3457 /******************* Bits definition for FLASH_SR register ******************/
bogdanm 0:9b334a45a8ff 3458 #define FLASH_SR_EOP ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3459 #define FLASH_SR_SOP ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3460 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3461 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3462 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3463 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3464 #define FLASH_SR_BSY ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3465
bogdanm 0:9b334a45a8ff 3466 /******************* Bits definition for FLASH_CR register ******************/
bogdanm 0:9b334a45a8ff 3467 #define FLASH_CR_PG ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3468 #define FLASH_CR_SER ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3469 #define FLASH_CR_MER ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3470 #define FLASH_CR_MER1 FLASH_CR_MER
bogdanm 0:9b334a45a8ff 3471 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
bogdanm 0:9b334a45a8ff 3472 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3473 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3474 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3475 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3476 #define FLASH_CR_SNB_4 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3477 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
bogdanm 0:9b334a45a8ff 3478 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3479 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3480 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3481 #define FLASH_CR_STRT ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3482 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3483 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 3484
bogdanm 0:9b334a45a8ff 3485 /******************* Bits definition for FLASH_OPTCR register ***************/
bogdanm 0:9b334a45a8ff 3486 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3487 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3488 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3489 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3490 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
bogdanm 0:9b334a45a8ff 3491 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3492 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3493 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3494 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
bogdanm 0:9b334a45a8ff 3495 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3496 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3497 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3498 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3499 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3500 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3501 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3502 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3503 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
bogdanm 0:9b334a45a8ff 3504 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3505 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3506 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3507 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3508 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3509 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3510 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3511 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3512 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3513 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3514 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3515 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3516
bogdanm 0:9b334a45a8ff 3517 /****************** Bits definition for FLASH_OPTCR1 register ***************/
bogdanm 0:9b334a45a8ff 3518 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
bogdanm 0:9b334a45a8ff 3519 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3520 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3521 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3522 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3523 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3524 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3525 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3526 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3527 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3528 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3529 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3530 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3531
bogdanm 0:9b334a45a8ff 3532
bogdanm 0:9b334a45a8ff 3533 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3534 /* */
bogdanm 0:9b334a45a8ff 3535 /* Flexible Static Memory Controller */
bogdanm 0:9b334a45a8ff 3536 /* */
bogdanm 0:9b334a45a8ff 3537 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3538 /****************** Bit definition for FSMC_BCR1 register *******************/
bogdanm 0:9b334a45a8ff 3539 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
bogdanm 0:9b334a45a8ff 3540 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
bogdanm 0:9b334a45a8ff 3541
bogdanm 0:9b334a45a8ff 3542 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
bogdanm 0:9b334a45a8ff 3543 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3544 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3545
bogdanm 0:9b334a45a8ff 3546 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
bogdanm 0:9b334a45a8ff 3547 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3548 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3549
bogdanm 0:9b334a45a8ff 3550 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
bogdanm 0:9b334a45a8ff 3551 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
bogdanm 0:9b334a45a8ff 3552 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
bogdanm 0:9b334a45a8ff 3553 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
bogdanm 0:9b334a45a8ff 3554 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
bogdanm 0:9b334a45a8ff 3555 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
bogdanm 0:9b334a45a8ff 3556 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
bogdanm 0:9b334a45a8ff 3557 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
bogdanm 0:9b334a45a8ff 3558 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
bogdanm 0:9b334a45a8ff 3559 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
bogdanm 0:9b334a45a8ff 3560
bogdanm 0:9b334a45a8ff 3561 /****************** Bit definition for FSMC_BCR2 register *******************/
bogdanm 0:9b334a45a8ff 3562 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
bogdanm 0:9b334a45a8ff 3563 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
bogdanm 0:9b334a45a8ff 3564
bogdanm 0:9b334a45a8ff 3565 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
bogdanm 0:9b334a45a8ff 3566 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3567 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3568
bogdanm 0:9b334a45a8ff 3569 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
bogdanm 0:9b334a45a8ff 3570 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3571 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3572
bogdanm 0:9b334a45a8ff 3573 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
bogdanm 0:9b334a45a8ff 3574 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
bogdanm 0:9b334a45a8ff 3575 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
bogdanm 0:9b334a45a8ff 3576 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
bogdanm 0:9b334a45a8ff 3577 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
bogdanm 0:9b334a45a8ff 3578 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
bogdanm 0:9b334a45a8ff 3579 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
bogdanm 0:9b334a45a8ff 3580 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
bogdanm 0:9b334a45a8ff 3581 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
bogdanm 0:9b334a45a8ff 3582 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
bogdanm 0:9b334a45a8ff 3583
bogdanm 0:9b334a45a8ff 3584 /****************** Bit definition for FSMC_BCR3 register *******************/
bogdanm 0:9b334a45a8ff 3585 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
bogdanm 0:9b334a45a8ff 3586 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
bogdanm 0:9b334a45a8ff 3587
bogdanm 0:9b334a45a8ff 3588 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
bogdanm 0:9b334a45a8ff 3589 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3590 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3591
bogdanm 0:9b334a45a8ff 3592 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
bogdanm 0:9b334a45a8ff 3593 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3594 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3595
bogdanm 0:9b334a45a8ff 3596 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
bogdanm 0:9b334a45a8ff 3597 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
bogdanm 0:9b334a45a8ff 3598 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
bogdanm 0:9b334a45a8ff 3599 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
bogdanm 0:9b334a45a8ff 3600 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
bogdanm 0:9b334a45a8ff 3601 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
bogdanm 0:9b334a45a8ff 3602 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
bogdanm 0:9b334a45a8ff 3603 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
bogdanm 0:9b334a45a8ff 3604 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
bogdanm 0:9b334a45a8ff 3605 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
bogdanm 0:9b334a45a8ff 3606
bogdanm 0:9b334a45a8ff 3607 /****************** Bit definition for FSMC_BCR4 register *******************/
bogdanm 0:9b334a45a8ff 3608 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
bogdanm 0:9b334a45a8ff 3609 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
bogdanm 0:9b334a45a8ff 3610
bogdanm 0:9b334a45a8ff 3611 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
bogdanm 0:9b334a45a8ff 3612 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3613 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3614
bogdanm 0:9b334a45a8ff 3615 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
bogdanm 0:9b334a45a8ff 3616 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3617 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3618
bogdanm 0:9b334a45a8ff 3619 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
bogdanm 0:9b334a45a8ff 3620 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
bogdanm 0:9b334a45a8ff 3621 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
bogdanm 0:9b334a45a8ff 3622 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
bogdanm 0:9b334a45a8ff 3623 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
bogdanm 0:9b334a45a8ff 3624 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
bogdanm 0:9b334a45a8ff 3625 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
bogdanm 0:9b334a45a8ff 3626 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
bogdanm 0:9b334a45a8ff 3627 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
bogdanm 0:9b334a45a8ff 3628 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
bogdanm 0:9b334a45a8ff 3629
bogdanm 0:9b334a45a8ff 3630 /****************** Bit definition for FSMC_BTR1 register ******************/
bogdanm 0:9b334a45a8ff 3631 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 0:9b334a45a8ff 3632 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3633 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3634 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3635 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3636
bogdanm 0:9b334a45a8ff 3637 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 0:9b334a45a8ff 3638 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3639 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3640 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3641 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3642
bogdanm 0:9b334a45a8ff 3643 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 0:9b334a45a8ff 3644 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3645 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3646 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3647 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3648
bogdanm 0:9b334a45a8ff 3649 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 0:9b334a45a8ff 3650 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3651 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3652 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3653 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3654
bogdanm 0:9b334a45a8ff 3655 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 0:9b334a45a8ff 3656 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3657 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3658 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3659 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3660
bogdanm 0:9b334a45a8ff 3661 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 0:9b334a45a8ff 3662 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3663 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3664 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3665 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3666
bogdanm 0:9b334a45a8ff 3667 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 0:9b334a45a8ff 3668 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3669 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3670
bogdanm 0:9b334a45a8ff 3671 /****************** Bit definition for FSMC_BTR2 register *******************/
bogdanm 0:9b334a45a8ff 3672 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 0:9b334a45a8ff 3673 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3674 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3675 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3676 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3677
bogdanm 0:9b334a45a8ff 3678 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 0:9b334a45a8ff 3679 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3680 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3681 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3682 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3683
bogdanm 0:9b334a45a8ff 3684 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 0:9b334a45a8ff 3685 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3686 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3687 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3688 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3689
bogdanm 0:9b334a45a8ff 3690 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 0:9b334a45a8ff 3691 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3692 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3693 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3694 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3695
bogdanm 0:9b334a45a8ff 3696 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 0:9b334a45a8ff 3697 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3698 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3699 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3700 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3701
bogdanm 0:9b334a45a8ff 3702 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 0:9b334a45a8ff 3703 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3704 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3705 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3706 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3707
bogdanm 0:9b334a45a8ff 3708 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 0:9b334a45a8ff 3709 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3710 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3711
bogdanm 0:9b334a45a8ff 3712 /******************* Bit definition for FSMC_BTR3 register *******************/
bogdanm 0:9b334a45a8ff 3713 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 0:9b334a45a8ff 3714 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3715 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3716 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3717 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3718
bogdanm 0:9b334a45a8ff 3719 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 0:9b334a45a8ff 3720 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3721 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3722 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3723 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3724
bogdanm 0:9b334a45a8ff 3725 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 0:9b334a45a8ff 3726 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3727 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3728 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3729 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3730
bogdanm 0:9b334a45a8ff 3731 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 0:9b334a45a8ff 3732 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3733 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3734 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3735 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3736
bogdanm 0:9b334a45a8ff 3737 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 0:9b334a45a8ff 3738 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3739 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3740 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3741 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3742
bogdanm 0:9b334a45a8ff 3743 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 0:9b334a45a8ff 3744 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3745 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3746 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3747 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3748
bogdanm 0:9b334a45a8ff 3749 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 0:9b334a45a8ff 3750 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3751 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3752
bogdanm 0:9b334a45a8ff 3753 /****************** Bit definition for FSMC_BTR4 register *******************/
bogdanm 0:9b334a45a8ff 3754 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 0:9b334a45a8ff 3755 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3756 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3757 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3758 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3759
bogdanm 0:9b334a45a8ff 3760 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 0:9b334a45a8ff 3761 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3762 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3763 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3764 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3765
bogdanm 0:9b334a45a8ff 3766 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 0:9b334a45a8ff 3767 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3768 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3769 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3770 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3771
bogdanm 0:9b334a45a8ff 3772 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
bogdanm 0:9b334a45a8ff 3773 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3774 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3775 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3776 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3777
bogdanm 0:9b334a45a8ff 3778 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 0:9b334a45a8ff 3779 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3780 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3781 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3782 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3783
bogdanm 0:9b334a45a8ff 3784 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 0:9b334a45a8ff 3785 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3786 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3787 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3788 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3789
bogdanm 0:9b334a45a8ff 3790 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 0:9b334a45a8ff 3791 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3792 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3793
bogdanm 0:9b334a45a8ff 3794 /****************** Bit definition for FSMC_BWTR1 register ******************/
bogdanm 0:9b334a45a8ff 3795 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 0:9b334a45a8ff 3796 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3797 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3798 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3799 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3800
bogdanm 0:9b334a45a8ff 3801 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 0:9b334a45a8ff 3802 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3803 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3804 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3805 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3806
bogdanm 0:9b334a45a8ff 3807 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 0:9b334a45a8ff 3808 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3809 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3810 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3811 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3812
bogdanm 0:9b334a45a8ff 3813 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 0:9b334a45a8ff 3814 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3815 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3816 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3817 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3818
bogdanm 0:9b334a45a8ff 3819 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 0:9b334a45a8ff 3820 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3821 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3822 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3823 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3824
bogdanm 0:9b334a45a8ff 3825 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 0:9b334a45a8ff 3826 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3827 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3828
bogdanm 0:9b334a45a8ff 3829 /****************** Bit definition for FSMC_BWTR2 register ******************/
bogdanm 0:9b334a45a8ff 3830 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 0:9b334a45a8ff 3831 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3832 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3833 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3834 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3835
bogdanm 0:9b334a45a8ff 3836 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 0:9b334a45a8ff 3837 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3838 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3839 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3840 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3841
bogdanm 0:9b334a45a8ff 3842 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 0:9b334a45a8ff 3843 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3844 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3845 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3846 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3847
bogdanm 0:9b334a45a8ff 3848 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 0:9b334a45a8ff 3849 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3850 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
bogdanm 0:9b334a45a8ff 3851 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3852 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3853
bogdanm 0:9b334a45a8ff 3854 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 0:9b334a45a8ff 3855 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3856 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3857 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3858 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3859
bogdanm 0:9b334a45a8ff 3860 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 0:9b334a45a8ff 3861 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3862 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3863
bogdanm 0:9b334a45a8ff 3864 /****************** Bit definition for FSMC_BWTR3 register ******************/
bogdanm 0:9b334a45a8ff 3865 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 0:9b334a45a8ff 3866 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3867 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3868 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3869 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3870
bogdanm 0:9b334a45a8ff 3871 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 0:9b334a45a8ff 3872 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3873 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3874 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3875 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3876
bogdanm 0:9b334a45a8ff 3877 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 0:9b334a45a8ff 3878 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3879 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3880 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3881 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3882
bogdanm 0:9b334a45a8ff 3883 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 0:9b334a45a8ff 3884 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3885 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3886 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3887 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3888
bogdanm 0:9b334a45a8ff 3889 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 0:9b334a45a8ff 3890 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3891 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3892 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3893 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3894
bogdanm 0:9b334a45a8ff 3895 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 0:9b334a45a8ff 3896 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3897 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3898
bogdanm 0:9b334a45a8ff 3899 /****************** Bit definition for FSMC_BWTR4 register ******************/
bogdanm 0:9b334a45a8ff 3900 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
bogdanm 0:9b334a45a8ff 3901 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3902 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3903 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3904 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3905
bogdanm 0:9b334a45a8ff 3906 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
bogdanm 0:9b334a45a8ff 3907 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3908 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3909 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3910 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3911
bogdanm 0:9b334a45a8ff 3912 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
bogdanm 0:9b334a45a8ff 3913 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3914 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3915 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3916 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3917
bogdanm 0:9b334a45a8ff 3918 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
bogdanm 0:9b334a45a8ff 3919 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3920 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3921 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3922 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3923
bogdanm 0:9b334a45a8ff 3924 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
bogdanm 0:9b334a45a8ff 3925 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3926 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3927 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3928 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3929
bogdanm 0:9b334a45a8ff 3930 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
bogdanm 0:9b334a45a8ff 3931 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3932 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3933
bogdanm 0:9b334a45a8ff 3934 /****************** Bit definition for FSMC_PCR2 register *******************/
bogdanm 0:9b334a45a8ff 3935 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
bogdanm 0:9b334a45a8ff 3936 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
bogdanm 0:9b334a45a8ff 3937 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
bogdanm 0:9b334a45a8ff 3938
bogdanm 0:9b334a45a8ff 3939 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
bogdanm 0:9b334a45a8ff 3940 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3941 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3942
bogdanm 0:9b334a45a8ff 3943 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
bogdanm 0:9b334a45a8ff 3944
bogdanm 0:9b334a45a8ff 3945 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
bogdanm 0:9b334a45a8ff 3946 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3947 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3948 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3949 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3950
bogdanm 0:9b334a45a8ff 3951 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
bogdanm 0:9b334a45a8ff 3952 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3953 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3954 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3955 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3956
bogdanm 0:9b334a45a8ff 3957 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
bogdanm 0:9b334a45a8ff 3958 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3959 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3960 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3961
bogdanm 0:9b334a45a8ff 3962 /****************** Bit definition for FSMC_PCR3 register *******************/
bogdanm 0:9b334a45a8ff 3963 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
bogdanm 0:9b334a45a8ff 3964 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
bogdanm 0:9b334a45a8ff 3965 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
bogdanm 0:9b334a45a8ff 3966
bogdanm 0:9b334a45a8ff 3967 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
bogdanm 0:9b334a45a8ff 3968 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3969 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3970
bogdanm 0:9b334a45a8ff 3971 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
bogdanm 0:9b334a45a8ff 3972
bogdanm 0:9b334a45a8ff 3973 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
bogdanm 0:9b334a45a8ff 3974 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3975 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3976 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3977 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3978
bogdanm 0:9b334a45a8ff 3979 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
bogdanm 0:9b334a45a8ff 3980 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3981 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3982 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3983 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3984
bogdanm 0:9b334a45a8ff 3985 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
bogdanm 0:9b334a45a8ff 3986 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3987 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3988 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3989
bogdanm 0:9b334a45a8ff 3990 /****************** Bit definition for FSMC_PCR4 register *******************/
bogdanm 0:9b334a45a8ff 3991 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
bogdanm 0:9b334a45a8ff 3992 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
bogdanm 0:9b334a45a8ff 3993 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
bogdanm 0:9b334a45a8ff 3994
bogdanm 0:9b334a45a8ff 3995 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
bogdanm 0:9b334a45a8ff 3996 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3997 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3998
bogdanm 0:9b334a45a8ff 3999 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
bogdanm 0:9b334a45a8ff 4000
bogdanm 0:9b334a45a8ff 4001 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
bogdanm 0:9b334a45a8ff 4002 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4003 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4004 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4005 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4006
bogdanm 0:9b334a45a8ff 4007 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
bogdanm 0:9b334a45a8ff 4008 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4009 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4010 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4011 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4012
bogdanm 0:9b334a45a8ff 4013 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
bogdanm 0:9b334a45a8ff 4014 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4015 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4016 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4017
bogdanm 0:9b334a45a8ff 4018 /******************* Bit definition for FSMC_SR2 register *******************/
bogdanm 0:9b334a45a8ff 4019 #define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
bogdanm 0:9b334a45a8ff 4020 #define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
bogdanm 0:9b334a45a8ff 4021 #define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
bogdanm 0:9b334a45a8ff 4022 #define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
bogdanm 0:9b334a45a8ff 4023 #define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
bogdanm 0:9b334a45a8ff 4024 #define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
bogdanm 0:9b334a45a8ff 4025 #define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
bogdanm 0:9b334a45a8ff 4026
bogdanm 0:9b334a45a8ff 4027 /******************* Bit definition for FSMC_SR3 register *******************/
bogdanm 0:9b334a45a8ff 4028 #define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
bogdanm 0:9b334a45a8ff 4029 #define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
bogdanm 0:9b334a45a8ff 4030 #define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
bogdanm 0:9b334a45a8ff 4031 #define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
bogdanm 0:9b334a45a8ff 4032 #define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
bogdanm 0:9b334a45a8ff 4033 #define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
bogdanm 0:9b334a45a8ff 4034 #define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
bogdanm 0:9b334a45a8ff 4035
bogdanm 0:9b334a45a8ff 4036 /******************* Bit definition for FSMC_SR4 register *******************/
bogdanm 0:9b334a45a8ff 4037 #define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
bogdanm 0:9b334a45a8ff 4038 #define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
bogdanm 0:9b334a45a8ff 4039 #define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
bogdanm 0:9b334a45a8ff 4040 #define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
bogdanm 0:9b334a45a8ff 4041 #define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
bogdanm 0:9b334a45a8ff 4042 #define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
bogdanm 0:9b334a45a8ff 4043 #define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
bogdanm 0:9b334a45a8ff 4044
bogdanm 0:9b334a45a8ff 4045 /****************** Bit definition for FSMC_PMEM2 register ******************/
bogdanm 0:9b334a45a8ff 4046 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
bogdanm 0:9b334a45a8ff 4047 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4048 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4049 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4050 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4051 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4052 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4053 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4054 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4055
bogdanm 0:9b334a45a8ff 4056 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
bogdanm 0:9b334a45a8ff 4057 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4058 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4059 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4060 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4061 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4062 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4063 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4064 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4065
bogdanm 0:9b334a45a8ff 4066 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
bogdanm 0:9b334a45a8ff 4067 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4068 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4069 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4070 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4071 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4072 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4073 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4074 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4075
bogdanm 0:9b334a45a8ff 4076 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
bogdanm 0:9b334a45a8ff 4077 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4078 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4079 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4080 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4081 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4082 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4083 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4084 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4085
bogdanm 0:9b334a45a8ff 4086 /****************** Bit definition for FSMC_PMEM3 register ******************/
bogdanm 0:9b334a45a8ff 4087 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
bogdanm 0:9b334a45a8ff 4088 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4089 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4090 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4091 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4092 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4093 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4094 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4095 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4096
bogdanm 0:9b334a45a8ff 4097 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
bogdanm 0:9b334a45a8ff 4098 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4099 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4100 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4101 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4102 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4103 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4104 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4105 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4106
bogdanm 0:9b334a45a8ff 4107 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
bogdanm 0:9b334a45a8ff 4108 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4109 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4110 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4111 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4112 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4113 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4114 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4115 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4116
bogdanm 0:9b334a45a8ff 4117 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
bogdanm 0:9b334a45a8ff 4118 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4119 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4120 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4121 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4122 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4123 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4124 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4125 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4126
bogdanm 0:9b334a45a8ff 4127 /****************** Bit definition for FSMC_PMEM4 register ******************/
bogdanm 0:9b334a45a8ff 4128 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
bogdanm 0:9b334a45a8ff 4129 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4130 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4131 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4132 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4133 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4134 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4135 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4136 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4137
bogdanm 0:9b334a45a8ff 4138 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
bogdanm 0:9b334a45a8ff 4139 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4140 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4141 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4142 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4143 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4144 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4145 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4146 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4147
bogdanm 0:9b334a45a8ff 4148 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
bogdanm 0:9b334a45a8ff 4149 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4150 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4151 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4152 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4153 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4154 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4155 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4156 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4157
bogdanm 0:9b334a45a8ff 4158 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
bogdanm 0:9b334a45a8ff 4159 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4160 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4161 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4162 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4163 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4164 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4165 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4166 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4167
bogdanm 0:9b334a45a8ff 4168 /****************** Bit definition for FSMC_PATT2 register ******************/
bogdanm 0:9b334a45a8ff 4169 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
bogdanm 0:9b334a45a8ff 4170 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4171 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4172 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4173 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4174 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4175 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4176 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4177 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4178
bogdanm 0:9b334a45a8ff 4179 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
bogdanm 0:9b334a45a8ff 4180 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4181 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4182 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4183 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4184 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4185 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4186 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4187 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4188
bogdanm 0:9b334a45a8ff 4189 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
bogdanm 0:9b334a45a8ff 4190 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4191 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4192 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4193 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4194 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4195 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4196 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4197 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4198
bogdanm 0:9b334a45a8ff 4199 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
bogdanm 0:9b334a45a8ff 4200 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4201 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4202 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4203 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4204 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4205 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4206 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4207 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4208
bogdanm 0:9b334a45a8ff 4209 /****************** Bit definition for FSMC_PATT3 register ******************/
bogdanm 0:9b334a45a8ff 4210 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
bogdanm 0:9b334a45a8ff 4211 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4212 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4213 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4214 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4215 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4216 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4217 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4218 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4219
bogdanm 0:9b334a45a8ff 4220 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
bogdanm 0:9b334a45a8ff 4221 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4222 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4223 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4224 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4225 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4226 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4227 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4228 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4229
bogdanm 0:9b334a45a8ff 4230 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
bogdanm 0:9b334a45a8ff 4231 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4232 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4233 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4234 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4235 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4236 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4237 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4238 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4239
bogdanm 0:9b334a45a8ff 4240 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
bogdanm 0:9b334a45a8ff 4241 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4242 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4243 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4244 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4245 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4246 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4247 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4248 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4249
bogdanm 0:9b334a45a8ff 4250 /****************** Bit definition for FSMC_PATT4 register ******************/
bogdanm 0:9b334a45a8ff 4251 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
bogdanm 0:9b334a45a8ff 4252 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4253 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4254 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4255 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4256 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4257 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4258 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4259 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4260
bogdanm 0:9b334a45a8ff 4261 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
bogdanm 0:9b334a45a8ff 4262 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4263 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4264 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4265 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4266 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4267 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4268 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4269 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4270
bogdanm 0:9b334a45a8ff 4271 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
bogdanm 0:9b334a45a8ff 4272 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4273 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4274 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4275 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4276 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4277 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4278 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4279 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4280
bogdanm 0:9b334a45a8ff 4281 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
bogdanm 0:9b334a45a8ff 4282 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4283 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4284 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4285 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4286 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4287 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4288 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4289 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4290
bogdanm 0:9b334a45a8ff 4291 /****************** Bit definition for FSMC_PIO4 register *******************/
bogdanm 0:9b334a45a8ff 4292 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
bogdanm 0:9b334a45a8ff 4293 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4294 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4295 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4296 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4297 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4298 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4299 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4300 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4301
bogdanm 0:9b334a45a8ff 4302 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
bogdanm 0:9b334a45a8ff 4303 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4304 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4305 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4306 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4307 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4308 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4309 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4310 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4311
bogdanm 0:9b334a45a8ff 4312 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
bogdanm 0:9b334a45a8ff 4313 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4314 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4315 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4316 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4317 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4318 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4319 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4320 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4321
bogdanm 0:9b334a45a8ff 4322 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
bogdanm 0:9b334a45a8ff 4323 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4324 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4325 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4326 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4327 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4328 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4329 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4330 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4331
bogdanm 0:9b334a45a8ff 4332 /****************** Bit definition for FSMC_ECCR2 register ******************/
bogdanm 0:9b334a45a8ff 4333 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
bogdanm 0:9b334a45a8ff 4334
bogdanm 0:9b334a45a8ff 4335 /****************** Bit definition for FSMC_ECCR3 register ******************/
bogdanm 0:9b334a45a8ff 4336 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
bogdanm 0:9b334a45a8ff 4337
bogdanm 0:9b334a45a8ff 4338
bogdanm 0:9b334a45a8ff 4339 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4340 /* */
bogdanm 0:9b334a45a8ff 4341 /* General Purpose I/O */
bogdanm 0:9b334a45a8ff 4342 /* */
bogdanm 0:9b334a45a8ff 4343 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4344 /****************** Bits definition for GPIO_MODER register *****************/
bogdanm 0:9b334a45a8ff 4345 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 4346 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4347 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4348
bogdanm 0:9b334a45a8ff 4349 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
bogdanm 0:9b334a45a8ff 4350 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4351 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4352
bogdanm 0:9b334a45a8ff 4353 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 4354 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4355 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4356
bogdanm 0:9b334a45a8ff 4357 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 4358 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 4359 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 4360
bogdanm 0:9b334a45a8ff 4361 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
bogdanm 0:9b334a45a8ff 4362 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4363 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 4364
bogdanm 0:9b334a45a8ff 4365 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
bogdanm 0:9b334a45a8ff 4366 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 4367 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 4368
bogdanm 0:9b334a45a8ff 4369 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
bogdanm 0:9b334a45a8ff 4370 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 4371 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4372
bogdanm 0:9b334a45a8ff 4373 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
bogdanm 0:9b334a45a8ff 4374 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 4375 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 4376
bogdanm 0:9b334a45a8ff 4377 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
bogdanm 0:9b334a45a8ff 4378 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 4379 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 4380
bogdanm 0:9b334a45a8ff 4381 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
bogdanm 0:9b334a45a8ff 4382 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 4383 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 4384
bogdanm 0:9b334a45a8ff 4385 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 4386 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 4387 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 4388
bogdanm 0:9b334a45a8ff 4389 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
bogdanm 0:9b334a45a8ff 4390 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 4391 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 4392
bogdanm 0:9b334a45a8ff 4393 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
bogdanm 0:9b334a45a8ff 4394 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 4395 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 4396
bogdanm 0:9b334a45a8ff 4397 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
bogdanm 0:9b334a45a8ff 4398 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 4399 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 4400
bogdanm 0:9b334a45a8ff 4401 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 4402 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 4403 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 4404
bogdanm 0:9b334a45a8ff 4405 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
bogdanm 0:9b334a45a8ff 4406 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 4407 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 4408
bogdanm 0:9b334a45a8ff 4409 /****************** Bits definition for GPIO_OTYPER register ****************/
bogdanm 0:9b334a45a8ff 4410 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4411 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4412 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4413 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4414 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4415 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4416 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 4417 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 4418 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4419 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 4420 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 4421 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 4422 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 4423 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4424 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 4425 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 4426
bogdanm 0:9b334a45a8ff 4427 /****************** Bits definition for GPIO_OSPEEDR register ***************/
bogdanm 0:9b334a45a8ff 4428 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 4429 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4430 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4431
bogdanm 0:9b334a45a8ff 4432 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
bogdanm 0:9b334a45a8ff 4433 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4434 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4435
bogdanm 0:9b334a45a8ff 4436 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 4437 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4438 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4439
bogdanm 0:9b334a45a8ff 4440 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 4441 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 4442 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 4443
bogdanm 0:9b334a45a8ff 4444 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
bogdanm 0:9b334a45a8ff 4445 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4446 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 4447
bogdanm 0:9b334a45a8ff 4448 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
bogdanm 0:9b334a45a8ff 4449 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 4450 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 4451
bogdanm 0:9b334a45a8ff 4452 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
bogdanm 0:9b334a45a8ff 4453 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 4454 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4455
bogdanm 0:9b334a45a8ff 4456 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
bogdanm 0:9b334a45a8ff 4457 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 4458 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 4459
bogdanm 0:9b334a45a8ff 4460 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
bogdanm 0:9b334a45a8ff 4461 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 4462 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 4463
bogdanm 0:9b334a45a8ff 4464 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
bogdanm 0:9b334a45a8ff 4465 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 4466 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 4467
bogdanm 0:9b334a45a8ff 4468 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 4469 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 4470 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 4471
bogdanm 0:9b334a45a8ff 4472 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
bogdanm 0:9b334a45a8ff 4473 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 4474 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 4475
bogdanm 0:9b334a45a8ff 4476 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
bogdanm 0:9b334a45a8ff 4477 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 4478 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 4479
bogdanm 0:9b334a45a8ff 4480 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
bogdanm 0:9b334a45a8ff 4481 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 4482 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 4483
bogdanm 0:9b334a45a8ff 4484 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 4485 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 4486 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 4487
bogdanm 0:9b334a45a8ff 4488 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
bogdanm 0:9b334a45a8ff 4489 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 4490 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 4491
bogdanm 0:9b334a45a8ff 4492 /****************** Bits definition for GPIO_PUPDR register *****************/
bogdanm 0:9b334a45a8ff 4493 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 4494 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4495 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4496
bogdanm 0:9b334a45a8ff 4497 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
bogdanm 0:9b334a45a8ff 4498 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4499 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4500
bogdanm 0:9b334a45a8ff 4501 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 4502 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4503 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4504
bogdanm 0:9b334a45a8ff 4505 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 4506 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 4507 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 4508
bogdanm 0:9b334a45a8ff 4509 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
bogdanm 0:9b334a45a8ff 4510 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4511 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 4512
bogdanm 0:9b334a45a8ff 4513 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
bogdanm 0:9b334a45a8ff 4514 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 4515 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 4516
bogdanm 0:9b334a45a8ff 4517 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
bogdanm 0:9b334a45a8ff 4518 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 4519 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4520
bogdanm 0:9b334a45a8ff 4521 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
bogdanm 0:9b334a45a8ff 4522 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 4523 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 4524
bogdanm 0:9b334a45a8ff 4525 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
bogdanm 0:9b334a45a8ff 4526 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 4527 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 4528
bogdanm 0:9b334a45a8ff 4529 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
bogdanm 0:9b334a45a8ff 4530 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 4531 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 4532
bogdanm 0:9b334a45a8ff 4533 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 4534 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 4535 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 4536
bogdanm 0:9b334a45a8ff 4537 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
bogdanm 0:9b334a45a8ff 4538 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 4539 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 4540
bogdanm 0:9b334a45a8ff 4541 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
bogdanm 0:9b334a45a8ff 4542 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 4543 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 4544
bogdanm 0:9b334a45a8ff 4545 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
bogdanm 0:9b334a45a8ff 4546 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 4547 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 4548
bogdanm 0:9b334a45a8ff 4549 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 4550 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 4551 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 4552
bogdanm 0:9b334a45a8ff 4553 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
bogdanm 0:9b334a45a8ff 4554 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 4555 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 4556
bogdanm 0:9b334a45a8ff 4557 /****************** Bits definition for GPIO_IDR register *******************/
bogdanm 0:9b334a45a8ff 4558 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4559 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4560 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4561 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4562 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4563 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4564 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 4565 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 4566 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4567 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 4568 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 4569 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 4570 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 4571 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4572 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 4573 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 4574 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 4575 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
bogdanm 0:9b334a45a8ff 4576 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
bogdanm 0:9b334a45a8ff 4577 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
bogdanm 0:9b334a45a8ff 4578 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
bogdanm 0:9b334a45a8ff 4579 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
bogdanm 0:9b334a45a8ff 4580 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
bogdanm 0:9b334a45a8ff 4581 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
bogdanm 0:9b334a45a8ff 4582 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
bogdanm 0:9b334a45a8ff 4583 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
bogdanm 0:9b334a45a8ff 4584 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
bogdanm 0:9b334a45a8ff 4585 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
bogdanm 0:9b334a45a8ff 4586 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
bogdanm 0:9b334a45a8ff 4587 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
bogdanm 0:9b334a45a8ff 4588 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
bogdanm 0:9b334a45a8ff 4589 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
bogdanm 0:9b334a45a8ff 4590 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
bogdanm 0:9b334a45a8ff 4591
bogdanm 0:9b334a45a8ff 4592 /****************** Bits definition for GPIO_ODR register *******************/
bogdanm 0:9b334a45a8ff 4593 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4594 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4595 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4596 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4597 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4598 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4599 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 4600 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 4601 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4602 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 4603 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 4604 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 4605 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 4606 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4607 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 4608 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 4609 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 4610 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
bogdanm 0:9b334a45a8ff 4611 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
bogdanm 0:9b334a45a8ff 4612 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
bogdanm 0:9b334a45a8ff 4613 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
bogdanm 0:9b334a45a8ff 4614 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
bogdanm 0:9b334a45a8ff 4615 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
bogdanm 0:9b334a45a8ff 4616 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
bogdanm 0:9b334a45a8ff 4617 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
bogdanm 0:9b334a45a8ff 4618 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
bogdanm 0:9b334a45a8ff 4619 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
bogdanm 0:9b334a45a8ff 4620 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
bogdanm 0:9b334a45a8ff 4621 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
bogdanm 0:9b334a45a8ff 4622 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
bogdanm 0:9b334a45a8ff 4623 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
bogdanm 0:9b334a45a8ff 4624 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
bogdanm 0:9b334a45a8ff 4625 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
bogdanm 0:9b334a45a8ff 4626
bogdanm 0:9b334a45a8ff 4627 /****************** Bits definition for GPIO_BSRR register ******************/
bogdanm 0:9b334a45a8ff 4628 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4629 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4630 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4631 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4632 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4633 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4634 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 4635 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 4636 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4637 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 4638 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 4639 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 4640 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 4641 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4642 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 4643 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 4644 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 4645 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 4646 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 4647 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 4648 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 4649 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 4650 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 4651 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 4652 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 4653 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 4654 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 4655 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 4656 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 4657 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 4658 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 4659 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 4660
bogdanm 0:9b334a45a8ff 4661 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4662 /* */
bogdanm 0:9b334a45a8ff 4663 /* HASH */
bogdanm 0:9b334a45a8ff 4664 /* */
bogdanm 0:9b334a45a8ff 4665 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4666 /****************** Bits definition for HASH_CR register ********************/
bogdanm 0:9b334a45a8ff 4667 #define HASH_CR_INIT ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4668 #define HASH_CR_DMAE ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4669 #define HASH_CR_DATATYPE ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 4670 #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4671 #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4672 #define HASH_CR_MODE ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 4673 #define HASH_CR_ALGO ((uint32_t)0x00040080)
bogdanm 0:9b334a45a8ff 4674 #define HASH_CR_ALGO_0 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 4675 #define HASH_CR_ALGO_1 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 4676 #define HASH_CR_NBW ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 4677 #define HASH_CR_NBW_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4678 #define HASH_CR_NBW_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 4679 #define HASH_CR_NBW_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 4680 #define HASH_CR_NBW_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 4681 #define HASH_CR_DINNE ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 4682 #define HASH_CR_MDMAT ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4683 #define HASH_CR_LKEY ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 4684
bogdanm 0:9b334a45a8ff 4685 /****************** Bits definition for HASH_STR register *******************/
bogdanm 0:9b334a45a8ff 4686 #define HASH_STR_NBW ((uint32_t)0x0000001F)
bogdanm 0:9b334a45a8ff 4687 #define HASH_STR_NBW_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4688 #define HASH_STR_NBW_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4689 #define HASH_STR_NBW_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4690 #define HASH_STR_NBW_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4691 #define HASH_STR_NBW_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4692 #define HASH_STR_DCAL ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4693
bogdanm 0:9b334a45a8ff 4694 /****************** Bits definition for HASH_IMR register *******************/
bogdanm 0:9b334a45a8ff 4695 #define HASH_IMR_DINIM ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4696 #define HASH_IMR_DCIM ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4697
bogdanm 0:9b334a45a8ff 4698 /****************** Bits definition for HASH_SR register ********************/
bogdanm 0:9b334a45a8ff 4699 #define HASH_SR_DINIS ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4700 #define HASH_SR_DCIS ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4701 #define HASH_SR_DMAS ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4702 #define HASH_SR_BUSY ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4703
bogdanm 0:9b334a45a8ff 4704 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4705 /* */
bogdanm 0:9b334a45a8ff 4706 /* Inter-integrated Circuit Interface */
bogdanm 0:9b334a45a8ff 4707 /* */
bogdanm 0:9b334a45a8ff 4708 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4709 /******************* Bit definition for I2C_CR1 register ********************/
bogdanm 0:9b334a45a8ff 4710 #define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
bogdanm 0:9b334a45a8ff 4711 #define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
bogdanm 0:9b334a45a8ff 4712 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
bogdanm 0:9b334a45a8ff 4713 #define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
bogdanm 0:9b334a45a8ff 4714 #define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
bogdanm 0:9b334a45a8ff 4715 #define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
bogdanm 0:9b334a45a8ff 4716 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
bogdanm 0:9b334a45a8ff 4717 #define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
bogdanm 0:9b334a45a8ff 4718 #define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
bogdanm 0:9b334a45a8ff 4719 #define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
bogdanm 0:9b334a45a8ff 4720 #define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
bogdanm 0:9b334a45a8ff 4721 #define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
bogdanm 0:9b334a45a8ff 4722 #define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
bogdanm 0:9b334a45a8ff 4723 #define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
bogdanm 0:9b334a45a8ff 4724
bogdanm 0:9b334a45a8ff 4725 /******************* Bit definition for I2C_CR2 register ********************/
bogdanm 0:9b334a45a8ff 4726 #define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
bogdanm 0:9b334a45a8ff 4727 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4728 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4729 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4730 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4731 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4732 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4733
bogdanm 0:9b334a45a8ff 4734 #define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 4735 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
bogdanm 0:9b334a45a8ff 4736 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
bogdanm 0:9b334a45a8ff 4737 #define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
bogdanm 0:9b334a45a8ff 4738 #define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
bogdanm 0:9b334a45a8ff 4739
bogdanm 0:9b334a45a8ff 4740 /******************* Bit definition for I2C_OAR1 register *******************/
bogdanm 0:9b334a45a8ff 4741 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
bogdanm 0:9b334a45a8ff 4742 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
bogdanm 0:9b334a45a8ff 4743
bogdanm 0:9b334a45a8ff 4744 #define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4745 #define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4746 #define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4747 #define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4748 #define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4749 #define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4750 #define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4751 #define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4752 #define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
bogdanm 0:9b334a45a8ff 4753 #define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
bogdanm 0:9b334a45a8ff 4754
bogdanm 0:9b334a45a8ff 4755 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
bogdanm 0:9b334a45a8ff 4756
bogdanm 0:9b334a45a8ff 4757 /******************* Bit definition for I2C_OAR2 register *******************/
bogdanm 0:9b334a45a8ff 4758 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
bogdanm 0:9b334a45a8ff 4759 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
bogdanm 0:9b334a45a8ff 4760
bogdanm 0:9b334a45a8ff 4761 /******************** Bit definition for I2C_DR register ********************/
bogdanm 0:9b334a45a8ff 4762 #define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
bogdanm 0:9b334a45a8ff 4763
bogdanm 0:9b334a45a8ff 4764 /******************* Bit definition for I2C_SR1 register ********************/
bogdanm 0:9b334a45a8ff 4765 #define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
bogdanm 0:9b334a45a8ff 4766 #define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
bogdanm 0:9b334a45a8ff 4767 #define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
bogdanm 0:9b334a45a8ff 4768 #define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
bogdanm 0:9b334a45a8ff 4769 #define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
bogdanm 0:9b334a45a8ff 4770 #define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
bogdanm 0:9b334a45a8ff 4771 #define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
bogdanm 0:9b334a45a8ff 4772 #define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
bogdanm 0:9b334a45a8ff 4773 #define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
bogdanm 0:9b334a45a8ff 4774 #define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
bogdanm 0:9b334a45a8ff 4775 #define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
bogdanm 0:9b334a45a8ff 4776 #define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
bogdanm 0:9b334a45a8ff 4777 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
bogdanm 0:9b334a45a8ff 4778 #define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
bogdanm 0:9b334a45a8ff 4779
bogdanm 0:9b334a45a8ff 4780 /******************* Bit definition for I2C_SR2 register ********************/
bogdanm 0:9b334a45a8ff 4781 #define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
bogdanm 0:9b334a45a8ff 4782 #define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
bogdanm 0:9b334a45a8ff 4783 #define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
bogdanm 0:9b334a45a8ff 4784 #define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
bogdanm 0:9b334a45a8ff 4785 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
bogdanm 0:9b334a45a8ff 4786 #define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
bogdanm 0:9b334a45a8ff 4787 #define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
bogdanm 0:9b334a45a8ff 4788 #define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
bogdanm 0:9b334a45a8ff 4789
bogdanm 0:9b334a45a8ff 4790 /******************* Bit definition for I2C_CCR register ********************/
bogdanm 0:9b334a45a8ff 4791 #define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
bogdanm 0:9b334a45a8ff 4792 #define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
bogdanm 0:9b334a45a8ff 4793 #define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
bogdanm 0:9b334a45a8ff 4794
bogdanm 0:9b334a45a8ff 4795 /****************** Bit definition for I2C_TRISE register *******************/
bogdanm 0:9b334a45a8ff 4796 #define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
bogdanm 0:9b334a45a8ff 4797
bogdanm 0:9b334a45a8ff 4798 /****************** Bit definition for I2C_FLTR register *******************/
bogdanm 0:9b334a45a8ff 4799 #define I2C_FLTR_DNF ((uint8_t)0x0F) /*!<Digital Noise Filter */
bogdanm 0:9b334a45a8ff 4800 #define I2C_FLTR_ANOFF ((uint8_t)0x10) /*!<Analog Noise Filter OFF */
bogdanm 0:9b334a45a8ff 4801
bogdanm 0:9b334a45a8ff 4802 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4803 /* */
bogdanm 0:9b334a45a8ff 4804 /* Independent WATCHDOG */
bogdanm 0:9b334a45a8ff 4805 /* */
bogdanm 0:9b334a45a8ff 4806 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4807 /******************* Bit definition for IWDG_KR register ********************/
bogdanm 0:9b334a45a8ff 4808 #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
bogdanm 0:9b334a45a8ff 4809
bogdanm 0:9b334a45a8ff 4810 /******************* Bit definition for IWDG_PR register ********************/
bogdanm 0:9b334a45a8ff 4811 #define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
bogdanm 0:9b334a45a8ff 4812 #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4813 #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4814 #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4815
bogdanm 0:9b334a45a8ff 4816 /******************* Bit definition for IWDG_RLR register *******************/
bogdanm 0:9b334a45a8ff 4817 #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
bogdanm 0:9b334a45a8ff 4818
bogdanm 0:9b334a45a8ff 4819 /******************* Bit definition for IWDG_SR register ********************/
bogdanm 0:9b334a45a8ff 4820 #define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
bogdanm 0:9b334a45a8ff 4821 #define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
bogdanm 0:9b334a45a8ff 4822
bogdanm 0:9b334a45a8ff 4823
bogdanm 0:9b334a45a8ff 4824 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4825 /* */
bogdanm 0:9b334a45a8ff 4826 /* Power Control */
bogdanm 0:9b334a45a8ff 4827 /* */
bogdanm 0:9b334a45a8ff 4828 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4829 /******************** Bit definition for PWR_CR register ********************/
bogdanm 0:9b334a45a8ff 4830 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
bogdanm 0:9b334a45a8ff 4831 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
bogdanm 0:9b334a45a8ff 4832 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
bogdanm 0:9b334a45a8ff 4833 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
bogdanm 0:9b334a45a8ff 4834 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
bogdanm 0:9b334a45a8ff 4835
bogdanm 0:9b334a45a8ff 4836 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
bogdanm 0:9b334a45a8ff 4837 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4838 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4839 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 4840
bogdanm 0:9b334a45a8ff 4841 /*!< PVD level configuration */
bogdanm 0:9b334a45a8ff 4842 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
bogdanm 0:9b334a45a8ff 4843 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
bogdanm 0:9b334a45a8ff 4844 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
bogdanm 0:9b334a45a8ff 4845 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
bogdanm 0:9b334a45a8ff 4846 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
bogdanm 0:9b334a45a8ff 4847 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
bogdanm 0:9b334a45a8ff 4848 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
bogdanm 0:9b334a45a8ff 4849 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
bogdanm 0:9b334a45a8ff 4850
bogdanm 0:9b334a45a8ff 4851 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
bogdanm 0:9b334a45a8ff 4852 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
bogdanm 0:9b334a45a8ff 4853 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
bogdanm 0:9b334a45a8ff 4854 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
bogdanm 0:9b334a45a8ff 4855
bogdanm 0:9b334a45a8ff 4856 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
bogdanm 0:9b334a45a8ff 4857 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4858 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4859
bogdanm 0:9b334a45a8ff 4860 /* Legacy define */
bogdanm 0:9b334a45a8ff 4861 #define PWR_CR_PMODE PWR_CR_VOS
bogdanm 0:9b334a45a8ff 4862
bogdanm 0:9b334a45a8ff 4863 /******************* Bit definition for PWR_CSR register ********************/
bogdanm 0:9b334a45a8ff 4864 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
bogdanm 0:9b334a45a8ff 4865 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
bogdanm 0:9b334a45a8ff 4866 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
bogdanm 0:9b334a45a8ff 4867 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
bogdanm 0:9b334a45a8ff 4868 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
bogdanm 0:9b334a45a8ff 4869 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
bogdanm 0:9b334a45a8ff 4870 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
bogdanm 0:9b334a45a8ff 4871
bogdanm 0:9b334a45a8ff 4872 /* Legacy define */
bogdanm 0:9b334a45a8ff 4873 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
bogdanm 0:9b334a45a8ff 4874
bogdanm 0:9b334a45a8ff 4875 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4876 /* */
bogdanm 0:9b334a45a8ff 4877 /* Reset and Clock Control */
bogdanm 0:9b334a45a8ff 4878 /* */
bogdanm 0:9b334a45a8ff 4879 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4880 /******************** Bit definition for RCC_CR register ********************/
bogdanm 0:9b334a45a8ff 4881 #define RCC_CR_HSION ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4882 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4883
bogdanm 0:9b334a45a8ff 4884 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
bogdanm 0:9b334a45a8ff 4885 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4886 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4887 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4888 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4889 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4890
bogdanm 0:9b334a45a8ff 4891 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
bogdanm 0:9b334a45a8ff 4892 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4893 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4894 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4895 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4896 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4897 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4898 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4899 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4900
bogdanm 0:9b334a45a8ff 4901 #define RCC_CR_HSEON ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 4902 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 4903 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 4904 #define RCC_CR_CSSON ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 4905 #define RCC_CR_PLLON ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 4906 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 4907 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 4908 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 4909
bogdanm 0:9b334a45a8ff 4910
bogdanm 0:9b334a45a8ff 4911 /******************** Bit definition for RCC_PLLCFGR register ***************/
bogdanm 0:9b334a45a8ff 4912 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
bogdanm 0:9b334a45a8ff 4913 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4914 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4915 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4916 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4917 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4918 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4919
bogdanm 0:9b334a45a8ff 4920 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
bogdanm 0:9b334a45a8ff 4921 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 4922 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 4923 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4924 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 4925 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 4926 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 4927 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 4928 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4929 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 4930
bogdanm 0:9b334a45a8ff 4931 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
bogdanm 0:9b334a45a8ff 4932 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 4933 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 4934
bogdanm 0:9b334a45a8ff 4935 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 4936 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 4937 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 4938
bogdanm 0:9b334a45a8ff 4939 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 4940 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 4941 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 4942 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 4943 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 4944
bogdanm 0:9b334a45a8ff 4945 /******************** Bit definition for RCC_CFGR register ******************/
bogdanm 0:9b334a45a8ff 4946 /*!< SW configuration */
bogdanm 0:9b334a45a8ff 4947 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
bogdanm 0:9b334a45a8ff 4948 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4949 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4950
bogdanm 0:9b334a45a8ff 4951 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
bogdanm 0:9b334a45a8ff 4952 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
bogdanm 0:9b334a45a8ff 4953 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
bogdanm 0:9b334a45a8ff 4954
bogdanm 0:9b334a45a8ff 4955 /*!< SWS configuration */
bogdanm 0:9b334a45a8ff 4956 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
bogdanm 0:9b334a45a8ff 4957 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4958 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4959
bogdanm 0:9b334a45a8ff 4960 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
bogdanm 0:9b334a45a8ff 4961 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
bogdanm 0:9b334a45a8ff 4962 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
bogdanm 0:9b334a45a8ff 4963
bogdanm 0:9b334a45a8ff 4964 /*!< HPRE configuration */
bogdanm 0:9b334a45a8ff 4965 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
bogdanm 0:9b334a45a8ff 4966 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4967 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4968 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 4969 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 4970
bogdanm 0:9b334a45a8ff 4971 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
bogdanm 0:9b334a45a8ff 4972 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
bogdanm 0:9b334a45a8ff 4973 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
bogdanm 0:9b334a45a8ff 4974 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
bogdanm 0:9b334a45a8ff 4975 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
bogdanm 0:9b334a45a8ff 4976 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
bogdanm 0:9b334a45a8ff 4977 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
bogdanm 0:9b334a45a8ff 4978 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
bogdanm 0:9b334a45a8ff 4979 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
bogdanm 0:9b334a45a8ff 4980
bogdanm 0:9b334a45a8ff 4981 /*!< PPRE1 configuration */
bogdanm 0:9b334a45a8ff 4982 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
bogdanm 0:9b334a45a8ff 4983 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4984 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4985 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 4986
bogdanm 0:9b334a45a8ff 4987 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 0:9b334a45a8ff 4988 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
bogdanm 0:9b334a45a8ff 4989 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
bogdanm 0:9b334a45a8ff 4990 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
bogdanm 0:9b334a45a8ff 4991 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
bogdanm 0:9b334a45a8ff 4992
bogdanm 0:9b334a45a8ff 4993 /*!< PPRE2 configuration */
bogdanm 0:9b334a45a8ff 4994 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
bogdanm 0:9b334a45a8ff 4995 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4996 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4997 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 4998
bogdanm 0:9b334a45a8ff 4999 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 0:9b334a45a8ff 5000 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
bogdanm 0:9b334a45a8ff 5001 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
bogdanm 0:9b334a45a8ff 5002 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
bogdanm 0:9b334a45a8ff 5003 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
bogdanm 0:9b334a45a8ff 5004
bogdanm 0:9b334a45a8ff 5005 /*!< RTCPRE configuration */
bogdanm 0:9b334a45a8ff 5006 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
bogdanm 0:9b334a45a8ff 5007 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5008 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5009 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5010 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5011 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5012
bogdanm 0:9b334a45a8ff 5013 /*!< MCO1 configuration */
bogdanm 0:9b334a45a8ff 5014 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
bogdanm 0:9b334a45a8ff 5015 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5016 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5017
bogdanm 0:9b334a45a8ff 5018 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5019
bogdanm 0:9b334a45a8ff 5020 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
bogdanm 0:9b334a45a8ff 5021 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 5022 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5023 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5024
bogdanm 0:9b334a45a8ff 5025 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
bogdanm 0:9b334a45a8ff 5026 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 5027 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 5028 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 5029
bogdanm 0:9b334a45a8ff 5030 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
bogdanm 0:9b334a45a8ff 5031 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 5032 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 5033
bogdanm 0:9b334a45a8ff 5034 /******************** Bit definition for RCC_CIR register *******************/
bogdanm 0:9b334a45a8ff 5035 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5036 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5037 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5038 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5039 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5040 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5041 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5042 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5043 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5044 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5045 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5046 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5047 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5048 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5049 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5050 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5051 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5052 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5053 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5054 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5055
bogdanm 0:9b334a45a8ff 5056 /******************** Bit definition for RCC_AHB1RSTR register **************/
bogdanm 0:9b334a45a8ff 5057 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5058 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5059 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5060 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5061 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5062 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5063 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5064 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5065 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5066 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5067 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5068 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5069 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5070 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 5071
bogdanm 0:9b334a45a8ff 5072 /******************** Bit definition for RCC_AHB2RSTR register **************/
bogdanm 0:9b334a45a8ff 5073 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5074 #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5075 #define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5076 /* maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 5077 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
bogdanm 0:9b334a45a8ff 5078 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5079 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5080
bogdanm 0:9b334a45a8ff 5081 /******************** Bit definition for RCC_AHB3RSTR register **************/
bogdanm 0:9b334a45a8ff 5082 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5083
bogdanm 0:9b334a45a8ff 5084 /******************** Bit definition for RCC_APB1RSTR register **************/
bogdanm 0:9b334a45a8ff 5085 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5086 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5087 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5088 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5089 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5090 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5091 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5092 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5093 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5094 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5095 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5096 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5097 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5098 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5099 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5100 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5101 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5102 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5103 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5104 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5105 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5106 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 5107 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 5108 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 5109 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 5110
bogdanm 0:9b334a45a8ff 5111 /******************** Bit definition for RCC_APB2RSTR register **************/
bogdanm 0:9b334a45a8ff 5112 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5113 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5114 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5115 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5116 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5117 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5118 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5119 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5120 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5121 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5122 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5123 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5124 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5125 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5126
bogdanm 0:9b334a45a8ff 5127 /* Old SPI1RST bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 5128 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
bogdanm 0:9b334a45a8ff 5129
bogdanm 0:9b334a45a8ff 5130 /******************** Bit definition for RCC_AHB1ENR register ***************/
bogdanm 0:9b334a45a8ff 5131 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5132 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5133 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5134 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5135 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5136 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5137 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5138 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5139 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5140 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5141 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5142 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5143 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5144 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5145 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5146 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5147 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 5148 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 5149 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 5150 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 5151
bogdanm 0:9b334a45a8ff 5152 /******************** Bit definition for RCC_AHB2ENR register ***************/
bogdanm 0:9b334a45a8ff 5153 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5154 #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5155 #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5156 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5157 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5158
bogdanm 0:9b334a45a8ff 5159 /******************** Bit definition for RCC_AHB3ENR register ***************/
bogdanm 0:9b334a45a8ff 5160 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5161
bogdanm 0:9b334a45a8ff 5162 /******************** Bit definition for RCC_APB1ENR register ***************/
bogdanm 0:9b334a45a8ff 5163 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5164 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5165 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5166 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5167 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5168 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5169 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5170 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5171 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5172 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5173 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5174 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5175 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5176 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5177 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5178 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5179 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5180 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5181 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5182 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5183 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5184 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 5185 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 5186 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 5187 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 5188
bogdanm 0:9b334a45a8ff 5189 /******************** Bit definition for RCC_APB2ENR register ***************/
bogdanm 0:9b334a45a8ff 5190 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5191 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5192 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5193 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5194 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5195 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5196 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5197 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5198 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5199 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5200 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5201 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5202 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5203 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5204 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5205 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5206
bogdanm 0:9b334a45a8ff 5207 /******************** Bit definition for RCC_AHB1LPENR register *************/
bogdanm 0:9b334a45a8ff 5208 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5209 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5210 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5211 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5212 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5213 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5214 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5215 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5216 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5217 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5218 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5219 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5220 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5221 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5222 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5223 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5224 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5225 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5226 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5227 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 5228 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 5229 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 5230 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 5231
bogdanm 0:9b334a45a8ff 5232 /******************** Bit definition for RCC_AHB2LPENR register *************/
bogdanm 0:9b334a45a8ff 5233 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5234 #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5235 #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5236 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5237 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5238
bogdanm 0:9b334a45a8ff 5239 /******************** Bit definition for RCC_AHB3LPENR register *************/
bogdanm 0:9b334a45a8ff 5240 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5241
bogdanm 0:9b334a45a8ff 5242 /******************** Bit definition for RCC_APB1LPENR register *************/
bogdanm 0:9b334a45a8ff 5243 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5244 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5245 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5246 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5247 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5248 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5249 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5250 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5251 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5252 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5253 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5254 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5255 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5256 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5257 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5258 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5259 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5260 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5261 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5262 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5263 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5264 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 5265 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 5266 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 5267 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 5268
bogdanm 0:9b334a45a8ff 5269 /******************** Bit definition for RCC_APB2LPENR register *************/
bogdanm 0:9b334a45a8ff 5270 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5271 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5272 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5273 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5274 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5275 #define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5276 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5277 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5278 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5279 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5280 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5281 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5282 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5283 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5284 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5285 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5286
bogdanm 0:9b334a45a8ff 5287 /******************** Bit definition for RCC_BDCR register ******************/
bogdanm 0:9b334a45a8ff 5288 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5289 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5290 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5291
bogdanm 0:9b334a45a8ff 5292 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
bogdanm 0:9b334a45a8ff 5293 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5294 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5295
bogdanm 0:9b334a45a8ff 5296 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5297 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5298
bogdanm 0:9b334a45a8ff 5299 /******************** Bit definition for RCC_CSR register *******************/
bogdanm 0:9b334a45a8ff 5300 #define RCC_CSR_LSION ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5301 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5302 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 5303 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5304 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5305 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 5306 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 5307 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 5308 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 5309 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 5310
bogdanm 0:9b334a45a8ff 5311 /******************** Bit definition for RCC_SSCGR register *****************/
bogdanm 0:9b334a45a8ff 5312 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
bogdanm 0:9b334a45a8ff 5313 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
bogdanm 0:9b334a45a8ff 5314 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 5315 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 5316
bogdanm 0:9b334a45a8ff 5317 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
bogdanm 0:9b334a45a8ff 5318 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
bogdanm 0:9b334a45a8ff 5319 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
bogdanm 0:9b334a45a8ff 5320
bogdanm 0:9b334a45a8ff 5321 /******************** Bit definition for RCC_DCKCFGR register ***************/
bogdanm 0:9b334a45a8ff 5322 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 5323
bogdanm 0:9b334a45a8ff 5324
bogdanm 0:9b334a45a8ff 5325 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5326 /* */
bogdanm 0:9b334a45a8ff 5327 /* RNG */
bogdanm 0:9b334a45a8ff 5328 /* */
bogdanm 0:9b334a45a8ff 5329 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5330 /******************** Bits definition for RNG_CR register *******************/
bogdanm 0:9b334a45a8ff 5331 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5332 #define RNG_CR_IE ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5333
bogdanm 0:9b334a45a8ff 5334 /******************** Bits definition for RNG_SR register *******************/
bogdanm 0:9b334a45a8ff 5335 #define RNG_SR_DRDY ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5336 #define RNG_SR_CECS ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5337 #define RNG_SR_SECS ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5338 #define RNG_SR_CEIS ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5339 #define RNG_SR_SEIS ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5340
bogdanm 0:9b334a45a8ff 5341 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5342 /* */
bogdanm 0:9b334a45a8ff 5343 /* Real-Time Clock (RTC) */
bogdanm 0:9b334a45a8ff 5344 /* */
bogdanm 0:9b334a45a8ff 5345 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5346 /******************** Bits definition for RTC_TR register *******************/
bogdanm 0:9b334a45a8ff 5347 #define RTC_TR_PM ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5348 #define RTC_TR_HT ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 5349 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5350 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5351 #define RTC_TR_HU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 5352 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5353 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5354 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5355 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5356 #define RTC_TR_MNT ((uint32_t)0x00007000)
bogdanm 0:9b334a45a8ff 5357 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5358 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5359 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5360 #define RTC_TR_MNU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 5361 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5362 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5363 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5364 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5365 #define RTC_TR_ST ((uint32_t)0x00000070)
bogdanm 0:9b334a45a8ff 5366 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5367 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5368 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5369 #define RTC_TR_SU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 5370 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5371 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5372 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5373 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5374
bogdanm 0:9b334a45a8ff 5375 /******************** Bits definition for RTC_DR register *******************/
bogdanm 0:9b334a45a8ff 5376 #define RTC_DR_YT ((uint32_t)0x00F00000)
bogdanm 0:9b334a45a8ff 5377 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5378 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5379 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5380 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5381 #define RTC_DR_YU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 5382 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5383 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5384 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5385 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5386 #define RTC_DR_WDU ((uint32_t)0x0000E000)
bogdanm 0:9b334a45a8ff 5387 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5388 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5389 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5390 #define RTC_DR_MT ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5391 #define RTC_DR_MU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 5392 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5393 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5394 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5395 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5396 #define RTC_DR_DT ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 5397 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5398 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5399 #define RTC_DR_DU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 5400 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5401 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5402 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5403 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5404
bogdanm 0:9b334a45a8ff 5405 /******************** Bits definition for RTC_CR register *******************/
bogdanm 0:9b334a45a8ff 5406 #define RTC_CR_COE ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5407 #define RTC_CR_OSEL ((uint32_t)0x00600000)
bogdanm 0:9b334a45a8ff 5408 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5409 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5410 #define RTC_CR_POL ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5411 #define RTC_CR_COSEL ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5412 #define RTC_CR_BCK ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5413 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5414 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5415 #define RTC_CR_TSIE ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5416 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5417 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5418 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5419 #define RTC_CR_TSE ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5420 #define RTC_CR_WUTE ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5421 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5422 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5423 #define RTC_CR_DCE ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5424 #define RTC_CR_FMT ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5425 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5426 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5427 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5428 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
bogdanm 0:9b334a45a8ff 5429 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5430 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5431 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5432
bogdanm 0:9b334a45a8ff 5433 /******************** Bits definition for RTC_ISR register ******************/
bogdanm 0:9b334a45a8ff 5434 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5435 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5436 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5437 #define RTC_ISR_TSF ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5438 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5439 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5440 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5441 #define RTC_ISR_INIT ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5442 #define RTC_ISR_INITF ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5443 #define RTC_ISR_RSF ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5444 #define RTC_ISR_INITS ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5445 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5446 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5447 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5448 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5449
bogdanm 0:9b334a45a8ff 5450 /******************** Bits definition for RTC_PRER register *****************/
bogdanm 0:9b334a45a8ff 5451 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
bogdanm 0:9b334a45a8ff 5452 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
bogdanm 0:9b334a45a8ff 5453
bogdanm 0:9b334a45a8ff 5454 /******************** Bits definition for RTC_WUTR register *****************/
bogdanm 0:9b334a45a8ff 5455 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
bogdanm 0:9b334a45a8ff 5456
bogdanm 0:9b334a45a8ff 5457 /******************** Bits definition for RTC_CALIBR register ***************/
bogdanm 0:9b334a45a8ff 5458 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5459 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
bogdanm 0:9b334a45a8ff 5460
bogdanm 0:9b334a45a8ff 5461 /******************** Bits definition for RTC_ALRMAR register ***************/
bogdanm 0:9b334a45a8ff 5462 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 5463 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 5464 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 5465 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 5466 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 5467 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 5468 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 5469 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5470 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5471 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 5472 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5473 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5474 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 5475 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5476 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5477 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 5478 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5479 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5480 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5481 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5482 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5483 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
bogdanm 0:9b334a45a8ff 5484 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5485 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5486 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5487 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 5488 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5489 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5490 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5491 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5492 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5493 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
bogdanm 0:9b334a45a8ff 5494 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5495 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5496 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5497 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 5498 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5499 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5500 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5501 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5502
bogdanm 0:9b334a45a8ff 5503 /******************** Bits definition for RTC_ALRMBR register ***************/
bogdanm 0:9b334a45a8ff 5504 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 5505 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 5506 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 5507 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 5508 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 5509 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 5510 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 5511 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5512 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5513 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 5514 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 5515 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5516 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 5517 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5518 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5519 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 5520 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5521 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5522 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5523 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5524 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5525 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
bogdanm 0:9b334a45a8ff 5526 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5527 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5528 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5529 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 5530 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5531 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5532 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5533 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5534 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5535 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
bogdanm 0:9b334a45a8ff 5536 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5537 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5538 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5539 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 5540 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5541 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5542 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5543 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5544
bogdanm 0:9b334a45a8ff 5545 /******************** Bits definition for RTC_WPR register ******************/
bogdanm 0:9b334a45a8ff 5546 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
bogdanm 0:9b334a45a8ff 5547
bogdanm 0:9b334a45a8ff 5548 /******************** Bits definition for RTC_SSR register ******************/
bogdanm 0:9b334a45a8ff 5549 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
bogdanm 0:9b334a45a8ff 5550
bogdanm 0:9b334a45a8ff 5551 /******************** Bits definition for RTC_SHIFTR register ***************/
bogdanm 0:9b334a45a8ff 5552 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
bogdanm 0:9b334a45a8ff 5553 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 5554
bogdanm 0:9b334a45a8ff 5555 /******************** Bits definition for RTC_TSTR register *****************/
bogdanm 0:9b334a45a8ff 5556 #define RTC_TSTR_PM ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 5557 #define RTC_TSTR_HT ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 5558 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 5559 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 5560 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 5561 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5562 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5563 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5564 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 5565 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
bogdanm 0:9b334a45a8ff 5566 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5567 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5568 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5569 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 5570 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5571 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5572 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5573 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5574 #define RTC_TSTR_ST ((uint32_t)0x00000070)
bogdanm 0:9b334a45a8ff 5575 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5576 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5577 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5578 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 5579 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5580 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5581 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5582 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5583
bogdanm 0:9b334a45a8ff 5584 /******************** Bits definition for RTC_TSDR register *****************/
bogdanm 0:9b334a45a8ff 5585 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
bogdanm 0:9b334a45a8ff 5586 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5587 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5588 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5589 #define RTC_TSDR_MT ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5590 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 5591 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5592 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5593 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5594 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5595 #define RTC_TSDR_DT ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 5596 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5597 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5598 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 5599 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5600 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5601 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5602 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5603
bogdanm 0:9b334a45a8ff 5604 /******************** Bits definition for RTC_TSSSR register ****************/
bogdanm 0:9b334a45a8ff 5605 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm 0:9b334a45a8ff 5606
bogdanm 0:9b334a45a8ff 5607 /******************** Bits definition for RTC_CAL register *****************/
bogdanm 0:9b334a45a8ff 5608 #define RTC_CALR_CALP ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5609 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5610 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5611 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
bogdanm 0:9b334a45a8ff 5612 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5613 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5614 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5615 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 5616 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 5617 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 5618 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 5619 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5620 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5621
bogdanm 0:9b334a45a8ff 5622 /******************** Bits definition for RTC_TAFCR register ****************/
bogdanm 0:9b334a45a8ff 5623 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 5624 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 5625 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 5626 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 5627 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
bogdanm 0:9b334a45a8ff 5628 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 5629 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 5630 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
bogdanm 0:9b334a45a8ff 5631 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 5632 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 5633 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
bogdanm 0:9b334a45a8ff 5634 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 5635 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 5636 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 5637 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 5638 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5639 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5640 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5641
bogdanm 0:9b334a45a8ff 5642 /******************** Bits definition for RTC_ALRMASSR register *************/
bogdanm 0:9b334a45a8ff 5643 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 5644 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 5645 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5646 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5647 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 5648 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm 0:9b334a45a8ff 5649
bogdanm 0:9b334a45a8ff 5650 /******************** Bits definition for RTC_ALRMBSSR register *************/
bogdanm 0:9b334a45a8ff 5651 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 5652 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 5653 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 5654 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 5655 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 5656 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
bogdanm 0:9b334a45a8ff 5657
bogdanm 0:9b334a45a8ff 5658 /******************** Bits definition for RTC_BKP0R register ****************/
bogdanm 0:9b334a45a8ff 5659 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5660
bogdanm 0:9b334a45a8ff 5661 /******************** Bits definition for RTC_BKP1R register ****************/
bogdanm 0:9b334a45a8ff 5662 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5663
bogdanm 0:9b334a45a8ff 5664 /******************** Bits definition for RTC_BKP2R register ****************/
bogdanm 0:9b334a45a8ff 5665 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5666
bogdanm 0:9b334a45a8ff 5667 /******************** Bits definition for RTC_BKP3R register ****************/
bogdanm 0:9b334a45a8ff 5668 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5669
bogdanm 0:9b334a45a8ff 5670 /******************** Bits definition for RTC_BKP4R register ****************/
bogdanm 0:9b334a45a8ff 5671 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5672
bogdanm 0:9b334a45a8ff 5673 /******************** Bits definition for RTC_BKP5R register ****************/
bogdanm 0:9b334a45a8ff 5674 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5675
bogdanm 0:9b334a45a8ff 5676 /******************** Bits definition for RTC_BKP6R register ****************/
bogdanm 0:9b334a45a8ff 5677 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5678
bogdanm 0:9b334a45a8ff 5679 /******************** Bits definition for RTC_BKP7R register ****************/
bogdanm 0:9b334a45a8ff 5680 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5681
bogdanm 0:9b334a45a8ff 5682 /******************** Bits definition for RTC_BKP8R register ****************/
bogdanm 0:9b334a45a8ff 5683 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5684
bogdanm 0:9b334a45a8ff 5685 /******************** Bits definition for RTC_BKP9R register ****************/
bogdanm 0:9b334a45a8ff 5686 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5687
bogdanm 0:9b334a45a8ff 5688 /******************** Bits definition for RTC_BKP10R register ***************/
bogdanm 0:9b334a45a8ff 5689 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5690
bogdanm 0:9b334a45a8ff 5691 /******************** Bits definition for RTC_BKP11R register ***************/
bogdanm 0:9b334a45a8ff 5692 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5693
bogdanm 0:9b334a45a8ff 5694 /******************** Bits definition for RTC_BKP12R register ***************/
bogdanm 0:9b334a45a8ff 5695 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5696
bogdanm 0:9b334a45a8ff 5697 /******************** Bits definition for RTC_BKP13R register ***************/
bogdanm 0:9b334a45a8ff 5698 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5699
bogdanm 0:9b334a45a8ff 5700 /******************** Bits definition for RTC_BKP14R register ***************/
bogdanm 0:9b334a45a8ff 5701 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5702
bogdanm 0:9b334a45a8ff 5703 /******************** Bits definition for RTC_BKP15R register ***************/
bogdanm 0:9b334a45a8ff 5704 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5705
bogdanm 0:9b334a45a8ff 5706 /******************** Bits definition for RTC_BKP16R register ***************/
bogdanm 0:9b334a45a8ff 5707 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5708
bogdanm 0:9b334a45a8ff 5709 /******************** Bits definition for RTC_BKP17R register ***************/
bogdanm 0:9b334a45a8ff 5710 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5711
bogdanm 0:9b334a45a8ff 5712 /******************** Bits definition for RTC_BKP18R register ***************/
bogdanm 0:9b334a45a8ff 5713 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5714
bogdanm 0:9b334a45a8ff 5715 /******************** Bits definition for RTC_BKP19R register ***************/
bogdanm 0:9b334a45a8ff 5716 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 5717
bogdanm 0:9b334a45a8ff 5718
bogdanm 0:9b334a45a8ff 5719 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5720 /* */
bogdanm 0:9b334a45a8ff 5721 /* SD host Interface */
bogdanm 0:9b334a45a8ff 5722 /* */
bogdanm 0:9b334a45a8ff 5723 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5724 /****************** Bit definition for SDIO_POWER register ******************/
bogdanm 0:9b334a45a8ff 5725 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
bogdanm 0:9b334a45a8ff 5726 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 5727 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 5728
bogdanm 0:9b334a45a8ff 5729 /****************** Bit definition for SDIO_CLKCR register ******************/
bogdanm 0:9b334a45a8ff 5730 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
bogdanm 0:9b334a45a8ff 5731 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
bogdanm 0:9b334a45a8ff 5732 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
bogdanm 0:9b334a45a8ff 5733 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
bogdanm 0:9b334a45a8ff 5734
bogdanm 0:9b334a45a8ff 5735 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
bogdanm 0:9b334a45a8ff 5736 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 5737 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 5738
bogdanm 0:9b334a45a8ff 5739 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
bogdanm 0:9b334a45a8ff 5740 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
bogdanm 0:9b334a45a8ff 5741
bogdanm 0:9b334a45a8ff 5742 /******************* Bit definition for SDIO_ARG register *******************/
bogdanm 0:9b334a45a8ff 5743 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
bogdanm 0:9b334a45a8ff 5744
bogdanm 0:9b334a45a8ff 5745 /******************* Bit definition for SDIO_CMD register *******************/
bogdanm 0:9b334a45a8ff 5746 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
bogdanm 0:9b334a45a8ff 5747
bogdanm 0:9b334a45a8ff 5748 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
bogdanm 0:9b334a45a8ff 5749 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5750 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5751
bogdanm 0:9b334a45a8ff 5752 #define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
bogdanm 0:9b334a45a8ff 5753 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
bogdanm 0:9b334a45a8ff 5754 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
bogdanm 0:9b334a45a8ff 5755 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
bogdanm 0:9b334a45a8ff 5756 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
bogdanm 0:9b334a45a8ff 5757 #define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
bogdanm 0:9b334a45a8ff 5758 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
bogdanm 0:9b334a45a8ff 5759
bogdanm 0:9b334a45a8ff 5760 /***************** Bit definition for SDIO_RESPCMD register *****************/
bogdanm 0:9b334a45a8ff 5761 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
bogdanm 0:9b334a45a8ff 5762
bogdanm 0:9b334a45a8ff 5763 /****************** Bit definition for SDIO_RESP0 register ******************/
bogdanm 0:9b334a45a8ff 5764 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 0:9b334a45a8ff 5765
bogdanm 0:9b334a45a8ff 5766 /****************** Bit definition for SDIO_RESP1 register ******************/
bogdanm 0:9b334a45a8ff 5767 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 0:9b334a45a8ff 5768
bogdanm 0:9b334a45a8ff 5769 /****************** Bit definition for SDIO_RESP2 register ******************/
bogdanm 0:9b334a45a8ff 5770 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 0:9b334a45a8ff 5771
bogdanm 0:9b334a45a8ff 5772 /****************** Bit definition for SDIO_RESP3 register ******************/
bogdanm 0:9b334a45a8ff 5773 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 0:9b334a45a8ff 5774
bogdanm 0:9b334a45a8ff 5775 /****************** Bit definition for SDIO_RESP4 register ******************/
bogdanm 0:9b334a45a8ff 5776 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 0:9b334a45a8ff 5777
bogdanm 0:9b334a45a8ff 5778 /****************** Bit definition for SDIO_DTIMER register *****************/
bogdanm 0:9b334a45a8ff 5779 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
bogdanm 0:9b334a45a8ff 5780
bogdanm 0:9b334a45a8ff 5781 /****************** Bit definition for SDIO_DLEN register *******************/
bogdanm 0:9b334a45a8ff 5782 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
bogdanm 0:9b334a45a8ff 5783
bogdanm 0:9b334a45a8ff 5784 /****************** Bit definition for SDIO_DCTRL register ******************/
bogdanm 0:9b334a45a8ff 5785 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
bogdanm 0:9b334a45a8ff 5786 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
bogdanm 0:9b334a45a8ff 5787 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
bogdanm 0:9b334a45a8ff 5788 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
bogdanm 0:9b334a45a8ff 5789
bogdanm 0:9b334a45a8ff 5790 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
bogdanm 0:9b334a45a8ff 5791 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 5792 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 5793 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 5794 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 5795
bogdanm 0:9b334a45a8ff 5796 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
bogdanm 0:9b334a45a8ff 5797 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
bogdanm 0:9b334a45a8ff 5798 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
bogdanm 0:9b334a45a8ff 5799 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
bogdanm 0:9b334a45a8ff 5800
bogdanm 0:9b334a45a8ff 5801 /****************** Bit definition for SDIO_DCOUNT register *****************/
bogdanm 0:9b334a45a8ff 5802 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
bogdanm 0:9b334a45a8ff 5803
bogdanm 0:9b334a45a8ff 5804 /****************** Bit definition for SDIO_STA register ********************/
bogdanm 0:9b334a45a8ff 5805 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
bogdanm 0:9b334a45a8ff 5806 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
bogdanm 0:9b334a45a8ff 5807 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
bogdanm 0:9b334a45a8ff 5808 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
bogdanm 0:9b334a45a8ff 5809 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
bogdanm 0:9b334a45a8ff 5810 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
bogdanm 0:9b334a45a8ff 5811 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
bogdanm 0:9b334a45a8ff 5812 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
bogdanm 0:9b334a45a8ff 5813 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
bogdanm 0:9b334a45a8ff 5814 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
bogdanm 0:9b334a45a8ff 5815 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
bogdanm 0:9b334a45a8ff 5816 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
bogdanm 0:9b334a45a8ff 5817 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
bogdanm 0:9b334a45a8ff 5818 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
bogdanm 0:9b334a45a8ff 5819 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
bogdanm 0:9b334a45a8ff 5820 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
bogdanm 0:9b334a45a8ff 5821 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
bogdanm 0:9b334a45a8ff 5822 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
bogdanm 0:9b334a45a8ff 5823 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
bogdanm 0:9b334a45a8ff 5824 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
bogdanm 0:9b334a45a8ff 5825 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
bogdanm 0:9b334a45a8ff 5826 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
bogdanm 0:9b334a45a8ff 5827 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
bogdanm 0:9b334a45a8ff 5828 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
bogdanm 0:9b334a45a8ff 5829
bogdanm 0:9b334a45a8ff 5830 /******************* Bit definition for SDIO_ICR register *******************/
bogdanm 0:9b334a45a8ff 5831 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
bogdanm 0:9b334a45a8ff 5832 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
bogdanm 0:9b334a45a8ff 5833 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
bogdanm 0:9b334a45a8ff 5834 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
bogdanm 0:9b334a45a8ff 5835 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
bogdanm 0:9b334a45a8ff 5836 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
bogdanm 0:9b334a45a8ff 5837 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
bogdanm 0:9b334a45a8ff 5838 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
bogdanm 0:9b334a45a8ff 5839 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
bogdanm 0:9b334a45a8ff 5840 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
bogdanm 0:9b334a45a8ff 5841 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
bogdanm 0:9b334a45a8ff 5842 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
bogdanm 0:9b334a45a8ff 5843 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
bogdanm 0:9b334a45a8ff 5844
bogdanm 0:9b334a45a8ff 5845 /****************** Bit definition for SDIO_MASK register *******************/
bogdanm 0:9b334a45a8ff 5846 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
bogdanm 0:9b334a45a8ff 5847 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
bogdanm 0:9b334a45a8ff 5848 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
bogdanm 0:9b334a45a8ff 5849 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
bogdanm 0:9b334a45a8ff 5850 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 5851 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 5852 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
bogdanm 0:9b334a45a8ff 5853 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
bogdanm 0:9b334a45a8ff 5854 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
bogdanm 0:9b334a45a8ff 5855 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 5856 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
bogdanm 0:9b334a45a8ff 5857 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
bogdanm 0:9b334a45a8ff 5858 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
bogdanm 0:9b334a45a8ff 5859 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
bogdanm 0:9b334a45a8ff 5860 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
bogdanm 0:9b334a45a8ff 5861 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
bogdanm 0:9b334a45a8ff 5862 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
bogdanm 0:9b334a45a8ff 5863 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
bogdanm 0:9b334a45a8ff 5864 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
bogdanm 0:9b334a45a8ff 5865 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
bogdanm 0:9b334a45a8ff 5866 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
bogdanm 0:9b334a45a8ff 5867 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
bogdanm 0:9b334a45a8ff 5868 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
bogdanm 0:9b334a45a8ff 5869 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
bogdanm 0:9b334a45a8ff 5870
bogdanm 0:9b334a45a8ff 5871 /***************** Bit definition for SDIO_FIFOCNT register *****************/
bogdanm 0:9b334a45a8ff 5872 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
bogdanm 0:9b334a45a8ff 5873
bogdanm 0:9b334a45a8ff 5874 /****************** Bit definition for SDIO_FIFO register *******************/
bogdanm 0:9b334a45a8ff 5875 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
bogdanm 0:9b334a45a8ff 5876
bogdanm 0:9b334a45a8ff 5877 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5878 /* */
bogdanm 0:9b334a45a8ff 5879 /* Serial Peripheral Interface */
bogdanm 0:9b334a45a8ff 5880 /* */
bogdanm 0:9b334a45a8ff 5881 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5882 /******************* Bit definition for SPI_CR1 register ********************/
bogdanm 0:9b334a45a8ff 5883 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
bogdanm 0:9b334a45a8ff 5884 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
bogdanm 0:9b334a45a8ff 5885 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
bogdanm 0:9b334a45a8ff 5886
bogdanm 0:9b334a45a8ff 5887 #define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
bogdanm 0:9b334a45a8ff 5888 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 5889 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 5890 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 5891
bogdanm 0:9b334a45a8ff 5892 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
bogdanm 0:9b334a45a8ff 5893 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
bogdanm 0:9b334a45a8ff 5894 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
bogdanm 0:9b334a45a8ff 5895 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
bogdanm 0:9b334a45a8ff 5896 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
bogdanm 0:9b334a45a8ff 5897 #define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
bogdanm 0:9b334a45a8ff 5898 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
bogdanm 0:9b334a45a8ff 5899 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
bogdanm 0:9b334a45a8ff 5900 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
bogdanm 0:9b334a45a8ff 5901 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
bogdanm 0:9b334a45a8ff 5902
bogdanm 0:9b334a45a8ff 5903 /******************* Bit definition for SPI_CR2 register ********************/
bogdanm 0:9b334a45a8ff 5904 #define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
bogdanm 0:9b334a45a8ff 5905 #define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
bogdanm 0:9b334a45a8ff 5906 #define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
bogdanm 0:9b334a45a8ff 5907 #define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 5908 #define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
bogdanm 0:9b334a45a8ff 5909 #define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
bogdanm 0:9b334a45a8ff 5910
bogdanm 0:9b334a45a8ff 5911 /******************** Bit definition for SPI_SR register ********************/
bogdanm 0:9b334a45a8ff 5912 #define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
bogdanm 0:9b334a45a8ff 5913 #define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
bogdanm 0:9b334a45a8ff 5914 #define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
bogdanm 0:9b334a45a8ff 5915 #define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
bogdanm 0:9b334a45a8ff 5916 #define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
bogdanm 0:9b334a45a8ff 5917 #define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
bogdanm 0:9b334a45a8ff 5918 #define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
bogdanm 0:9b334a45a8ff 5919 #define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
bogdanm 0:9b334a45a8ff 5920
bogdanm 0:9b334a45a8ff 5921 /******************** Bit definition for SPI_DR register ********************/
bogdanm 0:9b334a45a8ff 5922 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
bogdanm 0:9b334a45a8ff 5923
bogdanm 0:9b334a45a8ff 5924 /******************* Bit definition for SPI_CRCPR register ******************/
bogdanm 0:9b334a45a8ff 5925 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
bogdanm 0:9b334a45a8ff 5926
bogdanm 0:9b334a45a8ff 5927 /****************** Bit definition for SPI_RXCRCR register ******************/
bogdanm 0:9b334a45a8ff 5928 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
bogdanm 0:9b334a45a8ff 5929
bogdanm 0:9b334a45a8ff 5930 /****************** Bit definition for SPI_TXCRCR register ******************/
bogdanm 0:9b334a45a8ff 5931 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
bogdanm 0:9b334a45a8ff 5932
bogdanm 0:9b334a45a8ff 5933 /****************** Bit definition for SPI_I2SCFGR register *****************/
bogdanm 0:9b334a45a8ff 5934 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
bogdanm 0:9b334a45a8ff 5935
bogdanm 0:9b334a45a8ff 5936 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
bogdanm 0:9b334a45a8ff 5937 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 5938 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 5939
bogdanm 0:9b334a45a8ff 5940 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
bogdanm 0:9b334a45a8ff 5941
bogdanm 0:9b334a45a8ff 5942 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
bogdanm 0:9b334a45a8ff 5943 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 5944 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 5945
bogdanm 0:9b334a45a8ff 5946 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
bogdanm 0:9b334a45a8ff 5947
bogdanm 0:9b334a45a8ff 5948 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
bogdanm 0:9b334a45a8ff 5949 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 5950 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 5951
bogdanm 0:9b334a45a8ff 5952 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
bogdanm 0:9b334a45a8ff 5953 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
bogdanm 0:9b334a45a8ff 5954
bogdanm 0:9b334a45a8ff 5955 /****************** Bit definition for SPI_I2SPR register *******************/
bogdanm 0:9b334a45a8ff 5956 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
bogdanm 0:9b334a45a8ff 5957 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
bogdanm 0:9b334a45a8ff 5958 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
bogdanm 0:9b334a45a8ff 5959
bogdanm 0:9b334a45a8ff 5960 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5961 /* */
bogdanm 0:9b334a45a8ff 5962 /* SYSCFG */
bogdanm 0:9b334a45a8ff 5963 /* */
bogdanm 0:9b334a45a8ff 5964 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5965 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
bogdanm 0:9b334a45a8ff 5966 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
bogdanm 0:9b334a45a8ff 5967 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 5968 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 5969 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 5970
bogdanm 0:9b334a45a8ff 5971 #define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
bogdanm 0:9b334a45a8ff 5972
bogdanm 0:9b334a45a8ff 5973 /****************** Bit definition for SYSCFG_PMC register ******************/
bogdanm 0:9b334a45a8ff 5974 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
bogdanm 0:9b334a45a8ff 5975 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 5976 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
bogdanm 0:9b334a45a8ff 5977
bogdanm 0:9b334a45a8ff 5978 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
bogdanm 0:9b334a45a8ff 5979 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */
bogdanm 0:9b334a45a8ff 5980 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
bogdanm 0:9b334a45a8ff 5981 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
bogdanm 0:9b334a45a8ff 5982 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!<EXTI 3 configuration */
bogdanm 0:9b334a45a8ff 5983 /**
bogdanm 0:9b334a45a8ff 5984 * @brief EXTI0 configuration
bogdanm 0:9b334a45a8ff 5985 */
bogdanm 0:9b334a45a8ff 5986 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */
bogdanm 0:9b334a45a8ff 5987 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */
bogdanm 0:9b334a45a8ff 5988 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */
bogdanm 0:9b334a45a8ff 5989 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */
bogdanm 0:9b334a45a8ff 5990 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */
bogdanm 0:9b334a45a8ff 5991 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */
bogdanm 0:9b334a45a8ff 5992 #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */
bogdanm 0:9b334a45a8ff 5993 #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */
bogdanm 0:9b334a45a8ff 5994 #define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */
bogdanm 0:9b334a45a8ff 5995
bogdanm 0:9b334a45a8ff 5996 /**
bogdanm 0:9b334a45a8ff 5997 * @brief EXTI1 configuration
bogdanm 0:9b334a45a8ff 5998 */
bogdanm 0:9b334a45a8ff 5999 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */
bogdanm 0:9b334a45a8ff 6000 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */
bogdanm 0:9b334a45a8ff 6001 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */
bogdanm 0:9b334a45a8ff 6002 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */
bogdanm 0:9b334a45a8ff 6003 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */
bogdanm 0:9b334a45a8ff 6004 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */
bogdanm 0:9b334a45a8ff 6005 #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */
bogdanm 0:9b334a45a8ff 6006 #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */
bogdanm 0:9b334a45a8ff 6007 #define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */
bogdanm 0:9b334a45a8ff 6008
bogdanm 0:9b334a45a8ff 6009 /**
bogdanm 0:9b334a45a8ff 6010 * @brief EXTI2 configuration
bogdanm 0:9b334a45a8ff 6011 */
bogdanm 0:9b334a45a8ff 6012 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */
bogdanm 0:9b334a45a8ff 6013 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */
bogdanm 0:9b334a45a8ff 6014 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */
bogdanm 0:9b334a45a8ff 6015 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */
bogdanm 0:9b334a45a8ff 6016 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */
bogdanm 0:9b334a45a8ff 6017 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */
bogdanm 0:9b334a45a8ff 6018 #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */
bogdanm 0:9b334a45a8ff 6019 #define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */
bogdanm 0:9b334a45a8ff 6020 #define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */
bogdanm 0:9b334a45a8ff 6021
bogdanm 0:9b334a45a8ff 6022 /**
bogdanm 0:9b334a45a8ff 6023 * @brief EXTI3 configuration
bogdanm 0:9b334a45a8ff 6024 */
bogdanm 0:9b334a45a8ff 6025 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */
bogdanm 0:9b334a45a8ff 6026 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */
bogdanm 0:9b334a45a8ff 6027 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */
bogdanm 0:9b334a45a8ff 6028 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */
bogdanm 0:9b334a45a8ff 6029 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */
bogdanm 0:9b334a45a8ff 6030 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */
bogdanm 0:9b334a45a8ff 6031 #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */
bogdanm 0:9b334a45a8ff 6032 #define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */
bogdanm 0:9b334a45a8ff 6033 #define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */
bogdanm 0:9b334a45a8ff 6034
bogdanm 0:9b334a45a8ff 6035 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
bogdanm 0:9b334a45a8ff 6036 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!<EXTI 4 configuration */
bogdanm 0:9b334a45a8ff 6037 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
bogdanm 0:9b334a45a8ff 6038 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
bogdanm 0:9b334a45a8ff 6039 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!<EXTI 7 configuration */
bogdanm 0:9b334a45a8ff 6040 /**
bogdanm 0:9b334a45a8ff 6041 * @brief EXTI4 configuration
bogdanm 0:9b334a45a8ff 6042 */
bogdanm 0:9b334a45a8ff 6043 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */
bogdanm 0:9b334a45a8ff 6044 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */
bogdanm 0:9b334a45a8ff 6045 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */
bogdanm 0:9b334a45a8ff 6046 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */
bogdanm 0:9b334a45a8ff 6047 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */
bogdanm 0:9b334a45a8ff 6048 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */
bogdanm 0:9b334a45a8ff 6049 #define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */
bogdanm 0:9b334a45a8ff 6050 #define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */
bogdanm 0:9b334a45a8ff 6051 #define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */
bogdanm 0:9b334a45a8ff 6052
bogdanm 0:9b334a45a8ff 6053 /**
bogdanm 0:9b334a45a8ff 6054 * @brief EXTI5 configuration
bogdanm 0:9b334a45a8ff 6055 */
bogdanm 0:9b334a45a8ff 6056 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */
bogdanm 0:9b334a45a8ff 6057 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */
bogdanm 0:9b334a45a8ff 6058 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */
bogdanm 0:9b334a45a8ff 6059 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */
bogdanm 0:9b334a45a8ff 6060 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */
bogdanm 0:9b334a45a8ff 6061 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */
bogdanm 0:9b334a45a8ff 6062 #define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */
bogdanm 0:9b334a45a8ff 6063 #define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */
bogdanm 0:9b334a45a8ff 6064 #define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */
bogdanm 0:9b334a45a8ff 6065
bogdanm 0:9b334a45a8ff 6066 /**
bogdanm 0:9b334a45a8ff 6067 * @brief EXTI6 configuration
bogdanm 0:9b334a45a8ff 6068 */
bogdanm 0:9b334a45a8ff 6069 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */
bogdanm 0:9b334a45a8ff 6070 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */
bogdanm 0:9b334a45a8ff 6071 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */
bogdanm 0:9b334a45a8ff 6072 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */
bogdanm 0:9b334a45a8ff 6073 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */
bogdanm 0:9b334a45a8ff 6074 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */
bogdanm 0:9b334a45a8ff 6075 #define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */
bogdanm 0:9b334a45a8ff 6076 #define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */
bogdanm 0:9b334a45a8ff 6077 #define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */
bogdanm 0:9b334a45a8ff 6078
bogdanm 0:9b334a45a8ff 6079 /**
bogdanm 0:9b334a45a8ff 6080 * @brief EXTI7 configuration
bogdanm 0:9b334a45a8ff 6081 */
bogdanm 0:9b334a45a8ff 6082 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */
bogdanm 0:9b334a45a8ff 6083 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */
bogdanm 0:9b334a45a8ff 6084 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */
bogdanm 0:9b334a45a8ff 6085 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */
bogdanm 0:9b334a45a8ff 6086 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */
bogdanm 0:9b334a45a8ff 6087 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */
bogdanm 0:9b334a45a8ff 6088 #define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */
bogdanm 0:9b334a45a8ff 6089 #define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */
bogdanm 0:9b334a45a8ff 6090 #define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */
bogdanm 0:9b334a45a8ff 6091
bogdanm 0:9b334a45a8ff 6092 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
bogdanm 0:9b334a45a8ff 6093 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!<EXTI 8 configuration */
bogdanm 0:9b334a45a8ff 6094 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
bogdanm 0:9b334a45a8ff 6095 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
bogdanm 0:9b334a45a8ff 6096 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!<EXTI 11 configuration */
bogdanm 0:9b334a45a8ff 6097
bogdanm 0:9b334a45a8ff 6098 /**
bogdanm 0:9b334a45a8ff 6099 * @brief EXTI8 configuration
bogdanm 0:9b334a45a8ff 6100 */
bogdanm 0:9b334a45a8ff 6101 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */
bogdanm 0:9b334a45a8ff 6102 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */
bogdanm 0:9b334a45a8ff 6103 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */
bogdanm 0:9b334a45a8ff 6104 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */
bogdanm 0:9b334a45a8ff 6105 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */
bogdanm 0:9b334a45a8ff 6106 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */
bogdanm 0:9b334a45a8ff 6107 #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */
bogdanm 0:9b334a45a8ff 6108 #define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */
bogdanm 0:9b334a45a8ff 6109 #define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */
bogdanm 0:9b334a45a8ff 6110
bogdanm 0:9b334a45a8ff 6111 /**
bogdanm 0:9b334a45a8ff 6112 * @brief EXTI9 configuration
bogdanm 0:9b334a45a8ff 6113 */
bogdanm 0:9b334a45a8ff 6114 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */
bogdanm 0:9b334a45a8ff 6115 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */
bogdanm 0:9b334a45a8ff 6116 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */
bogdanm 0:9b334a45a8ff 6117 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */
bogdanm 0:9b334a45a8ff 6118 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */
bogdanm 0:9b334a45a8ff 6119 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */
bogdanm 0:9b334a45a8ff 6120 #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */
bogdanm 0:9b334a45a8ff 6121 #define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */
bogdanm 0:9b334a45a8ff 6122 #define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */
bogdanm 0:9b334a45a8ff 6123
bogdanm 0:9b334a45a8ff 6124 /**
bogdanm 0:9b334a45a8ff 6125 * @brief EXTI10 configuration
bogdanm 0:9b334a45a8ff 6126 */
bogdanm 0:9b334a45a8ff 6127 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */
bogdanm 0:9b334a45a8ff 6128 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */
bogdanm 0:9b334a45a8ff 6129 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */
bogdanm 0:9b334a45a8ff 6130 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */
bogdanm 0:9b334a45a8ff 6131 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */
bogdanm 0:9b334a45a8ff 6132 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */
bogdanm 0:9b334a45a8ff 6133 #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */
bogdanm 0:9b334a45a8ff 6134 #define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */
bogdanm 0:9b334a45a8ff 6135 #define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */
bogdanm 0:9b334a45a8ff 6136
bogdanm 0:9b334a45a8ff 6137 /**
bogdanm 0:9b334a45a8ff 6138 * @brief EXTI11 configuration
bogdanm 0:9b334a45a8ff 6139 */
bogdanm 0:9b334a45a8ff 6140 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */
bogdanm 0:9b334a45a8ff 6141 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */
bogdanm 0:9b334a45a8ff 6142 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */
bogdanm 0:9b334a45a8ff 6143 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */
bogdanm 0:9b334a45a8ff 6144 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */
bogdanm 0:9b334a45a8ff 6145 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */
bogdanm 0:9b334a45a8ff 6146 #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */
bogdanm 0:9b334a45a8ff 6147 #define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */
bogdanm 0:9b334a45a8ff 6148 #define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */
bogdanm 0:9b334a45a8ff 6149
bogdanm 0:9b334a45a8ff 6150 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
bogdanm 0:9b334a45a8ff 6151 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!<EXTI 12 configuration */
bogdanm 0:9b334a45a8ff 6152 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
bogdanm 0:9b334a45a8ff 6153 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
bogdanm 0:9b334a45a8ff 6154 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!<EXTI 15 configuration */
bogdanm 0:9b334a45a8ff 6155 /**
bogdanm 0:9b334a45a8ff 6156 * @brief EXTI12 configuration
bogdanm 0:9b334a45a8ff 6157 */
bogdanm 0:9b334a45a8ff 6158 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */
bogdanm 0:9b334a45a8ff 6159 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */
bogdanm 0:9b334a45a8ff 6160 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */
bogdanm 0:9b334a45a8ff 6161 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */
bogdanm 0:9b334a45a8ff 6162 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */
bogdanm 0:9b334a45a8ff 6163 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */
bogdanm 0:9b334a45a8ff 6164 #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */
bogdanm 0:9b334a45a8ff 6165 #define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */
bogdanm 0:9b334a45a8ff 6166
bogdanm 0:9b334a45a8ff 6167 /**
bogdanm 0:9b334a45a8ff 6168 * @brief EXTI13 configuration
bogdanm 0:9b334a45a8ff 6169 */
bogdanm 0:9b334a45a8ff 6170 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */
bogdanm 0:9b334a45a8ff 6171 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */
bogdanm 0:9b334a45a8ff 6172 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */
bogdanm 0:9b334a45a8ff 6173 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */
bogdanm 0:9b334a45a8ff 6174 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */
bogdanm 0:9b334a45a8ff 6175 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */
bogdanm 0:9b334a45a8ff 6176 #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */
bogdanm 0:9b334a45a8ff 6177 #define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */
bogdanm 0:9b334a45a8ff 6178
bogdanm 0:9b334a45a8ff 6179 /**
bogdanm 0:9b334a45a8ff 6180 * @brief EXTI14 configuration
bogdanm 0:9b334a45a8ff 6181 */
bogdanm 0:9b334a45a8ff 6182 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */
bogdanm 0:9b334a45a8ff 6183 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */
bogdanm 0:9b334a45a8ff 6184 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */
bogdanm 0:9b334a45a8ff 6185 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */
bogdanm 0:9b334a45a8ff 6186 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */
bogdanm 0:9b334a45a8ff 6187 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */
bogdanm 0:9b334a45a8ff 6188 #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */
bogdanm 0:9b334a45a8ff 6189 #define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */
bogdanm 0:9b334a45a8ff 6190
bogdanm 0:9b334a45a8ff 6191 /**
bogdanm 0:9b334a45a8ff 6192 * @brief EXTI15 configuration
bogdanm 0:9b334a45a8ff 6193 */
bogdanm 0:9b334a45a8ff 6194 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */
bogdanm 0:9b334a45a8ff 6195 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */
bogdanm 0:9b334a45a8ff 6196 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */
bogdanm 0:9b334a45a8ff 6197 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */
bogdanm 0:9b334a45a8ff 6198 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */
bogdanm 0:9b334a45a8ff 6199 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */
bogdanm 0:9b334a45a8ff 6200 #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */
bogdanm 0:9b334a45a8ff 6201 #define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */
bogdanm 0:9b334a45a8ff 6202
bogdanm 0:9b334a45a8ff 6203 /****************** Bit definition for SYSCFG_CMPCR register ****************/
bogdanm 0:9b334a45a8ff 6204 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
bogdanm 0:9b334a45a8ff 6205 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
bogdanm 0:9b334a45a8ff 6206
bogdanm 0:9b334a45a8ff 6207 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6208 /* */
bogdanm 0:9b334a45a8ff 6209 /* TIM */
bogdanm 0:9b334a45a8ff 6210 /* */
bogdanm 0:9b334a45a8ff 6211 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6212 /******************* Bit definition for TIM_CR1 register ********************/
bogdanm 0:9b334a45a8ff 6213 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
bogdanm 0:9b334a45a8ff 6214 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
bogdanm 0:9b334a45a8ff 6215 #define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
bogdanm 0:9b334a45a8ff 6216 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
bogdanm 0:9b334a45a8ff 6217 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
bogdanm 0:9b334a45a8ff 6218
bogdanm 0:9b334a45a8ff 6219 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
bogdanm 0:9b334a45a8ff 6220 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6221 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6222
bogdanm 0:9b334a45a8ff 6223 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
bogdanm 0:9b334a45a8ff 6224
bogdanm 0:9b334a45a8ff 6225 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
bogdanm 0:9b334a45a8ff 6226 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6227 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6228
bogdanm 0:9b334a45a8ff 6229 /******************* Bit definition for TIM_CR2 register ********************/
bogdanm 0:9b334a45a8ff 6230 #define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
bogdanm 0:9b334a45a8ff 6231 #define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
bogdanm 0:9b334a45a8ff 6232 #define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
bogdanm 0:9b334a45a8ff 6233
bogdanm 0:9b334a45a8ff 6234 #define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
bogdanm 0:9b334a45a8ff 6235 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6236 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6237 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6238
bogdanm 0:9b334a45a8ff 6239 #define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
bogdanm 0:9b334a45a8ff 6240 #define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
bogdanm 0:9b334a45a8ff 6241 #define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
bogdanm 0:9b334a45a8ff 6242 #define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
bogdanm 0:9b334a45a8ff 6243 #define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
bogdanm 0:9b334a45a8ff 6244 #define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
bogdanm 0:9b334a45a8ff 6245 #define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
bogdanm 0:9b334a45a8ff 6246 #define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
bogdanm 0:9b334a45a8ff 6247
bogdanm 0:9b334a45a8ff 6248 /******************* Bit definition for TIM_SMCR register *******************/
bogdanm 0:9b334a45a8ff 6249 #define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
bogdanm 0:9b334a45a8ff 6250 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6251 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6252 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6253
bogdanm 0:9b334a45a8ff 6254 #define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
bogdanm 0:9b334a45a8ff 6255 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6256 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6257 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6258
bogdanm 0:9b334a45a8ff 6259 #define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
bogdanm 0:9b334a45a8ff 6260
bogdanm 0:9b334a45a8ff 6261 #define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
bogdanm 0:9b334a45a8ff 6262 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6263 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6264 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6265 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6266
bogdanm 0:9b334a45a8ff 6267 #define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
bogdanm 0:9b334a45a8ff 6268 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6269 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6270
bogdanm 0:9b334a45a8ff 6271 #define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
bogdanm 0:9b334a45a8ff 6272 #define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
bogdanm 0:9b334a45a8ff 6273
bogdanm 0:9b334a45a8ff 6274 /******************* Bit definition for TIM_DIER register *******************/
bogdanm 0:9b334a45a8ff 6275 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
bogdanm 0:9b334a45a8ff 6276 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
bogdanm 0:9b334a45a8ff 6277 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
bogdanm 0:9b334a45a8ff 6278 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
bogdanm 0:9b334a45a8ff 6279 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
bogdanm 0:9b334a45a8ff 6280 #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
bogdanm 0:9b334a45a8ff 6281 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
bogdanm 0:9b334a45a8ff 6282 #define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
bogdanm 0:9b334a45a8ff 6283 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
bogdanm 0:9b334a45a8ff 6284 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
bogdanm 0:9b334a45a8ff 6285 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
bogdanm 0:9b334a45a8ff 6286 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
bogdanm 0:9b334a45a8ff 6287 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
bogdanm 0:9b334a45a8ff 6288 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
bogdanm 0:9b334a45a8ff 6289 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
bogdanm 0:9b334a45a8ff 6290
bogdanm 0:9b334a45a8ff 6291 /******************** Bit definition for TIM_SR register ********************/
bogdanm 0:9b334a45a8ff 6292 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
bogdanm 0:9b334a45a8ff 6293 #define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
bogdanm 0:9b334a45a8ff 6294 #define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
bogdanm 0:9b334a45a8ff 6295 #define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
bogdanm 0:9b334a45a8ff 6296 #define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
bogdanm 0:9b334a45a8ff 6297 #define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
bogdanm 0:9b334a45a8ff 6298 #define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
bogdanm 0:9b334a45a8ff 6299 #define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
bogdanm 0:9b334a45a8ff 6300 #define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
bogdanm 0:9b334a45a8ff 6301 #define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
bogdanm 0:9b334a45a8ff 6302 #define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
bogdanm 0:9b334a45a8ff 6303 #define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
bogdanm 0:9b334a45a8ff 6304
bogdanm 0:9b334a45a8ff 6305 /******************* Bit definition for TIM_EGR register ********************/
bogdanm 0:9b334a45a8ff 6306 #define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
bogdanm 0:9b334a45a8ff 6307 #define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
bogdanm 0:9b334a45a8ff 6308 #define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
bogdanm 0:9b334a45a8ff 6309 #define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
bogdanm 0:9b334a45a8ff 6310 #define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
bogdanm 0:9b334a45a8ff 6311 #define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
bogdanm 0:9b334a45a8ff 6312 #define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
bogdanm 0:9b334a45a8ff 6313 #define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
bogdanm 0:9b334a45a8ff 6314
bogdanm 0:9b334a45a8ff 6315 /****************** Bit definition for TIM_CCMR1 register *******************/
bogdanm 0:9b334a45a8ff 6316 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
bogdanm 0:9b334a45a8ff 6317 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6318 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6319
bogdanm 0:9b334a45a8ff 6320 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
bogdanm 0:9b334a45a8ff 6321 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
bogdanm 0:9b334a45a8ff 6322
bogdanm 0:9b334a45a8ff 6323 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
bogdanm 0:9b334a45a8ff 6324 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6325 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6326 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6327
bogdanm 0:9b334a45a8ff 6328 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
bogdanm 0:9b334a45a8ff 6329
bogdanm 0:9b334a45a8ff 6330 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
bogdanm 0:9b334a45a8ff 6331 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6332 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6333
bogdanm 0:9b334a45a8ff 6334 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
bogdanm 0:9b334a45a8ff 6335 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
bogdanm 0:9b334a45a8ff 6336
bogdanm 0:9b334a45a8ff 6337 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
bogdanm 0:9b334a45a8ff 6338 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6339 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6340 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6341
bogdanm 0:9b334a45a8ff 6342 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
bogdanm 0:9b334a45a8ff 6343
bogdanm 0:9b334a45a8ff 6344 /*----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 6345
bogdanm 0:9b334a45a8ff 6346 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
bogdanm 0:9b334a45a8ff 6347 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6348 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6349
bogdanm 0:9b334a45a8ff 6350 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
bogdanm 0:9b334a45a8ff 6351 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6352 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6353 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6354 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6355
bogdanm 0:9b334a45a8ff 6356 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
bogdanm 0:9b334a45a8ff 6357 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6358 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6359
bogdanm 0:9b334a45a8ff 6360 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
bogdanm 0:9b334a45a8ff 6361 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6362 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6363 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6364 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6365
bogdanm 0:9b334a45a8ff 6366 /****************** Bit definition for TIM_CCMR2 register *******************/
bogdanm 0:9b334a45a8ff 6367 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
bogdanm 0:9b334a45a8ff 6368 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6369 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6370
bogdanm 0:9b334a45a8ff 6371 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
bogdanm 0:9b334a45a8ff 6372 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
bogdanm 0:9b334a45a8ff 6373
bogdanm 0:9b334a45a8ff 6374 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
bogdanm 0:9b334a45a8ff 6375 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6376 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6377 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6378
bogdanm 0:9b334a45a8ff 6379 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
bogdanm 0:9b334a45a8ff 6380
bogdanm 0:9b334a45a8ff 6381 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
bogdanm 0:9b334a45a8ff 6382 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6383 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6384
bogdanm 0:9b334a45a8ff 6385 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
bogdanm 0:9b334a45a8ff 6386 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
bogdanm 0:9b334a45a8ff 6387
bogdanm 0:9b334a45a8ff 6388 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
bogdanm 0:9b334a45a8ff 6389 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6390 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6391 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6392
bogdanm 0:9b334a45a8ff 6393 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
bogdanm 0:9b334a45a8ff 6394
bogdanm 0:9b334a45a8ff 6395 /*----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 6396
bogdanm 0:9b334a45a8ff 6397 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
bogdanm 0:9b334a45a8ff 6398 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6399 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6400
bogdanm 0:9b334a45a8ff 6401 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
bogdanm 0:9b334a45a8ff 6402 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6403 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6404 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6405 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6406
bogdanm 0:9b334a45a8ff 6407 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
bogdanm 0:9b334a45a8ff 6408 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6409 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6410
bogdanm 0:9b334a45a8ff 6411 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
bogdanm 0:9b334a45a8ff 6412 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6413 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6414 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6415 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6416
bogdanm 0:9b334a45a8ff 6417 /******************* Bit definition for TIM_CCER register *******************/
bogdanm 0:9b334a45a8ff 6418 #define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
bogdanm 0:9b334a45a8ff 6419 #define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
bogdanm 0:9b334a45a8ff 6420 #define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
bogdanm 0:9b334a45a8ff 6421 #define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 6422 #define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
bogdanm 0:9b334a45a8ff 6423 #define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
bogdanm 0:9b334a45a8ff 6424 #define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
bogdanm 0:9b334a45a8ff 6425 #define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 6426 #define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
bogdanm 0:9b334a45a8ff 6427 #define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
bogdanm 0:9b334a45a8ff 6428 #define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
bogdanm 0:9b334a45a8ff 6429 #define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 6430 #define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
bogdanm 0:9b334a45a8ff 6431 #define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
bogdanm 0:9b334a45a8ff 6432 #define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 6433
bogdanm 0:9b334a45a8ff 6434 /******************* Bit definition for TIM_CNT register ********************/
bogdanm 0:9b334a45a8ff 6435 #define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
bogdanm 0:9b334a45a8ff 6436
bogdanm 0:9b334a45a8ff 6437 /******************* Bit definition for TIM_PSC register ********************/
bogdanm 0:9b334a45a8ff 6438 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
bogdanm 0:9b334a45a8ff 6439
bogdanm 0:9b334a45a8ff 6440 /******************* Bit definition for TIM_ARR register ********************/
bogdanm 0:9b334a45a8ff 6441 #define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
bogdanm 0:9b334a45a8ff 6442
bogdanm 0:9b334a45a8ff 6443 /******************* Bit definition for TIM_RCR register ********************/
bogdanm 0:9b334a45a8ff 6444 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
bogdanm 0:9b334a45a8ff 6445
bogdanm 0:9b334a45a8ff 6446 /******************* Bit definition for TIM_CCR1 register *******************/
bogdanm 0:9b334a45a8ff 6447 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
bogdanm 0:9b334a45a8ff 6448
bogdanm 0:9b334a45a8ff 6449 /******************* Bit definition for TIM_CCR2 register *******************/
bogdanm 0:9b334a45a8ff 6450 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
bogdanm 0:9b334a45a8ff 6451
bogdanm 0:9b334a45a8ff 6452 /******************* Bit definition for TIM_CCR3 register *******************/
bogdanm 0:9b334a45a8ff 6453 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
bogdanm 0:9b334a45a8ff 6454
bogdanm 0:9b334a45a8ff 6455 /******************* Bit definition for TIM_CCR4 register *******************/
bogdanm 0:9b334a45a8ff 6456 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
bogdanm 0:9b334a45a8ff 6457
bogdanm 0:9b334a45a8ff 6458 /******************* Bit definition for TIM_BDTR register *******************/
bogdanm 0:9b334a45a8ff 6459 #define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
bogdanm 0:9b334a45a8ff 6460 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6461 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6462 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6463 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6464 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 6465 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 6466 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 6467 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 6468
bogdanm 0:9b334a45a8ff 6469 #define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
bogdanm 0:9b334a45a8ff 6470 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6471 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6472
bogdanm 0:9b334a45a8ff 6473 #define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
bogdanm 0:9b334a45a8ff 6474 #define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
bogdanm 0:9b334a45a8ff 6475 #define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
bogdanm 0:9b334a45a8ff 6476 #define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
bogdanm 0:9b334a45a8ff 6477 #define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
bogdanm 0:9b334a45a8ff 6478 #define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
bogdanm 0:9b334a45a8ff 6479
bogdanm 0:9b334a45a8ff 6480 /******************* Bit definition for TIM_DCR register ********************/
bogdanm 0:9b334a45a8ff 6481 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
bogdanm 0:9b334a45a8ff 6482 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6483 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6484 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6485 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6486 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 6487
bogdanm 0:9b334a45a8ff 6488 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
bogdanm 0:9b334a45a8ff 6489 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6490 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6491 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6492 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6493 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 6494
bogdanm 0:9b334a45a8ff 6495 /******************* Bit definition for TIM_DMAR register *******************/
bogdanm 0:9b334a45a8ff 6496 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
bogdanm 0:9b334a45a8ff 6497
bogdanm 0:9b334a45a8ff 6498 /******************* Bit definition for TIM_OR register *********************/
bogdanm 0:9b334a45a8ff 6499 #define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
bogdanm 0:9b334a45a8ff 6500 #define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6501 #define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6502 #define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
bogdanm 0:9b334a45a8ff 6503 #define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6504 #define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6505
bogdanm 0:9b334a45a8ff 6506
bogdanm 0:9b334a45a8ff 6507 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6508 /* */
bogdanm 0:9b334a45a8ff 6509 /* Universal Synchronous Asynchronous Receiver Transmitter */
bogdanm 0:9b334a45a8ff 6510 /* */
bogdanm 0:9b334a45a8ff 6511 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6512 /******************* Bit definition for USART_SR register *******************/
bogdanm 0:9b334a45a8ff 6513 #define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
bogdanm 0:9b334a45a8ff 6514 #define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
bogdanm 0:9b334a45a8ff 6515 #define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
bogdanm 0:9b334a45a8ff 6516 #define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
bogdanm 0:9b334a45a8ff 6517 #define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
bogdanm 0:9b334a45a8ff 6518 #define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
bogdanm 0:9b334a45a8ff 6519 #define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
bogdanm 0:9b334a45a8ff 6520 #define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
bogdanm 0:9b334a45a8ff 6521 #define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
bogdanm 0:9b334a45a8ff 6522 #define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
bogdanm 0:9b334a45a8ff 6523
bogdanm 0:9b334a45a8ff 6524 /******************* Bit definition for USART_DR register *******************/
bogdanm 0:9b334a45a8ff 6525 #define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
bogdanm 0:9b334a45a8ff 6526
bogdanm 0:9b334a45a8ff 6527 /****************** Bit definition for USART_BRR register *******************/
bogdanm 0:9b334a45a8ff 6528 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
bogdanm 0:9b334a45a8ff 6529 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
bogdanm 0:9b334a45a8ff 6530
bogdanm 0:9b334a45a8ff 6531 /****************** Bit definition for USART_CR1 register *******************/
bogdanm 0:9b334a45a8ff 6532 #define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
bogdanm 0:9b334a45a8ff 6533 #define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
bogdanm 0:9b334a45a8ff 6534 #define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
bogdanm 0:9b334a45a8ff 6535 #define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
bogdanm 0:9b334a45a8ff 6536 #define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
bogdanm 0:9b334a45a8ff 6537 #define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
bogdanm 0:9b334a45a8ff 6538 #define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
bogdanm 0:9b334a45a8ff 6539 #define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
bogdanm 0:9b334a45a8ff 6540 #define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
bogdanm 0:9b334a45a8ff 6541 #define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
bogdanm 0:9b334a45a8ff 6542 #define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
bogdanm 0:9b334a45a8ff 6543 #define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
bogdanm 0:9b334a45a8ff 6544 #define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
bogdanm 0:9b334a45a8ff 6545 #define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
bogdanm 0:9b334a45a8ff 6546 #define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversampling by 8 enable */
bogdanm 0:9b334a45a8ff 6547
bogdanm 0:9b334a45a8ff 6548 /****************** Bit definition for USART_CR2 register *******************/
bogdanm 0:9b334a45a8ff 6549 #define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
bogdanm 0:9b334a45a8ff 6550 #define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
bogdanm 0:9b334a45a8ff 6551 #define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
bogdanm 0:9b334a45a8ff 6552 #define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
bogdanm 0:9b334a45a8ff 6553 #define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
bogdanm 0:9b334a45a8ff 6554 #define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
bogdanm 0:9b334a45a8ff 6555 #define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
bogdanm 0:9b334a45a8ff 6556
bogdanm 0:9b334a45a8ff 6557 #define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
bogdanm 0:9b334a45a8ff 6558 #define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6559 #define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6560
bogdanm 0:9b334a45a8ff 6561 #define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
bogdanm 0:9b334a45a8ff 6562
bogdanm 0:9b334a45a8ff 6563 /****************** Bit definition for USART_CR3 register *******************/
bogdanm 0:9b334a45a8ff 6564 #define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 6565 #define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
bogdanm 0:9b334a45a8ff 6566 #define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
bogdanm 0:9b334a45a8ff 6567 #define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
bogdanm 0:9b334a45a8ff 6568 #define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
bogdanm 0:9b334a45a8ff 6569 #define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
bogdanm 0:9b334a45a8ff 6570 #define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
bogdanm 0:9b334a45a8ff 6571 #define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
bogdanm 0:9b334a45a8ff 6572 #define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
bogdanm 0:9b334a45a8ff 6573 #define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
bogdanm 0:9b334a45a8ff 6574 #define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
bogdanm 0:9b334a45a8ff 6575 #define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<USART One bit method enable */
bogdanm 0:9b334a45a8ff 6576
bogdanm 0:9b334a45a8ff 6577 /****************** Bit definition for USART_GTPR register ******************/
bogdanm 0:9b334a45a8ff 6578 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
bogdanm 0:9b334a45a8ff 6579 #define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6580 #define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6581 #define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6582 #define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6583 #define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 6584 #define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 6585 #define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 6586 #define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 6587
bogdanm 0:9b334a45a8ff 6588 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
bogdanm 0:9b334a45a8ff 6589
bogdanm 0:9b334a45a8ff 6590 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6591 /* */
bogdanm 0:9b334a45a8ff 6592 /* Window WATCHDOG */
bogdanm 0:9b334a45a8ff 6593 /* */
bogdanm 0:9b334a45a8ff 6594 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6595 /******************* Bit definition for WWDG_CR register ********************/
bogdanm 0:9b334a45a8ff 6596 #define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
bogdanm 0:9b334a45a8ff 6597 #define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6598 #define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6599 #define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6600 #define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6601 #define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 6602 #define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 6603 #define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 6604
bogdanm 0:9b334a45a8ff 6605 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
bogdanm 0:9b334a45a8ff 6606
bogdanm 0:9b334a45a8ff 6607 /******************* Bit definition for WWDG_CFR register *******************/
bogdanm 0:9b334a45a8ff 6608 #define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
bogdanm 0:9b334a45a8ff 6609 #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6610 #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6611 #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 6612 #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 6613 #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 6614 #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 6615 #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 6616
bogdanm 0:9b334a45a8ff 6617 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
bogdanm 0:9b334a45a8ff 6618 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6619 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6620
bogdanm 0:9b334a45a8ff 6621 #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
bogdanm 0:9b334a45a8ff 6622
bogdanm 0:9b334a45a8ff 6623 /******************* Bit definition for WWDG_SR register ********************/
bogdanm 0:9b334a45a8ff 6624 #define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
bogdanm 0:9b334a45a8ff 6625
bogdanm 0:9b334a45a8ff 6626
bogdanm 0:9b334a45a8ff 6627 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6628 /* */
bogdanm 0:9b334a45a8ff 6629 /* DBG */
bogdanm 0:9b334a45a8ff 6630 /* */
bogdanm 0:9b334a45a8ff 6631 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6632 /******************** Bit definition for DBGMCU_IDCODE register *************/
bogdanm 0:9b334a45a8ff 6633 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
bogdanm 0:9b334a45a8ff 6634 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
bogdanm 0:9b334a45a8ff 6635
bogdanm 0:9b334a45a8ff 6636 /******************** Bit definition for DBGMCU_CR register *****************/
bogdanm 0:9b334a45a8ff 6637 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 6638 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 6639 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 6640 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 6641
bogdanm 0:9b334a45a8ff 6642 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 6643 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
bogdanm 0:9b334a45a8ff 6644 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
bogdanm 0:9b334a45a8ff 6645
bogdanm 0:9b334a45a8ff 6646 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
bogdanm 0:9b334a45a8ff 6647 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 6648 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 6649 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 6650 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 6651 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 6652 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 6653 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 6654 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 6655 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 6656 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 6657 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 6658 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 6659 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 6660 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 6661 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 6662 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 6663 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 6664 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 6665 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
bogdanm 0:9b334a45a8ff 6666
bogdanm 0:9b334a45a8ff 6667 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
bogdanm 0:9b334a45a8ff 6668 #define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 6669 #define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 6670 #define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 6671 #define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 6672 #define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 6673
bogdanm 0:9b334a45a8ff 6674 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6675 /* */
bogdanm 0:9b334a45a8ff 6676 /* Ethernet MAC Registers bits definitions */
bogdanm 0:9b334a45a8ff 6677 /* */
bogdanm 0:9b334a45a8ff 6678 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6679 /* Bit definition for Ethernet MAC Control Register register */
bogdanm 0:9b334a45a8ff 6680 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
bogdanm 0:9b334a45a8ff 6681 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
bogdanm 0:9b334a45a8ff 6682 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
bogdanm 0:9b334a45a8ff 6683 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
bogdanm 0:9b334a45a8ff 6684 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
bogdanm 0:9b334a45a8ff 6685 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
bogdanm 0:9b334a45a8ff 6686 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
bogdanm 0:9b334a45a8ff 6687 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
bogdanm 0:9b334a45a8ff 6688 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
bogdanm 0:9b334a45a8ff 6689 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
bogdanm 0:9b334a45a8ff 6690 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
bogdanm 0:9b334a45a8ff 6691 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
bogdanm 0:9b334a45a8ff 6692 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
bogdanm 0:9b334a45a8ff 6693 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
bogdanm 0:9b334a45a8ff 6694 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
bogdanm 0:9b334a45a8ff 6695 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
bogdanm 0:9b334a45a8ff 6696 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
bogdanm 0:9b334a45a8ff 6697 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
bogdanm 0:9b334a45a8ff 6698 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
bogdanm 0:9b334a45a8ff 6699 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
bogdanm 0:9b334a45a8ff 6700 a transmission attempt during retries after a collision: 0 =< r <2^k */
bogdanm 0:9b334a45a8ff 6701 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
bogdanm 0:9b334a45a8ff 6702 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
bogdanm 0:9b334a45a8ff 6703 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
bogdanm 0:9b334a45a8ff 6704 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
bogdanm 0:9b334a45a8ff 6705 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
bogdanm 0:9b334a45a8ff 6706 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
bogdanm 0:9b334a45a8ff 6707 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
bogdanm 0:9b334a45a8ff 6708
bogdanm 0:9b334a45a8ff 6709 /* Bit definition for Ethernet MAC Frame Filter Register */
bogdanm 0:9b334a45a8ff 6710 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
bogdanm 0:9b334a45a8ff 6711 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
bogdanm 0:9b334a45a8ff 6712 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
bogdanm 0:9b334a45a8ff 6713 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
bogdanm 0:9b334a45a8ff 6714 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
bogdanm 0:9b334a45a8ff 6715 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
bogdanm 0:9b334a45a8ff 6716 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
bogdanm 0:9b334a45a8ff 6717 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
bogdanm 0:9b334a45a8ff 6718 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
bogdanm 0:9b334a45a8ff 6719 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
bogdanm 0:9b334a45a8ff 6720 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
bogdanm 0:9b334a45a8ff 6721 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
bogdanm 0:9b334a45a8ff 6722 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
bogdanm 0:9b334a45a8ff 6723 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
bogdanm 0:9b334a45a8ff 6724
bogdanm 0:9b334a45a8ff 6725 /* Bit definition for Ethernet MAC Hash Table High Register */
bogdanm 0:9b334a45a8ff 6726 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
bogdanm 0:9b334a45a8ff 6727
bogdanm 0:9b334a45a8ff 6728 /* Bit definition for Ethernet MAC Hash Table Low Register */
bogdanm 0:9b334a45a8ff 6729 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
bogdanm 0:9b334a45a8ff 6730
bogdanm 0:9b334a45a8ff 6731 /* Bit definition for Ethernet MAC MII Address Register */
bogdanm 0:9b334a45a8ff 6732 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
bogdanm 0:9b334a45a8ff 6733 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
bogdanm 0:9b334a45a8ff 6734 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
bogdanm 0:9b334a45a8ff 6735 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
bogdanm 0:9b334a45a8ff 6736 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
bogdanm 0:9b334a45a8ff 6737 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
bogdanm 0:9b334a45a8ff 6738 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
bogdanm 0:9b334a45a8ff 6739 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
bogdanm 0:9b334a45a8ff 6740 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
bogdanm 0:9b334a45a8ff 6741 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
bogdanm 0:9b334a45a8ff 6742
bogdanm 0:9b334a45a8ff 6743 /* Bit definition for Ethernet MAC MII Data Register */
bogdanm 0:9b334a45a8ff 6744 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
bogdanm 0:9b334a45a8ff 6745
bogdanm 0:9b334a45a8ff 6746 /* Bit definition for Ethernet MAC Flow Control Register */
bogdanm 0:9b334a45a8ff 6747 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
bogdanm 0:9b334a45a8ff 6748 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
bogdanm 0:9b334a45a8ff 6749 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
bogdanm 0:9b334a45a8ff 6750 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
bogdanm 0:9b334a45a8ff 6751 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
bogdanm 0:9b334a45a8ff 6752 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
bogdanm 0:9b334a45a8ff 6753 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
bogdanm 0:9b334a45a8ff 6754 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
bogdanm 0:9b334a45a8ff 6755 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
bogdanm 0:9b334a45a8ff 6756 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
bogdanm 0:9b334a45a8ff 6757 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
bogdanm 0:9b334a45a8ff 6758
bogdanm 0:9b334a45a8ff 6759 /* Bit definition for Ethernet MAC VLAN Tag Register */
bogdanm 0:9b334a45a8ff 6760 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
bogdanm 0:9b334a45a8ff 6761 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
bogdanm 0:9b334a45a8ff 6762
bogdanm 0:9b334a45a8ff 6763 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
bogdanm 0:9b334a45a8ff 6764 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
bogdanm 0:9b334a45a8ff 6765 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
bogdanm 0:9b334a45a8ff 6766 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
bogdanm 0:9b334a45a8ff 6767 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
bogdanm 0:9b334a45a8ff 6768 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
bogdanm 0:9b334a45a8ff 6769 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
bogdanm 0:9b334a45a8ff 6770 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
bogdanm 0:9b334a45a8ff 6771 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
bogdanm 0:9b334a45a8ff 6772 RSVD - Filter1 Command - RSVD - Filter0 Command
bogdanm 0:9b334a45a8ff 6773 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
bogdanm 0:9b334a45a8ff 6774 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
bogdanm 0:9b334a45a8ff 6775 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
bogdanm 0:9b334a45a8ff 6776
bogdanm 0:9b334a45a8ff 6777 /* Bit definition for Ethernet MAC PMT Control and Status Register */
bogdanm 0:9b334a45a8ff 6778 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
bogdanm 0:9b334a45a8ff 6779 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
bogdanm 0:9b334a45a8ff 6780 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
bogdanm 0:9b334a45a8ff 6781 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
bogdanm 0:9b334a45a8ff 6782 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
bogdanm 0:9b334a45a8ff 6783 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
bogdanm 0:9b334a45a8ff 6784 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
bogdanm 0:9b334a45a8ff 6785
bogdanm 0:9b334a45a8ff 6786 /* Bit definition for Ethernet MAC Status Register */
bogdanm 0:9b334a45a8ff 6787 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
bogdanm 0:9b334a45a8ff 6788 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
bogdanm 0:9b334a45a8ff 6789 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
bogdanm 0:9b334a45a8ff 6790 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
bogdanm 0:9b334a45a8ff 6791 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
bogdanm 0:9b334a45a8ff 6792
bogdanm 0:9b334a45a8ff 6793 /* Bit definition for Ethernet MAC Interrupt Mask Register */
bogdanm 0:9b334a45a8ff 6794 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
bogdanm 0:9b334a45a8ff 6795 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
bogdanm 0:9b334a45a8ff 6796
bogdanm 0:9b334a45a8ff 6797 /* Bit definition for Ethernet MAC Address0 High Register */
bogdanm 0:9b334a45a8ff 6798 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
bogdanm 0:9b334a45a8ff 6799
bogdanm 0:9b334a45a8ff 6800 /* Bit definition for Ethernet MAC Address0 Low Register */
bogdanm 0:9b334a45a8ff 6801 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
bogdanm 0:9b334a45a8ff 6802
bogdanm 0:9b334a45a8ff 6803 /* Bit definition for Ethernet MAC Address1 High Register */
bogdanm 0:9b334a45a8ff 6804 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
bogdanm 0:9b334a45a8ff 6805 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
bogdanm 0:9b334a45a8ff 6806 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
bogdanm 0:9b334a45a8ff 6807 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
bogdanm 0:9b334a45a8ff 6808 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
bogdanm 0:9b334a45a8ff 6809 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
bogdanm 0:9b334a45a8ff 6810 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
bogdanm 0:9b334a45a8ff 6811 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
bogdanm 0:9b334a45a8ff 6812 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
bogdanm 0:9b334a45a8ff 6813 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
bogdanm 0:9b334a45a8ff 6814
bogdanm 0:9b334a45a8ff 6815 /* Bit definition for Ethernet MAC Address1 Low Register */
bogdanm 0:9b334a45a8ff 6816 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
bogdanm 0:9b334a45a8ff 6817
bogdanm 0:9b334a45a8ff 6818 /* Bit definition for Ethernet MAC Address2 High Register */
bogdanm 0:9b334a45a8ff 6819 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
bogdanm 0:9b334a45a8ff 6820 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
bogdanm 0:9b334a45a8ff 6821 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
bogdanm 0:9b334a45a8ff 6822 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
bogdanm 0:9b334a45a8ff 6823 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
bogdanm 0:9b334a45a8ff 6824 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
bogdanm 0:9b334a45a8ff 6825 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
bogdanm 0:9b334a45a8ff 6826 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
bogdanm 0:9b334a45a8ff 6827 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
bogdanm 0:9b334a45a8ff 6828 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
bogdanm 0:9b334a45a8ff 6829
bogdanm 0:9b334a45a8ff 6830 /* Bit definition for Ethernet MAC Address2 Low Register */
bogdanm 0:9b334a45a8ff 6831 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
bogdanm 0:9b334a45a8ff 6832
bogdanm 0:9b334a45a8ff 6833 /* Bit definition for Ethernet MAC Address3 High Register */
bogdanm 0:9b334a45a8ff 6834 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
bogdanm 0:9b334a45a8ff 6835 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
bogdanm 0:9b334a45a8ff 6836 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
bogdanm 0:9b334a45a8ff 6837 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
bogdanm 0:9b334a45a8ff 6838 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
bogdanm 0:9b334a45a8ff 6839 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
bogdanm 0:9b334a45a8ff 6840 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
bogdanm 0:9b334a45a8ff 6841 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
bogdanm 0:9b334a45a8ff 6842 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
bogdanm 0:9b334a45a8ff 6843 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
bogdanm 0:9b334a45a8ff 6844
bogdanm 0:9b334a45a8ff 6845 /* Bit definition for Ethernet MAC Address3 Low Register */
bogdanm 0:9b334a45a8ff 6846 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
bogdanm 0:9b334a45a8ff 6847
bogdanm 0:9b334a45a8ff 6848 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6849 /* Ethernet MMC Registers bits definition */
bogdanm 0:9b334a45a8ff 6850 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6851
bogdanm 0:9b334a45a8ff 6852 /* Bit definition for Ethernet MMC Contol Register */
bogdanm 0:9b334a45a8ff 6853 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
bogdanm 0:9b334a45a8ff 6854 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
bogdanm 0:9b334a45a8ff 6855 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
bogdanm 0:9b334a45a8ff 6856 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
bogdanm 0:9b334a45a8ff 6857 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
bogdanm 0:9b334a45a8ff 6858 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
bogdanm 0:9b334a45a8ff 6859
bogdanm 0:9b334a45a8ff 6860 /* Bit definition for Ethernet MMC Receive Interrupt Register */
bogdanm 0:9b334a45a8ff 6861 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
bogdanm 0:9b334a45a8ff 6862 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
bogdanm 0:9b334a45a8ff 6863 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
bogdanm 0:9b334a45a8ff 6864
bogdanm 0:9b334a45a8ff 6865 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
bogdanm 0:9b334a45a8ff 6866 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
bogdanm 0:9b334a45a8ff 6867 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
bogdanm 0:9b334a45a8ff 6868 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
bogdanm 0:9b334a45a8ff 6869
bogdanm 0:9b334a45a8ff 6870 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
bogdanm 0:9b334a45a8ff 6871 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
bogdanm 0:9b334a45a8ff 6872 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
bogdanm 0:9b334a45a8ff 6873 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
bogdanm 0:9b334a45a8ff 6874
bogdanm 0:9b334a45a8ff 6875 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
bogdanm 0:9b334a45a8ff 6876 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
bogdanm 0:9b334a45a8ff 6877 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
bogdanm 0:9b334a45a8ff 6878 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
bogdanm 0:9b334a45a8ff 6879
bogdanm 0:9b334a45a8ff 6880 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
bogdanm 0:9b334a45a8ff 6881 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
bogdanm 0:9b334a45a8ff 6882
bogdanm 0:9b334a45a8ff 6883 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
bogdanm 0:9b334a45a8ff 6884 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
bogdanm 0:9b334a45a8ff 6885
bogdanm 0:9b334a45a8ff 6886 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
bogdanm 0:9b334a45a8ff 6887 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
bogdanm 0:9b334a45a8ff 6888
bogdanm 0:9b334a45a8ff 6889 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
bogdanm 0:9b334a45a8ff 6890 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
bogdanm 0:9b334a45a8ff 6891
bogdanm 0:9b334a45a8ff 6892 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
bogdanm 0:9b334a45a8ff 6893 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
bogdanm 0:9b334a45a8ff 6894
bogdanm 0:9b334a45a8ff 6895 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
bogdanm 0:9b334a45a8ff 6896 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
bogdanm 0:9b334a45a8ff 6897
bogdanm 0:9b334a45a8ff 6898 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6899 /* Ethernet PTP Registers bits definition */
bogdanm 0:9b334a45a8ff 6900 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6901
bogdanm 0:9b334a45a8ff 6902 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
bogdanm 0:9b334a45a8ff 6903 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
bogdanm 0:9b334a45a8ff 6904 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
bogdanm 0:9b334a45a8ff 6905 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
bogdanm 0:9b334a45a8ff 6906 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
bogdanm 0:9b334a45a8ff 6907 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
bogdanm 0:9b334a45a8ff 6908 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
bogdanm 0:9b334a45a8ff 6909 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
bogdanm 0:9b334a45a8ff 6910 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
bogdanm 0:9b334a45a8ff 6911 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
bogdanm 0:9b334a45a8ff 6912
bogdanm 0:9b334a45a8ff 6913 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
bogdanm 0:9b334a45a8ff 6914 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
bogdanm 0:9b334a45a8ff 6915 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
bogdanm 0:9b334a45a8ff 6916 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
bogdanm 0:9b334a45a8ff 6917 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
bogdanm 0:9b334a45a8ff 6918 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
bogdanm 0:9b334a45a8ff 6919
bogdanm 0:9b334a45a8ff 6920 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
bogdanm 0:9b334a45a8ff 6921 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
bogdanm 0:9b334a45a8ff 6922
bogdanm 0:9b334a45a8ff 6923 /* Bit definition for Ethernet PTP Time Stamp High Register */
bogdanm 0:9b334a45a8ff 6924 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
bogdanm 0:9b334a45a8ff 6925
bogdanm 0:9b334a45a8ff 6926 /* Bit definition for Ethernet PTP Time Stamp Low Register */
bogdanm 0:9b334a45a8ff 6927 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
bogdanm 0:9b334a45a8ff 6928 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
bogdanm 0:9b334a45a8ff 6929
bogdanm 0:9b334a45a8ff 6930 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
bogdanm 0:9b334a45a8ff 6931 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
bogdanm 0:9b334a45a8ff 6932
bogdanm 0:9b334a45a8ff 6933 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
bogdanm 0:9b334a45a8ff 6934 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
bogdanm 0:9b334a45a8ff 6935 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
bogdanm 0:9b334a45a8ff 6936
bogdanm 0:9b334a45a8ff 6937 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
bogdanm 0:9b334a45a8ff 6938 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
bogdanm 0:9b334a45a8ff 6939
bogdanm 0:9b334a45a8ff 6940 /* Bit definition for Ethernet PTP Target Time High Register */
bogdanm 0:9b334a45a8ff 6941 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
bogdanm 0:9b334a45a8ff 6942
bogdanm 0:9b334a45a8ff 6943 /* Bit definition for Ethernet PTP Target Time Low Register */
bogdanm 0:9b334a45a8ff 6944 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
bogdanm 0:9b334a45a8ff 6945
bogdanm 0:9b334a45a8ff 6946 /* Bit definition for Ethernet PTP Time Stamp Status Register */
bogdanm 0:9b334a45a8ff 6947 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
bogdanm 0:9b334a45a8ff 6948 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
bogdanm 0:9b334a45a8ff 6949
bogdanm 0:9b334a45a8ff 6950 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6951 /* Ethernet DMA Registers bits definition */
bogdanm 0:9b334a45a8ff 6952 /******************************************************************************/
bogdanm 0:9b334a45a8ff 6953
bogdanm 0:9b334a45a8ff 6954 /* Bit definition for Ethernet DMA Bus Mode Register */
bogdanm 0:9b334a45a8ff 6955 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
bogdanm 0:9b334a45a8ff 6956 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
bogdanm 0:9b334a45a8ff 6957 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
bogdanm 0:9b334a45a8ff 6958 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
bogdanm 0:9b334a45a8ff 6959 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
bogdanm 0:9b334a45a8ff 6960 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
bogdanm 0:9b334a45a8ff 6961 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
bogdanm 0:9b334a45a8ff 6962 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
bogdanm 0:9b334a45a8ff 6963 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
bogdanm 0:9b334a45a8ff 6964 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
bogdanm 0:9b334a45a8ff 6965 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
bogdanm 0:9b334a45a8ff 6966 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
bogdanm 0:9b334a45a8ff 6967 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
bogdanm 0:9b334a45a8ff 6968 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
bogdanm 0:9b334a45a8ff 6969 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
bogdanm 0:9b334a45a8ff 6970 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
bogdanm 0:9b334a45a8ff 6971 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
bogdanm 0:9b334a45a8ff 6972 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
bogdanm 0:9b334a45a8ff 6973 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
bogdanm 0:9b334a45a8ff 6974 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
bogdanm 0:9b334a45a8ff 6975 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
bogdanm 0:9b334a45a8ff 6976 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
bogdanm 0:9b334a45a8ff 6977 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
bogdanm 0:9b334a45a8ff 6978 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
bogdanm 0:9b334a45a8ff 6979 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
bogdanm 0:9b334a45a8ff 6980 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
bogdanm 0:9b334a45a8ff 6981 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
bogdanm 0:9b334a45a8ff 6982 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
bogdanm 0:9b334a45a8ff 6983 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
bogdanm 0:9b334a45a8ff 6984 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
bogdanm 0:9b334a45a8ff 6985 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
bogdanm 0:9b334a45a8ff 6986 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
bogdanm 0:9b334a45a8ff 6987 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
bogdanm 0:9b334a45a8ff 6988 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
bogdanm 0:9b334a45a8ff 6989 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
bogdanm 0:9b334a45a8ff 6990 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
bogdanm 0:9b334a45a8ff 6991 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
bogdanm 0:9b334a45a8ff 6992 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
bogdanm 0:9b334a45a8ff 6993 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
bogdanm 0:9b334a45a8ff 6994
bogdanm 0:9b334a45a8ff 6995 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
bogdanm 0:9b334a45a8ff 6996 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
bogdanm 0:9b334a45a8ff 6997
bogdanm 0:9b334a45a8ff 6998 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
bogdanm 0:9b334a45a8ff 6999 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
bogdanm 0:9b334a45a8ff 7000
bogdanm 0:9b334a45a8ff 7001 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
bogdanm 0:9b334a45a8ff 7002 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
bogdanm 0:9b334a45a8ff 7003
bogdanm 0:9b334a45a8ff 7004 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
bogdanm 0:9b334a45a8ff 7005 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
bogdanm 0:9b334a45a8ff 7006
bogdanm 0:9b334a45a8ff 7007 /* Bit definition for Ethernet DMA Status Register */
bogdanm 0:9b334a45a8ff 7008 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
bogdanm 0:9b334a45a8ff 7009 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
bogdanm 0:9b334a45a8ff 7010 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
bogdanm 0:9b334a45a8ff 7011 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
bogdanm 0:9b334a45a8ff 7012 /* combination with EBS[2:0] for GetFlagStatus function */
bogdanm 0:9b334a45a8ff 7013 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
bogdanm 0:9b334a45a8ff 7014 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
bogdanm 0:9b334a45a8ff 7015 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
bogdanm 0:9b334a45a8ff 7016 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
bogdanm 0:9b334a45a8ff 7017 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
bogdanm 0:9b334a45a8ff 7018 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
bogdanm 0:9b334a45a8ff 7019 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
bogdanm 0:9b334a45a8ff 7020 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
bogdanm 0:9b334a45a8ff 7021 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
bogdanm 0:9b334a45a8ff 7022 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
bogdanm 0:9b334a45a8ff 7023 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
bogdanm 0:9b334a45a8ff 7024 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
bogdanm 0:9b334a45a8ff 7025 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
bogdanm 0:9b334a45a8ff 7026 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
bogdanm 0:9b334a45a8ff 7027 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
bogdanm 0:9b334a45a8ff 7028 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
bogdanm 0:9b334a45a8ff 7029 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
bogdanm 0:9b334a45a8ff 7030 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
bogdanm 0:9b334a45a8ff 7031 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
bogdanm 0:9b334a45a8ff 7032 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
bogdanm 0:9b334a45a8ff 7033 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
bogdanm 0:9b334a45a8ff 7034 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
bogdanm 0:9b334a45a8ff 7035 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
bogdanm 0:9b334a45a8ff 7036 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
bogdanm 0:9b334a45a8ff 7037 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
bogdanm 0:9b334a45a8ff 7038 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
bogdanm 0:9b334a45a8ff 7039 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
bogdanm 0:9b334a45a8ff 7040 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
bogdanm 0:9b334a45a8ff 7041 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
bogdanm 0:9b334a45a8ff 7042 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
bogdanm 0:9b334a45a8ff 7043 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
bogdanm 0:9b334a45a8ff 7044 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
bogdanm 0:9b334a45a8ff 7045
bogdanm 0:9b334a45a8ff 7046 /* Bit definition for Ethernet DMA Operation Mode Register */
bogdanm 0:9b334a45a8ff 7047 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
bogdanm 0:9b334a45a8ff 7048 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
bogdanm 0:9b334a45a8ff 7049 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
bogdanm 0:9b334a45a8ff 7050 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
bogdanm 0:9b334a45a8ff 7051 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
bogdanm 0:9b334a45a8ff 7052 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
bogdanm 0:9b334a45a8ff 7053 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
bogdanm 0:9b334a45a8ff 7054 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
bogdanm 0:9b334a45a8ff 7055 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
bogdanm 0:9b334a45a8ff 7056 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
bogdanm 0:9b334a45a8ff 7057 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
bogdanm 0:9b334a45a8ff 7058 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
bogdanm 0:9b334a45a8ff 7059 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
bogdanm 0:9b334a45a8ff 7060 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
bogdanm 0:9b334a45a8ff 7061 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
bogdanm 0:9b334a45a8ff 7062 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
bogdanm 0:9b334a45a8ff 7063 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
bogdanm 0:9b334a45a8ff 7064 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
bogdanm 0:9b334a45a8ff 7065 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
bogdanm 0:9b334a45a8ff 7066 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
bogdanm 0:9b334a45a8ff 7067 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
bogdanm 0:9b334a45a8ff 7068 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
bogdanm 0:9b334a45a8ff 7069 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
bogdanm 0:9b334a45a8ff 7070 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
bogdanm 0:9b334a45a8ff 7071
bogdanm 0:9b334a45a8ff 7072 /* Bit definition for Ethernet DMA Interrupt Enable Register */
bogdanm 0:9b334a45a8ff 7073 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
bogdanm 0:9b334a45a8ff 7074 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
bogdanm 0:9b334a45a8ff 7075 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
bogdanm 0:9b334a45a8ff 7076 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
bogdanm 0:9b334a45a8ff 7077 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
bogdanm 0:9b334a45a8ff 7078 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
bogdanm 0:9b334a45a8ff 7079 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
bogdanm 0:9b334a45a8ff 7080 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
bogdanm 0:9b334a45a8ff 7081 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
bogdanm 0:9b334a45a8ff 7082 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
bogdanm 0:9b334a45a8ff 7083 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
bogdanm 0:9b334a45a8ff 7084 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
bogdanm 0:9b334a45a8ff 7085 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
bogdanm 0:9b334a45a8ff 7086 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
bogdanm 0:9b334a45a8ff 7087 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
bogdanm 0:9b334a45a8ff 7088
bogdanm 0:9b334a45a8ff 7089 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
bogdanm 0:9b334a45a8ff 7090 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
bogdanm 0:9b334a45a8ff 7091 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
bogdanm 0:9b334a45a8ff 7092 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
bogdanm 0:9b334a45a8ff 7093 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
bogdanm 0:9b334a45a8ff 7094
bogdanm 0:9b334a45a8ff 7095 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
bogdanm 0:9b334a45a8ff 7096 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
bogdanm 0:9b334a45a8ff 7097
bogdanm 0:9b334a45a8ff 7098 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
bogdanm 0:9b334a45a8ff 7099 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
bogdanm 0:9b334a45a8ff 7100
bogdanm 0:9b334a45a8ff 7101 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
bogdanm 0:9b334a45a8ff 7102 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
bogdanm 0:9b334a45a8ff 7103
bogdanm 0:9b334a45a8ff 7104 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
bogdanm 0:9b334a45a8ff 7105 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
bogdanm 0:9b334a45a8ff 7106
bogdanm 0:9b334a45a8ff 7107 /**
bogdanm 0:9b334a45a8ff 7108 *
bogdanm 0:9b334a45a8ff 7109 */
bogdanm 0:9b334a45a8ff 7110
bogdanm 0:9b334a45a8ff 7111 /**
bogdanm 0:9b334a45a8ff 7112 * @}
bogdanm 0:9b334a45a8ff 7113 */
bogdanm 0:9b334a45a8ff 7114
bogdanm 0:9b334a45a8ff 7115 #ifdef USE_STDPERIPH_DRIVER
bogdanm 0:9b334a45a8ff 7116 #include "stm32f4xx_conf.h"
bogdanm 0:9b334a45a8ff 7117 #endif /* USE_STDPERIPH_DRIVER */
bogdanm 0:9b334a45a8ff 7118
bogdanm 0:9b334a45a8ff 7119 /** @addtogroup Exported_macro
bogdanm 0:9b334a45a8ff 7120 * @{
bogdanm 0:9b334a45a8ff 7121 */
bogdanm 0:9b334a45a8ff 7122
bogdanm 0:9b334a45a8ff 7123 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
bogdanm 0:9b334a45a8ff 7124
bogdanm 0:9b334a45a8ff 7125 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
bogdanm 0:9b334a45a8ff 7126
bogdanm 0:9b334a45a8ff 7127 #define READ_BIT(REG, BIT) ((REG) & (BIT))
bogdanm 0:9b334a45a8ff 7128
bogdanm 0:9b334a45a8ff 7129 #define CLEAR_REG(REG) ((REG) = (0x0))
bogdanm 0:9b334a45a8ff 7130
bogdanm 0:9b334a45a8ff 7131 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
bogdanm 0:9b334a45a8ff 7132
bogdanm 0:9b334a45a8ff 7133 #define READ_REG(REG) ((REG))
bogdanm 0:9b334a45a8ff 7134
bogdanm 0:9b334a45a8ff 7135 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
bogdanm 0:9b334a45a8ff 7136
bogdanm 0:9b334a45a8ff 7137 /**
bogdanm 0:9b334a45a8ff 7138 * @}
bogdanm 0:9b334a45a8ff 7139 */
bogdanm 0:9b334a45a8ff 7140
bogdanm 0:9b334a45a8ff 7141 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 7142 }
bogdanm 0:9b334a45a8ff 7143 #endif /* __cplusplus */
bogdanm 0:9b334a45a8ff 7144
bogdanm 0:9b334a45a8ff 7145 #endif /* __STM32F4xx_H */
bogdanm 0:9b334a45a8ff 7146
bogdanm 0:9b334a45a8ff 7147 /**
bogdanm 0:9b334a45a8ff 7148 * @}
bogdanm 0:9b334a45a8ff 7149 */
bogdanm 0:9b334a45a8ff 7150
bogdanm 0:9b334a45a8ff 7151 /**
bogdanm 0:9b334a45a8ff 7152 * @}
bogdanm 0:9b334a45a8ff 7153 */
bogdanm 0:9b334a45a8ff 7154
bogdanm 0:9b334a45a8ff 7155 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/