mbed-dev - mbed library sources. Supersedes mbed-src. Fixes…

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mbed library sources. Supersedes mbed-src. Fixes analogIn and analogOut problems for TARGET_STM32F3. Tested on NUCLEO-F303K8, using 3 analogout and 7 analogin channels simultaneously. Added ability for STM32F334R8 and STM32F303K8 to use all three channels of DAC simultaneously. https://developer.mbed.org/users/StevieWray/code/mbed-dev/ Added ability for TARGET_STM32F3 to use more than one ADC simultaneously. https://developer.mbed.org/questions/67997/NUCLEO-F303K8ADC/

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h@70:b3a5af880266, 2016-02-23 (annotated)

Committer:: neurofun
Date:: Tue Feb 23 21:59:35 2016 +0000
Revision:: 70:b3a5af880266
Parent:: 0:9b334a45a8ff

Edited DAC routines to allow for the simultaneous use of three channels from two DACs as seen on the STM32F334R8 and STM32F303K8. Edited ADC routines to allow for the simultaneous use of more than one ADC.

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1
bogdanm	0:9b334a45a8ff	2	/**************************************************************************************************//
bogdanm	0:9b334a45a8ff	3	* @file LPC82x.h
bogdanm	0:9b334a45a8ff	4	*
bogdanm	0:9b334a45a8ff	5	* @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
bogdanm	0:9b334a45a8ff	6	* LPC82x from .
bogdanm	0:9b334a45a8ff	7	*
bogdanm	0:9b334a45a8ff	8	* @version V0.4
bogdanm	0:9b334a45a8ff	9	* @date 17. June 2014
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* @note Generated with SVDConv V2.80
bogdanm	0:9b334a45a8ff	12	* from CMSIS SVD File 'LPC82x.svd' Version 0.4,
bogdanm	0:9b334a45a8ff	13	*******************************************************************************************************/
bogdanm	0:9b334a45a8ff	14
bogdanm	0:9b334a45a8ff	15
bogdanm	0:9b334a45a8ff	16
bogdanm	0:9b334a45a8ff	17	/** @addtogroup (null)
bogdanm	0:9b334a45a8ff	18	* @{
bogdanm	0:9b334a45a8ff	19	*/
bogdanm	0:9b334a45a8ff	20
bogdanm	0:9b334a45a8ff	21	/** @addtogroup LPC82x
bogdanm	0:9b334a45a8ff	22	* @{
bogdanm	0:9b334a45a8ff	23	*/
bogdanm	0:9b334a45a8ff	24
bogdanm	0:9b334a45a8ff	25	#ifndef LPC82X_H
bogdanm	0:9b334a45a8ff	26	#define LPC82X_H
bogdanm	0:9b334a45a8ff	27
bogdanm	0:9b334a45a8ff	28	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	29	extern "C" {
bogdanm	0:9b334a45a8ff	30	#endif
bogdanm	0:9b334a45a8ff	31
bogdanm	0:9b334a45a8ff	32
bogdanm	0:9b334a45a8ff	33	/* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm	0:9b334a45a8ff	34
bogdanm	0:9b334a45a8ff	35	typedef enum {
bogdanm	0:9b334a45a8ff	36	/* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
bogdanm	0:9b334a45a8ff	37	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
bogdanm	0:9b334a45a8ff	38	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
bogdanm	0:9b334a45a8ff	39	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
bogdanm	0:9b334a45a8ff	40	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
bogdanm	0:9b334a45a8ff	41	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
bogdanm	0:9b334a45a8ff	42	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
bogdanm	0:9b334a45a8ff	43	SysTick_IRQn = -1, /!< 15 System Tick Timer /
bogdanm	0:9b334a45a8ff	44	/* ---------------------- LPC82x Specific Interrupt Numbers --------------------- */
bogdanm	0:9b334a45a8ff	45	SPI0_IRQn = 0, /!< 0 SPI0 /
bogdanm	0:9b334a45a8ff	46	SPI1_IRQn = 1, /!< 1 SPI1 /
bogdanm	0:9b334a45a8ff	47	UART0_IRQn = 3, /!< 3 UART0 /
bogdanm	0:9b334a45a8ff	48	UART1_IRQn = 4, /!< 4 UART1 /
bogdanm	0:9b334a45a8ff	49	UART2_IRQn = 5, /!< 5 UART2 /
bogdanm	0:9b334a45a8ff	50	I2C1_IRQn = 7, /!< 7 I2C1 /
bogdanm	0:9b334a45a8ff	51	I2C0_IRQn = 8, /!< 8 I2C0 /
bogdanm	0:9b334a45a8ff	52	SCT_IRQn = 9, /!< 9 SCT /
bogdanm	0:9b334a45a8ff	53	MRT_IRQn = 10, /!< 10 MRT /
bogdanm	0:9b334a45a8ff	54	CMP_IRQn = 11, /!< 11 CMP /
bogdanm	0:9b334a45a8ff	55	WDT_IRQn = 12, /!< 12 WDT /
bogdanm	0:9b334a45a8ff	56	BOD_IRQn = 13, /!< 13 BOD /
bogdanm	0:9b334a45a8ff	57	FLASH_IRQn = 14, /!< 14 FLASH /
bogdanm	0:9b334a45a8ff	58	WKT_IRQn = 15, /!< 15 WKT /
bogdanm	0:9b334a45a8ff	59	ADC_SEQA_IRQn = 16, /!< 16 ADC_SEQA /
bogdanm	0:9b334a45a8ff	60	ADC_SEQB_IRQn = 17, /!< 17 ADC_SEQB /
bogdanm	0:9b334a45a8ff	61	ADC_THCMP_IRQn = 18, /!< 18 ADC_THCMP /
bogdanm	0:9b334a45a8ff	62	ADC_OVR_IRQn = 19, /!< 19 ADC_OVR /
bogdanm	0:9b334a45a8ff	63	DMA_IRQn = 20, /!< 20 DMA /
bogdanm	0:9b334a45a8ff	64	I2C2_IRQn = 21, /!< 21 I2C2 /
bogdanm	0:9b334a45a8ff	65	I2C3_IRQn = 22, /!< 22 I2C3 /
bogdanm	0:9b334a45a8ff	66	PIN_INT0_IRQn = 24, /!< 24 PIN_INT0 /
bogdanm	0:9b334a45a8ff	67	PIN_INT1_IRQn = 25, /!< 25 PIN_INT1 /
bogdanm	0:9b334a45a8ff	68	PIN_INT2_IRQn = 26, /!< 26 PIN_INT2 /
bogdanm	0:9b334a45a8ff	69	PIN_INT3_IRQn = 27, /!< 27 PIN_INT3 /
bogdanm	0:9b334a45a8ff	70	PIN_INT4_IRQn = 28, /!< 28 PIN_INT4 /
bogdanm	0:9b334a45a8ff	71	PIN_INT5_IRQn = 29, /!< 29 PIN_INT5 /
bogdanm	0:9b334a45a8ff	72	PIN_INT6_IRQn = 30, /!< 30 PIN_INT6 /
bogdanm	0:9b334a45a8ff	73	PIN_INT7_IRQn = 31 /!< 31 PIN_INT7 /
bogdanm	0:9b334a45a8ff	74	} IRQn_Type;
bogdanm	0:9b334a45a8ff	75
bogdanm	0:9b334a45a8ff	76
bogdanm	0:9b334a45a8ff	77	/** @addtogroup Configuration_of_CMSIS
bogdanm	0:9b334a45a8ff	78	* @{
bogdanm	0:9b334a45a8ff	79	*/
bogdanm	0:9b334a45a8ff	80
bogdanm	0:9b334a45a8ff	81
bogdanm	0:9b334a45a8ff	82	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	83	/* ================ Processor and Core Peripheral Section ================ */
bogdanm	0:9b334a45a8ff	84	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	/* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
bogdanm	0:9b334a45a8ff	87	#define __CM0PLUS_REV 0x0001 /!< Cortex-M0PLUS Core Revision /
bogdanm	0:9b334a45a8ff	88	#define __MPU_PRESENT 0 /!< MPU present or not /
bogdanm	0:9b334a45a8ff	89	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
bogdanm	0:9b334a45a8ff	90	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	0:9b334a45a8ff	91	#define __VTOR_PRESENT 1 /!< Set to 1 if CPU supports Vector Table Offset Register /
bogdanm	0:9b334a45a8ff	92	/** @} / / End of group Configuration_of_CMSIS */
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	#include "core_cm0plus.h" /!< Cortex-M0PLUS processor and core peripherals /
bogdanm	0:9b334a45a8ff	95	#include "system_LPC82x.h" /!< LPC82x System /
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	99	/* ================ Device Specific Peripheral Section ================ */
bogdanm	0:9b334a45a8ff	100	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	101
bogdanm	0:9b334a45a8ff	102
bogdanm	0:9b334a45a8ff	103	/** @addtogroup Device_Peripheral_Registers
bogdanm	0:9b334a45a8ff	104	* @{
bogdanm	0:9b334a45a8ff	105	*/
bogdanm	0:9b334a45a8ff	106
bogdanm	0:9b334a45a8ff	107
bogdanm	0:9b334a45a8ff	108	/* ------------------- Start of section using anonymous unions ------------------ */
bogdanm	0:9b334a45a8ff	109	#if defined(__CC_ARM)
bogdanm	0:9b334a45a8ff	110	#pragma push
bogdanm	0:9b334a45a8ff	111	#pragma anon_unions
bogdanm	0:9b334a45a8ff	112	#elif defined(__ICCARM__)
bogdanm	0:9b334a45a8ff	113	#pragma language=extended
bogdanm	0:9b334a45a8ff	114	#elif defined(__GNUC__)
bogdanm	0:9b334a45a8ff	115	/* anonymous unions are enabled by default */
bogdanm	0:9b334a45a8ff	116	#elif defined(__TMS470__)
bogdanm	0:9b334a45a8ff	117	/* anonymous unions are enabled by default */
bogdanm	0:9b334a45a8ff	118	#elif defined(__TASKING__)
bogdanm	0:9b334a45a8ff	119	#pragma warning 586
bogdanm	0:9b334a45a8ff	120	#else
bogdanm	0:9b334a45a8ff	121	#warning Not supported compiler type
bogdanm	0:9b334a45a8ff	122	#endif
bogdanm	0:9b334a45a8ff	123
bogdanm	0:9b334a45a8ff	124
bogdanm	0:9b334a45a8ff	125
bogdanm	0:9b334a45a8ff	126	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	127	/* ================ WWDT ================ */
bogdanm	0:9b334a45a8ff	128	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	129
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	/**
bogdanm	0:9b334a45a8ff	132	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
bogdanm	0:9b334a45a8ff	133	*/
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	typedef struct { /!< (@ 0x40000000) WWDT Structure /
bogdanm	0:9b334a45a8ff	136	__IO uint32_t MOD; /*!< (@ 0x40000000) Watchdog mode register. This register contains
bogdanm	0:9b334a45a8ff	137	the basic mode and status of the Watchdog Timer. */
bogdanm	0:9b334a45a8ff	138	__IO uint32_t TC; /*!< (@ 0x40000004) Watchdog timer constant register. This 24-bit
bogdanm	0:9b334a45a8ff	139	register determines the time-out value. */
bogdanm	0:9b334a45a8ff	140	__O uint32_t FEED; /*!< (@ 0x40000008) Watchdog feed sequence register. Writing 0xAA
bogdanm	0:9b334a45a8ff	141	followed by 0x55 to this register reloads the Watchdog timer
bogdanm	0:9b334a45a8ff	142	with the value contained in WDTC. */
bogdanm	0:9b334a45a8ff	143	__I uint32_t TV; /*!< (@ 0x4000000C) Watchdog timer value register. This 24-bit register
bogdanm	0:9b334a45a8ff	144	reads out the current value of the Watchdog timer. */
bogdanm	0:9b334a45a8ff	145	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	146	__IO uint32_t WARNINT; /!< (@ 0x40000014) Watchdog Warning Interrupt compare value. /
bogdanm	0:9b334a45a8ff	147	__IO uint32_t WINDOW; /!< (@ 0x40000018) Watchdog Window compare value. /
bogdanm	0:9b334a45a8ff	148	} LPC_WWDT_Type;
bogdanm	0:9b334a45a8ff	149
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	152	/* ================ MRT ================ */
bogdanm	0:9b334a45a8ff	153	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	/**
bogdanm	0:9b334a45a8ff	157	* @brief Multi-Rate Timer (MRT) (MRT)
bogdanm	0:9b334a45a8ff	158	*/
bogdanm	0:9b334a45a8ff	159
bogdanm	0:9b334a45a8ff	160	typedef struct { /!< (@ 0x40004000) MRT Structure /
bogdanm	0:9b334a45a8ff	161	__IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
bogdanm	0:9b334a45a8ff	162	is loaded into the TIMER0 register. */
bogdanm	0:9b334a45a8ff	163	__I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
bogdanm	0:9b334a45a8ff	164	value of the down-counter. */
bogdanm	0:9b334a45a8ff	165	__IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
bogdanm	0:9b334a45a8ff	166	the MRT0 modes. */
bogdanm	0:9b334a45a8ff	167	__IO uint32_t STAT0; /!< (@ 0x4000400C) MRT0 Status register. /
bogdanm	0:9b334a45a8ff	168	__IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
bogdanm	0:9b334a45a8ff	169	is loaded into the TIMER0 register. */
bogdanm	0:9b334a45a8ff	170	__I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
bogdanm	0:9b334a45a8ff	171	value of the down-counter. */
bogdanm	0:9b334a45a8ff	172	__IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
bogdanm	0:9b334a45a8ff	173	the MRT0 modes. */
bogdanm	0:9b334a45a8ff	174	__IO uint32_t STAT1; /!< (@ 0x4000401C) MRT0 Status register. /
bogdanm	0:9b334a45a8ff	175	__IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
bogdanm	0:9b334a45a8ff	176	is loaded into the TIMER0 register. */
bogdanm	0:9b334a45a8ff	177	__I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
bogdanm	0:9b334a45a8ff	178	value of the down-counter. */
bogdanm	0:9b334a45a8ff	179	__IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
bogdanm	0:9b334a45a8ff	180	the MRT0 modes. */
bogdanm	0:9b334a45a8ff	181	__IO uint32_t STAT2; /!< (@ 0x4000402C) MRT0 Status register. /
bogdanm	0:9b334a45a8ff	182	__IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
bogdanm	0:9b334a45a8ff	183	is loaded into the TIMER0 register. */
bogdanm	0:9b334a45a8ff	184	__I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
bogdanm	0:9b334a45a8ff	185	value of the down-counter. */
bogdanm	0:9b334a45a8ff	186	__IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
bogdanm	0:9b334a45a8ff	187	the MRT0 modes. */
bogdanm	0:9b334a45a8ff	188	__IO uint32_t STAT3; /!< (@ 0x4000403C) MRT0 Status register. /
bogdanm	0:9b334a45a8ff	189	__I uint32_t RESERVED0[45];
bogdanm	0:9b334a45a8ff	190	__I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
bogdanm	0:9b334a45a8ff	191	the number of the first idle channel. */
bogdanm	0:9b334a45a8ff	192	__IO uint32_t IRQ_FLAG; /!< (@ 0x400040F8) Global interrupt flag register /
bogdanm	0:9b334a45a8ff	193	} LPC_MRT_Type;
bogdanm	0:9b334a45a8ff	194
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	197	/* ================ WKT ================ */
bogdanm	0:9b334a45a8ff	198	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	199
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	/**
bogdanm	0:9b334a45a8ff	202	* @brief Self wake-up timer (WKT) (WKT)
bogdanm	0:9b334a45a8ff	203	*/
bogdanm	0:9b334a45a8ff	204
bogdanm	0:9b334a45a8ff	205	typedef struct { /!< (@ 0x40008000) WKT Structure /
bogdanm	0:9b334a45a8ff	206	__IO uint32_t CTRL; /!< (@ 0x40008000) Self wake-up timer control register. /
bogdanm	0:9b334a45a8ff	207	__I uint32_t RESERVED0[2];
bogdanm	0:9b334a45a8ff	208	__IO uint32_t COUNT; /!< (@ 0x4000800C) Counter register. /
bogdanm	0:9b334a45a8ff	209	} LPC_WKT_Type;
bogdanm	0:9b334a45a8ff	210
bogdanm	0:9b334a45a8ff	211
bogdanm	0:9b334a45a8ff	212	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	213	/* ================ SWM ================ */
bogdanm	0:9b334a45a8ff	214	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	215
bogdanm	0:9b334a45a8ff	216
bogdanm	0:9b334a45a8ff	217	/**
bogdanm	0:9b334a45a8ff	218	* @brief Switch matrix (SWM) (SWM)
bogdanm	0:9b334a45a8ff	219	*/
bogdanm	0:9b334a45a8ff	220
bogdanm	0:9b334a45a8ff	221	typedef struct { /!< (@ 0x4000C000) SWM Structure /
bogdanm	0:9b334a45a8ff	222	union {
bogdanm	0:9b334a45a8ff	223	__IO uint32_t PINASSIGN[12];
bogdanm	0:9b334a45a8ff	224	struct {
bogdanm	0:9b334a45a8ff	225	__IO uint32_t PINASSIGN0; /*!< (@ 0x4000C000) Pin assign register 0. Assign movable functions
bogdanm	0:9b334a45a8ff	226	U0_TXD, U0_RXD, U0_RTS, U0_CTS. */
bogdanm	0:9b334a45a8ff	227	__IO uint32_t PINASSIGN1; /*!< (@ 0x4000C004) Pin assign register 1. Assign movable functions
bogdanm	0:9b334a45a8ff	228	U0_SCLK, U1_TXD, U1_RXD, U1_RTS. */
bogdanm	0:9b334a45a8ff	229	__IO uint32_t PINASSIGN2; /*!< (@ 0x4000C008) Pin assign register 2. Assign movable functions
bogdanm	0:9b334a45a8ff	230	U1_CTS, U1_SCLK, U2_TXD, U2_RXD. */
bogdanm	0:9b334a45a8ff	231	__IO uint32_t PINASSIGN3; /*!< (@ 0x4000C00C) Pin assign register 3. Assign movable function
bogdanm	0:9b334a45a8ff	232	U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. */
bogdanm	0:9b334a45a8ff	233	__IO uint32_t PINASSIGN4; /*!< (@ 0x4000C010) Pin assign register 4. Assign movable functions
bogdanm	0:9b334a45a8ff	234	SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1. */
bogdanm	0:9b334a45a8ff	235	__IO uint32_t PINASSIGN5; /*!< (@ 0x4000C014) Pin assign register 5. Assign movable functions
bogdanm	0:9b334a45a8ff	236	SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI */
bogdanm	0:9b334a45a8ff	237	__IO uint32_t PINASSIGN6; /*!< (@ 0x4000C018) Pin assign register 6. Assign movable functions
bogdanm	0:9b334a45a8ff	238	SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0. */
bogdanm	0:9b334a45a8ff	239	__IO uint32_t PINASSIGN7; /*!< (@ 0x4000C01C) Pin assign register 7. Assign movable functions
bogdanm	0:9b334a45a8ff	240	SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0. */
bogdanm	0:9b334a45a8ff	241	__IO uint32_t PINASSIGN8; /*!< (@ 0x4000C020) Pin assign register 8. Assign movable functions
bogdanm	0:9b334a45a8ff	242	SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4. */
bogdanm	0:9b334a45a8ff	243	__IO uint32_t PINASSIGN9; /*!< (@ 0x4000C024) Pin assign register 9. Assign movable functions
bogdanm	0:9b334a45a8ff	244	SCT_OUT5, I2C1_SDA, I2C1_SCL, I2C2_SDA. */
bogdanm	0:9b334a45a8ff	245	__IO uint32_t PINASSIGN10; /*!< (@ 0x4000C028) Pin assign register 10. Assign movable functions
bogdanm	0:9b334a45a8ff	246	I2C2_SCL, I2C3_SDA, I2C3_SCL, ADC_PINTRIG0. */
bogdanm	0:9b334a45a8ff	247	__IO uint32_t PINASSIGN11; /*!< (@ 0x4000C02C) Pin assign register 11. Assign movable functions
bogdanm	0:9b334a45a8ff	248	ADC_PINTRIG1, ACMP_O, CLKOUT, GPIO_INT_BMAT */
bogdanm	0:9b334a45a8ff	249	};
bogdanm	0:9b334a45a8ff	250	};
bogdanm	0:9b334a45a8ff	251	__I uint32_t RESERVED0[100];
bogdanm	0:9b334a45a8ff	252	__IO uint32_t PINENABLE0; /*!< (@ 0x4000C1C0) Pin enable register 0. Enables fixed-pin functions
bogdanm	0:9b334a45a8ff	253	ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN,
bogdanm	0:9b334a45a8ff	254	VDDCMP. */
bogdanm	0:9b334a45a8ff	255	} LPC_SWM_Type;
bogdanm	0:9b334a45a8ff	256
bogdanm	0:9b334a45a8ff	257
bogdanm	0:9b334a45a8ff	258	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	259	/* ================ ADC ================ */
bogdanm	0:9b334a45a8ff	260	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	261
bogdanm	0:9b334a45a8ff	262
bogdanm	0:9b334a45a8ff	263	/**
bogdanm	0:9b334a45a8ff	264	* @brief 12-bit Analog-to-Digital Converter (ADC) (ADC)
bogdanm	0:9b334a45a8ff	265	*/
bogdanm	0:9b334a45a8ff	266
bogdanm	0:9b334a45a8ff	267	typedef struct { /!< (@ 0x4001C000) ADC Structure /
bogdanm	0:9b334a45a8ff	268	__IO uint32_t CTRL; /*!< (@ 0x4001C000) A/D Control Register. Contains the clock divide
bogdanm	0:9b334a45a8ff	269	value, enable bits for each sequence and the A/D power-down
bogdanm	0:9b334a45a8ff	270	bit. */
bogdanm	0:9b334a45a8ff	271	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	272	__IO uint32_t SEQA_CTRL; /*!< (@ 0x4001C008) A/D Conversion Sequence-A control Register: Controls
bogdanm	0:9b334a45a8ff	273	triggering and channel selection for conversion sequence-A.
bogdanm	0:9b334a45a8ff	274	Also specifies interrupt mode for sequence-A. */
bogdanm	0:9b334a45a8ff	275	__IO uint32_t SEQB_CTRL; /*!< (@ 0x4001C00C) A/D Conversion Sequence-B Control Register: Controls
bogdanm	0:9b334a45a8ff	276	triggering and channel selection for conversion sequence-B.
bogdanm	0:9b334a45a8ff	277	Also specifies interrupt mode for sequence-B. */
bogdanm	0:9b334a45a8ff	278	__IO uint32_t SEQA_GDAT; /*!< (@ 0x4001C010) A/D Sequence-A Global Data Register. This register
bogdanm	0:9b334a45a8ff	279	contains the result of the most recent A/D conversion performed
bogdanm	0:9b334a45a8ff	280	under sequence-A */
bogdanm	0:9b334a45a8ff	281	__IO uint32_t SEQB_GDAT; /*!< (@ 0x4001C014) A/D Sequence-B Global Data Register. This register
bogdanm	0:9b334a45a8ff	282	contains the result of the most recent A/D conversion performed
bogdanm	0:9b334a45a8ff	283	under sequence-B */
bogdanm	0:9b334a45a8ff	284	__I uint32_t RESERVED1[2];
bogdanm	0:9b334a45a8ff	285	__I uint32_t DAT0; /*!< (@ 0x4001C020) A/D Channel 0 Data Register. This register contains
bogdanm	0:9b334a45a8ff	286	the result of the most recent conversion completed on channel
bogdanm	0:9b334a45a8ff	287	0. */
bogdanm	0:9b334a45a8ff	288	__I uint32_t DAT1; /*!< (@ 0x4001C024) A/D Channel 0 Data Register. This register contains
bogdanm	0:9b334a45a8ff	289	the result of the most recent conversion completed on channel
bogdanm	0:9b334a45a8ff	290	0. */
bogdanm	0:9b334a45a8ff	291	__I uint32_t DAT2; /*!< (@ 0x4001C028) A/D Channel 0 Data Register. This register contains
bogdanm	0:9b334a45a8ff	292	the result of the most recent conversion completed on channel
bogdanm	0:9b334a45a8ff	293	0. */
bogdanm	0:9b334a45a8ff	294	__I uint32_t DAT3; /*!< (@ 0x4001C02C) A/D Channel 0 Data Register. This register contains
bogdanm	0:9b334a45a8ff	295	the result of the most recent conversion completed on channel
bogdanm	0:9b334a45a8ff	296	0. */
bogdanm	0:9b334a45a8ff	297	__I uint32_t DAT4; /*!< (@ 0x4001C030) A/D Channel 0 Data Register. This register contains
bogdanm	0:9b334a45a8ff	298	the result of the most recent conversion completed on channel
bogdanm	0:9b334a45a8ff	299	0. */
bogdanm	0:9b334a45a8ff	300	__I uint32_t DAT5; /*!< (@ 0x4001C034) A/D Channel 0 Data Register. This register contains
bogdanm	0:9b334a45a8ff	301	the result of the most recent conversion completed on channel
bogdanm	0:9b334a45a8ff	302	0. */
bogdanm	0:9b334a45a8ff	303	__I uint32_t DAT6; /*!< (@ 0x4001C038) A/D Channel 0 Data Register. This register contains
bogdanm	0:9b334a45a8ff	304	the result of the most recent conversion completed on channel
bogdanm	0:9b334a45a8ff	305	0. */
bogdanm	0:9b334a45a8ff	306	__I uint32_t DAT7; /*!< (@ 0x4001C03C) A/D Channel 0 Data Register. This register contains
bogdanm	0:9b334a45a8ff	307	the result of the most recent conversion completed on channel
bogdanm	0:9b334a45a8ff	308	0. */
bogdanm	0:9b334a45a8ff	309	__I uint32_t DAT8; /*!< (@ 0x4001C040) A/D Channel 0 Data Register. This register contains
bogdanm	0:9b334a45a8ff	310	the result of the most recent conversion completed on channel
bogdanm	0:9b334a45a8ff	311	0. */
bogdanm	0:9b334a45a8ff	312	__I uint32_t DAT9; /*!< (@ 0x4001C044) A/D Channel 0 Data Register. This register contains
bogdanm	0:9b334a45a8ff	313	the result of the most recent conversion completed on channel
bogdanm	0:9b334a45a8ff	314	0. */
bogdanm	0:9b334a45a8ff	315	__I uint32_t DAT10; /*!< (@ 0x4001C048) A/D Channel 0 Data Register. This register contains
bogdanm	0:9b334a45a8ff	316	the result of the most recent conversion completed on channel
bogdanm	0:9b334a45a8ff	317	0. */
bogdanm	0:9b334a45a8ff	318	__I uint32_t DAT11; /*!< (@ 0x4001C04C) A/D Channel 0 Data Register. This register contains
bogdanm	0:9b334a45a8ff	319	the result of the most recent conversion completed on channel
bogdanm	0:9b334a45a8ff	320	0. */
bogdanm	0:9b334a45a8ff	321	__IO uint32_t THR0_LOW; /*!< (@ 0x4001C050) A/D Low Compare Threshold Register 0 : Contains
bogdanm	0:9b334a45a8ff	322	the lower threshold level for automatic threshold comparison
bogdanm	0:9b334a45a8ff	323	for any channels linked to threshold pair 0. */
bogdanm	0:9b334a45a8ff	324	__IO uint32_t THR1_LOW; /*!< (@ 0x4001C054) A/D Low Compare Threshold Register 1: Contains
bogdanm	0:9b334a45a8ff	325	the lower threshold level for automatic threshold comparison
bogdanm	0:9b334a45a8ff	326	for any channels linked to threshold pair 1. */
bogdanm	0:9b334a45a8ff	327	__IO uint32_t THR0_HIGH; /*!< (@ 0x4001C058) A/D High Compare Threshold Register 0: Contains
bogdanm	0:9b334a45a8ff	328	the upper threshold level for automatic threshold comparison
bogdanm	0:9b334a45a8ff	329	for any channels linked to threshold pair 0. */
bogdanm	0:9b334a45a8ff	330	__IO uint32_t THR1_HIGH; /*!< (@ 0x4001C05C) A/D High Compare Threshold Register 1: Contains
bogdanm	0:9b334a45a8ff	331	the upper threshold level for automatic threshold comparison
bogdanm	0:9b334a45a8ff	332	for any channels linked to threshold pair 1. */
bogdanm	0:9b334a45a8ff	333	__IO uint32_t CHAN_THRSEL; /*!< (@ 0x4001C060) A/D Channel-Threshold Select Register. Specifies
bogdanm	0:9b334a45a8ff	334	which set of threshold compare registers are to be used for
bogdanm	0:9b334a45a8ff	335	each channel */
bogdanm	0:9b334a45a8ff	336	__IO uint32_t INTEN; /*!< (@ 0x4001C064) A/D Interrupt Enable Register. This register
bogdanm	0:9b334a45a8ff	337	contains enable bits that enable the sequence-A, sequence-B,
bogdanm	0:9b334a45a8ff	338	threshold compare and data overrun interrupts to be generated. */
bogdanm	0:9b334a45a8ff	339	__IO uint32_t FLAGS; /*!< (@ 0x4001C068) A/D Flags Register. Contains the four interrupt
bogdanm	0:9b334a45a8ff	340	request flags and the individual component overrun and threshold-compare
bogdanm	0:9b334a45a8ff	341	flags. (The overrun bits replicate information stored in the
bogdanm	0:9b334a45a8ff	342	result registers). */
bogdanm	0:9b334a45a8ff	343	__IO uint32_t TRM; /!< (@ 0x4001C06C) ADC trim register. /
bogdanm	0:9b334a45a8ff	344	} LPC_ADC_Type;
bogdanm	0:9b334a45a8ff	345
bogdanm	0:9b334a45a8ff	346
bogdanm	0:9b334a45a8ff	347	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	348	/* ================ PMU ================ */
bogdanm	0:9b334a45a8ff	349	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/**
bogdanm	0:9b334a45a8ff	353	* @brief Power Management Unit (PMU) (PMU)
bogdanm	0:9b334a45a8ff	354	*/
bogdanm	0:9b334a45a8ff	355
bogdanm	0:9b334a45a8ff	356	typedef struct { /!< (@ 0x40020000) PMU Structure /
bogdanm	0:9b334a45a8ff	357	__IO uint32_t PCON; /!< (@ 0x40020000) Power control register /
bogdanm	0:9b334a45a8ff	358	__IO uint32_t GPREG0; /!< (@ 0x40020004) General purpose register 0 /
bogdanm	0:9b334a45a8ff	359	__IO uint32_t GPREG1; /!< (@ 0x40020008) General purpose register 0 /
bogdanm	0:9b334a45a8ff	360	__IO uint32_t GPREG2; /!< (@ 0x4002000C) General purpose register 0 /
bogdanm	0:9b334a45a8ff	361	__IO uint32_t GPREG3; /!< (@ 0x40020010) General purpose register 0 /
bogdanm	0:9b334a45a8ff	362	__IO uint32_t DPDCTRL; /*!< (@ 0x40020014) Deep power-down control register. Also includes
bogdanm	0:9b334a45a8ff	363	bits for general purpose storage. */
bogdanm	0:9b334a45a8ff	364	} LPC_PMU_Type;
bogdanm	0:9b334a45a8ff	365
bogdanm	0:9b334a45a8ff	366
bogdanm	0:9b334a45a8ff	367	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	368	/* ================ CMP ================ */
bogdanm	0:9b334a45a8ff	369	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371
bogdanm	0:9b334a45a8ff	372	/**
bogdanm	0:9b334a45a8ff	373	* @brief Analog comparator (CMP)
bogdanm	0:9b334a45a8ff	374	*/
bogdanm	0:9b334a45a8ff	375
bogdanm	0:9b334a45a8ff	376	typedef struct { /!< (@ 0x40024000) CMP Structure /
bogdanm	0:9b334a45a8ff	377	__IO uint32_t CTRL; /!< (@ 0x40024000) Comparator control register /
bogdanm	0:9b334a45a8ff	378	__IO uint32_t LAD; /!< (@ 0x40024004) Voltage ladder register /
bogdanm	0:9b334a45a8ff	379	} LPC_CMP_Type;
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381
bogdanm	0:9b334a45a8ff	382	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	383	/* ================ DMATRIGMUX ================ */
bogdanm	0:9b334a45a8ff	384	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	385
bogdanm	0:9b334a45a8ff	386
bogdanm	0:9b334a45a8ff	387	/**
bogdanm	0:9b334a45a8ff	388	* @brief DMA trigger mux (DMATRIGMUX)
bogdanm	0:9b334a45a8ff	389	*/
bogdanm	0:9b334a45a8ff	390
bogdanm	0:9b334a45a8ff	391	typedef struct { /!< (@ 0x40028000) DMATRIGMUX Structure /
bogdanm	0:9b334a45a8ff	392	__IO uint32_t DMA_ITRIG_INMUX0; /*!< (@ 0x40028000) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	393	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	394	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	395	__IO uint32_t DMA_ITRIG_INMUX1; /*!< (@ 0x40028004) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	396	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	397	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	398	__IO uint32_t DMA_ITRIG_INMUX2; /*!< (@ 0x40028008) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	399	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	400	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	401	__IO uint32_t DMA_ITRIG_INMUX3; /*!< (@ 0x4002800C) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	402	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	403	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	404	__IO uint32_t DMA_ITRIG_INMUX4; /*!< (@ 0x40028010) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	405	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	406	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	407	__IO uint32_t DMA_ITRIG_INMUX5; /*!< (@ 0x40028014) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	408	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	409	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	410	__IO uint32_t DMA_ITRIG_INMUX6; /*!< (@ 0x40028018) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	411	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	412	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	413	__IO uint32_t DMA_ITRIG_INMUX7; /*!< (@ 0x4002801C) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	414	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	415	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	416	__IO uint32_t DMA_ITRIG_INMUX8; /*!< (@ 0x40028020) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	417	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	418	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	419	__IO uint32_t DMA_ITRIG_INMUX9; /*!< (@ 0x40028024) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	420	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	421	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	422	__IO uint32_t DMA_ITRIG_INMUX10; /*!< (@ 0x40028028) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	423	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	424	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	425	__IO uint32_t DMA_ITRIG_INMUX11; /*!< (@ 0x4002802C) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	426	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	427	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	428	__IO uint32_t DMA_ITRIG_INMUX12; /*!< (@ 0x40028030) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	429	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	430	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	431	__IO uint32_t DMA_ITRIG_INMUX13; /*!< (@ 0x40028034) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	432	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	433	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	434	__IO uint32_t DMA_ITRIG_INMUX14; /*!< (@ 0x40028038) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	435	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	436	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	437	__IO uint32_t DMA_ITRIG_INMUX15; /*!< (@ 0x4002803C) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	438	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	439	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	440	__IO uint32_t DMA_ITRIG_INMUX16; /*!< (@ 0x40028040) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	441	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	442	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	443	__IO uint32_t DMA_ITRIG_INMUX17; /*!< (@ 0x40028044) Input mux register for trigger inputs 0 to 23
bogdanm	0:9b334a45a8ff	444	connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
bogdanm	0:9b334a45a8ff	445	interrupts, and DMA requests. */
bogdanm	0:9b334a45a8ff	446	} LPC_DMATRIGMUX_Type;
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	450	/* ================ INPUTMUX ================ */
bogdanm	0:9b334a45a8ff	451	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	452
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	/**
bogdanm	0:9b334a45a8ff	455	* @brief Input multiplexing (INPUTMUX)
bogdanm	0:9b334a45a8ff	456	*/
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	typedef struct { /!< (@ 0x4002C000) INPUTMUX Structure /
bogdanm	0:9b334a45a8ff	459	__IO uint32_t DMA_INMUX_INMUX0; /*!< (@ 0x4002C000) Input mux register for DMA trigger input 20.
bogdanm	0:9b334a45a8ff	460	Selects from 18 DMA trigger outputs. */
bogdanm	0:9b334a45a8ff	461	__IO uint32_t DMA_INMUX_INMUX1; /*!< (@ 0x4002C004) Input mux register for DMA trigger input 20.
bogdanm	0:9b334a45a8ff	462	Selects from 18 DMA trigger outputs. */
bogdanm	0:9b334a45a8ff	463	__I uint32_t RESERVED0[6];
bogdanm	0:9b334a45a8ff	464	__IO uint32_t SCT0_INMUX0; /!< (@ 0x4002C020) Input mux register for SCT input 0 /
bogdanm	0:9b334a45a8ff	465	__IO uint32_t SCT0_INMUX1; /!< (@ 0x4002C024) Input mux register for SCT input 0 /
bogdanm	0:9b334a45a8ff	466	__IO uint32_t SCT0_INMUX2; /!< (@ 0x4002C028) Input mux register for SCT input 0 /
bogdanm	0:9b334a45a8ff	467	__IO uint32_t SCT0_INMUX3; /!< (@ 0x4002C02C) Input mux register for SCT input 0 /
bogdanm	0:9b334a45a8ff	468	} LPC_INPUTMUX_Type;
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470
bogdanm	0:9b334a45a8ff	471	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	472	/* ================ FLASHCTRL ================ */
bogdanm	0:9b334a45a8ff	473	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	474
bogdanm	0:9b334a45a8ff	475
bogdanm	0:9b334a45a8ff	476	/**
bogdanm	0:9b334a45a8ff	477	* @brief Flash controller (FLASHCTRL)
bogdanm	0:9b334a45a8ff	478	*/
bogdanm	0:9b334a45a8ff	479
bogdanm	0:9b334a45a8ff	480	typedef struct { /!< (@ 0x40040000) FLASHCTRL Structure /
bogdanm	0:9b334a45a8ff	481	__I uint32_t RESERVED0[4];
bogdanm	0:9b334a45a8ff	482	__IO uint32_t FLASHCFG; /!< (@ 0x40040010) Flash configuration register /
bogdanm	0:9b334a45a8ff	483	__I uint32_t RESERVED1[3];
bogdanm	0:9b334a45a8ff	484	__IO uint32_t FMSSTART; /!< (@ 0x40040020) Signature start address register /
bogdanm	0:9b334a45a8ff	485	__IO uint32_t FMSSTOP; /!< (@ 0x40040024) Signature stop-address register /
bogdanm	0:9b334a45a8ff	486	__I uint32_t RESERVED2;
bogdanm	0:9b334a45a8ff	487	__I uint32_t FMSW0; /!< (@ 0x4004002C) Signature Word /
bogdanm	0:9b334a45a8ff	488	} LPC_FLASHCTRL_Type;
bogdanm	0:9b334a45a8ff	489
bogdanm	0:9b334a45a8ff	490
bogdanm	0:9b334a45a8ff	491	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	492	/* ================ IOCON ================ */
bogdanm	0:9b334a45a8ff	493	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495
bogdanm	0:9b334a45a8ff	496	/**
bogdanm	0:9b334a45a8ff	497	* @brief I/O configuration (IOCON) (IOCON)
bogdanm	0:9b334a45a8ff	498	*/
bogdanm	0:9b334a45a8ff	499
bogdanm	0:9b334a45a8ff	500	typedef struct { /!< (@ 0x40044000) IOCON Structure /
bogdanm	0:9b334a45a8ff	501	__IO uint32_t PIO0_17; /!< (@ 0x40044000) I/O configuration for pin PIO0_17 /
bogdanm	0:9b334a45a8ff	502	__IO uint32_t PIO0_13; /!< (@ 0x40044004) I/O configuration for pin PIO0_13 /
bogdanm	0:9b334a45a8ff	503	__IO uint32_t PIO0_12; /!< (@ 0x40044008) I/O configuration for pin PIO0_12 /
bogdanm	0:9b334a45a8ff	504	__IO uint32_t PIO0_5; /!< (@ 0x4004400C) I/O configuration for pin PIO0_5/RESET /
bogdanm	0:9b334a45a8ff	505	__IO uint32_t PIO0_4; /!< (@ 0x40044010) I/O configuration for pin PIO0_4 /
bogdanm	0:9b334a45a8ff	506	__IO uint32_t PIO0_3; /!< (@ 0x40044014) I/O configuration for pin PIO0_3/SWCLK /
bogdanm	0:9b334a45a8ff	507	__IO uint32_t PIO0_2; /!< (@ 0x40044018) I/O configuration for pin PIO0_2/SWDIO /
bogdanm	0:9b334a45a8ff	508	__IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11. This is the
bogdanm	0:9b334a45a8ff	509	pin configuration for the true open-drain pin. */
bogdanm	0:9b334a45a8ff	510	__IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10. This is the
bogdanm	0:9b334a45a8ff	511	pin configuration for the true open-drain pin. */
bogdanm	0:9b334a45a8ff	512	__IO uint32_t PIO0_16; /!< (@ 0x40044024) I/O configuration for pin PIO0_16 /
bogdanm	0:9b334a45a8ff	513	__IO uint32_t PIO0_15; /!< (@ 0x40044028) I/O configuration for pin PIO0_15 /
bogdanm	0:9b334a45a8ff	514	__IO uint32_t PIO0_1; /!< (@ 0x4004402C) I/O configuration for pin PIO0_17 /
bogdanm	0:9b334a45a8ff	515	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	516	__IO uint32_t PIO0_9; /!< (@ 0x40044034) I/O configuration for pin PIO0_9/XTALOUT /
bogdanm	0:9b334a45a8ff	517	__IO uint32_t PIO0_8; /!< (@ 0x40044038) I/O configuration for pin PIO0_8/XTALIN /
bogdanm	0:9b334a45a8ff	518	__IO uint32_t PIO0_7; /!< (@ 0x4004403C) I/O configuration for pin PIO0_7 /
bogdanm	0:9b334a45a8ff	519	__IO uint32_t PIO0_6; /!< (@ 0x40044040) I/O configuration for pin PIO0_6/VDDCMP /
bogdanm	0:9b334a45a8ff	520	__IO uint32_t PIO0_0; /!< (@ 0x40044044) I/O configuration for pin PIO0_0/ACMP_I0 /
bogdanm	0:9b334a45a8ff	521	__IO uint32_t PIO0_14; /!< (@ 0x40044048) I/O configuration for pin PIO0_14 /
bogdanm	0:9b334a45a8ff	522	__I uint32_t RESERVED1;
bogdanm	0:9b334a45a8ff	523	__IO uint32_t PIO0_28; /!< (@ 0x40044050) I/O configuration for pin PIO0_28 /
bogdanm	0:9b334a45a8ff	524	__IO uint32_t PIO0_27; /!< (@ 0x40044054) I/O configuration for pin PIO0_27 /
bogdanm	0:9b334a45a8ff	525	__IO uint32_t PIO0_26; /!< (@ 0x40044058) I/O configuration for pin PIO0_26 /
bogdanm	0:9b334a45a8ff	526	__IO uint32_t PIO0_25; /!< (@ 0x4004405C) I/O configuration for pin PIO0_25 /
bogdanm	0:9b334a45a8ff	527	__IO uint32_t PIO0_24; /!< (@ 0x40044060) I/O configuration for pin PIO0_24 /
bogdanm	0:9b334a45a8ff	528	__IO uint32_t PIO0_23; /!< (@ 0x40044064) I/O configuration for pin PIO0_23/ADC_3 /
bogdanm	0:9b334a45a8ff	529	__IO uint32_t PIO0_22; /!< (@ 0x40044068) I/O configuration for pin PIO0_22/ADC_4 /
bogdanm	0:9b334a45a8ff	530	__IO uint32_t PIO0_21; /!< (@ 0x4004406C) I/O configuration for pin PIO0_21/ACMP_I4/ADC_5 /
bogdanm	0:9b334a45a8ff	531	__IO uint32_t PIO0_20; /!< (@ 0x40044070) I/O configuration for pin PIO0_20/ADC_6 /
bogdanm	0:9b334a45a8ff	532	__IO uint32_t PIO0_19; /!< (@ 0x40044074) I/O configuration for pin PIO0_19/ADC_7 /
bogdanm	0:9b334a45a8ff	533	__IO uint32_t PIO0_18; /!< (@ 0x40044078) I/O configuration for pin PIO0_18/ADC_8 /
bogdanm	0:9b334a45a8ff	534	} LPC_IOCON_Type;
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536
bogdanm	0:9b334a45a8ff	537	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	538	/* ================ SYSCON ================ */
bogdanm	0:9b334a45a8ff	539	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	540
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	/**
bogdanm	0:9b334a45a8ff	543	* @brief System configuration (SYSCON) (SYSCON)
bogdanm	0:9b334a45a8ff	544	*/
bogdanm	0:9b334a45a8ff	545
bogdanm	0:9b334a45a8ff	546	typedef struct { /!< (@ 0x40048000) SYSCON Structure /
bogdanm	0:9b334a45a8ff	547	__IO uint32_t SYSMEMREMAP; /!< (@ 0x40048000) System memory remap /
bogdanm	0:9b334a45a8ff	548	__IO uint32_t PRESETCTRL; /!< (@ 0x40048004) Peripheral reset control /
bogdanm	0:9b334a45a8ff	549	__IO uint32_t SYSPLLCTRL; /!< (@ 0x40048008) System PLL control /
bogdanm	0:9b334a45a8ff	550	__I uint32_t SYSPLLSTAT; /!< (@ 0x4004800C) System PLL status /
bogdanm	0:9b334a45a8ff	551	__I uint32_t RESERVED0[4];
bogdanm	0:9b334a45a8ff	552	__IO uint32_t SYSOSCCTRL; /!< (@ 0x40048020) System oscillator control /
bogdanm	0:9b334a45a8ff	553	__IO uint32_t WDTOSCCTRL; /!< (@ 0x40048024) Watchdog oscillator control /
bogdanm	0:9b334a45a8ff	554	__IO uint32_t IRCCTRL; /!< (@ 0x40048028) IRC control /
bogdanm	0:9b334a45a8ff	555	__I uint32_t RESERVED1;
bogdanm	0:9b334a45a8ff	556	__IO uint32_t SYSRSTSTAT; /!< (@ 0x40048030) System reset status register /
bogdanm	0:9b334a45a8ff	557	__I uint32_t RESERVED2[3];
bogdanm	0:9b334a45a8ff	558	__IO uint32_t SYSPLLCLKSEL; /!< (@ 0x40048040) System PLL clock source select /
bogdanm	0:9b334a45a8ff	559	__IO uint32_t SYSPLLCLKUEN; /!< (@ 0x40048044) System PLL clock source update enable /
bogdanm	0:9b334a45a8ff	560	__I uint32_t RESERVED3[10];
bogdanm	0:9b334a45a8ff	561	__IO uint32_t MAINCLKSEL; /!< (@ 0x40048070) Main clock source select /
bogdanm	0:9b334a45a8ff	562	__IO uint32_t MAINCLKUEN; /!< (@ 0x40048074) Main clock source update enable /
bogdanm	0:9b334a45a8ff	563	__IO uint32_t SYSAHBCLKDIV; /!< (@ 0x40048078) System clock divider /
bogdanm	0:9b334a45a8ff	564	__I uint32_t RESERVED4;
bogdanm	0:9b334a45a8ff	565	__IO uint32_t SYSAHBCLKCTRL; /!< (@ 0x40048080) System clock control /
bogdanm	0:9b334a45a8ff	566	__I uint32_t RESERVED5[4];
bogdanm	0:9b334a45a8ff	567	__IO uint32_t UARTCLKDIV; /!< (@ 0x40048094) USART clock divider /
bogdanm	0:9b334a45a8ff	568	__I uint32_t RESERVED6[18];
bogdanm	0:9b334a45a8ff	569	__IO uint32_t CLKOUTSEL; /!< (@ 0x400480E0) CLKOUT clock source select /
bogdanm	0:9b334a45a8ff	570	__IO uint32_t CLKOUTUEN; /!< (@ 0x400480E4) CLKOUT clock source update enable /
bogdanm	0:9b334a45a8ff	571	__IO uint32_t CLKOUTDIV; /!< (@ 0x400480E8) CLKOUT clock divider /
bogdanm	0:9b334a45a8ff	572	__I uint32_t RESERVED7;
bogdanm	0:9b334a45a8ff	573	__IO uint32_t UARTFRGDIV; /*!< (@ 0x400480F0) USART1 to USART4 common fractional generator
bogdanm	0:9b334a45a8ff	574	divider value */
bogdanm	0:9b334a45a8ff	575	__IO uint32_t UARTFRGMULT; /*!< (@ 0x400480F4) USART1 to USART4 common fractional generator
bogdanm	0:9b334a45a8ff	576	multiplier value */
bogdanm	0:9b334a45a8ff	577	__I uint32_t RESERVED8;
bogdanm	0:9b334a45a8ff	578	__IO uint32_t EXTTRACECMD; /!< (@ 0x400480FC) External trace buffer command register /
bogdanm	0:9b334a45a8ff	579	__I uint32_t PIOPORCAP0; /!< (@ 0x40048100) POR captured PIO status 0 /
bogdanm	0:9b334a45a8ff	580	__I uint32_t RESERVED9[12];
bogdanm	0:9b334a45a8ff	581	__IO uint32_t IOCONCLKDIV6; /*!< (@ 0x40048134) Peripheral clock 6 to the IOCON block for programmable
bogdanm	0:9b334a45a8ff	582	glitch filter */
bogdanm	0:9b334a45a8ff	583	__I uint32_t RESERVED10[6];
bogdanm	0:9b334a45a8ff	584	__IO uint32_t BODCTRL; /!< (@ 0x40048150) Brown-Out Detect /
bogdanm	0:9b334a45a8ff	585	__IO uint32_t SYSTCKCAL; /!< (@ 0x40048154) System tick counter calibration /
bogdanm	0:9b334a45a8ff	586	__I uint32_t RESERVED11[6];
bogdanm	0:9b334a45a8ff	587	__IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt
bogdanm	0:9b334a45a8ff	588	latency and determinism. */
bogdanm	0:9b334a45a8ff	589	__IO uint32_t NMISRC; /!< (@ 0x40048174) NMI Source Control /
bogdanm	0:9b334a45a8ff	590	union {
bogdanm	0:9b334a45a8ff	591	__IO uint32_t PINTSEL[8];
bogdanm	0:9b334a45a8ff	592	struct {
bogdanm	0:9b334a45a8ff	593	__IO uint32_t PINTSEL0; /!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	594	__IO uint32_t PINTSEL1; /!< (@ 0x4004817C) GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	595	__IO uint32_t PINTSEL2; /!< (@ 0x40048180) GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	596	__IO uint32_t PINTSEL3; /!< (@ 0x40048184) GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	597	__IO uint32_t PINTSEL4; /!< (@ 0x40048188) GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	598	__IO uint32_t PINTSEL5; /!< (@ 0x4004818C) GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	599	__IO uint32_t PINTSEL6; /!< (@ 0x40048190) GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	600	__IO uint32_t PINTSEL7; /!< (@ 0x40048194) GPIO Pin Interrupt Select register 0 /
bogdanm	0:9b334a45a8ff	601	};
bogdanm	0:9b334a45a8ff	602	};
bogdanm	0:9b334a45a8ff	603	__I uint32_t RESERVED12[27];
bogdanm	0:9b334a45a8ff	604	__IO uint32_t STARTERP0; /!< (@ 0x40048204) Start logic 0 pin wake-up enable register /
bogdanm	0:9b334a45a8ff	605	__I uint32_t RESERVED13[3];
bogdanm	0:9b334a45a8ff	606	__IO uint32_t STARTERP1; /!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register /
bogdanm	0:9b334a45a8ff	607	__I uint32_t RESERVED14[6];
bogdanm	0:9b334a45a8ff	608	__IO uint32_t PDSLEEPCFG; /!< (@ 0x40048230) Power-down states in deep-sleep mode /
bogdanm	0:9b334a45a8ff	609	__IO uint32_t PDAWAKECFG; /!< (@ 0x40048234) Power-down states for wake-up from deep-sleep /
bogdanm	0:9b334a45a8ff	610	__IO uint32_t PDRUNCFG; /!< (@ 0x40048238) Power configuration register /
bogdanm	0:9b334a45a8ff	611	__I uint32_t RESERVED15[111];
bogdanm	0:9b334a45a8ff	612	__I uint32_t DEVICE_ID; /!< (@ 0x400483F8) Device ID /
bogdanm	0:9b334a45a8ff	613	} LPC_SYSCON_Type;
bogdanm	0:9b334a45a8ff	614
bogdanm	0:9b334a45a8ff	615
bogdanm	0:9b334a45a8ff	616	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	617	/* ================ I2C0 ================ */
bogdanm	0:9b334a45a8ff	618	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	619
bogdanm	0:9b334a45a8ff	620
bogdanm	0:9b334a45a8ff	621	/**
bogdanm	0:9b334a45a8ff	622	* @brief I2C0-bus interface (I2C0)
bogdanm	0:9b334a45a8ff	623	*/
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625	typedef struct { /!< (@ 0x40050000) I2C0 Structure /
bogdanm	0:9b334a45a8ff	626	__IO uint32_t CFG; /!< (@ 0x40050000) Configuration for shared functions. /
bogdanm	0:9b334a45a8ff	627	__IO uint32_t STAT; /*!< (@ 0x40050004) Status register for Master, Slave, and Monitor
bogdanm	0:9b334a45a8ff	628	functions. */
bogdanm	0:9b334a45a8ff	629	__IO uint32_t INTENSET; /!< (@ 0x40050008) Interrupt Enable Set and read register. /
bogdanm	0:9b334a45a8ff	630	__O uint32_t INTENCLR; /!< (@ 0x4005000C) Interrupt Enable Clear register. /
bogdanm	0:9b334a45a8ff	631	__IO uint32_t TIMEOUT; /!< (@ 0x40050010) Time-out value register. /
bogdanm	0:9b334a45a8ff	632	__IO uint32_t CLKDIV; /*!< (@ 0x40050014) Clock pre-divider for the entire I2C block. This
bogdanm	0:9b334a45a8ff	633	determines what time increments are used for the MSTTIME and
bogdanm	0:9b334a45a8ff	634	SLVTIME registers. */
bogdanm	0:9b334a45a8ff	635	__I uint32_t INTSTAT; /*!< (@ 0x40050018) Interrupt Status register for Master, Slave,
bogdanm	0:9b334a45a8ff	636	and Monitor functions. */
bogdanm	0:9b334a45a8ff	637	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	638	__IO uint32_t MSTCTL; /!< (@ 0x40050020) Master control register. /
bogdanm	0:9b334a45a8ff	639	__IO uint32_t MSTTIME; /!< (@ 0x40050024) Master timing configuration. /
bogdanm	0:9b334a45a8ff	640	__IO uint32_t MSTDAT; /*!< (@ 0x40050028) Combined Master receiver and transmitter data
bogdanm	0:9b334a45a8ff	641	register. */
bogdanm	0:9b334a45a8ff	642	__I uint32_t RESERVED1[5];
bogdanm	0:9b334a45a8ff	643	__IO uint32_t SLVCTL; /!< (@ 0x40050040) Slave control register. /
bogdanm	0:9b334a45a8ff	644	__IO uint32_t SLVDAT; /*!< (@ 0x40050044) Combined Slave receiver and transmitter data
bogdanm	0:9b334a45a8ff	645	register. */
bogdanm	0:9b334a45a8ff	646	union {
bogdanm	0:9b334a45a8ff	647	__IO uint32_t SLVADR[4];
bogdanm	0:9b334a45a8ff	648	struct {
bogdanm	0:9b334a45a8ff	649	__IO uint32_t SLVADR0; /!< (@ 0x40050048) Slave address 0. /
bogdanm	0:9b334a45a8ff	650	__IO uint32_t SLVADR1; /!< (@ 0x4005004C) Slave address 0. /
bogdanm	0:9b334a45a8ff	651	__IO uint32_t SLVADR2; /!< (@ 0x40050050) Slave address 0. /
bogdanm	0:9b334a45a8ff	652	__IO uint32_t SLVADR3; /!< (@ 0x40050054) Slave address 0. /
bogdanm	0:9b334a45a8ff	653	};
bogdanm	0:9b334a45a8ff	654	};
bogdanm	0:9b334a45a8ff	655	__IO uint32_t SLVQUAL0; /!< (@ 0x40050058) Slave Qualification for address 0. /
bogdanm	0:9b334a45a8ff	656	__I uint32_t RESERVED2[9];
bogdanm	0:9b334a45a8ff	657	__I uint32_t MONRXDAT; /!< (@ 0x40050080) Monitor receiver data register. /
bogdanm	0:9b334a45a8ff	658	} LPC_I2C0_Type;
bogdanm	0:9b334a45a8ff	659
bogdanm	0:9b334a45a8ff	660
bogdanm	0:9b334a45a8ff	661	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	662	/* ================ SPI0 ================ */
bogdanm	0:9b334a45a8ff	663	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	664
bogdanm	0:9b334a45a8ff	665
bogdanm	0:9b334a45a8ff	666	/**
bogdanm	0:9b334a45a8ff	667	* @brief SPI0 (SPI0)
bogdanm	0:9b334a45a8ff	668	*/
bogdanm	0:9b334a45a8ff	669
bogdanm	0:9b334a45a8ff	670	typedef struct { /!< (@ 0x40058000) SPI0 Structure /
bogdanm	0:9b334a45a8ff	671	__IO uint32_t CFG; /!< (@ 0x40058000) SPI Configuration register /
bogdanm	0:9b334a45a8ff	672	__IO uint32_t DLY; /!< (@ 0x40058004) SPI Delay register /
bogdanm	0:9b334a45a8ff	673	__IO uint32_t STAT; /*!< (@ 0x40058008) SPI Status. Some status flags can be cleared
bogdanm	0:9b334a45a8ff	674	by writing a 1 to that bit position */
bogdanm	0:9b334a45a8ff	675	__IO uint32_t INTENSET; /*!< (@ 0x4005800C) SPI Interrupt Enable read and Set. A complete
bogdanm	0:9b334a45a8ff	676	value may be read from this register. Writing a 1 to any implemented
bogdanm	0:9b334a45a8ff	677	bit position causes that bit to be set. */
bogdanm	0:9b334a45a8ff	678	__O uint32_t INTENCLR; /*!< (@ 0x40058010) SPI Interrupt Enable Clear. Writing a 1 to any
bogdanm	0:9b334a45a8ff	679	implemented bit position causes the corresponding bit in INTENSET
bogdanm	0:9b334a45a8ff	680	to be cleared. */
bogdanm	0:9b334a45a8ff	681	__I uint32_t RXDAT; /!< (@ 0x40058014) SPI Receive Data /
bogdanm	0:9b334a45a8ff	682	__IO uint32_t TXDATCTL; /!< (@ 0x40058018) SPI Transmit Data with Control /
bogdanm	0:9b334a45a8ff	683	__IO uint32_t TXDAT; /!< (@ 0x4005801C) SPI Transmit Data /
bogdanm	0:9b334a45a8ff	684	__IO uint32_t TXCTL; /!< (@ 0x40058020) SPI Transmit Control /
bogdanm	0:9b334a45a8ff	685	__IO uint32_t DIV; /!< (@ 0x40058024) SPI clock Divider /
bogdanm	0:9b334a45a8ff	686	__I uint32_t INTSTAT; /!< (@ 0x40058028) SPI Interrupt Status /
bogdanm	0:9b334a45a8ff	687	} LPC_SPI0_Type;
bogdanm	0:9b334a45a8ff	688
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	691	/* ================ USART0 ================ */
bogdanm	0:9b334a45a8ff	692	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694
bogdanm	0:9b334a45a8ff	695	/**
bogdanm	0:9b334a45a8ff	696	* @brief USART0 (USART0)
bogdanm	0:9b334a45a8ff	697	*/
bogdanm	0:9b334a45a8ff	698
bogdanm	0:9b334a45a8ff	699	typedef struct { /!< (@ 0x40064000) USART0 Structure /
bogdanm	0:9b334a45a8ff	700	__IO uint32_t CFG; /*!< (@ 0x40064000) USART Configuration register. Basic USART configuration
bogdanm	0:9b334a45a8ff	701	settings that typically are not changed during operation. */
bogdanm	0:9b334a45a8ff	702	__IO uint32_t CTL; /*!< (@ 0x40064004) USART Control register. USART control settings
bogdanm	0:9b334a45a8ff	703	that are more likely to change during operation. */
bogdanm	0:9b334a45a8ff	704	__IO uint32_t STAT; /*!< (@ 0x40064008) USART Status register. The complete status value
bogdanm	0:9b334a45a8ff	705	can be read here. Writing ones clears some bits in the register.
bogdanm	0:9b334a45a8ff	706	Some bits can be cleared by writing a 1 to them. */
bogdanm	0:9b334a45a8ff	707	__IO uint32_t INTENSET; /*!< (@ 0x4006400C) Interrupt Enable read and Set register. Contains
bogdanm	0:9b334a45a8ff	708	an individual interrupt enable bit for each potential USART
bogdanm	0:9b334a45a8ff	709	interrupt. A complete value may be read from this register.
bogdanm	0:9b334a45a8ff	710	Writing a 1 to any implemented bit position causes that bit
bogdanm	0:9b334a45a8ff	711	to be set. */
bogdanm	0:9b334a45a8ff	712	__O uint32_t INTENCLR; /*!< (@ 0x40064010) Interrupt Enable Clear register. Allows clearing
bogdanm	0:9b334a45a8ff	713	any combination of bits in the INTENSET register. Writing a
bogdanm	0:9b334a45a8ff	714	1 to any implemented bit position causes the corresponding bit
bogdanm	0:9b334a45a8ff	715	to be cleared. */
bogdanm	0:9b334a45a8ff	716	__I uint32_t RXDAT; /*!< (@ 0x40064014) Receiver Data register. Contains the last character
bogdanm	0:9b334a45a8ff	717	received. */
bogdanm	0:9b334a45a8ff	718	__I uint32_t RXDATSTAT; /*!< (@ 0x40064018) Receiver Data with Status register. Combines
bogdanm	0:9b334a45a8ff	719	the last character received with the current USART receive status.
bogdanm	0:9b334a45a8ff	720	Allows DMA or software to recover incoming data and status together. */
bogdanm	0:9b334a45a8ff	721	__IO uint32_t TXDAT; /*!< (@ 0x4006401C) Transmit Data register. Data to be transmitted
bogdanm	0:9b334a45a8ff	722	is written here. */
bogdanm	0:9b334a45a8ff	723	__IO uint32_t BRG; /*!< (@ 0x40064020) Baud Rate Generator register. 16-bit integer
bogdanm	0:9b334a45a8ff	724	baud rate divisor value. */
bogdanm	0:9b334a45a8ff	725	__I uint32_t INTSTAT; /*!< (@ 0x40064024) Interrupt status register. Reflects interrupts
bogdanm	0:9b334a45a8ff	726	that are currently enabled. */
bogdanm	0:9b334a45a8ff	727	__IO uint32_t OSR; /*!< (@ 0x40064028) Oversample selection register for asynchronous
bogdanm	0:9b334a45a8ff	728	communication. */
bogdanm	0:9b334a45a8ff	729	__IO uint32_t ADDR; /!< (@ 0x4006402C) Address register for automatic address matching. /
bogdanm	0:9b334a45a8ff	730	} LPC_USART0_Type;
bogdanm	0:9b334a45a8ff	731
bogdanm	0:9b334a45a8ff	732
bogdanm	0:9b334a45a8ff	733	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	734	/* ================ CRC ================ */
bogdanm	0:9b334a45a8ff	735	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	736
bogdanm	0:9b334a45a8ff	737
bogdanm	0:9b334a45a8ff	738	/**
bogdanm	0:9b334a45a8ff	739	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
bogdanm	0:9b334a45a8ff	740	*/
bogdanm	0:9b334a45a8ff	741
bogdanm	0:9b334a45a8ff	742	typedef struct { /!< (@ 0x50000000) CRC Structure /
bogdanm	0:9b334a45a8ff	743	__IO uint32_t MODE; /!< (@ 0x50000000) CRC mode register /
bogdanm	0:9b334a45a8ff	744	__IO uint32_t SEED; /!< (@ 0x50000004) CRC seed register /
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	union {
bogdanm	0:9b334a45a8ff	747	__O uint32_t WR_DATA; /!< (@ 0x50000008) CRC data register /
bogdanm	0:9b334a45a8ff	748	__I uint32_t SUM; /!< (@ 0x50000008) CRC checksum register /
bogdanm	0:9b334a45a8ff	749	};
bogdanm	0:9b334a45a8ff	750	} LPC_CRC_Type;
bogdanm	0:9b334a45a8ff	751
bogdanm	0:9b334a45a8ff	752
bogdanm	0:9b334a45a8ff	753	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	754	/* ================ SCT ================ */
bogdanm	0:9b334a45a8ff	755	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757
bogdanm	0:9b334a45a8ff	758	/**
bogdanm	0:9b334a45a8ff	759	* @brief State Configurable Timer (SCT) (SCT)
bogdanm	0:9b334a45a8ff	760	*/
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762	typedef struct { /!< (@ 0x50004000) SCT Structure /
bogdanm	0:9b334a45a8ff	763	__IO uint32_t CONFIG; /!< (@ 0x50004000) SCT configuration register /
bogdanm	0:9b334a45a8ff	764	__IO uint32_t CTRL; /!< (@ 0x50004004) SCT control register /
bogdanm	0:9b334a45a8ff	765	__IO uint32_t LIMIT; /!< (@ 0x50004008) SCT limit register /
bogdanm	0:9b334a45a8ff	766	__IO uint32_t HALT; /!< (@ 0x5000400C) SCT halt condition register /
bogdanm	0:9b334a45a8ff	767	__IO uint32_t STOP; /!< (@ 0x50004010) SCT stop condition register /
bogdanm	0:9b334a45a8ff	768	__IO uint32_t START; /!< (@ 0x50004014) SCT start condition register /
bogdanm	0:9b334a45a8ff	769	__I uint32_t RESERVED0[10];
bogdanm	0:9b334a45a8ff	770	__IO uint32_t COUNT; /!< (@ 0x50004040) SCT counter register /
bogdanm	0:9b334a45a8ff	771	__IO uint32_t STATE; /!< (@ 0x50004044) SCT state register /
bogdanm	0:9b334a45a8ff	772	__I uint32_t INPUT; /!< (@ 0x50004048) SCT input register /
bogdanm	0:9b334a45a8ff	773	__IO uint32_t REGMODE; /!< (@ 0x5000404C) SCT match/capture registers mode register /
bogdanm	0:9b334a45a8ff	774	__IO uint32_t OUTPUT; /!< (@ 0x50004050) SCT output register /
bogdanm	0:9b334a45a8ff	775	__IO uint32_t OUTPUTDIRCTRL; /!< (@ 0x50004054) SCT output counter direction control register /
bogdanm	0:9b334a45a8ff	776	__IO uint32_t RES; /!< (@ 0x50004058) SCT conflict resolution register /
bogdanm	0:9b334a45a8ff	777	__IO uint32_t DMAREQ0; /!< (@ 0x5000405C) SCT DMA request 0 register /
bogdanm	0:9b334a45a8ff	778	__IO uint32_t DMAREQ1; /!< (@ 0x50004060) SCT DMA request 1 register /
bogdanm	0:9b334a45a8ff	779	__I uint32_t RESERVED1[35];
bogdanm	0:9b334a45a8ff	780	__IO uint32_t EVEN; /!< (@ 0x500040F0) SCT event enable register /
bogdanm	0:9b334a45a8ff	781	__IO uint32_t EVFLAG; /!< (@ 0x500040F4) SCT event flag register /
bogdanm	0:9b334a45a8ff	782	__IO uint32_t CONEN; /!< (@ 0x500040F8) SCT conflict enable register /
bogdanm	0:9b334a45a8ff	783	__IO uint32_t CONFLAG; /!< (@ 0x500040FC) SCT conflict flag register /
bogdanm	0:9b334a45a8ff	784
bogdanm	0:9b334a45a8ff	785	union {
bogdanm	0:9b334a45a8ff	786	union {
bogdanm	0:9b334a45a8ff	787	__IO uint32_t CAP0; /*!< (@ 0x50004100) SCT capture register of capture channel 0 to
bogdanm	0:9b334a45a8ff	788	7; REGMOD0 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	789	__IO uint32_t MATCH0; /*!< (@ 0x50004100) SCT match value register of match channels 0
bogdanm	0:9b334a45a8ff	790	to 7; REGMOD0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	791	};
bogdanm	0:9b334a45a8ff	792
bogdanm	0:9b334a45a8ff	793	union {
bogdanm	0:9b334a45a8ff	794	__IO uint32_t CAP1; /*!< (@ 0x50004104) SCT capture register of capture channel 0 to
bogdanm	0:9b334a45a8ff	795	7; REGMOD0 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	796	__IO uint32_t MATCH1; /*!< (@ 0x50004104) SCT match value register of match channels 0
bogdanm	0:9b334a45a8ff	797	to 7; REGMOD0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	798	};
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	union {
bogdanm	0:9b334a45a8ff	801	__IO uint32_t CAP2; /*!< (@ 0x50004108) SCT capture register of capture channel 0 to
bogdanm	0:9b334a45a8ff	802	7; REGMOD0 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	803	__IO uint32_t MATCH2; /*!< (@ 0x50004108) SCT match value register of match channels 0
bogdanm	0:9b334a45a8ff	804	to 7; REGMOD0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	805	};
bogdanm	0:9b334a45a8ff	806
bogdanm	0:9b334a45a8ff	807	union {
bogdanm	0:9b334a45a8ff	808	__IO uint32_t MATCH3; /*!< (@ 0x5000410C) SCT match value register of match channels 0
bogdanm	0:9b334a45a8ff	809	to 7; REGMOD0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	810	__IO uint32_t CAP3; /*!< (@ 0x5000410C) SCT capture register of capture channel 0 to
bogdanm	0:9b334a45a8ff	811	7; REGMOD0 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	812	};
bogdanm	0:9b334a45a8ff	813
bogdanm	0:9b334a45a8ff	814	union {
bogdanm	0:9b334a45a8ff	815	__IO uint32_t CAP4; /*!< (@ 0x50004110) SCT capture register of capture channel 0 to
bogdanm	0:9b334a45a8ff	816	7; REGMOD0 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	817	__IO uint32_t MATCH4; /*!< (@ 0x50004110) SCT match value register of match channels 0
bogdanm	0:9b334a45a8ff	818	to 7; REGMOD0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	819	};
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	union {
bogdanm	0:9b334a45a8ff	822	__IO uint32_t MATCH5; /*!< (@ 0x50004114) SCT match value register of match channels 0
bogdanm	0:9b334a45a8ff	823	to 7; REGMOD0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	824	__IO uint32_t CAP5; /*!< (@ 0x50004114) SCT capture register of capture channel 0 to
bogdanm	0:9b334a45a8ff	825	7; REGMOD0 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	826	};
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	union {
bogdanm	0:9b334a45a8ff	829	__IO uint32_t CAP6; /*!< (@ 0x50004118) SCT capture register of capture channel 0 to
bogdanm	0:9b334a45a8ff	830	7; REGMOD0 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	831	__IO uint32_t MATCH6; /*!< (@ 0x50004118) SCT match value register of match channels 0
bogdanm	0:9b334a45a8ff	832	to 7; REGMOD0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	833	};
bogdanm	0:9b334a45a8ff	834
bogdanm	0:9b334a45a8ff	835	union {
bogdanm	0:9b334a45a8ff	836	__IO uint32_t CAP7; /*!< (@ 0x5000411C) SCT capture register of capture channel 0 to
bogdanm	0:9b334a45a8ff	837	7; REGMOD0 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	838	__IO uint32_t MATCH7; /*!< (@ 0x5000411C) SCT match value register of match channels 0
bogdanm	0:9b334a45a8ff	839	to 7; REGMOD0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	840	};
bogdanm	0:9b334a45a8ff	841	__IO uint32_t CAP[8];
bogdanm	0:9b334a45a8ff	842	__IO uint32_t MATCH[8];
bogdanm	0:9b334a45a8ff	843	};
bogdanm	0:9b334a45a8ff	844	__I uint32_t RESERVED2[56];
bogdanm	0:9b334a45a8ff	845
bogdanm	0:9b334a45a8ff	846	union {
bogdanm	0:9b334a45a8ff	847	struct {
bogdanm	0:9b334a45a8ff	848	union {
bogdanm	0:9b334a45a8ff	849	__IO uint32_t CAPCTRL0; /*!< (@ 0x50004200) SCT capture control register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	850	= 1 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	851	__IO uint32_t MATCHREL0; /*!< (@ 0x50004200) SCT match reload value register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	852	= 0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	853	};
bogdanm	0:9b334a45a8ff	854
bogdanm	0:9b334a45a8ff	855	union {
bogdanm	0:9b334a45a8ff	856	__IO uint32_t CAPCTRL1; /*!< (@ 0x50004204) SCT capture control register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	857	= 1 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	858	__IO uint32_t MATCHREL1; /*!< (@ 0x50004204) SCT match reload value register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	859	= 0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	860	};
bogdanm	0:9b334a45a8ff	861
bogdanm	0:9b334a45a8ff	862	union {
bogdanm	0:9b334a45a8ff	863	__IO uint32_t CAPCTRL2; /*!< (@ 0x50004208) SCT capture control register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	864	= 1 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	865	__IO uint32_t MATCHREL2; /*!< (@ 0x50004208) SCT match reload value register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	866	= 0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	867	};
bogdanm	0:9b334a45a8ff	868
bogdanm	0:9b334a45a8ff	869	union {
bogdanm	0:9b334a45a8ff	870	__IO uint32_t MATCHREL3; /*!< (@ 0x5000420C) SCT match reload value register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	871	= 0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	872	__IO uint32_t CAPCTRL3; /*!< (@ 0x5000420C) SCT capture control register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	873	= 1 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	874	};
bogdanm	0:9b334a45a8ff	875
bogdanm	0:9b334a45a8ff	876	union {
bogdanm	0:9b334a45a8ff	877	__IO uint32_t CAPCTRL4; /*!< (@ 0x50004210) SCT capture control register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	878	= 1 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	879	__IO uint32_t MATCHREL4; /*!< (@ 0x50004210) SCT match reload value register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	880	= 0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	881	};
bogdanm	0:9b334a45a8ff	882
bogdanm	0:9b334a45a8ff	883	union {
bogdanm	0:9b334a45a8ff	884	__IO uint32_t CAPCTRL5; /*!< (@ 0x50004214) SCT capture control register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	885	= 1 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	886	__IO uint32_t MATCHREL5; /*!< (@ 0x50004214) SCT match reload value register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	887	= 0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	888	};
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	union {
bogdanm	0:9b334a45a8ff	891	__IO uint32_t CAPCTRL6; /*!< (@ 0x50004218) SCT capture control register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	892	= 1 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	893	__IO uint32_t MATCHREL6; /*!< (@ 0x50004218) SCT match reload value register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	894	= 0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	895	};
bogdanm	0:9b334a45a8ff	896
bogdanm	0:9b334a45a8ff	897	union {
bogdanm	0:9b334a45a8ff	898	__IO uint32_t CAPCTRL7; /*!< (@ 0x5000421C) SCT capture control register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	899	= 1 to REGMODE7 = 1 */
bogdanm	0:9b334a45a8ff	900	__IO uint32_t MATCHREL7; /*!< (@ 0x5000421C) SCT match reload value register 0 to 7; REGMOD0
bogdanm	0:9b334a45a8ff	901	= 0 to REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	902	};
bogdanm	0:9b334a45a8ff	903	};
bogdanm	0:9b334a45a8ff	904	__IO uint32_t MATCHREL[8];
bogdanm	0:9b334a45a8ff	905	};
bogdanm	0:9b334a45a8ff	906	__I uint32_t RESERVED3[56];
bogdanm	0:9b334a45a8ff	907
bogdanm	0:9b334a45a8ff	908	union {
bogdanm	0:9b334a45a8ff	909	struct {
bogdanm	0:9b334a45a8ff	910	__IO uint32_t EV0_STATE; /!< (@ 0x50004300) SCT event state register 0 /
bogdanm	0:9b334a45a8ff	911	__IO uint32_t EV0_CTRL; /!< (@ 0x50004304) SCT event control register 0 /
bogdanm	0:9b334a45a8ff	912	__IO uint32_t EV1_STATE; /!< (@ 0x50004308) SCT event state register 0 /
bogdanm	0:9b334a45a8ff	913	__IO uint32_t EV1_CTRL; /!< (@ 0x5000430C) SCT event control register 0 /
bogdanm	0:9b334a45a8ff	914	__IO uint32_t EV2_STATE; /!< (@ 0x50004310) SCT event state register 0 /
bogdanm	0:9b334a45a8ff	915	__IO uint32_t EV2_CTRL; /!< (@ 0x50004314) SCT event control register 0 /
bogdanm	0:9b334a45a8ff	916	__IO uint32_t EV3_STATE; /!< (@ 0x50004318) SCT event state register 0 /
bogdanm	0:9b334a45a8ff	917	__IO uint32_t EV3_CTRL; /!< (@ 0x5000431C) SCT event control register 0 /
bogdanm	0:9b334a45a8ff	918	__IO uint32_t EV4_STATE; /!< (@ 0x50004320) SCT event state register 0 /
bogdanm	0:9b334a45a8ff	919	__IO uint32_t EV4_CTRL; /!< (@ 0x50004324) SCT event control register 0 /
bogdanm	0:9b334a45a8ff	920	__IO uint32_t EV5_STATE; /!< (@ 0x50004328) SCT event state register 0 /
bogdanm	0:9b334a45a8ff	921	__IO uint32_t EV5_CTRL; /!< (@ 0x5000432C) SCT event control register 0 /
bogdanm	0:9b334a45a8ff	922	__IO uint32_t EV6_STATE; /!< (@ 0x50004330) SCT event state register 0 /
bogdanm	0:9b334a45a8ff	923	__IO uint32_t EV6_CTRL; /!< (@ 0x50004334) SCT event control register 0 /
bogdanm	0:9b334a45a8ff	924	__IO uint32_t EV7_STATE; /!< (@ 0x50004338) SCT event state register 0 /
bogdanm	0:9b334a45a8ff	925	__IO uint32_t EV7_CTRL; /!< (@ 0x5000433C) SCT event control register 0 /
bogdanm	0:9b334a45a8ff	926	};
bogdanm	0:9b334a45a8ff	927	__IO struct {
bogdanm	0:9b334a45a8ff	928	uint32_t STATE;
bogdanm	0:9b334a45a8ff	929	uint32_t CTRL;
bogdanm	0:9b334a45a8ff	930	} EVENT[8];
bogdanm	0:9b334a45a8ff	931	};
bogdanm	0:9b334a45a8ff	932
bogdanm	0:9b334a45a8ff	933	__I uint32_t RESERVED4[112];
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	union {
bogdanm	0:9b334a45a8ff	936	struct {
bogdanm	0:9b334a45a8ff	937	__IO uint32_t OUT0_SET; /!< (@ 0x50004500) SCT output 0 set register /
bogdanm	0:9b334a45a8ff	938	__IO uint32_t OUT0_CLR; /!< (@ 0x50004504) SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	939	__IO uint32_t OUT1_SET; /!< (@ 0x50004508) SCT output 0 set register /
bogdanm	0:9b334a45a8ff	940	__IO uint32_t OUT1_CLR; /!< (@ 0x5000450C) SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	941	__IO uint32_t OUT2_SET; /!< (@ 0x50004510) SCT output 0 set register /
bogdanm	0:9b334a45a8ff	942	__IO uint32_t OUT2_CLR; /!< (@ 0x50004514) SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	943	__IO uint32_t OUT3_SET; /!< (@ 0x50004518) SCT output 0 set register /
bogdanm	0:9b334a45a8ff	944	__IO uint32_t OUT3_CLR; /!< (@ 0x5000451C) SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	945	__IO uint32_t OUT4_SET; /!< (@ 0x50004520) SCT output 0 set register /
bogdanm	0:9b334a45a8ff	946	__IO uint32_t OUT4_CLR; /!< (@ 0x50004524) SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	947	__IO uint32_t OUT5_SET; /!< (@ 0x50004528) SCT output 0 set register /
bogdanm	0:9b334a45a8ff	948	__IO uint32_t OUT5_CLR; /!< (@ 0x5000452C) SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	949	};
bogdanm	0:9b334a45a8ff	950	__IO struct {
bogdanm	0:9b334a45a8ff	951	uint32_t SET;
bogdanm	0:9b334a45a8ff	952	uint32_t CLR;
bogdanm	0:9b334a45a8ff	953	} OUT[6];
bogdanm	0:9b334a45a8ff	954	};
bogdanm	0:9b334a45a8ff	955
bogdanm	0:9b334a45a8ff	956	} LPC_SCT_Type;
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	960	/* ================ DMA ================ */
bogdanm	0:9b334a45a8ff	961	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963
bogdanm	0:9b334a45a8ff	964	/**
bogdanm	0:9b334a45a8ff	965	* @brief DMA controller (DMA)
bogdanm	0:9b334a45a8ff	966	*/
bogdanm	0:9b334a45a8ff	967
bogdanm	0:9b334a45a8ff	968	typedef struct { /!< (@ 0x50008000) DMA Structure /
bogdanm	0:9b334a45a8ff	969	__IO uint32_t CTRL; /!< (@ 0x50008000) DMA control. /
bogdanm	0:9b334a45a8ff	970	__I uint32_t INTSTAT; /!< (@ 0x50008004) Interrupt status. /
bogdanm	0:9b334a45a8ff	971	__IO uint32_t SRAMBASE; /!< (@ 0x50008008) SRAM address of the channel configuration table. /
bogdanm	0:9b334a45a8ff	972	__I uint32_t RESERVED0[5];
bogdanm	0:9b334a45a8ff	973	__IO uint32_t ENABLESET0; /!< (@ 0x50008020) Channel Enable read and Set for all DMA channels. /
bogdanm	0:9b334a45a8ff	974	__I uint32_t RESERVED1;
bogdanm	0:9b334a45a8ff	975	__O uint32_t ENABLECLR0; /!< (@ 0x50008028) Channel Enable Clear for all DMA channels. /
bogdanm	0:9b334a45a8ff	976	__I uint32_t RESERVED2;
bogdanm	0:9b334a45a8ff	977	__I uint32_t ACTIVE0; /!< (@ 0x50008030) Channel Active status for all DMA channels. /
bogdanm	0:9b334a45a8ff	978	__I uint32_t RESERVED3;
bogdanm	0:9b334a45a8ff	979	__I uint32_t BUSY0; /!< (@ 0x50008038) Channel Busy status for all DMA channels. /
bogdanm	0:9b334a45a8ff	980	__I uint32_t RESERVED4;
bogdanm	0:9b334a45a8ff	981	__IO uint32_t ERRINT0; /!< (@ 0x50008040) Error Interrupt status for all DMA channels. /
bogdanm	0:9b334a45a8ff	982	__I uint32_t RESERVED5;
bogdanm	0:9b334a45a8ff	983	__IO uint32_t INTENSET0; /!< (@ 0x50008048) Interrupt Enable read and Set for all DMA channels. /
bogdanm	0:9b334a45a8ff	984	__I uint32_t RESERVED6;
bogdanm	0:9b334a45a8ff	985	__O uint32_t INTENCLR0; /!< (@ 0x50008050) Interrupt Enable Clear for all DMA channels. /
bogdanm	0:9b334a45a8ff	986	__I uint32_t RESERVED7;
bogdanm	0:9b334a45a8ff	987	__IO uint32_t INTA0; /!< (@ 0x50008058) Interrupt A status for all DMA channels. /
bogdanm	0:9b334a45a8ff	988	__I uint32_t RESERVED8;
bogdanm	0:9b334a45a8ff	989	__IO uint32_t INTB0; /!< (@ 0x50008060) Interrupt B status for all DMA channels. /
bogdanm	0:9b334a45a8ff	990	__I uint32_t RESERVED9;
bogdanm	0:9b334a45a8ff	991	__O uint32_t SETVALID0; /!< (@ 0x50008068) Set ValidPending control bits for all DMA channels. /
bogdanm	0:9b334a45a8ff	992	__I uint32_t RESERVED10;
bogdanm	0:9b334a45a8ff	993	__O uint32_t SETTRIG0; /!< (@ 0x50008070) Set Trigger control bits for all DMA channels. /
bogdanm	0:9b334a45a8ff	994	__I uint32_t RESERVED11;
bogdanm	0:9b334a45a8ff	995	__O uint32_t ABORT0; /!< (@ 0x50008078) Channel Abort control for all DMA channels. /
bogdanm	0:9b334a45a8ff	996	__I uint32_t RESERVED12[225];
bogdanm	0:9b334a45a8ff	997	__IO uint32_t CFG0; /!< (@ 0x50008400) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	998	__I uint32_t CTLSTAT0; /!< (@ 0x50008404) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	999	__IO uint32_t XFERCFG0; /*!< (@ 0x50008408) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1000	0. */
bogdanm	0:9b334a45a8ff	1001	__I uint32_t RESERVED13;
bogdanm	0:9b334a45a8ff	1002	__IO uint32_t CFG1; /!< (@ 0x50008410) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1003	__I uint32_t CTLSTAT1; /!< (@ 0x50008414) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1004	__IO uint32_t XFERCFG1; /*!< (@ 0x50008418) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1005	0. */
bogdanm	0:9b334a45a8ff	1006	__I uint32_t RESERVED14;
bogdanm	0:9b334a45a8ff	1007	__IO uint32_t CFG2; /!< (@ 0x50008420) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1008	__I uint32_t CTLSTAT2; /!< (@ 0x50008424) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1009	__IO uint32_t XFERCFG2; /*!< (@ 0x50008428) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1010	0. */
bogdanm	0:9b334a45a8ff	1011	__I uint32_t RESERVED15;
bogdanm	0:9b334a45a8ff	1012	__IO uint32_t CFG3; /!< (@ 0x50008430) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1013	__I uint32_t CTLSTAT3; /!< (@ 0x50008434) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1014	__IO uint32_t XFERCFG3; /*!< (@ 0x50008438) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1015	0. */
bogdanm	0:9b334a45a8ff	1016	__I uint32_t RESERVED16;
bogdanm	0:9b334a45a8ff	1017	__IO uint32_t CFG4; /!< (@ 0x50008440) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1018	__I uint32_t CTLSTAT4; /!< (@ 0x50008444) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1019	__IO uint32_t XFERCFG4; /*!< (@ 0x50008448) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1020	0. */
bogdanm	0:9b334a45a8ff	1021	__I uint32_t RESERVED17;
bogdanm	0:9b334a45a8ff	1022	__IO uint32_t CFG5; /!< (@ 0x50008450) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1023	__I uint32_t CTLSTAT5; /!< (@ 0x50008454) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1024	__IO uint32_t XFERCFG5; /*!< (@ 0x50008458) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1025	0. */
bogdanm	0:9b334a45a8ff	1026	__I uint32_t RESERVED18;
bogdanm	0:9b334a45a8ff	1027	__IO uint32_t CFG6; /!< (@ 0x50008460) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1028	__I uint32_t CTLSTAT6; /!< (@ 0x50008464) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1029	__IO uint32_t XFERCFG6; /*!< (@ 0x50008468) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1030	0. */
bogdanm	0:9b334a45a8ff	1031	__I uint32_t RESERVED19;
bogdanm	0:9b334a45a8ff	1032	__IO uint32_t CFG7; /!< (@ 0x50008470) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1033	__I uint32_t CTLSTAT7; /!< (@ 0x50008474) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1034	__IO uint32_t XFERCFG7; /*!< (@ 0x50008478) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1035	0. */
bogdanm	0:9b334a45a8ff	1036	__I uint32_t RESERVED20;
bogdanm	0:9b334a45a8ff	1037	__IO uint32_t CFG8; /!< (@ 0x50008480) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1038	__I uint32_t CTLSTAT8; /!< (@ 0x50008484) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1039	__IO uint32_t XFERCFG8; /*!< (@ 0x50008488) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1040	0. */
bogdanm	0:9b334a45a8ff	1041	__I uint32_t RESERVED21;
bogdanm	0:9b334a45a8ff	1042	__IO uint32_t CFG9; /!< (@ 0x50008490) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1043	__I uint32_t CTLSTAT9; /!< (@ 0x50008494) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1044	__IO uint32_t XFERCFG9; /*!< (@ 0x50008498) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1045	0. */
bogdanm	0:9b334a45a8ff	1046	__I uint32_t RESERVED22;
bogdanm	0:9b334a45a8ff	1047	__IO uint32_t CFG10; /!< (@ 0x500084A0) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1048	__I uint32_t CTLSTAT10; /!< (@ 0x500084A4) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1049	__IO uint32_t XFERCFG10; /*!< (@ 0x500084A8) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1050	0. */
bogdanm	0:9b334a45a8ff	1051	__I uint32_t RESERVED23;
bogdanm	0:9b334a45a8ff	1052	__IO uint32_t CFG11; /!< (@ 0x500084B0) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1053	__I uint32_t CTLSTAT11; /!< (@ 0x500084B4) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1054	__IO uint32_t XFERCFG11; /*!< (@ 0x500084B8) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1055	0. */
bogdanm	0:9b334a45a8ff	1056	__I uint32_t RESERVED24;
bogdanm	0:9b334a45a8ff	1057	__IO uint32_t CFG12; /!< (@ 0x500084C0) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1058	__I uint32_t CTLSTAT12; /!< (@ 0x500084C4) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1059	__IO uint32_t XFERCFG12; /*!< (@ 0x500084C8) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1060	0. */
bogdanm	0:9b334a45a8ff	1061	__I uint32_t RESERVED25;
bogdanm	0:9b334a45a8ff	1062	__IO uint32_t CFG13; /!< (@ 0x500084D0) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1063	__I uint32_t CTLSTAT13; /!< (@ 0x500084D4) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1064	__IO uint32_t XFERCFG13; /*!< (@ 0x500084D8) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1065	0. */
bogdanm	0:9b334a45a8ff	1066	__I uint32_t RESERVED26;
bogdanm	0:9b334a45a8ff	1067	__IO uint32_t CFG14; /!< (@ 0x500084E0) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1068	__I uint32_t CTLSTAT14; /!< (@ 0x500084E4) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1069	__IO uint32_t XFERCFG14; /*!< (@ 0x500084E8) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1070	0. */
bogdanm	0:9b334a45a8ff	1071	__I uint32_t RESERVED27;
bogdanm	0:9b334a45a8ff	1072	__IO uint32_t CFG15; /!< (@ 0x500084F0) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1073	__I uint32_t CTLSTAT15; /!< (@ 0x500084F4) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1074	__IO uint32_t XFERCFG15; /*!< (@ 0x500084F8) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1075	0. */
bogdanm	0:9b334a45a8ff	1076	__I uint32_t RESERVED28;
bogdanm	0:9b334a45a8ff	1077	__IO uint32_t CFG16; /!< (@ 0x50008500) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1078	__I uint32_t CTLSTAT16; /!< (@ 0x50008504) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1079	__IO uint32_t XFERCFG16; /*!< (@ 0x50008508) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1080	0. */
bogdanm	0:9b334a45a8ff	1081	__I uint32_t RESERVED29;
bogdanm	0:9b334a45a8ff	1082	__IO uint32_t CFG17; /!< (@ 0x50008510) Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1083	__I uint32_t CTLSTAT17; /!< (@ 0x50008514) Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	1084	__IO uint32_t XFERCFG17; /*!< (@ 0x50008518) Transfer configuration register for DMA channel
bogdanm	0:9b334a45a8ff	1085	0. */
bogdanm	0:9b334a45a8ff	1086	} LPC_DMA_Type;
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088
bogdanm	0:9b334a45a8ff	1089	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1090	/* ================ GPIO_PORT ================ */
bogdanm	0:9b334a45a8ff	1091	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1092
bogdanm	0:9b334a45a8ff	1093
bogdanm	0:9b334a45a8ff	1094	/**
bogdanm	0:9b334a45a8ff	1095	* @brief General Purpose I/O port (GPIO) (GPIO_PORT)
bogdanm	0:9b334a45a8ff	1096	*/
bogdanm	0:9b334a45a8ff	1097
bogdanm	0:9b334a45a8ff	1098	typedef struct { /!< (@ 0xA0000000) GPIO_PORT Structure /
bogdanm	0:9b334a45a8ff	1099	__IO uint8_t B0; /!< (@ 0xA0000000) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1100	__IO uint8_t B1; /!< (@ 0xA0000001) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1101	__IO uint8_t B2; /!< (@ 0xA0000002) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1102	__IO uint8_t B3; /!< (@ 0xA0000003) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1103	__IO uint8_t B4; /!< (@ 0xA0000004) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1104	__IO uint8_t B5; /!< (@ 0xA0000005) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1105	__IO uint8_t B6; /!< (@ 0xA0000006) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1106	__IO uint8_t B7; /!< (@ 0xA0000007) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1107	__IO uint8_t B8; /!< (@ 0xA0000008) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1108	__IO uint8_t B9; /!< (@ 0xA0000009) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1109	__IO uint8_t B10; /!< (@ 0xA000000A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1110	__IO uint8_t B11; /!< (@ 0xA000000B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1111	__IO uint8_t B12; /!< (@ 0xA000000C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1112	__IO uint8_t B13; /!< (@ 0xA000000D) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1113	__IO uint8_t B14; /!< (@ 0xA000000E) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1114	__IO uint8_t B15; /!< (@ 0xA000000F) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1115	__IO uint8_t B16; /!< (@ 0xA0000010) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1116	__IO uint8_t B17; /!< (@ 0xA0000011) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1117	__IO uint8_t B18; /!< (@ 0xA0000012) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1118	__IO uint8_t B19; /!< (@ 0xA0000013) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1119	__IO uint8_t B20; /!< (@ 0xA0000014) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1120	__IO uint8_t B21; /!< (@ 0xA0000015) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1121	__IO uint8_t B22; /!< (@ 0xA0000016) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1122	__IO uint8_t B23; /!< (@ 0xA0000017) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1123	__IO uint8_t B24; /!< (@ 0xA0000018) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1124	__IO uint8_t B25; /!< (@ 0xA0000019) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1125	__IO uint8_t B26; /!< (@ 0xA000001A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1126	__IO uint8_t B27; /!< (@ 0xA000001B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1127	__IO uint8_t B28; /!< (@ 0xA000001C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 /
bogdanm	0:9b334a45a8ff	1128	__I uint8_t RESERVED0[4067];
bogdanm	0:9b334a45a8ff	1129	__IO uint32_t W0; /!< (@ 0xA0001000) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1130	__IO uint32_t W1; /!< (@ 0xA0001004) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1131	__IO uint32_t W2; /!< (@ 0xA0001008) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1132	__IO uint32_t W3; /!< (@ 0xA000100C) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1133	__IO uint32_t W4; /!< (@ 0xA0001010) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1134	__IO uint32_t W5; /!< (@ 0xA0001014) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1135	__IO uint32_t W6; /!< (@ 0xA0001018) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1136	__IO uint32_t W7; /!< (@ 0xA000101C) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1137	__IO uint32_t W8; /!< (@ 0xA0001020) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1138	__IO uint32_t W9; /!< (@ 0xA0001024) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1139	__IO uint32_t W10; /!< (@ 0xA0001028) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1140	__IO uint32_t W11; /!< (@ 0xA000102C) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1141	__IO uint32_t W12; /!< (@ 0xA0001030) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1142	__IO uint32_t W13; /!< (@ 0xA0001034) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1143	__IO uint32_t W14; /!< (@ 0xA0001038) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1144	__IO uint32_t W15; /!< (@ 0xA000103C) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1145	__IO uint32_t W16; /!< (@ 0xA0001040) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1146	__IO uint32_t W17; /!< (@ 0xA0001044) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1147	__IO uint32_t W18; /!< (@ 0xA0001048) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1148	__IO uint32_t W19; /!< (@ 0xA000104C) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1149	__IO uint32_t W20; /!< (@ 0xA0001050) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1150	__IO uint32_t W21; /!< (@ 0xA0001054) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1151	__IO uint32_t W22; /!< (@ 0xA0001058) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1152	__IO uint32_t W23; /!< (@ 0xA000105C) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1153	__IO uint32_t W24; /!< (@ 0xA0001060) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1154	__IO uint32_t W25; /!< (@ 0xA0001064) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1155	__IO uint32_t W26; /!< (@ 0xA0001068) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1156	__IO uint32_t W27; /!< (@ 0xA000106C) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1157	__IO uint32_t W28; /!< (@ 0xA0001070) Word pin registers port 0 /
bogdanm	0:9b334a45a8ff	1158	__I uint32_t RESERVED1[995];
bogdanm	0:9b334a45a8ff	1159	__IO uint32_t DIR0; /!< (@ 0xA0002000) Direction registers port 0 /
bogdanm	0:9b334a45a8ff	1160	__I uint32_t RESERVED2[31];
bogdanm	0:9b334a45a8ff	1161	__IO uint32_t MASK0; /!< (@ 0xA0002080) Mask register port 0 /
bogdanm	0:9b334a45a8ff	1162	__I uint32_t RESERVED3[31];
bogdanm	0:9b334a45a8ff	1163	__IO uint32_t PIN0; /!< (@ 0xA0002100) Port pin register port 0 /
bogdanm	0:9b334a45a8ff	1164	__I uint32_t RESERVED4[31];
bogdanm	0:9b334a45a8ff	1165	__IO uint32_t MPIN0; /!< (@ 0xA0002180) Masked port register port 0 /
bogdanm	0:9b334a45a8ff	1166	__I uint32_t RESERVED5[31];
bogdanm	0:9b334a45a8ff	1167	__IO uint32_t SET0; /*!< (@ 0xA0002200) Write: Set register for port 0 Read: output bits
bogdanm	0:9b334a45a8ff	1168	for port 0 */
bogdanm	0:9b334a45a8ff	1169	__I uint32_t RESERVED6[31];
bogdanm	0:9b334a45a8ff	1170	__O uint32_t CLR0; /!< (@ 0xA0002280) Clear port 0 /
bogdanm	0:9b334a45a8ff	1171	__I uint32_t RESERVED7[31];
bogdanm	0:9b334a45a8ff	1172	__O uint32_t NOT0; /!< (@ 0xA0002300) Toggle port 0 /
bogdanm	0:9b334a45a8ff	1173	__I uint32_t RESERVED8[31];
bogdanm	0:9b334a45a8ff	1174	__O uint32_t DIRSET0; /!< (@ 0xA0002380) Set pin direction bits for port 0. /
bogdanm	0:9b334a45a8ff	1175	__I uint32_t RESERVED9[31];
bogdanm	0:9b334a45a8ff	1176	__O uint32_t DIRCLR0; /!< (@ 0xA0002400) Clear pin direction bits for port 0. /
bogdanm	0:9b334a45a8ff	1177	__I uint32_t RESERVED10[31];
bogdanm	0:9b334a45a8ff	1178	__O uint32_t DIRNOT0; /!< (@ 0xA0002480) Toggle pin direction bits for port 0. /
bogdanm	0:9b334a45a8ff	1179	} LPC_GPIO_PORT_Type;
bogdanm	0:9b334a45a8ff	1180
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1183	/* ================ PIN_INT ================ */
bogdanm	0:9b334a45a8ff	1184	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1185
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	/**
bogdanm	0:9b334a45a8ff	1188	* @brief Pin interrupt and pattern match engine (PIN_INT)
bogdanm	0:9b334a45a8ff	1189	*/
bogdanm	0:9b334a45a8ff	1190
bogdanm	0:9b334a45a8ff	1191	typedef struct { /!< (@ 0xA0004000) PIN_INT Structure /
bogdanm	0:9b334a45a8ff	1192	__IO uint32_t ISEL; /!< (@ 0xA0004000) Pin Interrupt Mode register /
bogdanm	0:9b334a45a8ff	1193	__IO uint32_t IENR; /*!< (@ 0xA0004004) Pin interrupt level or rising edge interrupt
bogdanm	0:9b334a45a8ff	1194	enable register */
bogdanm	0:9b334a45a8ff	1195	__O uint32_t SIENR; /*!< (@ 0xA0004008) Pin interrupt level (rising edge) interrupt set
bogdanm	0:9b334a45a8ff	1196	register */
bogdanm	0:9b334a45a8ff	1197	__O uint32_t CIENR; /*!< (@ 0xA000400C) Pin interrupt level or rising edge interrupt
bogdanm	0:9b334a45a8ff	1198	clear register */
bogdanm	0:9b334a45a8ff	1199	__IO uint32_t IENF; /*!< (@ 0xA0004010) Pin interrupt active level or falling edge interrupt
bogdanm	0:9b334a45a8ff	1200	enable register */
bogdanm	0:9b334a45a8ff	1201	__O uint32_t SIENF; /*!< (@ 0xA0004014) Pin interrupt active level or falling edge interrupt
bogdanm	0:9b334a45a8ff	1202	set register */
bogdanm	0:9b334a45a8ff	1203	__O uint32_t CIENF; /*!< (@ 0xA0004018) Pin interrupt active level (falling edge) interrupt
bogdanm	0:9b334a45a8ff	1204	clear register */
bogdanm	0:9b334a45a8ff	1205	__IO uint32_t RISE; /!< (@ 0xA000401C) Pin interrupt rising edge register /
bogdanm	0:9b334a45a8ff	1206	__IO uint32_t FALL; /!< (@ 0xA0004020) Pin interrupt falling edge register /
bogdanm	0:9b334a45a8ff	1207	__IO uint32_t IST; /!< (@ 0xA0004024) Pin interrupt status register /
bogdanm	0:9b334a45a8ff	1208	__IO uint32_t PMCTRL; /!< (@ 0xA0004028) GPIO pattern match interrupt control register /
bogdanm	0:9b334a45a8ff	1209	__IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source
bogdanm	0:9b334a45a8ff	1210	register */
bogdanm	0:9b334a45a8ff	1211	__IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration
bogdanm	0:9b334a45a8ff	1212	register */
bogdanm	0:9b334a45a8ff	1213	} LPC_PIN_INT_Type;
bogdanm	0:9b334a45a8ff	1214
bogdanm	0:9b334a45a8ff	1215
bogdanm	0:9b334a45a8ff	1216	/* -------------------- End of section using anonymous unions ------------------- */
bogdanm	0:9b334a45a8ff	1217	#if defined(__CC_ARM)
bogdanm	0:9b334a45a8ff	1218	#pragma pop
bogdanm	0:9b334a45a8ff	1219	#elif defined(__ICCARM__)
bogdanm	0:9b334a45a8ff	1220	/* leave anonymous unions enabled */
bogdanm	0:9b334a45a8ff	1221	#elif defined(__GNUC__)
bogdanm	0:9b334a45a8ff	1222	/* anonymous unions are enabled by default */
bogdanm	0:9b334a45a8ff	1223	#elif defined(__TMS470__)
bogdanm	0:9b334a45a8ff	1224	/* anonymous unions are enabled by default */
bogdanm	0:9b334a45a8ff	1225	#elif defined(__TASKING__)
bogdanm	0:9b334a45a8ff	1226	#pragma warning restore
bogdanm	0:9b334a45a8ff	1227	#else
bogdanm	0:9b334a45a8ff	1228	#warning Not supported compiler type
bogdanm	0:9b334a45a8ff	1229	#endif
bogdanm	0:9b334a45a8ff	1230
bogdanm	0:9b334a45a8ff	1231
bogdanm	0:9b334a45a8ff	1232
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1235	/* ================ Peripheral memory map ================ */
bogdanm	0:9b334a45a8ff	1236	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1237
bogdanm	0:9b334a45a8ff	1238	#define LPC_WWDT_BASE 0x40000000UL
bogdanm	0:9b334a45a8ff	1239	#define LPC_MRT_BASE 0x40004000UL
bogdanm	0:9b334a45a8ff	1240	#define LPC_WKT_BASE 0x40008000UL
bogdanm	0:9b334a45a8ff	1241	#define LPC_SWM_BASE 0x4000C000UL
bogdanm	0:9b334a45a8ff	1242	#define LPC_ADC_BASE 0x4001C000UL
bogdanm	0:9b334a45a8ff	1243	#define LPC_PMU_BASE 0x40020000UL
bogdanm	0:9b334a45a8ff	1244	#define LPC_CMP_BASE 0x40024000UL
bogdanm	0:9b334a45a8ff	1245	#define LPC_DMATRIGMUX_BASE 0x40028000UL
bogdanm	0:9b334a45a8ff	1246	#define LPC_INPUTMUX_BASE 0x4002C000UL
bogdanm	0:9b334a45a8ff	1247	#define LPC_FLASHCTRL_BASE 0x40040000UL
bogdanm	0:9b334a45a8ff	1248	#define LPC_IOCON_BASE 0x40044000UL
bogdanm	0:9b334a45a8ff	1249	#define LPC_SYSCON_BASE 0x40048000UL
bogdanm	0:9b334a45a8ff	1250	#define LPC_I2C0_BASE 0x40050000UL
bogdanm	0:9b334a45a8ff	1251	#define LPC_I2C1_BASE 0x40054000UL
bogdanm	0:9b334a45a8ff	1252	#define LPC_SPI0_BASE 0x40058000UL
bogdanm	0:9b334a45a8ff	1253	#define LPC_SPI1_BASE 0x4005C000UL
bogdanm	0:9b334a45a8ff	1254	#define LPC_USART0_BASE 0x40064000UL
bogdanm	0:9b334a45a8ff	1255	#define LPC_USART1_BASE 0x40068000UL
bogdanm	0:9b334a45a8ff	1256	#define LPC_USART2_BASE 0x4006C000UL
bogdanm	0:9b334a45a8ff	1257	#define LPC_I2C2_BASE 0x40070000UL
bogdanm	0:9b334a45a8ff	1258	#define LPC_I2C3_BASE 0x40074000UL
bogdanm	0:9b334a45a8ff	1259	#define LPC_CRC_BASE 0x50000000UL
bogdanm	0:9b334a45a8ff	1260	#define LPC_SCT_BASE 0x50004000UL
bogdanm	0:9b334a45a8ff	1261	#define LPC_DMA_BASE 0x50008000UL
bogdanm	0:9b334a45a8ff	1262	#define LPC_GPIO_PORT_BASE 0xA0000000UL
bogdanm	0:9b334a45a8ff	1263	#define LPC_PIN_INT_BASE 0xA0004000UL
bogdanm	0:9b334a45a8ff	1264
bogdanm	0:9b334a45a8ff	1265
bogdanm	0:9b334a45a8ff	1266	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1267	/* ================ Peripheral declaration ================ */
bogdanm	0:9b334a45a8ff	1268	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1269
bogdanm	0:9b334a45a8ff	1270	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
bogdanm	0:9b334a45a8ff	1271	#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
bogdanm	0:9b334a45a8ff	1272	#define LPC_WKT ((LPC_WKT_Type *) LPC_WKT_BASE)
bogdanm	0:9b334a45a8ff	1273	#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
bogdanm	0:9b334a45a8ff	1274	#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
bogdanm	0:9b334a45a8ff	1275	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
bogdanm	0:9b334a45a8ff	1276	#define LPC_CMP ((LPC_CMP_Type *) LPC_CMP_BASE)
bogdanm	0:9b334a45a8ff	1277	#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
bogdanm	0:9b334a45a8ff	1278	#define LPC_INPUTMUX ((LPC_INPUTMUX_Type *) LPC_INPUTMUX_BASE)
bogdanm	0:9b334a45a8ff	1279	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
bogdanm	0:9b334a45a8ff	1280	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
bogdanm	0:9b334a45a8ff	1281	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
bogdanm	0:9b334a45a8ff	1282	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
bogdanm	0:9b334a45a8ff	1283	#define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
bogdanm	0:9b334a45a8ff	1284	#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
bogdanm	0:9b334a45a8ff	1285	#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
bogdanm	0:9b334a45a8ff	1286	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
bogdanm	0:9b334a45a8ff	1287	#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
bogdanm	0:9b334a45a8ff	1288	#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
bogdanm	0:9b334a45a8ff	1289	#define LPC_I2C2 ((LPC_I2C0_Type *) LPC_I2C2_BASE)
bogdanm	0:9b334a45a8ff	1290	#define LPC_I2C3 ((LPC_I2C0_Type *) LPC_I2C3_BASE)
bogdanm	0:9b334a45a8ff	1291	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
bogdanm	0:9b334a45a8ff	1292	#define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE)
bogdanm	0:9b334a45a8ff	1293	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
bogdanm	0:9b334a45a8ff	1294	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
bogdanm	0:9b334a45a8ff	1295	#define LPC_PIN_INT ((LPC_PIN_INT_Type *) LPC_PIN_INT_BASE)
bogdanm	0:9b334a45a8ff	1296
bogdanm	0:9b334a45a8ff	1297
bogdanm	0:9b334a45a8ff	1298	/** @} / / End of group Device_Peripheral_Registers */
bogdanm	0:9b334a45a8ff	1299	/** @} / / End of group LPC82x */
bogdanm	0:9b334a45a8ff	1300	/** @} / / End of group (null) */
bogdanm	0:9b334a45a8ff	1301
bogdanm	0:9b334a45a8ff	1302	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1303	}
bogdanm	0:9b334a45a8ff	1304	#endif
bogdanm	0:9b334a45a8ff	1305
bogdanm	0:9b334a45a8ff	1306
bogdanm	0:9b334a45a8ff	1307	#endif /* LPC82x_H */
bogdanm	0:9b334a45a8ff	1308

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Type:	Library
Created:	23 Feb 2016
Imports:	88
Forks:	0
Commits:	71
Dependents:	0
Dependencies:	0
Followers:	2

targets/cmsis/TARGET_NXP/TARGET_LPC82X/LPC82x.h@70:b3a5af880266, 2016-02-23 (annotated)

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