philippe s. / mbed-dev

mbed library sources. Supersedes mbed-src. Fixes analogIn and analogOut problems for TARGET_STM32F3. Tested on NUCLEO-F303K8, using 3 analogout and 7 analogin channels simultaneously. Added ability for STM32F334R8 and STM32F303K8 to use all three channels of DAC simultaneously. https://developer.mbed.org/users/StevieWray/code/mbed-dev/ Added ability for TARGET_STM32F3 to use more than one ADC simultaneously. https://developer.mbed.org/questions/67997/NUCLEO-F303K8ADC/

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC23XX/LPC23xx.h@70:b3a5af880266, 2016-02-23 (annotated)

Committer:
neurofun
Date:
Tue Feb 23 21:59:35 2016 +0000
Revision:
70:b3a5af880266
Parent:
0:9b334a45a8ff 
Edited DAC routines to allow for the simultaneous use of three channels from two DACs as seen on the STM32F334R8 and STM32F303K8. Edited ADC routines to allow for the simultaneous use of more than one ADC.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library - LPC23xx CMSIS-like structs
bogdanm 0:9b334a45a8ff 2 * Copyright (C) 2009 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
bogdanm 0:9b334a45a8ff 5 */
bogdanm 0:9b334a45a8ff 6
bogdanm 0:9b334a45a8ff 7 #ifndef __LPC23xx_H
bogdanm 0:9b334a45a8ff 8 #define __LPC23xx_H
bogdanm 0:9b334a45a8ff 9
bogdanm 0:9b334a45a8ff 10 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 11 extern "C" {
bogdanm 0:9b334a45a8ff 12 #endif
bogdanm 0:9b334a45a8ff 13
bogdanm 0:9b334a45a8ff 14 /*
bogdanm 0:9b334a45a8ff 15 * ==========================================================================
bogdanm 0:9b334a45a8ff 16 * ---------- Interrupt Number Definition -----------------------------------
bogdanm 0:9b334a45a8ff 17 * ==========================================================================
bogdanm 0:9b334a45a8ff 18 */
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 typedef enum IRQn
bogdanm 0:9b334a45a8ff 21 {
bogdanm 0:9b334a45a8ff 22 /****** LPC23xx Specific Interrupt Numbers *******************************************************/
bogdanm 0:9b334a45a8ff 23 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
bogdanm 0:9b334a45a8ff 26 TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
bogdanm 0:9b334a45a8ff 27 UART0_IRQn = 6, /*!< UART0 Interrupt */
bogdanm 0:9b334a45a8ff 28 UART1_IRQn = 7, /*!< UART1 Interrupt */
bogdanm 0:9b334a45a8ff 29 PWM1_IRQn = 8, /*!< PWM1 Interrupt */
bogdanm 0:9b334a45a8ff 30 I2C0_IRQn = 9, /*!< I2C0 Interrupt */
bogdanm 0:9b334a45a8ff 31 SPI_IRQn = 10, /*!< SPI Interrupt */
bogdanm 0:9b334a45a8ff 32 SSP0_IRQn = 10, /*!< SSP0 Interrupt */
bogdanm 0:9b334a45a8ff 33 SSP1_IRQn = 11, /*!< SSP1 Interrupt */
bogdanm 0:9b334a45a8ff 34 PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
bogdanm 0:9b334a45a8ff 35 RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
bogdanm 0:9b334a45a8ff 36 EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
bogdanm 0:9b334a45a8ff 37 EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
bogdanm 0:9b334a45a8ff 38 EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
bogdanm 0:9b334a45a8ff 39 EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
bogdanm 0:9b334a45a8ff 40 ADC_IRQn = 18, /*!< A/D Converter Interrupt */
bogdanm 0:9b334a45a8ff 41 I2C1_IRQn = 19, /*!< I2C1 Interrupt */
bogdanm 0:9b334a45a8ff 42 BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
bogdanm 0:9b334a45a8ff 43 ENET_IRQn = 21, /*!< Ethernet Interrupt */
bogdanm 0:9b334a45a8ff 44 USB_IRQn = 22, /*!< USB Interrupt */
bogdanm 0:9b334a45a8ff 45 CAN_IRQn = 23, /*!< CAN Interrupt */
bogdanm 0:9b334a45a8ff 46 MIC_IRQn = 24, /*!< Multimedia Interface Controler */
bogdanm 0:9b334a45a8ff 47 DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
bogdanm 0:9b334a45a8ff 48 TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
bogdanm 0:9b334a45a8ff 49 TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
bogdanm 0:9b334a45a8ff 50 UART2_IRQn = 28, /*!< UART2 Interrupt */
bogdanm 0:9b334a45a8ff 51 UART3_IRQn = 29, /*!< UART3 Interrupt */
bogdanm 0:9b334a45a8ff 52 I2C2_IRQn = 30, /*!< I2C2 Interrupt */
bogdanm 0:9b334a45a8ff 53 I2S_IRQn = 31, /*!< I2S Interrupt */
bogdanm 0:9b334a45a8ff 54 } IRQn_Type;
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 /*
bogdanm 0:9b334a45a8ff 57 * ==========================================================================
bogdanm 0:9b334a45a8ff 58 * ----------- Processor and Core Peripheral Section ------------------------
bogdanm 0:9b334a45a8ff 59 * ==========================================================================
bogdanm 0:9b334a45a8ff 60 */
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 /* Configuration of the ARM7 Processor and Core Peripherals */
bogdanm 0:9b334a45a8ff 63 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 0:9b334a45a8ff 64 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
bogdanm 0:9b334a45a8ff 65 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 #include <core_arm7.h>
bogdanm 0:9b334a45a8ff 69 #include "system_LPC23xx.h" /* System Header */
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 /******************************************************************************/
bogdanm 0:9b334a45a8ff 73 /* Device Specific Peripheral registers structures */
bogdanm 0:9b334a45a8ff 74 /******************************************************************************/
bogdanm 0:9b334a45a8ff 75 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 76 #pragma anon_unions
bogdanm 0:9b334a45a8ff 77 #endif
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 /*------------- Vector Interupt Controler (VIC) ------------------------------*/
bogdanm 0:9b334a45a8ff 80 typedef struct
bogdanm 0:9b334a45a8ff 81 {
bogdanm 0:9b334a45a8ff 82 __I uint32_t IRQStatus;
bogdanm 0:9b334a45a8ff 83 __I uint32_t FIQStatus;
bogdanm 0:9b334a45a8ff 84 __I uint32_t RawIntr;
bogdanm 0:9b334a45a8ff 85 __IO uint32_t IntSelect;
bogdanm 0:9b334a45a8ff 86 __IO uint32_t IntEnable;
bogdanm 0:9b334a45a8ff 87 __O uint32_t IntEnClr;
bogdanm 0:9b334a45a8ff 88 __IO uint32_t SoftInt;
bogdanm 0:9b334a45a8ff 89 __O uint32_t SoftIntClr;
bogdanm 0:9b334a45a8ff 90 __IO uint32_t Protection;
bogdanm 0:9b334a45a8ff 91 __IO uint32_t SWPriorityMask;
bogdanm 0:9b334a45a8ff 92 __IO uint32_t RESERVED0[54];
bogdanm 0:9b334a45a8ff 93 __IO uint32_t VectAddr[32];
bogdanm 0:9b334a45a8ff 94 __IO uint32_t RESERVED1[32];
bogdanm 0:9b334a45a8ff 95 __IO uint32_t VectPriority[32];
bogdanm 0:9b334a45a8ff 96 __IO uint32_t RESERVED2[800];
bogdanm 0:9b334a45a8ff 97 __IO uint32_t Address;
bogdanm 0:9b334a45a8ff 98 } LPC_VIC_TypeDef;
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 /*------------- System Control (SC) ------------------------------------------*/
bogdanm 0:9b334a45a8ff 101 typedef struct
bogdanm 0:9b334a45a8ff 102 {
bogdanm 0:9b334a45a8ff 103 __IO uint32_t MAMCR;
bogdanm 0:9b334a45a8ff 104 __IO uint32_t MAMTIM;
bogdanm 0:9b334a45a8ff 105 uint32_t RESERVED0[14];
bogdanm 0:9b334a45a8ff 106 __IO uint32_t MEMMAP;
bogdanm 0:9b334a45a8ff 107 uint32_t RESERVED1[15];
bogdanm 0:9b334a45a8ff 108 __IO uint32_t PLL0CON; /* Clocking and Power Control */
bogdanm 0:9b334a45a8ff 109 __IO uint32_t PLL0CFG;
bogdanm 0:9b334a45a8ff 110 __I uint32_t PLL0STAT;
bogdanm 0:9b334a45a8ff 111 __O uint32_t PLL0FEED;
bogdanm 0:9b334a45a8ff 112 uint32_t RESERVED2[12];
bogdanm 0:9b334a45a8ff 113 __IO uint32_t PCON;
bogdanm 0:9b334a45a8ff 114 __IO uint32_t PCONP;
bogdanm 0:9b334a45a8ff 115 uint32_t RESERVED3[15];
bogdanm 0:9b334a45a8ff 116 __IO uint32_t CCLKCFG;
bogdanm 0:9b334a45a8ff 117 __IO uint32_t USBCLKCFG;
bogdanm 0:9b334a45a8ff 118 __IO uint32_t CLKSRCSEL;
bogdanm 0:9b334a45a8ff 119 uint32_t RESERVED4[12];
bogdanm 0:9b334a45a8ff 120 __IO uint32_t EXTINT; /* External Interrupts */
bogdanm 0:9b334a45a8ff 121 __IO uint32_t INTWAKE;
bogdanm 0:9b334a45a8ff 122 __IO uint32_t EXTMODE;
bogdanm 0:9b334a45a8ff 123 __IO uint32_t EXTPOLAR;
bogdanm 0:9b334a45a8ff 124 uint32_t RESERVED6[12];
bogdanm 0:9b334a45a8ff 125 __IO uint32_t RSID; /* Reset */
bogdanm 0:9b334a45a8ff 126 __IO uint32_t CSPR;
bogdanm 0:9b334a45a8ff 127 __IO uint32_t AHBCFG1;
bogdanm 0:9b334a45a8ff 128 __IO uint32_t AHBCFG2;
bogdanm 0:9b334a45a8ff 129 uint32_t RESERVED7[4];
bogdanm 0:9b334a45a8ff 130 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
bogdanm 0:9b334a45a8ff 131 __IO uint32_t IRCTRIM; /* Clock Dividers */
bogdanm 0:9b334a45a8ff 132 __IO uint32_t PCLKSEL0;
bogdanm 0:9b334a45a8ff 133 __IO uint32_t PCLKSEL1;
bogdanm 0:9b334a45a8ff 134 uint32_t RESERVED8[4];
bogdanm 0:9b334a45a8ff 135 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
bogdanm 0:9b334a45a8ff 136 uint32_t RESERVED9;
bogdanm 0:9b334a45a8ff 137 // __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
bogdanm 0:9b334a45a8ff 138 } LPC_SC_TypeDef;
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
bogdanm 0:9b334a45a8ff 141 typedef struct
bogdanm 0:9b334a45a8ff 142 {
bogdanm 0:9b334a45a8ff 143 __IO uint32_t PINSEL0;
bogdanm 0:9b334a45a8ff 144 __IO uint32_t PINSEL1;
bogdanm 0:9b334a45a8ff 145 __IO uint32_t PINSEL2;
bogdanm 0:9b334a45a8ff 146 __IO uint32_t PINSEL3;
bogdanm 0:9b334a45a8ff 147 __IO uint32_t PINSEL4;
bogdanm 0:9b334a45a8ff 148 __IO uint32_t PINSEL5;
bogdanm 0:9b334a45a8ff 149 __IO uint32_t PINSEL6;
bogdanm 0:9b334a45a8ff 150 __IO uint32_t PINSEL7;
bogdanm 0:9b334a45a8ff 151 __IO uint32_t PINSEL8;
bogdanm 0:9b334a45a8ff 152 __IO uint32_t PINSEL9;
bogdanm 0:9b334a45a8ff 153 __IO uint32_t PINSEL10;
bogdanm 0:9b334a45a8ff 154 uint32_t RESERVED0[5];
bogdanm 0:9b334a45a8ff 155 __IO uint32_t PINMODE0;
bogdanm 0:9b334a45a8ff 156 __IO uint32_t PINMODE1;
bogdanm 0:9b334a45a8ff 157 __IO uint32_t PINMODE2;
bogdanm 0:9b334a45a8ff 158 __IO uint32_t PINMODE3;
bogdanm 0:9b334a45a8ff 159 __IO uint32_t PINMODE4;
bogdanm 0:9b334a45a8ff 160 __IO uint32_t PINMODE5;
bogdanm 0:9b334a45a8ff 161 __IO uint32_t PINMODE6;
bogdanm 0:9b334a45a8ff 162 __IO uint32_t PINMODE7;
bogdanm 0:9b334a45a8ff 163 __IO uint32_t PINMODE8;
bogdanm 0:9b334a45a8ff 164 __IO uint32_t PINMODE9;
bogdanm 0:9b334a45a8ff 165 __IO uint32_t PINMODE_OD0;
bogdanm 0:9b334a45a8ff 166 __IO uint32_t PINMODE_OD1;
bogdanm 0:9b334a45a8ff 167 __IO uint32_t PINMODE_OD2;
bogdanm 0:9b334a45a8ff 168 __IO uint32_t PINMODE_OD3;
bogdanm 0:9b334a45a8ff 169 __IO uint32_t PINMODE_OD4;
bogdanm 0:9b334a45a8ff 170 } LPC_PINCON_TypeDef;
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
bogdanm 0:9b334a45a8ff 173 typedef struct
bogdanm 0:9b334a45a8ff 174 {
bogdanm 0:9b334a45a8ff 175 __IO uint32_t FIODIR;
bogdanm 0:9b334a45a8ff 176 uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 177 __IO uint32_t FIOMASK;
bogdanm 0:9b334a45a8ff 178 __IO uint32_t FIOPIN;
bogdanm 0:9b334a45a8ff 179 __IO uint32_t FIOSET;
bogdanm 0:9b334a45a8ff 180 __O uint32_t FIOCLR;
bogdanm 0:9b334a45a8ff 181 } LPC_GPIO_TypeDef;
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 typedef struct
bogdanm 0:9b334a45a8ff 184 {
bogdanm 0:9b334a45a8ff 185 __I uint32_t IntStatus;
bogdanm 0:9b334a45a8ff 186 __I uint32_t IO0IntStatR;
bogdanm 0:9b334a45a8ff 187 __I uint32_t IO0IntStatF;
bogdanm 0:9b334a45a8ff 188 __O uint32_t IO0IntClr;
bogdanm 0:9b334a45a8ff 189 __IO uint32_t IO0IntEnR;
bogdanm 0:9b334a45a8ff 190 __IO uint32_t IO0IntEnF;
bogdanm 0:9b334a45a8ff 191 uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 192 __I uint32_t IO2IntStatR;
bogdanm 0:9b334a45a8ff 193 __I uint32_t IO2IntStatF;
bogdanm 0:9b334a45a8ff 194 __O uint32_t IO2IntClr;
bogdanm 0:9b334a45a8ff 195 __IO uint32_t IO2IntEnR;
bogdanm 0:9b334a45a8ff 196 __IO uint32_t IO2IntEnF;
bogdanm 0:9b334a45a8ff 197 } LPC_GPIOINT_TypeDef;
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 /*------------- Timer (TIM) --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 200 typedef struct
bogdanm 0:9b334a45a8ff 201 {
bogdanm 0:9b334a45a8ff 202 __IO uint32_t IR;
bogdanm 0:9b334a45a8ff 203 __IO uint32_t TCR;
bogdanm 0:9b334a45a8ff 204 __IO uint32_t TC;
bogdanm 0:9b334a45a8ff 205 __IO uint32_t PR;
bogdanm 0:9b334a45a8ff 206 __IO uint32_t PC;
bogdanm 0:9b334a45a8ff 207 __IO uint32_t MCR;
bogdanm 0:9b334a45a8ff 208 __IO uint32_t MR0;
bogdanm 0:9b334a45a8ff 209 __IO uint32_t MR1;
bogdanm 0:9b334a45a8ff 210 __IO uint32_t MR2;
bogdanm 0:9b334a45a8ff 211 __IO uint32_t MR3;
bogdanm 0:9b334a45a8ff 212 __IO uint32_t CCR;
bogdanm 0:9b334a45a8ff 213 __I uint32_t CR0;
bogdanm 0:9b334a45a8ff 214 __I uint32_t CR1;
bogdanm 0:9b334a45a8ff 215 uint32_t RESERVED0[2];
bogdanm 0:9b334a45a8ff 216 __IO uint32_t EMR;
bogdanm 0:9b334a45a8ff 217 uint32_t RESERVED1[12];
bogdanm 0:9b334a45a8ff 218 __IO uint32_t CTCR;
bogdanm 0:9b334a45a8ff 219 } LPC_TIM_TypeDef;
bogdanm 0:9b334a45a8ff 220
bogdanm 0:9b334a45a8ff 221 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
bogdanm 0:9b334a45a8ff 222 typedef struct
bogdanm 0:9b334a45a8ff 223 {
bogdanm 0:9b334a45a8ff 224 __IO uint32_t IR;
bogdanm 0:9b334a45a8ff 225 __IO uint32_t TCR;
bogdanm 0:9b334a45a8ff 226 __IO uint32_t TC;
bogdanm 0:9b334a45a8ff 227 __IO uint32_t PR;
bogdanm 0:9b334a45a8ff 228 __IO uint32_t PC;
bogdanm 0:9b334a45a8ff 229 __IO uint32_t MCR;
bogdanm 0:9b334a45a8ff 230 __IO uint32_t MR0;
bogdanm 0:9b334a45a8ff 231 __IO uint32_t MR1;
bogdanm 0:9b334a45a8ff 232 __IO uint32_t MR2;
bogdanm 0:9b334a45a8ff 233 __IO uint32_t MR3;
bogdanm 0:9b334a45a8ff 234 __IO uint32_t CCR;
bogdanm 0:9b334a45a8ff 235 __I uint32_t CR0;
bogdanm 0:9b334a45a8ff 236 __I uint32_t CR1;
bogdanm 0:9b334a45a8ff 237 __I uint32_t CR2;
bogdanm 0:9b334a45a8ff 238 __I uint32_t CR3;
bogdanm 0:9b334a45a8ff 239 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 240 __IO uint32_t MR4;
bogdanm 0:9b334a45a8ff 241 __IO uint32_t MR5;
bogdanm 0:9b334a45a8ff 242 __IO uint32_t MR6;
bogdanm 0:9b334a45a8ff 243 __IO uint32_t PCR;
bogdanm 0:9b334a45a8ff 244 __IO uint32_t LER;
bogdanm 0:9b334a45a8ff 245 uint32_t RESERVED1[7];
bogdanm 0:9b334a45a8ff 246 __IO uint32_t CTCR;
bogdanm 0:9b334a45a8ff 247 } LPC_PWM_TypeDef;
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
bogdanm 0:9b334a45a8ff 250 typedef struct
bogdanm 0:9b334a45a8ff 251 {
bogdanm 0:9b334a45a8ff 252 union {
bogdanm 0:9b334a45a8ff 253 __I uint8_t RBR;
bogdanm 0:9b334a45a8ff 254 __O uint8_t THR;
bogdanm 0:9b334a45a8ff 255 __IO uint8_t DLL;
bogdanm 0:9b334a45a8ff 256 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 257 };
bogdanm 0:9b334a45a8ff 258 union {
bogdanm 0:9b334a45a8ff 259 __IO uint8_t DLM;
bogdanm 0:9b334a45a8ff 260 __IO uint32_t IER;
bogdanm 0:9b334a45a8ff 261 };
bogdanm 0:9b334a45a8ff 262 union {
bogdanm 0:9b334a45a8ff 263 __I uint32_t IIR;
bogdanm 0:9b334a45a8ff 264 __O uint8_t FCR;
bogdanm 0:9b334a45a8ff 265 };
bogdanm 0:9b334a45a8ff 266 __IO uint8_t LCR;
bogdanm 0:9b334a45a8ff 267 uint8_t RESERVED1[7];
bogdanm 0:9b334a45a8ff 268 __IO uint8_t LSR;
bogdanm 0:9b334a45a8ff 269 uint8_t RESERVED2[7];
bogdanm 0:9b334a45a8ff 270 __IO uint8_t SCR;
bogdanm 0:9b334a45a8ff 271 uint8_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 272 __IO uint32_t ACR;
bogdanm 0:9b334a45a8ff 273 __IO uint8_t ICR;
bogdanm 0:9b334a45a8ff 274 uint8_t RESERVED4[3];
bogdanm 0:9b334a45a8ff 275 __IO uint8_t FDR;
bogdanm 0:9b334a45a8ff 276 uint8_t RESERVED5[7];
bogdanm 0:9b334a45a8ff 277 __IO uint8_t TER;
bogdanm 0:9b334a45a8ff 278 uint8_t RESERVED6[27];
bogdanm 0:9b334a45a8ff 279 __IO uint8_t RS485CTRL;
bogdanm 0:9b334a45a8ff 280 uint8_t RESERVED7[3];
bogdanm 0:9b334a45a8ff 281 __IO uint8_t ADRMATCH;
bogdanm 0:9b334a45a8ff 282 } LPC_UART_TypeDef;
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 typedef struct
bogdanm 0:9b334a45a8ff 285 {
bogdanm 0:9b334a45a8ff 286 union {
bogdanm 0:9b334a45a8ff 287 __I uint8_t RBR;
bogdanm 0:9b334a45a8ff 288 __O uint8_t THR;
bogdanm 0:9b334a45a8ff 289 __IO uint8_t DLL;
bogdanm 0:9b334a45a8ff 290 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 291 };
bogdanm 0:9b334a45a8ff 292 union {
bogdanm 0:9b334a45a8ff 293 __IO uint8_t DLM;
bogdanm 0:9b334a45a8ff 294 __IO uint32_t IER;
bogdanm 0:9b334a45a8ff 295 };
bogdanm 0:9b334a45a8ff 296 union {
bogdanm 0:9b334a45a8ff 297 __I uint32_t IIR;
bogdanm 0:9b334a45a8ff 298 __O uint8_t FCR;
bogdanm 0:9b334a45a8ff 299 };
bogdanm 0:9b334a45a8ff 300 __IO uint8_t LCR;
bogdanm 0:9b334a45a8ff 301 uint8_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 302 __IO uint8_t MCR;
bogdanm 0:9b334a45a8ff 303 uint8_t RESERVED2[3];
bogdanm 0:9b334a45a8ff 304 __IO uint8_t LSR;
bogdanm 0:9b334a45a8ff 305 uint8_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 306 __IO uint8_t MSR;
bogdanm 0:9b334a45a8ff 307 uint8_t RESERVED4[3];
bogdanm 0:9b334a45a8ff 308 __IO uint8_t SCR;
bogdanm 0:9b334a45a8ff 309 uint8_t RESERVED5[3];
bogdanm 0:9b334a45a8ff 310 __IO uint32_t ACR;
bogdanm 0:9b334a45a8ff 311 uint32_t RESERVED6;
bogdanm 0:9b334a45a8ff 312 __IO uint32_t FDR;
bogdanm 0:9b334a45a8ff 313 uint32_t RESERVED7;
bogdanm 0:9b334a45a8ff 314 __IO uint8_t TER;
bogdanm 0:9b334a45a8ff 315 uint8_t RESERVED8[27];
bogdanm 0:9b334a45a8ff 316 __IO uint8_t RS485CTRL;
bogdanm 0:9b334a45a8ff 317 uint8_t RESERVED9[3];
bogdanm 0:9b334a45a8ff 318 __IO uint8_t ADRMATCH;
bogdanm 0:9b334a45a8ff 319 uint8_t RESERVED10[3];
bogdanm 0:9b334a45a8ff 320 __IO uint8_t RS485DLY;
bogdanm 0:9b334a45a8ff 321 } LPC_UART1_TypeDef;
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
bogdanm 0:9b334a45a8ff 324 typedef struct
bogdanm 0:9b334a45a8ff 325 {
bogdanm 0:9b334a45a8ff 326 __IO uint32_t SPCR;
bogdanm 0:9b334a45a8ff 327 __I uint32_t SPSR;
bogdanm 0:9b334a45a8ff 328 __IO uint32_t SPDR;
bogdanm 0:9b334a45a8ff 329 __IO uint32_t SPCCR;
bogdanm 0:9b334a45a8ff 330 uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 331 __IO uint32_t SPINT;
bogdanm 0:9b334a45a8ff 332 } LPC_SPI_TypeDef;
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
bogdanm 0:9b334a45a8ff 335 typedef struct
bogdanm 0:9b334a45a8ff 336 {
bogdanm 0:9b334a45a8ff 337 __IO uint32_t CR0;
bogdanm 0:9b334a45a8ff 338 __IO uint32_t CR1;
bogdanm 0:9b334a45a8ff 339 __IO uint32_t DR;
bogdanm 0:9b334a45a8ff 340 __I uint32_t SR;
bogdanm 0:9b334a45a8ff 341 __IO uint32_t CPSR;
bogdanm 0:9b334a45a8ff 342 __IO uint32_t IMSC;
bogdanm 0:9b334a45a8ff 343 __IO uint32_t RIS;
bogdanm 0:9b334a45a8ff 344 __IO uint32_t MIS;
bogdanm 0:9b334a45a8ff 345 __IO uint32_t ICR;
bogdanm 0:9b334a45a8ff 346 __IO uint32_t DMACR;
bogdanm 0:9b334a45a8ff 347 } LPC_SSP_TypeDef;
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
bogdanm 0:9b334a45a8ff 350 typedef struct
bogdanm 0:9b334a45a8ff 351 {
bogdanm 0:9b334a45a8ff 352 __IO uint32_t I2CONSET;
bogdanm 0:9b334a45a8ff 353 __I uint32_t I2STAT;
bogdanm 0:9b334a45a8ff 354 __IO uint32_t I2DAT;
bogdanm 0:9b334a45a8ff 355 __IO uint32_t I2ADR0;
bogdanm 0:9b334a45a8ff 356 __IO uint32_t I2SCLH;
bogdanm 0:9b334a45a8ff 357 __IO uint32_t I2SCLL;
bogdanm 0:9b334a45a8ff 358 __O uint32_t I2CONCLR;
bogdanm 0:9b334a45a8ff 359 __IO uint32_t MMCTRL;
bogdanm 0:9b334a45a8ff 360 __IO uint32_t I2ADR1;
bogdanm 0:9b334a45a8ff 361 __IO uint32_t I2ADR2;
bogdanm 0:9b334a45a8ff 362 __IO uint32_t I2ADR3;
bogdanm 0:9b334a45a8ff 363 __I uint32_t I2DATA_BUFFER;
bogdanm 0:9b334a45a8ff 364 __IO uint32_t I2MASK0;
bogdanm 0:9b334a45a8ff 365 __IO uint32_t I2MASK1;
bogdanm 0:9b334a45a8ff 366 __IO uint32_t I2MASK2;
bogdanm 0:9b334a45a8ff 367 __IO uint32_t I2MASK3;
bogdanm 0:9b334a45a8ff 368 } LPC_I2C_TypeDef;
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
bogdanm 0:9b334a45a8ff 371 typedef struct
bogdanm 0:9b334a45a8ff 372 {
bogdanm 0:9b334a45a8ff 373 __IO uint32_t I2SDAO;
bogdanm 0:9b334a45a8ff 374 __I uint32_t I2SDAI;
bogdanm 0:9b334a45a8ff 375 __O uint32_t I2STXFIFO;
bogdanm 0:9b334a45a8ff 376 __I uint32_t I2SRXFIFO;
bogdanm 0:9b334a45a8ff 377 __I uint32_t I2SSTATE;
bogdanm 0:9b334a45a8ff 378 __IO uint32_t I2SDMA1;
bogdanm 0:9b334a45a8ff 379 __IO uint32_t I2SDMA2;
bogdanm 0:9b334a45a8ff 380 __IO uint32_t I2SIRQ;
bogdanm 0:9b334a45a8ff 381 __IO uint32_t I2STXRATE;
bogdanm 0:9b334a45a8ff 382 __IO uint32_t I2SRXRATE;
bogdanm 0:9b334a45a8ff 383 __IO uint32_t I2STXBITRATE;
bogdanm 0:9b334a45a8ff 384 __IO uint32_t I2SRXBITRATE;
bogdanm 0:9b334a45a8ff 385 __IO uint32_t I2STXMODE;
bogdanm 0:9b334a45a8ff 386 __IO uint32_t I2SRXMODE;
bogdanm 0:9b334a45a8ff 387 } LPC_I2S_TypeDef;
bogdanm 0:9b334a45a8ff 388
bogdanm 0:9b334a45a8ff 389 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
bogdanm 0:9b334a45a8ff 390 typedef struct
bogdanm 0:9b334a45a8ff 391 {
bogdanm 0:9b334a45a8ff 392 __IO uint8_t ILR;
bogdanm 0:9b334a45a8ff 393 uint8_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 394 __IO uint8_t CTC;
bogdanm 0:9b334a45a8ff 395 uint8_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 396 __IO uint8_t CCR;
bogdanm 0:9b334a45a8ff 397 uint8_t RESERVED2[3];
bogdanm 0:9b334a45a8ff 398 __IO uint8_t CIIR;
bogdanm 0:9b334a45a8ff 399 uint8_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 400 __IO uint8_t AMR;
bogdanm 0:9b334a45a8ff 401 uint8_t RESERVED4[3];
bogdanm 0:9b334a45a8ff 402 __I uint32_t CTIME0;
bogdanm 0:9b334a45a8ff 403 __I uint32_t CTIME1;
bogdanm 0:9b334a45a8ff 404 __I uint32_t CTIME2;
bogdanm 0:9b334a45a8ff 405 __IO uint8_t SEC;
bogdanm 0:9b334a45a8ff 406 uint8_t RESERVED5[3];
bogdanm 0:9b334a45a8ff 407 __IO uint8_t MIN;
bogdanm 0:9b334a45a8ff 408 uint8_t RESERVED6[3];
bogdanm 0:9b334a45a8ff 409 __IO uint8_t HOUR;
bogdanm 0:9b334a45a8ff 410 uint8_t RESERVED7[3];
bogdanm 0:9b334a45a8ff 411 __IO uint8_t DOM;
bogdanm 0:9b334a45a8ff 412 uint8_t RESERVED8[3];
bogdanm 0:9b334a45a8ff 413 __IO uint8_t DOW;
bogdanm 0:9b334a45a8ff 414 uint8_t RESERVED9[3];
bogdanm 0:9b334a45a8ff 415 __IO uint16_t DOY;
bogdanm 0:9b334a45a8ff 416 uint16_t RESERVED10;
bogdanm 0:9b334a45a8ff 417 __IO uint8_t MONTH;
bogdanm 0:9b334a45a8ff 418 uint8_t RESERVED11[3];
bogdanm 0:9b334a45a8ff 419 __IO uint16_t YEAR;
bogdanm 0:9b334a45a8ff 420 uint16_t RESERVED12;
bogdanm 0:9b334a45a8ff 421 __IO uint32_t CALIBRATION;
bogdanm 0:9b334a45a8ff 422 __IO uint32_t GPREG0;
bogdanm 0:9b334a45a8ff 423 __IO uint32_t GPREG1;
bogdanm 0:9b334a45a8ff 424 __IO uint32_t GPREG2;
bogdanm 0:9b334a45a8ff 425 __IO uint32_t GPREG3;
bogdanm 0:9b334a45a8ff 426 __IO uint32_t GPREG4;
bogdanm 0:9b334a45a8ff 427 __IO uint8_t WAKEUPDIS;
bogdanm 0:9b334a45a8ff 428 uint8_t RESERVED13[3];
bogdanm 0:9b334a45a8ff 429 __IO uint8_t PWRCTRL;
bogdanm 0:9b334a45a8ff 430 uint8_t RESERVED14[3];
bogdanm 0:9b334a45a8ff 431 __IO uint8_t ALSEC;
bogdanm 0:9b334a45a8ff 432 uint8_t RESERVED15[3];
bogdanm 0:9b334a45a8ff 433 __IO uint8_t ALMIN;
bogdanm 0:9b334a45a8ff 434 uint8_t RESERVED16[3];
bogdanm 0:9b334a45a8ff 435 __IO uint8_t ALHOUR;
bogdanm 0:9b334a45a8ff 436 uint8_t RESERVED17[3];
bogdanm 0:9b334a45a8ff 437 __IO uint8_t ALDOM;
bogdanm 0:9b334a45a8ff 438 uint8_t RESERVED18[3];
bogdanm 0:9b334a45a8ff 439 __IO uint8_t ALDOW;
bogdanm 0:9b334a45a8ff 440 uint8_t RESERVED19[3];
bogdanm 0:9b334a45a8ff 441 __IO uint16_t ALDOY;
bogdanm 0:9b334a45a8ff 442 uint16_t RESERVED20;
bogdanm 0:9b334a45a8ff 443 __IO uint8_t ALMON;
bogdanm 0:9b334a45a8ff 444 uint8_t RESERVED21[3];
bogdanm 0:9b334a45a8ff 445 __IO uint16_t ALYEAR;
bogdanm 0:9b334a45a8ff 446 uint16_t RESERVED22;
bogdanm 0:9b334a45a8ff 447 } LPC_RTC_TypeDef;
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
bogdanm 0:9b334a45a8ff 450 typedef struct
bogdanm 0:9b334a45a8ff 451 {
bogdanm 0:9b334a45a8ff 452 __IO uint8_t WDMOD;
bogdanm 0:9b334a45a8ff 453 uint8_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 454 __IO uint32_t WDTC;
bogdanm 0:9b334a45a8ff 455 __O uint8_t WDFEED;
bogdanm 0:9b334a45a8ff 456 uint8_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 457 __I uint32_t WDTV;
bogdanm 0:9b334a45a8ff 458 __IO uint32_t WDCLKSEL;
bogdanm 0:9b334a45a8ff 459 } LPC_WDT_TypeDef;
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
bogdanm 0:9b334a45a8ff 462 typedef struct
bogdanm 0:9b334a45a8ff 463 {
bogdanm 0:9b334a45a8ff 464 __IO uint32_t ADCR;
bogdanm 0:9b334a45a8ff 465 __IO uint32_t ADGDR;
bogdanm 0:9b334a45a8ff 466 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 467 __IO uint32_t ADINTEN;
bogdanm 0:9b334a45a8ff 468 __I uint32_t ADDR0;
bogdanm 0:9b334a45a8ff 469 __I uint32_t ADDR1;
bogdanm 0:9b334a45a8ff 470 __I uint32_t ADDR2;
bogdanm 0:9b334a45a8ff 471 __I uint32_t ADDR3;
bogdanm 0:9b334a45a8ff 472 __I uint32_t ADDR4;
bogdanm 0:9b334a45a8ff 473 __I uint32_t ADDR5;
bogdanm 0:9b334a45a8ff 474 __I uint32_t ADDR6;
bogdanm 0:9b334a45a8ff 475 __I uint32_t ADDR7;
bogdanm 0:9b334a45a8ff 476 __I uint32_t ADSTAT;
bogdanm 0:9b334a45a8ff 477 __IO uint32_t ADTRM;
bogdanm 0:9b334a45a8ff 478 } LPC_ADC_TypeDef;
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
bogdanm 0:9b334a45a8ff 481 typedef struct
bogdanm 0:9b334a45a8ff 482 {
bogdanm 0:9b334a45a8ff 483 __IO uint32_t DACR;
bogdanm 0:9b334a45a8ff 484 __IO uint32_t DACCTRL;
bogdanm 0:9b334a45a8ff 485 __IO uint16_t DACCNTVAL;
bogdanm 0:9b334a45a8ff 486 } LPC_DAC_TypeDef;
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 /*------------- Multimedia Card Interface (MCI) ------------------------------*/
bogdanm 0:9b334a45a8ff 489 typedef struct
bogdanm 0:9b334a45a8ff 490 {
bogdanm 0:9b334a45a8ff 491 __IO uint32_t MCIPower; /* Power control */
bogdanm 0:9b334a45a8ff 492 __IO uint32_t MCIClock; /* Clock control */
bogdanm 0:9b334a45a8ff 493 __IO uint32_t MCIArgument;
bogdanm 0:9b334a45a8ff 494 __IO uint32_t MMCCommand;
bogdanm 0:9b334a45a8ff 495 __I uint32_t MCIRespCmd;
bogdanm 0:9b334a45a8ff 496 __I uint32_t MCIResponse0;
bogdanm 0:9b334a45a8ff 497 __I uint32_t MCIResponse1;
bogdanm 0:9b334a45a8ff 498 __I uint32_t MCIResponse2;
bogdanm 0:9b334a45a8ff 499 __I uint32_t MCIResponse3;
bogdanm 0:9b334a45a8ff 500 __IO uint32_t MCIDataTimer;
bogdanm 0:9b334a45a8ff 501 __IO uint32_t MCIDataLength;
bogdanm 0:9b334a45a8ff 502 __IO uint32_t MCIDataCtrl;
bogdanm 0:9b334a45a8ff 503 __I uint32_t MCIDataCnt;
bogdanm 0:9b334a45a8ff 504 } LPC_MCI_TypeDef;
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 /*------------- Controller Area Network (CAN) --------------------------------*/
bogdanm 0:9b334a45a8ff 507 typedef struct
bogdanm 0:9b334a45a8ff 508 {
bogdanm 0:9b334a45a8ff 509 __IO uint32_t mask[512]; /* ID Masks */
bogdanm 0:9b334a45a8ff 510 } LPC_CANAF_RAM_TypeDef;
bogdanm 0:9b334a45a8ff 511
bogdanm 0:9b334a45a8ff 512 typedef struct /* Acceptance Filter Registers */
bogdanm 0:9b334a45a8ff 513 {
bogdanm 0:9b334a45a8ff 514 __IO uint32_t AFMR;
bogdanm 0:9b334a45a8ff 515 __IO uint32_t SFF_sa;
bogdanm 0:9b334a45a8ff 516 __IO uint32_t SFF_GRP_sa;
bogdanm 0:9b334a45a8ff 517 __IO uint32_t EFF_sa;
bogdanm 0:9b334a45a8ff 518 __IO uint32_t EFF_GRP_sa;
bogdanm 0:9b334a45a8ff 519 __IO uint32_t ENDofTable;
bogdanm 0:9b334a45a8ff 520 __I uint32_t LUTerrAd;
bogdanm 0:9b334a45a8ff 521 __I uint32_t LUTerr;
bogdanm 0:9b334a45a8ff 522 } LPC_CANAF_TypeDef;
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 typedef struct /* Central Registers */
bogdanm 0:9b334a45a8ff 525 {
bogdanm 0:9b334a45a8ff 526 __I uint32_t CANTxSR;
bogdanm 0:9b334a45a8ff 527 __I uint32_t CANRxSR;
bogdanm 0:9b334a45a8ff 528 __I uint32_t CANMSR;
bogdanm 0:9b334a45a8ff 529 } LPC_CANCR_TypeDef;
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 typedef struct /* Controller Registers */
bogdanm 0:9b334a45a8ff 532 {
bogdanm 0:9b334a45a8ff 533 __IO uint32_t MOD;
bogdanm 0:9b334a45a8ff 534 __O uint32_t CMR;
bogdanm 0:9b334a45a8ff 535 __IO uint32_t GSR;
bogdanm 0:9b334a45a8ff 536 __I uint32_t ICR;
bogdanm 0:9b334a45a8ff 537 __IO uint32_t IER;
bogdanm 0:9b334a45a8ff 538 __IO uint32_t BTR;
bogdanm 0:9b334a45a8ff 539 __IO uint32_t EWL;
bogdanm 0:9b334a45a8ff 540 __I uint32_t SR;
bogdanm 0:9b334a45a8ff 541 __IO uint32_t RFS;
bogdanm 0:9b334a45a8ff 542 __IO uint32_t RID;
bogdanm 0:9b334a45a8ff 543 __IO uint32_t RDA;
bogdanm 0:9b334a45a8ff 544 __IO uint32_t RDB;
bogdanm 0:9b334a45a8ff 545 __IO uint32_t TFI1;
bogdanm 0:9b334a45a8ff 546 __IO uint32_t TID1;
bogdanm 0:9b334a45a8ff 547 __IO uint32_t TDA1;
bogdanm 0:9b334a45a8ff 548 __IO uint32_t TDB1;
bogdanm 0:9b334a45a8ff 549 __IO uint32_t TFI2;
bogdanm 0:9b334a45a8ff 550 __IO uint32_t TID2;
bogdanm 0:9b334a45a8ff 551 __IO uint32_t TDA2;
bogdanm 0:9b334a45a8ff 552 __IO uint32_t TDB2;
bogdanm 0:9b334a45a8ff 553 __IO uint32_t TFI3;
bogdanm 0:9b334a45a8ff 554 __IO uint32_t TID3;
bogdanm 0:9b334a45a8ff 555 __IO uint32_t TDA3;
bogdanm 0:9b334a45a8ff 556 __IO uint32_t TDB3;
bogdanm 0:9b334a45a8ff 557 } LPC_CAN_TypeDef;
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
bogdanm 0:9b334a45a8ff 560 typedef struct /* Common Registers */
bogdanm 0:9b334a45a8ff 561 {
bogdanm 0:9b334a45a8ff 562 __I uint32_t DMACIntStat;
bogdanm 0:9b334a45a8ff 563 __I uint32_t DMACIntTCStat;
bogdanm 0:9b334a45a8ff 564 __O uint32_t DMACIntTCClear;
bogdanm 0:9b334a45a8ff 565 __I uint32_t DMACIntErrStat;
bogdanm 0:9b334a45a8ff 566 __O uint32_t DMACIntErrClr;
bogdanm 0:9b334a45a8ff 567 __I uint32_t DMACRawIntTCStat;
bogdanm 0:9b334a45a8ff 568 __I uint32_t DMACRawIntErrStat;
bogdanm 0:9b334a45a8ff 569 __I uint32_t DMACEnbldChns;
bogdanm 0:9b334a45a8ff 570 __IO uint32_t DMACSoftBReq;
bogdanm 0:9b334a45a8ff 571 __IO uint32_t DMACSoftSReq;
bogdanm 0:9b334a45a8ff 572 __IO uint32_t DMACSoftLBReq;
bogdanm 0:9b334a45a8ff 573 __IO uint32_t DMACSoftLSReq;
bogdanm 0:9b334a45a8ff 574 __IO uint32_t DMACConfig;
bogdanm 0:9b334a45a8ff 575 __IO uint32_t DMACSync;
bogdanm 0:9b334a45a8ff 576 } LPC_GPDMA_TypeDef;
bogdanm 0:9b334a45a8ff 577
bogdanm 0:9b334a45a8ff 578 typedef struct /* Channel Registers */
bogdanm 0:9b334a45a8ff 579 {
bogdanm 0:9b334a45a8ff 580 __IO uint32_t DMACCSrcAddr;
bogdanm 0:9b334a45a8ff 581 __IO uint32_t DMACCDestAddr;
bogdanm 0:9b334a45a8ff 582 __IO uint32_t DMACCLLI;
bogdanm 0:9b334a45a8ff 583 __IO uint32_t DMACCControl;
bogdanm 0:9b334a45a8ff 584 __IO uint32_t DMACCConfig;
bogdanm 0:9b334a45a8ff 585 } LPC_GPDMACH_TypeDef;
bogdanm 0:9b334a45a8ff 586
bogdanm 0:9b334a45a8ff 587 /*------------- Universal Serial Bus (USB) -----------------------------------*/
bogdanm 0:9b334a45a8ff 588 typedef struct
bogdanm 0:9b334a45a8ff 589 {
bogdanm 0:9b334a45a8ff 590 __I uint32_t HcRevision; /* USB Host Registers */
bogdanm 0:9b334a45a8ff 591 __IO uint32_t HcControl;
bogdanm 0:9b334a45a8ff 592 __IO uint32_t HcCommandStatus;
bogdanm 0:9b334a45a8ff 593 __IO uint32_t HcInterruptStatus;
bogdanm 0:9b334a45a8ff 594 __IO uint32_t HcInterruptEnable;
bogdanm 0:9b334a45a8ff 595 __IO uint32_t HcInterruptDisable;
bogdanm 0:9b334a45a8ff 596 __IO uint32_t HcHCCA;
bogdanm 0:9b334a45a8ff 597 __I uint32_t HcPeriodCurrentED;
bogdanm 0:9b334a45a8ff 598 __IO uint32_t HcControlHeadED;
bogdanm 0:9b334a45a8ff 599 __IO uint32_t HcControlCurrentED;
bogdanm 0:9b334a45a8ff 600 __IO uint32_t HcBulkHeadED;
bogdanm 0:9b334a45a8ff 601 __IO uint32_t HcBulkCurrentED;
bogdanm 0:9b334a45a8ff 602 __I uint32_t HcDoneHead;
bogdanm 0:9b334a45a8ff 603 __IO uint32_t HcFmInterval;
bogdanm 0:9b334a45a8ff 604 __I uint32_t HcFmRemaining;
bogdanm 0:9b334a45a8ff 605 __I uint32_t HcFmNumber;
bogdanm 0:9b334a45a8ff 606 __IO uint32_t HcPeriodicStart;
bogdanm 0:9b334a45a8ff 607 __IO uint32_t HcLSTreshold;
bogdanm 0:9b334a45a8ff 608 __IO uint32_t HcRhDescriptorA;
bogdanm 0:9b334a45a8ff 609 __IO uint32_t HcRhDescriptorB;
bogdanm 0:9b334a45a8ff 610 __IO uint32_t HcRhStatus;
bogdanm 0:9b334a45a8ff 611 __IO uint32_t HcRhPortStatus1;
bogdanm 0:9b334a45a8ff 612 __IO uint32_t HcRhPortStatus2;
bogdanm 0:9b334a45a8ff 613 uint32_t RESERVED0[40];
bogdanm 0:9b334a45a8ff 614 __I uint32_t Module_ID;
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
bogdanm 0:9b334a45a8ff 617 __IO uint32_t OTGIntEn;
bogdanm 0:9b334a45a8ff 618 __O uint32_t OTGIntSet;
bogdanm 0:9b334a45a8ff 619 __O uint32_t OTGIntClr;
bogdanm 0:9b334a45a8ff 620 __IO uint32_t OTGStCtrl;
bogdanm 0:9b334a45a8ff 621 __IO uint32_t OTGTmr;
bogdanm 0:9b334a45a8ff 622 uint32_t RESERVED1[58];
bogdanm 0:9b334a45a8ff 623
bogdanm 0:9b334a45a8ff 624 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
bogdanm 0:9b334a45a8ff 625 __IO uint32_t USBDevIntEn;
bogdanm 0:9b334a45a8ff 626 __O uint32_t USBDevIntClr;
bogdanm 0:9b334a45a8ff 627 __O uint32_t USBDevIntSet;
bogdanm 0:9b334a45a8ff 628
bogdanm 0:9b334a45a8ff 629 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
bogdanm 0:9b334a45a8ff 630 __I uint32_t USBCmdData;
bogdanm 0:9b334a45a8ff 631
bogdanm 0:9b334a45a8ff 632 __I uint32_t USBRxData; /* USB Device Transfer Registers */
bogdanm 0:9b334a45a8ff 633 __O uint32_t USBTxData;
bogdanm 0:9b334a45a8ff 634 __I uint32_t USBRxPLen;
bogdanm 0:9b334a45a8ff 635 __O uint32_t USBTxPLen;
bogdanm 0:9b334a45a8ff 636 __IO uint32_t USBCtrl;
bogdanm 0:9b334a45a8ff 637 __O uint32_t USBDevIntPri;
bogdanm 0:9b334a45a8ff 638
bogdanm 0:9b334a45a8ff 639 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
bogdanm 0:9b334a45a8ff 640 __IO uint32_t USBEpIntEn;
bogdanm 0:9b334a45a8ff 641 __O uint32_t USBEpIntClr;
bogdanm 0:9b334a45a8ff 642 __O uint32_t USBEpIntSet;
bogdanm 0:9b334a45a8ff 643 __O uint32_t USBEpIntPri;
bogdanm 0:9b334a45a8ff 644
bogdanm 0:9b334a45a8ff 645 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
bogdanm 0:9b334a45a8ff 646 __O uint32_t USBEpInd;
bogdanm 0:9b334a45a8ff 647 __IO uint32_t USBMaxPSize;
bogdanm 0:9b334a45a8ff 648
bogdanm 0:9b334a45a8ff 649 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
bogdanm 0:9b334a45a8ff 650 __O uint32_t USBDMARClr;
bogdanm 0:9b334a45a8ff 651 __O uint32_t USBDMARSet;
bogdanm 0:9b334a45a8ff 652 uint32_t RESERVED2[9];
bogdanm 0:9b334a45a8ff 653 __IO uint32_t USBUDCAH;
bogdanm 0:9b334a45a8ff 654 __I uint32_t USBEpDMASt;
bogdanm 0:9b334a45a8ff 655 __O uint32_t USBEpDMAEn;
bogdanm 0:9b334a45a8ff 656 __O uint32_t USBEpDMADis;
bogdanm 0:9b334a45a8ff 657 __I uint32_t USBDMAIntSt;
bogdanm 0:9b334a45a8ff 658 __IO uint32_t USBDMAIntEn;
bogdanm 0:9b334a45a8ff 659 uint32_t RESERVED3[2];
bogdanm 0:9b334a45a8ff 660 __I uint32_t USBEoTIntSt;
bogdanm 0:9b334a45a8ff 661 __O uint32_t USBEoTIntClr;
bogdanm 0:9b334a45a8ff 662 __O uint32_t USBEoTIntSet;
bogdanm 0:9b334a45a8ff 663 __I uint32_t USBNDDRIntSt;
bogdanm 0:9b334a45a8ff 664 __O uint32_t USBNDDRIntClr;
bogdanm 0:9b334a45a8ff 665 __O uint32_t USBNDDRIntSet;
bogdanm 0:9b334a45a8ff 666 __I uint32_t USBSysErrIntSt;
bogdanm 0:9b334a45a8ff 667 __O uint32_t USBSysErrIntClr;
bogdanm 0:9b334a45a8ff 668 __O uint32_t USBSysErrIntSet;
bogdanm 0:9b334a45a8ff 669 uint32_t RESERVED4[15];
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
bogdanm 0:9b334a45a8ff 672 __O uint32_t I2C_WO;
bogdanm 0:9b334a45a8ff 673 __I uint32_t I2C_STS;
bogdanm 0:9b334a45a8ff 674 __IO uint32_t I2C_CTL;
bogdanm 0:9b334a45a8ff 675 __IO uint32_t I2C_CLKHI;
bogdanm 0:9b334a45a8ff 676 __O uint32_t I2C_CLKLO;
bogdanm 0:9b334a45a8ff 677 uint32_t RESERVED5[823];
bogdanm 0:9b334a45a8ff 678
bogdanm 0:9b334a45a8ff 679 union {
bogdanm 0:9b334a45a8ff 680 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
bogdanm 0:9b334a45a8ff 681 __IO uint32_t OTGClkCtrl;
bogdanm 0:9b334a45a8ff 682 };
bogdanm 0:9b334a45a8ff 683 union {
bogdanm 0:9b334a45a8ff 684 __I uint32_t USBClkSt;
bogdanm 0:9b334a45a8ff 685 __I uint32_t OTGClkSt;
bogdanm 0:9b334a45a8ff 686 };
bogdanm 0:9b334a45a8ff 687 } LPC_USB_TypeDef;
bogdanm 0:9b334a45a8ff 688
bogdanm 0:9b334a45a8ff 689 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
bogdanm 0:9b334a45a8ff 690 typedef struct
bogdanm 0:9b334a45a8ff 691 {
bogdanm 0:9b334a45a8ff 692 __IO uint32_t MAC1; /* MAC Registers */
bogdanm 0:9b334a45a8ff 693 __IO uint32_t MAC2;
bogdanm 0:9b334a45a8ff 694 __IO uint32_t IPGT;
bogdanm 0:9b334a45a8ff 695 __IO uint32_t IPGR;
bogdanm 0:9b334a45a8ff 696 __IO uint32_t CLRT;
bogdanm 0:9b334a45a8ff 697 __IO uint32_t MAXF;
bogdanm 0:9b334a45a8ff 698 __IO uint32_t SUPP;
bogdanm 0:9b334a45a8ff 699 __IO uint32_t TEST;
bogdanm 0:9b334a45a8ff 700 __IO uint32_t MCFG;
bogdanm 0:9b334a45a8ff 701 __IO uint32_t MCMD;
bogdanm 0:9b334a45a8ff 702 __IO uint32_t MADR;
bogdanm 0:9b334a45a8ff 703 __O uint32_t MWTD;
bogdanm 0:9b334a45a8ff 704 __I uint32_t MRDD;
bogdanm 0:9b334a45a8ff 705 __I uint32_t MIND;
bogdanm 0:9b334a45a8ff 706 uint32_t RESERVED0[2];
bogdanm 0:9b334a45a8ff 707 __IO uint32_t SA0;
bogdanm 0:9b334a45a8ff 708 __IO uint32_t SA1;
bogdanm 0:9b334a45a8ff 709 __IO uint32_t SA2;
bogdanm 0:9b334a45a8ff 710 uint32_t RESERVED1[45];
bogdanm 0:9b334a45a8ff 711 __IO uint32_t Command; /* Control Registers */
bogdanm 0:9b334a45a8ff 712 __I uint32_t Status;
bogdanm 0:9b334a45a8ff 713 __IO uint32_t RxDescriptor;
bogdanm 0:9b334a45a8ff 714 __IO uint32_t RxStatus;
bogdanm 0:9b334a45a8ff 715 __IO uint32_t RxDescriptorNumber;
bogdanm 0:9b334a45a8ff 716 __I uint32_t RxProduceIndex;
bogdanm 0:9b334a45a8ff 717 __IO uint32_t RxConsumeIndex;
bogdanm 0:9b334a45a8ff 718 __IO uint32_t TxDescriptor;
bogdanm 0:9b334a45a8ff 719 __IO uint32_t TxStatus;
bogdanm 0:9b334a45a8ff 720 __IO uint32_t TxDescriptorNumber;
bogdanm 0:9b334a45a8ff 721 __IO uint32_t TxProduceIndex;
bogdanm 0:9b334a45a8ff 722 __I uint32_t TxConsumeIndex;
bogdanm 0:9b334a45a8ff 723 uint32_t RESERVED2[10];
bogdanm 0:9b334a45a8ff 724 __I uint32_t TSV0;
bogdanm 0:9b334a45a8ff 725 __I uint32_t TSV1;
bogdanm 0:9b334a45a8ff 726 __I uint32_t RSV;
bogdanm 0:9b334a45a8ff 727 uint32_t RESERVED3[3];
bogdanm 0:9b334a45a8ff 728 __IO uint32_t FlowControlCounter;
bogdanm 0:9b334a45a8ff 729 __I uint32_t FlowControlStatus;
bogdanm 0:9b334a45a8ff 730 uint32_t RESERVED4[34];
bogdanm 0:9b334a45a8ff 731 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
bogdanm 0:9b334a45a8ff 732 __IO uint32_t RxFilterWoLStatus;
bogdanm 0:9b334a45a8ff 733 __IO uint32_t RxFilterWoLClear;
bogdanm 0:9b334a45a8ff 734 uint32_t RESERVED5;
bogdanm 0:9b334a45a8ff 735 __IO uint32_t HashFilterL;
bogdanm 0:9b334a45a8ff 736 __IO uint32_t HashFilterH;
bogdanm 0:9b334a45a8ff 737 uint32_t RESERVED6[882];
bogdanm 0:9b334a45a8ff 738 __I uint32_t IntStatus; /* Module Control Registers */
bogdanm 0:9b334a45a8ff 739 __IO uint32_t IntEnable;
bogdanm 0:9b334a45a8ff 740 __O uint32_t IntClear;
bogdanm 0:9b334a45a8ff 741 __O uint32_t IntSet;
bogdanm 0:9b334a45a8ff 742 uint32_t RESERVED7;
bogdanm 0:9b334a45a8ff 743 __IO uint32_t PowerDown;
bogdanm 0:9b334a45a8ff 744 uint32_t RESERVED8;
bogdanm 0:9b334a45a8ff 745 __IO uint32_t Module_ID;
bogdanm 0:9b334a45a8ff 746 } LPC_EMAC_TypeDef;
bogdanm 0:9b334a45a8ff 747
bogdanm 0:9b334a45a8ff 748 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 749 #pragma no_anon_unions
bogdanm 0:9b334a45a8ff 750 #endif
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 /******************************************************************************/
bogdanm 0:9b334a45a8ff 753 /* Peripheral memory map */
bogdanm 0:9b334a45a8ff 754 /******************************************************************************/
bogdanm 0:9b334a45a8ff 755 /* Base addresses */
bogdanm 0:9b334a45a8ff 756
bogdanm 0:9b334a45a8ff 757 /* AHB Peripheral # 0 */
bogdanm 0:9b334a45a8ff 758
bogdanm 0:9b334a45a8ff 759 /*
bogdanm 0:9b334a45a8ff 760 #define FLASH_BASE (0x00000000UL)
bogdanm 0:9b334a45a8ff 761 #define RAM_BASE (0x10000000UL)
bogdanm 0:9b334a45a8ff 762 #define GPIO_BASE (0x2009C000UL)
bogdanm 0:9b334a45a8ff 763 #define APB0_BASE (0x40000000UL)
bogdanm 0:9b334a45a8ff 764 #define APB1_BASE (0x40080000UL)
bogdanm 0:9b334a45a8ff 765 #define AHB_BASE (0x50000000UL)
bogdanm 0:9b334a45a8ff 766 #define CM3_BASE (0xE0000000UL)
bogdanm 0:9b334a45a8ff 767 */
bogdanm 0:9b334a45a8ff 768
bogdanm 0:9b334a45a8ff 769 // TODO - #define VIC_BASE_ADDR 0xFFFFF000
bogdanm 0:9b334a45a8ff 770
bogdanm 0:9b334a45a8ff 771 #define LPC_WDT_BASE (0xE0000000)
bogdanm 0:9b334a45a8ff 772 #define LPC_TIM0_BASE (0xE0004000)
bogdanm 0:9b334a45a8ff 773 #define LPC_TIM1_BASE (0xE0008000)
bogdanm 0:9b334a45a8ff 774 #define LPC_UART0_BASE (0xE000C000)
bogdanm 0:9b334a45a8ff 775 #define LPC_UART1_BASE (0xE0010000)
bogdanm 0:9b334a45a8ff 776 #define LPC_PWM1_BASE (0xE0018000)
bogdanm 0:9b334a45a8ff 777 #define LPC_I2C0_BASE (0xE001C000)
bogdanm 0:9b334a45a8ff 778 #define LPC_SPI_BASE (0xE0020000)
bogdanm 0:9b334a45a8ff 779 #define LPC_RTC_BASE (0xE0024000)
bogdanm 0:9b334a45a8ff 780 #define LPC_GPIOINT_BASE (0xE0028080)
bogdanm 0:9b334a45a8ff 781 #define LPC_PINCON_BASE (0xE002C000)
bogdanm 0:9b334a45a8ff 782 #define LPC_SSP1_BASE (0xE0030000)
bogdanm 0:9b334a45a8ff 783 #define LPC_ADC_BASE (0xE0034000)
bogdanm 0:9b334a45a8ff 784 #define LPC_CANAF_RAM_BASE (0xE0038000)
bogdanm 0:9b334a45a8ff 785 #define LPC_CANAF_BASE (0xE003C000)
bogdanm 0:9b334a45a8ff 786 #define LPC_CANCR_BASE (0xE0040000)
bogdanm 0:9b334a45a8ff 787 #define LPC_CAN1_BASE (0xE0044000)
bogdanm 0:9b334a45a8ff 788 #define LPC_CAN2_BASE (0xE0048000)
bogdanm 0:9b334a45a8ff 789 #define LPC_I2C1_BASE (0xE005C000)
bogdanm 0:9b334a45a8ff 790 #define LPC_SSP0_BASE (0xE0068000)
bogdanm 0:9b334a45a8ff 791 #define LPC_DAC_BASE (0xE006C000)
bogdanm 0:9b334a45a8ff 792 #define LPC_TIM2_BASE (0xE0070000)
bogdanm 0:9b334a45a8ff 793 #define LPC_TIM3_BASE (0xE0074000)
bogdanm 0:9b334a45a8ff 794 #define LPC_UART2_BASE (0xE0078000)
bogdanm 0:9b334a45a8ff 795 #define LPC_UART3_BASE (0xE007C000)
bogdanm 0:9b334a45a8ff 796 #define LPC_I2C2_BASE (0xE0080000)
bogdanm 0:9b334a45a8ff 797 #define LPC_I2S_BASE (0xE0088000)
bogdanm 0:9b334a45a8ff 798 #define LPC_MCI_BASE (0xE008C000)
bogdanm 0:9b334a45a8ff 799 #define LPC_SC_BASE (0xE01FC000)
bogdanm 0:9b334a45a8ff 800 #define LPC_EMAC_BASE (0xFFE00000)
bogdanm 0:9b334a45a8ff 801 #define LPC_GPDMA_BASE (0xFFE04000)
bogdanm 0:9b334a45a8ff 802 #define LPC_GPDMACH0_BASE (0xFFE04100)
bogdanm 0:9b334a45a8ff 803 #define LPC_GPDMACH1_BASE (0xFFE04120)
bogdanm 0:9b334a45a8ff 804 #define LPC_USB_BASE (0xFFE0C000)
bogdanm 0:9b334a45a8ff 805 #define LPC_VIC_BASE (0xFFFFF000)
bogdanm 0:9b334a45a8ff 806
bogdanm 0:9b334a45a8ff 807 /* GPIOs */
bogdanm 0:9b334a45a8ff 808 #define LPC_GPIO0_BASE (0x3FFFC000)
bogdanm 0:9b334a45a8ff 809 #define LPC_GPIO1_BASE (0x3FFFC020)
bogdanm 0:9b334a45a8ff 810 #define LPC_GPIO2_BASE (0x3FFFC040)
bogdanm 0:9b334a45a8ff 811 #define LPC_GPIO3_BASE (0x3FFFC060)
bogdanm 0:9b334a45a8ff 812 #define LPC_GPIO4_BASE (0x3FFFC080)
bogdanm 0:9b334a45a8ff 813
bogdanm 0:9b334a45a8ff 814
bogdanm 0:9b334a45a8ff 815 /******************************************************************************/
bogdanm 0:9b334a45a8ff 816 /* Peripheral declaration */
bogdanm 0:9b334a45a8ff 817 /******************************************************************************/
bogdanm 0:9b334a45a8ff 818 #define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
bogdanm 0:9b334a45a8ff 819 #define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
bogdanm 0:9b334a45a8ff 820 #define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
bogdanm 0:9b334a45a8ff 821 #define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
bogdanm 0:9b334a45a8ff 822 #define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
bogdanm 0:9b334a45a8ff 823 #define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
bogdanm 0:9b334a45a8ff 824 #define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
bogdanm 0:9b334a45a8ff 825 #define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
bogdanm 0:9b334a45a8ff 826 #define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
bogdanm 0:9b334a45a8ff 827 #define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
bogdanm 0:9b334a45a8ff 828 #define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
bogdanm 0:9b334a45a8ff 829 #define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
bogdanm 0:9b334a45a8ff 830 #define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
bogdanm 0:9b334a45a8ff 831 #define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
bogdanm 0:9b334a45a8ff 832 #define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
bogdanm 0:9b334a45a8ff 833 #define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
bogdanm 0:9b334a45a8ff 834 #define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
bogdanm 0:9b334a45a8ff 835 #define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
bogdanm 0:9b334a45a8ff 836 #define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
bogdanm 0:9b334a45a8ff 837 #define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
bogdanm 0:9b334a45a8ff 838 #define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
bogdanm 0:9b334a45a8ff 839 #define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
bogdanm 0:9b334a45a8ff 840 #define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
bogdanm 0:9b334a45a8ff 841 #define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
bogdanm 0:9b334a45a8ff 842 #define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
bogdanm 0:9b334a45a8ff 843 #define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
bogdanm 0:9b334a45a8ff 844 #define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
bogdanm 0:9b334a45a8ff 845 #define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
bogdanm 0:9b334a45a8ff 846 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
bogdanm 0:9b334a45a8ff 847 #define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
bogdanm 0:9b334a45a8ff 848 #define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
bogdanm 0:9b334a45a8ff 849 #define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
bogdanm 0:9b334a45a8ff 850 #define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
bogdanm 0:9b334a45a8ff 851 #define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
bogdanm 0:9b334a45a8ff 852 #define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
bogdanm 0:9b334a45a8ff 853 #define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
bogdanm 0:9b334a45a8ff 854 #define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
bogdanm 0:9b334a45a8ff 855 #define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
bogdanm 0:9b334a45a8ff 856 #define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
bogdanm 0:9b334a45a8ff 857 #define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
bogdanm 0:9b334a45a8ff 858
bogdanm 0:9b334a45a8ff 859 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 860 }
bogdanm 0:9b334a45a8ff 861 #endif
bogdanm 0:9b334a45a8ff 862
bogdanm 0:9b334a45a8ff 863 #endif // __LPC23xx_H
bogdanm 0:9b334a45a8ff 864