mbed-dev - mbed library sources. Supersedes mbed-src. Fixes…

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mbed library sources. Supersedes mbed-src. Fixes analogIn and analogOut problems for TARGET_STM32F3. Tested on NUCLEO-F303K8, using 3 analogout and 7 analogin channels simultaneously. Added ability for STM32F334R8 and STM32F303K8 to use all three channels of DAC simultaneously. https://developer.mbed.org/users/StevieWray/code/mbed-dev/ Added ability for TARGET_STM32F3 to use more than one ADC simultaneously. https://developer.mbed.org/questions/67997/NUCLEO-F303K8ADC/

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1
bogdanm	0:9b334a45a8ff	2	/**************************************************************************************************//
bogdanm	0:9b334a45a8ff	3	* @file LPC15xx.h
bogdanm	0:9b334a45a8ff	4	*
bogdanm	0:9b334a45a8ff	5	* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
bogdanm	0:9b334a45a8ff	6	* LPC15xx from .
bogdanm	0:9b334a45a8ff	7	*
bogdanm	0:9b334a45a8ff	8	* @version V0.3
bogdanm	0:9b334a45a8ff	9	* @date 17. July 2013
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* @note Generated with SVDConv V2.80
bogdanm	0:9b334a45a8ff	12	* from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
bogdanm	0:9b334a45a8ff	13	*
bogdanm	0:9b334a45a8ff	14	* modified by Keil
bogdanm	0:9b334a45a8ff	15	* modified by ytsuboi
bogdanm	0:9b334a45a8ff	16	*******************************************************************************************************/
bogdanm	0:9b334a45a8ff	17
bogdanm	0:9b334a45a8ff	18
bogdanm	0:9b334a45a8ff	19
bogdanm	0:9b334a45a8ff	20	/** @addtogroup (null)
bogdanm	0:9b334a45a8ff	21	* @{
bogdanm	0:9b334a45a8ff	22	*/
bogdanm	0:9b334a45a8ff	23
bogdanm	0:9b334a45a8ff	24	/** @addtogroup LPC15xx
bogdanm	0:9b334a45a8ff	25	* @{
bogdanm	0:9b334a45a8ff	26	*/
bogdanm	0:9b334a45a8ff	27
bogdanm	0:9b334a45a8ff	28	#ifndef LPC15XX_H
bogdanm	0:9b334a45a8ff	29	#define LPC15XX_H
bogdanm	0:9b334a45a8ff	30
bogdanm	0:9b334a45a8ff	31	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	32	extern "C" {
bogdanm	0:9b334a45a8ff	33	#endif
bogdanm	0:9b334a45a8ff	34
bogdanm	0:9b334a45a8ff	35
bogdanm	0:9b334a45a8ff	36	/* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	typedef enum {
bogdanm	0:9b334a45a8ff	39	/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
bogdanm	0:9b334a45a8ff	40	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
bogdanm	0:9b334a45a8ff	41	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
bogdanm	0:9b334a45a8ff	42	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
bogdanm	0:9b334a45a8ff	43	MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
bogdanm	0:9b334a45a8ff	44	and No Match */
bogdanm	0:9b334a45a8ff	45	BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
bogdanm	0:9b334a45a8ff	46	related Fault */
bogdanm	0:9b334a45a8ff	47	UsageFault_IRQn = -10, /!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition /
bogdanm	0:9b334a45a8ff	48	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
bogdanm	0:9b334a45a8ff	49	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
bogdanm	0:9b334a45a8ff	50	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
bogdanm	0:9b334a45a8ff	51	SysTick_IRQn = -1, /!< 15 System Tick Timer /
bogdanm	0:9b334a45a8ff	52	/* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
bogdanm	0:9b334a45a8ff	53	WDT_IRQn = 0, /!< 0 WDT /
bogdanm	0:9b334a45a8ff	54	BOD_IRQn = 1, /!< 1 BOD /
bogdanm	0:9b334a45a8ff	55	FLASH_IRQn = 2, /!< 2 FLASH /
bogdanm	0:9b334a45a8ff	56	EE_IRQn = 3, /!< 3 EE /
bogdanm	0:9b334a45a8ff	57	DMA_IRQn = 4, /!< 4 DMA /
bogdanm	0:9b334a45a8ff	58	GINT0_IRQn = 5, /!< 5 GINT0 /
bogdanm	0:9b334a45a8ff	59	GINT1_IRQn = 6, /!< 6 GINT1 /
bogdanm	0:9b334a45a8ff	60	PIN_INT0_IRQn = 7, /!< 7 PIN_INT0 /
bogdanm	0:9b334a45a8ff	61	PIN_INT1_IRQn = 8, /!< 8 PIN_INT1 /
bogdanm	0:9b334a45a8ff	62	PIN_INT2_IRQn = 9, /!< 9 PIN_INT2 /
bogdanm	0:9b334a45a8ff	63	PIN_INT3_IRQn = 10, /!< 10 PIN_INT3 /
bogdanm	0:9b334a45a8ff	64	PIN_INT4_IRQn = 11, /!< 11 PIN_INT4 /
bogdanm	0:9b334a45a8ff	65	PIN_INT5_IRQn = 12, /!< 12 PIN_INT5 /
bogdanm	0:9b334a45a8ff	66	PIN_INT6_IRQn = 13, /!< 13 PIN_INT6 /
bogdanm	0:9b334a45a8ff	67	PIN_INT7_IRQn = 14, /!< 14 PIN_INT7 /
bogdanm	0:9b334a45a8ff	68	RIT_IRQn = 15, /!< 15 RIT /
bogdanm	0:9b334a45a8ff	69	SCT0_IRQn = 16, /!< 16 SCT0 /
bogdanm	0:9b334a45a8ff	70	SCT1_IRQn = 17, /!< 17 SCT1 /
bogdanm	0:9b334a45a8ff	71	SCT2_IRQn = 18, /!< 18 SCT2 /
bogdanm	0:9b334a45a8ff	72	SCT3_IRQn = 19, /!< 19 SCT3 /
bogdanm	0:9b334a45a8ff	73	MRT_IRQn = 20, /!< 20 MRT /
bogdanm	0:9b334a45a8ff	74	UART0_IRQn = 21, /!< 21 UART0 /
bogdanm	0:9b334a45a8ff	75	UART1_IRQn = 22, /!< 22 UART1 /
bogdanm	0:9b334a45a8ff	76	UART2_IRQn = 23, /!< 23 UART2 /
bogdanm	0:9b334a45a8ff	77	I2C0_IRQn = 24, /!< 24 I2C0 /
bogdanm	0:9b334a45a8ff	78	SPI0_IRQn = 25, /!< 25 SPI0 /
bogdanm	0:9b334a45a8ff	79	SPI1_IRQn = 26, /!< 26 SPI1 /
bogdanm	0:9b334a45a8ff	80	C_CAN0_IRQn = 27, /!< 27 C_CAN0 /
bogdanm	0:9b334a45a8ff	81	USB_IRQ_IRQn = 28, /!< 28 USB_IRQ /
bogdanm	0:9b334a45a8ff	82	USB_FIQ_IRQn = 29, /!< 29 USB_FIQ /
bogdanm	0:9b334a45a8ff	83	USBWAKEUP_IRQn = 30, /!< 30 USBWAKEUP /
bogdanm	0:9b334a45a8ff	84	ADC0_SEQA_IRQn = 31, /!< 31 ADC0_SEQA /
bogdanm	0:9b334a45a8ff	85	ADC0_SEQB_IRQn = 32, /!< 32 ADC0_SEQB /
bogdanm	0:9b334a45a8ff	86	ADC0_THCMP_IRQn = 33, /!< 33 ADC0_THCMP /
bogdanm	0:9b334a45a8ff	87	ADC0_OVR_IRQn = 34, /!< 34 ADC0_OVR /
bogdanm	0:9b334a45a8ff	88	ADC1_SEQA_IRQn = 35, /!< 35 ADC1_SEQA /
bogdanm	0:9b334a45a8ff	89	ADC1_SEQB_IRQn = 36, /!< 36 ADC1_SEQB /
bogdanm	0:9b334a45a8ff	90	ADC1_THCMP_IRQn = 37, /!< 37 ADC1_THCMP /
bogdanm	0:9b334a45a8ff	91	ADC1_OVR_IRQn = 38, /!< 38 ADC1_OVR /
bogdanm	0:9b334a45a8ff	92	DAC_IRQn = 39, /!< 39 DAC /
bogdanm	0:9b334a45a8ff	93	CMP0_IRQn = 40, /!< 40 CMP0 /
bogdanm	0:9b334a45a8ff	94	CMP1_IRQn = 41, /!< 41 CMP1 /
bogdanm	0:9b334a45a8ff	95	CMP2_IRQn = 42, /!< 42 CMP2 /
bogdanm	0:9b334a45a8ff	96	CMP3_IRQn = 43, /!< 43 CMP3 /
bogdanm	0:9b334a45a8ff	97	QEI_IRQn = 44, /!< 44 QEI /
bogdanm	0:9b334a45a8ff	98	RTC_ALARM_IRQn = 45, /!< 45 RTC_ALARM /
bogdanm	0:9b334a45a8ff	99	RTC_WAKE_IRQn = 46 /!< 46 RTC_WAKE /
bogdanm	0:9b334a45a8ff	100	} IRQn_Type;
bogdanm	0:9b334a45a8ff	101
bogdanm	0:9b334a45a8ff	102
bogdanm	0:9b334a45a8ff	103	/** @addtogroup Configuration_of_CMSIS
bogdanm	0:9b334a45a8ff	104	* @{
bogdanm	0:9b334a45a8ff	105	*/
bogdanm	0:9b334a45a8ff	106
bogdanm	0:9b334a45a8ff	107
bogdanm	0:9b334a45a8ff	108	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	109	/* ================ Processor and Core Peripheral Section ================ */
bogdanm	0:9b334a45a8ff	110	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	111
bogdanm	0:9b334a45a8ff	112	/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
bogdanm	0:9b334a45a8ff	113	#define __CM3_REV 0x0201 /!< Cortex-M3 Core Revision /
bogdanm	0:9b334a45a8ff	114	#define __MPU_PRESENT 0 /!< MPU present or not /
bogdanm	0:9b334a45a8ff	115	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
bogdanm	0:9b334a45a8ff	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	0:9b334a45a8ff	117	/** @} / / End of group Configuration_of_CMSIS */
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	#include "core_cm3.h" /!< Cortex-M3 processor and core peripherals /
bogdanm	0:9b334a45a8ff	120	#include "system_LPC15xx.h" /!< LPC15xx System /
bogdanm	0:9b334a45a8ff	121
bogdanm	0:9b334a45a8ff	122
bogdanm	0:9b334a45a8ff	123	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	124	/* ================ Device Specific Peripheral Section ================ */
bogdanm	0:9b334a45a8ff	125	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	126
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	/** @addtogroup Device_Peripheral_Registers
bogdanm	0:9b334a45a8ff	129	* @{
bogdanm	0:9b334a45a8ff	130	*/
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	/* ------------------- Start of section using anonymous unions ------------------ */
bogdanm	0:9b334a45a8ff	134	#if defined(__CC_ARM)
bogdanm	0:9b334a45a8ff	135	#pragma push
bogdanm	0:9b334a45a8ff	136	#pragma anon_unions
bogdanm	0:9b334a45a8ff	137	#elif defined(__ICCARM__)
bogdanm	0:9b334a45a8ff	138	#pragma language=extended
bogdanm	0:9b334a45a8ff	139	#elif defined(__GNUC__)
bogdanm	0:9b334a45a8ff	140	/* anonymous unions are enabled by default */
bogdanm	0:9b334a45a8ff	141	#elif defined(__TMS470__)
bogdanm	0:9b334a45a8ff	142	/* anonymous unions are enabled by default */
bogdanm	0:9b334a45a8ff	143	#elif defined(__TASKING__)
bogdanm	0:9b334a45a8ff	144	#pragma warning 586
bogdanm	0:9b334a45a8ff	145	#else
bogdanm	0:9b334a45a8ff	146	#warning Not supported compiler type
bogdanm	0:9b334a45a8ff	147	#endif
bogdanm	0:9b334a45a8ff	148
bogdanm	0:9b334a45a8ff	149
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	152	/* ================ GPIO_PORT ================ */
bogdanm	0:9b334a45a8ff	153	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	/**
bogdanm	0:9b334a45a8ff	157	* @brief General Purpose I/O (GPIO) (GPIO_PORT)
bogdanm	0:9b334a45a8ff	158	*/
bogdanm	0:9b334a45a8ff	159
bogdanm	0:9b334a45a8ff	160	typedef struct { /!< GPIO_PORT Structure /
bogdanm	0:9b334a45a8ff	161	__IO uint8_t B[76]; /!< Byte pin registers /
bogdanm	0:9b334a45a8ff	162	__I uint32_t RESERVED0[1005];
bogdanm	0:9b334a45a8ff	163	__IO uint32_t W[76]; /!< Word pin registers /
bogdanm	0:9b334a45a8ff	164	__I uint32_t RESERVED1[948];
bogdanm	0:9b334a45a8ff	165	__IO uint32_t DIR[3]; /!< Port Direction registers /
bogdanm	0:9b334a45a8ff	166	__I uint32_t RESERVED2[29];
bogdanm	0:9b334a45a8ff	167	__IO uint32_t MASK[3]; /!< Port Mask register /
bogdanm	0:9b334a45a8ff	168	__I uint32_t RESERVED3[29];
bogdanm	0:9b334a45a8ff	169	__IO uint32_t PIN[3]; /!< Port pin register /
bogdanm	0:9b334a45a8ff	170	__I uint32_t RESERVED4[29];
bogdanm	0:9b334a45a8ff	171	__IO uint32_t MPIN[3]; /!< Masked port register /
bogdanm	0:9b334a45a8ff	172	__I uint32_t RESERVED5[29];
bogdanm	0:9b334a45a8ff	173	__IO uint32_t SET[3]; /!< Write: Set port register Read: port output bits /
bogdanm	0:9b334a45a8ff	174	__I uint32_t RESERVED6[29];
bogdanm	0:9b334a45a8ff	175	__O uint32_t CLR[3]; /!< Clear port /
bogdanm	0:9b334a45a8ff	176	__I uint32_t RESERVED7[29];
bogdanm	0:9b334a45a8ff	177	__O uint32_t NOT[3]; /!< Toggle port /
bogdanm	0:9b334a45a8ff	178	} LPC_GPIO_PORT_Type;
bogdanm	0:9b334a45a8ff	179
bogdanm	0:9b334a45a8ff	180
bogdanm	0:9b334a45a8ff	181	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	182	/* ================ DMA ================ */
bogdanm	0:9b334a45a8ff	183	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	/**
bogdanm	0:9b334a45a8ff	187	* @brief DMA controller (DMA)
bogdanm	0:9b334a45a8ff	188	*/
bogdanm	0:9b334a45a8ff	189
bogdanm	0:9b334a45a8ff	190	typedef struct { /!< DMA Structure /
bogdanm	0:9b334a45a8ff	191	__IO uint32_t CTRL; /!< DMA control. /
bogdanm	0:9b334a45a8ff	192	__I uint32_t INTSTAT; /!< Interrupt status. /
bogdanm	0:9b334a45a8ff	193	__IO uint32_t SRAMBASE; /!< SRAM address of the channel configuration table. /
bogdanm	0:9b334a45a8ff	194	__I uint32_t RESERVED0[5];
bogdanm	0:9b334a45a8ff	195	__IO uint32_t ENABLESET0; /!< Channel Enable read and Set for all DMA channels. /
bogdanm	0:9b334a45a8ff	196	__I uint32_t RESERVED1;
bogdanm	0:9b334a45a8ff	197	__O uint32_t ENABLECLR0; /!< Channel Enable Clear for all DMA channels. /
bogdanm	0:9b334a45a8ff	198	__I uint32_t RESERVED2;
bogdanm	0:9b334a45a8ff	199	__I uint32_t ACTIVE0; /!< Channel Active status for all DMA channels. /
bogdanm	0:9b334a45a8ff	200	__I uint32_t RESERVED3;
bogdanm	0:9b334a45a8ff	201	__I uint32_t BUSY0; /!< Channel Busy status for all DMA channels. /
bogdanm	0:9b334a45a8ff	202	__I uint32_t RESERVED4;
bogdanm	0:9b334a45a8ff	203	__IO uint32_t ERRINT0; /!< Error Interrupt status for all DMA channels. /
bogdanm	0:9b334a45a8ff	204	__I uint32_t RESERVED5;
bogdanm	0:9b334a45a8ff	205	__IO uint32_t INTENSET0; /!< Interrupt Enable read and Set for all DMA channels. /
bogdanm	0:9b334a45a8ff	206	__I uint32_t RESERVED6;
bogdanm	0:9b334a45a8ff	207	__O uint32_t INTENCLR0; /!< Interrupt Enable Clear for all DMA channels. /
bogdanm	0:9b334a45a8ff	208	__I uint32_t RESERVED7;
bogdanm	0:9b334a45a8ff	209	__IO uint32_t INTA0; /!< Interrupt A status for all DMA channels. /
bogdanm	0:9b334a45a8ff	210	__I uint32_t RESERVED8;
bogdanm	0:9b334a45a8ff	211	__IO uint32_t INTB0; /!< Interrupt B status for all DMA channels. /
bogdanm	0:9b334a45a8ff	212	__I uint32_t RESERVED9;
bogdanm	0:9b334a45a8ff	213	__O uint32_t SETVALID0; /!< Set ValidPending control bits for all DMA channels. /
bogdanm	0:9b334a45a8ff	214	__I uint32_t RESERVED10;
bogdanm	0:9b334a45a8ff	215	__O uint32_t SETTRIG0; /!< Set Trigger control bits for all DMA channels. /
bogdanm	0:9b334a45a8ff	216	__I uint32_t RESERVED11;
bogdanm	0:9b334a45a8ff	217	__O uint32_t ABORT0; /!< Channel Abort control for all DMA channels. /
bogdanm	0:9b334a45a8ff	218	__I uint32_t RESERVED12[225];
bogdanm	0:9b334a45a8ff	219	__IO uint32_t CFG0; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	220	__I uint32_t CTLSTAT0; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	221	__IO uint32_t XFERCFG0; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	222	__I uint32_t RESERVED13;
bogdanm	0:9b334a45a8ff	223	__IO uint32_t CFG1; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	224	__I uint32_t CTLSTAT1; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	225	__IO uint32_t XFERCFG1; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	226	__I uint32_t RESERVED14;
bogdanm	0:9b334a45a8ff	227	__IO uint32_t CFG2; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	228	__I uint32_t CTLSTAT2; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	229	__IO uint32_t XFERCFG2; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	230	__I uint32_t RESERVED15;
bogdanm	0:9b334a45a8ff	231	__IO uint32_t CFG3; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	232	__I uint32_t CTLSTAT3; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	233	__IO uint32_t XFERCFG3; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	234	__I uint32_t RESERVED16;
bogdanm	0:9b334a45a8ff	235	__IO uint32_t CFG4; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	236	__I uint32_t CTLSTAT4; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	237	__IO uint32_t XFERCFG4; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	238	__I uint32_t RESERVED17;
bogdanm	0:9b334a45a8ff	239	__IO uint32_t CFG5; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	240	__I uint32_t CTLSTAT5; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	241	__IO uint32_t XFERCFG5; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	242	__I uint32_t RESERVED18;
bogdanm	0:9b334a45a8ff	243	__IO uint32_t CFG6; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	244	__I uint32_t CTLSTAT6; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	245	__IO uint32_t XFERCFG6; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	246	__I uint32_t RESERVED19;
bogdanm	0:9b334a45a8ff	247	__IO uint32_t CFG7; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	248	__I uint32_t CTLSTAT7; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	249	__IO uint32_t XFERCFG7; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	250	__I uint32_t RESERVED20;
bogdanm	0:9b334a45a8ff	251	__IO uint32_t CFG8; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	252	__I uint32_t CTLSTAT8; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	253	__IO uint32_t XFERCFG8; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	254	__I uint32_t RESERVED21;
bogdanm	0:9b334a45a8ff	255	__IO uint32_t CFG9; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	256	__I uint32_t CTLSTAT9; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	257	__IO uint32_t XFERCFG9; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	258	__I uint32_t RESERVED22;
bogdanm	0:9b334a45a8ff	259	__IO uint32_t CFG10; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	260	__I uint32_t CTLSTAT10; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	261	__IO uint32_t XFERCFG10; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	262	__I uint32_t RESERVED23;
bogdanm	0:9b334a45a8ff	263	__IO uint32_t CFG11; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	264	__I uint32_t CTLSTAT11; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	265	__IO uint32_t XFERCFG11; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	266	__I uint32_t RESERVED24;
bogdanm	0:9b334a45a8ff	267	__IO uint32_t CFG12; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	268	__I uint32_t CTLSTAT12; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	269	__IO uint32_t XFERCFG12; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	270	__I uint32_t RESERVED25;
bogdanm	0:9b334a45a8ff	271	__IO uint32_t CFG13; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	272	__I uint32_t CTLSTAT13; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	273	__IO uint32_t XFERCFG13; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	274	__I uint32_t RESERVED26;
bogdanm	0:9b334a45a8ff	275	__IO uint32_t CFG14; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	276	__I uint32_t CTLSTAT14; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	277	__IO uint32_t XFERCFG14; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	278	__I uint32_t RESERVED27;
bogdanm	0:9b334a45a8ff	279	__IO uint32_t CFG15; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	280	__I uint32_t CTLSTAT15; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	281	__IO uint32_t XFERCFG15; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	282	__I uint32_t RESERVED28;
bogdanm	0:9b334a45a8ff	283	__IO uint32_t CFG16; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	284	__I uint32_t CTLSTAT16; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	285	__IO uint32_t XFERCFG16; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	286	__I uint32_t RESERVED29;
bogdanm	0:9b334a45a8ff	287	__IO uint32_t CFG17; /!< Configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	288	__I uint32_t CTLSTAT17; /!< Control and status register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	289	__IO uint32_t XFERCFG17; /!< Transfer configuration register for DMA channel 0. /
bogdanm	0:9b334a45a8ff	290	} LPC_DMA_Type;
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292
bogdanm	0:9b334a45a8ff	293	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	294	/* ================ USB ================ */
bogdanm	0:9b334a45a8ff	295	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	296
bogdanm	0:9b334a45a8ff	297
bogdanm	0:9b334a45a8ff	298	/**
bogdanm	0:9b334a45a8ff	299	* @brief USB device controller (USB)
bogdanm	0:9b334a45a8ff	300	*/
bogdanm	0:9b334a45a8ff	301
bogdanm	0:9b334a45a8ff	302	typedef struct { /!< USB Structure /
bogdanm	0:9b334a45a8ff	303	__IO uint32_t DEVCMDSTAT; /!< USB Device Command/Status register /
bogdanm	0:9b334a45a8ff	304	__IO uint32_t INFO; /!< USB Info register /
bogdanm	0:9b334a45a8ff	305	__IO uint32_t EPLISTSTART; /!< USB EP Command/Status List start address /
bogdanm	0:9b334a45a8ff	306	__IO uint32_t DATABUFSTART; /!< USB Data buffer start address /
bogdanm	0:9b334a45a8ff	307	__IO uint32_t LPM; /!< Link Power Management register /
bogdanm	0:9b334a45a8ff	308	__IO uint32_t EPSKIP; /!< USB Endpoint skip /
bogdanm	0:9b334a45a8ff	309	__IO uint32_t EPINUSE; /!< USB Endpoint Buffer in use /
bogdanm	0:9b334a45a8ff	310	__IO uint32_t EPBUFCFG; /!< USB Endpoint Buffer Configuration register /
bogdanm	0:9b334a45a8ff	311	__IO uint32_t INTSTAT; /!< USB interrupt status register /
bogdanm	0:9b334a45a8ff	312	__IO uint32_t INTEN; /!< USB interrupt enable register /
bogdanm	0:9b334a45a8ff	313	__IO uint32_t INTSETSTAT; /!< USB set interrupt status register /
bogdanm	0:9b334a45a8ff	314	__IO uint32_t INTROUTING; /!< USB interrupt routing register /
bogdanm	0:9b334a45a8ff	315	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	316	__I uint32_t EPTOGGLE; /!< USB Endpoint toggle register /
bogdanm	0:9b334a45a8ff	317	} LPC_USB_Type;
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	321	/* ================ CRC ================ */
bogdanm	0:9b334a45a8ff	322	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	323
bogdanm	0:9b334a45a8ff	324
bogdanm	0:9b334a45a8ff	325	/**
bogdanm	0:9b334a45a8ff	326	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
bogdanm	0:9b334a45a8ff	327	*/
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	typedef struct { /!< CRC Structure /
bogdanm	0:9b334a45a8ff	330	__IO uint32_t MODE; /!< CRC mode register /
bogdanm	0:9b334a45a8ff	331	__IO uint32_t SEED; /!< CRC seed register /
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	union {
bogdanm	0:9b334a45a8ff	334	__O uint32_t WR_DATA; /!< CRC data register /
bogdanm	0:9b334a45a8ff	335	__I uint32_t SUM; /!< CRC checksum register /
bogdanm	0:9b334a45a8ff	336	};
bogdanm	0:9b334a45a8ff	337	} LPC_CRC_Type;
bogdanm	0:9b334a45a8ff	338
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	341	/* ================ SCT0 ================ */
bogdanm	0:9b334a45a8ff	342	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	/**
bogdanm	0:9b334a45a8ff	346	* @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
bogdanm	0:9b334a45a8ff	347	*/
bogdanm	0:9b334a45a8ff	348
bogdanm	0:9b334a45a8ff	349	typedef struct { /!< SCT0 Structure /
bogdanm	0:9b334a45a8ff	350	__IO uint32_t CONFIG; /!< SCT configuration register /
bogdanm	0:9b334a45a8ff	351	__IO uint32_t CTRL; /!< SCT control register /
bogdanm	0:9b334a45a8ff	352	__IO uint32_t LIMIT; /!< SCT limit register /
bogdanm	0:9b334a45a8ff	353	__IO uint32_t HALT; /!< SCT halt condition register /
bogdanm	0:9b334a45a8ff	354	__IO uint32_t STOP; /!< SCT stop condition register /
bogdanm	0:9b334a45a8ff	355	__IO uint32_t START; /!< SCT start condition register /
bogdanm	0:9b334a45a8ff	356	__IO uint32_t DITHER; /!< SCT dither condition register /
bogdanm	0:9b334a45a8ff	357	__I uint32_t RESERVED0[9];
bogdanm	0:9b334a45a8ff	358	__IO uint32_t COUNT; /!< SCT counter register /
bogdanm	0:9b334a45a8ff	359	__IO uint32_t STATE; /!< SCT state register /
bogdanm	0:9b334a45a8ff	360	__I uint32_t INPUT; /!< SCT input register /
bogdanm	0:9b334a45a8ff	361	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
bogdanm	0:9b334a45a8ff	362	__IO uint32_t OUTPUT; /!< SCT output register /
bogdanm	0:9b334a45a8ff	363	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
bogdanm	0:9b334a45a8ff	364	__IO uint32_t RES; /!< SCT conflict resolution register /
bogdanm	0:9b334a45a8ff	365	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
bogdanm	0:9b334a45a8ff	366	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
bogdanm	0:9b334a45a8ff	367	__I uint32_t RESERVED1[35];
bogdanm	0:9b334a45a8ff	368	__IO uint32_t EVEN; /!< SCT event enable register /
bogdanm	0:9b334a45a8ff	369	__IO uint32_t EVFLAG; /!< SCT event flag register /
bogdanm	0:9b334a45a8ff	370	__IO uint32_t CONEN; /!< SCT conflict enable register /
bogdanm	0:9b334a45a8ff	371	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
bogdanm	0:9b334a45a8ff	372
bogdanm	0:9b334a45a8ff	373	union {
bogdanm	0:9b334a45a8ff	374	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	375	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	376	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	377	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	378	};
bogdanm	0:9b334a45a8ff	379
bogdanm	0:9b334a45a8ff	380	union {
bogdanm	0:9b334a45a8ff	381	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	382	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	383	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	384	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	385	};
bogdanm	0:9b334a45a8ff	386
bogdanm	0:9b334a45a8ff	387	union {
bogdanm	0:9b334a45a8ff	388	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	389	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	390	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	391	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	392	};
bogdanm	0:9b334a45a8ff	393
bogdanm	0:9b334a45a8ff	394	union {
bogdanm	0:9b334a45a8ff	395	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	396	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	397	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	398	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	399	};
bogdanm	0:9b334a45a8ff	400
bogdanm	0:9b334a45a8ff	401	union {
bogdanm	0:9b334a45a8ff	402	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	403	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	404	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	405	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	406	};
bogdanm	0:9b334a45a8ff	407
bogdanm	0:9b334a45a8ff	408	union {
bogdanm	0:9b334a45a8ff	409	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	410	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	411	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	412	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	413	};
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	union {
bogdanm	0:9b334a45a8ff	416	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	417	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	418	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	419	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	420	};
bogdanm	0:9b334a45a8ff	421
bogdanm	0:9b334a45a8ff	422	union {
bogdanm	0:9b334a45a8ff	423	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	424	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	425	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	426	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	427	};
bogdanm	0:9b334a45a8ff	428
bogdanm	0:9b334a45a8ff	429	union {
bogdanm	0:9b334a45a8ff	430	__I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	431	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	432	__IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	433	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	434	};
bogdanm	0:9b334a45a8ff	435
bogdanm	0:9b334a45a8ff	436	union {
bogdanm	0:9b334a45a8ff	437	__IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	438	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	439	__I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	440	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	441	};
bogdanm	0:9b334a45a8ff	442
bogdanm	0:9b334a45a8ff	443	union {
bogdanm	0:9b334a45a8ff	444	__IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	445	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	446	__I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	447	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	448	};
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	union {
bogdanm	0:9b334a45a8ff	451	__IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	452	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	453	__I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	454	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	455	};
bogdanm	0:9b334a45a8ff	456
bogdanm	0:9b334a45a8ff	457	union {
bogdanm	0:9b334a45a8ff	458	__IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	459	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	460	__I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	461	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	462	};
bogdanm	0:9b334a45a8ff	463
bogdanm	0:9b334a45a8ff	464	union {
bogdanm	0:9b334a45a8ff	465	__IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	466	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	467	__I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	468	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	469	};
bogdanm	0:9b334a45a8ff	470
bogdanm	0:9b334a45a8ff	471	union {
bogdanm	0:9b334a45a8ff	472	__I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	473	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	474	__IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	475	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	476	};
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478	union {
bogdanm	0:9b334a45a8ff	479	__IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
bogdanm	0:9b334a45a8ff	480	to REGMODE15 = 0 */
bogdanm	0:9b334a45a8ff	481	__I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
bogdanm	0:9b334a45a8ff	482	REGMODE15 = 1 */
bogdanm	0:9b334a45a8ff	483	};
bogdanm	0:9b334a45a8ff	484	__IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
bogdanm	0:9b334a45a8ff	485	0 to 5. */
bogdanm	0:9b334a45a8ff	486	__IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
bogdanm	0:9b334a45a8ff	487	0 to 5. */
bogdanm	0:9b334a45a8ff	488	__IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
bogdanm	0:9b334a45a8ff	489	0 to 5. */
bogdanm	0:9b334a45a8ff	490	__IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
bogdanm	0:9b334a45a8ff	491	0 to 5. */
bogdanm	0:9b334a45a8ff	492	__IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
bogdanm	0:9b334a45a8ff	493	0 to 5. */
bogdanm	0:9b334a45a8ff	494	__IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
bogdanm	0:9b334a45a8ff	495	0 to 5. */
bogdanm	0:9b334a45a8ff	496	__I uint32_t RESERVED2[42];
bogdanm	0:9b334a45a8ff	497
bogdanm	0:9b334a45a8ff	498	union {
bogdanm	0:9b334a45a8ff	499	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	500	= 1 */
bogdanm	0:9b334a45a8ff	501	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	502	= 0 */
bogdanm	0:9b334a45a8ff	503	};
bogdanm	0:9b334a45a8ff	504
bogdanm	0:9b334a45a8ff	505	union {
bogdanm	0:9b334a45a8ff	506	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	507	= 0 */
bogdanm	0:9b334a45a8ff	508	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	509	= 1 */
bogdanm	0:9b334a45a8ff	510	};
bogdanm	0:9b334a45a8ff	511
bogdanm	0:9b334a45a8ff	512	union {
bogdanm	0:9b334a45a8ff	513	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	514	= 0 */
bogdanm	0:9b334a45a8ff	515	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	516	= 1 */
bogdanm	0:9b334a45a8ff	517	};
bogdanm	0:9b334a45a8ff	518
bogdanm	0:9b334a45a8ff	519	union {
bogdanm	0:9b334a45a8ff	520	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	521	= 1 */
bogdanm	0:9b334a45a8ff	522	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	523	= 0 */
bogdanm	0:9b334a45a8ff	524	};
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	union {
bogdanm	0:9b334a45a8ff	527	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	528	= 1 */
bogdanm	0:9b334a45a8ff	529	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	530	= 0 */
bogdanm	0:9b334a45a8ff	531	};
bogdanm	0:9b334a45a8ff	532
bogdanm	0:9b334a45a8ff	533	union {
bogdanm	0:9b334a45a8ff	534	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	535	= 1 */
bogdanm	0:9b334a45a8ff	536	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	537	= 0 */
bogdanm	0:9b334a45a8ff	538	};
bogdanm	0:9b334a45a8ff	539
bogdanm	0:9b334a45a8ff	540	union {
bogdanm	0:9b334a45a8ff	541	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	542	= 0 */
bogdanm	0:9b334a45a8ff	543	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	544	= 1 */
bogdanm	0:9b334a45a8ff	545	};
bogdanm	0:9b334a45a8ff	546
bogdanm	0:9b334a45a8ff	547	union {
bogdanm	0:9b334a45a8ff	548	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	549	= 0 */
bogdanm	0:9b334a45a8ff	550	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	551	= 1 */
bogdanm	0:9b334a45a8ff	552	};
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554	union {
bogdanm	0:9b334a45a8ff	555	__IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	556	= 1 */
bogdanm	0:9b334a45a8ff	557	__IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	558	= 0 */
bogdanm	0:9b334a45a8ff	559	};
bogdanm	0:9b334a45a8ff	560
bogdanm	0:9b334a45a8ff	561	union {
bogdanm	0:9b334a45a8ff	562	__IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	563	= 1 */
bogdanm	0:9b334a45a8ff	564	__IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	565	= 0 */
bogdanm	0:9b334a45a8ff	566	};
bogdanm	0:9b334a45a8ff	567
bogdanm	0:9b334a45a8ff	568	union {
bogdanm	0:9b334a45a8ff	569	__IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	570	= 1 */
bogdanm	0:9b334a45a8ff	571	__IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	572	= 0 */
bogdanm	0:9b334a45a8ff	573	};
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	union {
bogdanm	0:9b334a45a8ff	576	__IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	577	= 1 */
bogdanm	0:9b334a45a8ff	578	__IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	579	= 0 */
bogdanm	0:9b334a45a8ff	580	};
bogdanm	0:9b334a45a8ff	581
bogdanm	0:9b334a45a8ff	582	union {
bogdanm	0:9b334a45a8ff	583	__IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	584	= 0 */
bogdanm	0:9b334a45a8ff	585	__IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	586	= 1 */
bogdanm	0:9b334a45a8ff	587	};
bogdanm	0:9b334a45a8ff	588
bogdanm	0:9b334a45a8ff	589	union {
bogdanm	0:9b334a45a8ff	590	__IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	591	= 0 */
bogdanm	0:9b334a45a8ff	592	__IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	593	= 1 */
bogdanm	0:9b334a45a8ff	594	};
bogdanm	0:9b334a45a8ff	595
bogdanm	0:9b334a45a8ff	596	union {
bogdanm	0:9b334a45a8ff	597	__IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	598	= 1 */
bogdanm	0:9b334a45a8ff	599	__IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	600	= 0 */
bogdanm	0:9b334a45a8ff	601	};
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	union {
bogdanm	0:9b334a45a8ff	604	__IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
bogdanm	0:9b334a45a8ff	605	= 1 */
bogdanm	0:9b334a45a8ff	606	__IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
bogdanm	0:9b334a45a8ff	607	= 0 */
bogdanm	0:9b334a45a8ff	608	};
bogdanm	0:9b334a45a8ff	609	__IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
bogdanm	0:9b334a45a8ff	610	registers 0 to 5. */
bogdanm	0:9b334a45a8ff	611	__IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
bogdanm	0:9b334a45a8ff	612	registers 0 to 5. */
bogdanm	0:9b334a45a8ff	613	__IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
bogdanm	0:9b334a45a8ff	614	registers 0 to 5. */
bogdanm	0:9b334a45a8ff	615	__IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
bogdanm	0:9b334a45a8ff	616	registers 0 to 5. */
bogdanm	0:9b334a45a8ff	617	__IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
bogdanm	0:9b334a45a8ff	618	registers 0 to 5. */
bogdanm	0:9b334a45a8ff	619	__IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
bogdanm	0:9b334a45a8ff	620	registers 0 to 5. */
bogdanm	0:9b334a45a8ff	621	__I uint32_t RESERVED3[42];
bogdanm	0:9b334a45a8ff	622	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	623	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	624	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	625	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	626	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	627	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	628	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	629	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	630	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	631	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	632	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	633	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	634	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	635	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	636	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	637	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	638	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	639	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	640	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	641	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	642	__IO uint32_t EV10_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	643	__IO uint32_t EV10_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	644	__IO uint32_t EV11_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	645	__IO uint32_t EV11_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	646	__IO uint32_t EV12_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	647	__IO uint32_t EV12_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	648	__IO uint32_t EV13_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	649	__IO uint32_t EV13_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	650	__IO uint32_t EV14_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	651	__IO uint32_t EV14_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	652	__IO uint32_t EV15_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	653	__IO uint32_t EV15_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	654	__I uint32_t RESERVED4[96];
bogdanm	0:9b334a45a8ff	655	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	656	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	657	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	658	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	659	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	660	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	661	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	662	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	663	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	664	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	665	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	666	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	667	__IO uint32_t OUT6_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	668	__IO uint32_t OUT6_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	669	__IO uint32_t OUT7_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	670	__IO uint32_t OUT7_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	671	__IO uint32_t OUT8_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	672	__IO uint32_t OUT8_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	673	__IO uint32_t OUT9_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	674	__IO uint32_t OUT9_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	675	} LPC_SCT0_Type;
bogdanm	0:9b334a45a8ff	676
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	679	/* ================ SCT2 ================ */
bogdanm	0:9b334a45a8ff	680	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682
bogdanm	0:9b334a45a8ff	683	/**
bogdanm	0:9b334a45a8ff	684	* @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
bogdanm	0:9b334a45a8ff	685	*/
bogdanm	0:9b334a45a8ff	686
bogdanm	0:9b334a45a8ff	687	typedef struct { /!< SCT2 Structure /
bogdanm	0:9b334a45a8ff	688	__IO uint32_t CONFIG; /!< SCT configuration register /
bogdanm	0:9b334a45a8ff	689	__IO uint32_t CTRL; /!< SCT control register /
bogdanm	0:9b334a45a8ff	690	__IO uint32_t LIMIT; /!< SCT limit register /
bogdanm	0:9b334a45a8ff	691	__IO uint32_t HALT; /!< SCT halt condition register /
bogdanm	0:9b334a45a8ff	692	__IO uint32_t STOP; /!< SCT stop condition register /
bogdanm	0:9b334a45a8ff	693	__IO uint32_t START; /!< SCT start condition register /
bogdanm	0:9b334a45a8ff	694	__I uint32_t RESERVED0[10];
bogdanm	0:9b334a45a8ff	695	__IO uint32_t COUNT; /!< SCT counter register /
bogdanm	0:9b334a45a8ff	696	__IO uint32_t STATE; /!< SCT state register /
bogdanm	0:9b334a45a8ff	697	__I uint32_t INPUT; /!< SCT input register /
bogdanm	0:9b334a45a8ff	698	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
bogdanm	0:9b334a45a8ff	699	__IO uint32_t OUTPUT; /!< SCT output register /
bogdanm	0:9b334a45a8ff	700	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
bogdanm	0:9b334a45a8ff	701	__IO uint32_t RES; /!< SCT conflict resolution register /
bogdanm	0:9b334a45a8ff	702	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
bogdanm	0:9b334a45a8ff	703	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
bogdanm	0:9b334a45a8ff	704	__I uint32_t RESERVED1[35];
bogdanm	0:9b334a45a8ff	705	__IO uint32_t EVEN; /!< SCT event enable register /
bogdanm	0:9b334a45a8ff	706	__IO uint32_t EVFLAG; /!< SCT event flag register /
bogdanm	0:9b334a45a8ff	707	__IO uint32_t CONEN; /!< SCT conflict enable register /
bogdanm	0:9b334a45a8ff	708	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
bogdanm	0:9b334a45a8ff	709
bogdanm	0:9b334a45a8ff	710	union {
bogdanm	0:9b334a45a8ff	711	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
bogdanm	0:9b334a45a8ff	712	= 1 */
bogdanm	0:9b334a45a8ff	713	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
bogdanm	0:9b334a45a8ff	714	REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	715	};
bogdanm	0:9b334a45a8ff	716
bogdanm	0:9b334a45a8ff	717	union {
bogdanm	0:9b334a45a8ff	718	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
bogdanm	0:9b334a45a8ff	719	= 1 */
bogdanm	0:9b334a45a8ff	720	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
bogdanm	0:9b334a45a8ff	721	REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	722	};
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	union {
bogdanm	0:9b334a45a8ff	725	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
bogdanm	0:9b334a45a8ff	726	= 1 */
bogdanm	0:9b334a45a8ff	727	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
bogdanm	0:9b334a45a8ff	728	REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	729	};
bogdanm	0:9b334a45a8ff	730
bogdanm	0:9b334a45a8ff	731	union {
bogdanm	0:9b334a45a8ff	732	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
bogdanm	0:9b334a45a8ff	733	REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	734	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
bogdanm	0:9b334a45a8ff	735	= 1 */
bogdanm	0:9b334a45a8ff	736	};
bogdanm	0:9b334a45a8ff	737
bogdanm	0:9b334a45a8ff	738	union {
bogdanm	0:9b334a45a8ff	739	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
bogdanm	0:9b334a45a8ff	740	= 1 */
bogdanm	0:9b334a45a8ff	741	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
bogdanm	0:9b334a45a8ff	742	REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	743	};
bogdanm	0:9b334a45a8ff	744
bogdanm	0:9b334a45a8ff	745	union {
bogdanm	0:9b334a45a8ff	746	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
bogdanm	0:9b334a45a8ff	747	REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	748	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
bogdanm	0:9b334a45a8ff	749	= 1 */
bogdanm	0:9b334a45a8ff	750	};
bogdanm	0:9b334a45a8ff	751
bogdanm	0:9b334a45a8ff	752	union {
bogdanm	0:9b334a45a8ff	753	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
bogdanm	0:9b334a45a8ff	754	= 1 */
bogdanm	0:9b334a45a8ff	755	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
bogdanm	0:9b334a45a8ff	756	REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	757	};
bogdanm	0:9b334a45a8ff	758
bogdanm	0:9b334a45a8ff	759	union {
bogdanm	0:9b334a45a8ff	760	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
bogdanm	0:9b334a45a8ff	761	= 1 */
bogdanm	0:9b334a45a8ff	762	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
bogdanm	0:9b334a45a8ff	763	REGMODE7 = 0 */
bogdanm	0:9b334a45a8ff	764	};
bogdanm	0:9b334a45a8ff	765	__I uint32_t RESERVED2[56];
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	union {
bogdanm	0:9b334a45a8ff	768	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
bogdanm	0:9b334a45a8ff	769	= 1 */
bogdanm	0:9b334a45a8ff	770	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
bogdanm	0:9b334a45a8ff	771	= 0 */
bogdanm	0:9b334a45a8ff	772	};
bogdanm	0:9b334a45a8ff	773
bogdanm	0:9b334a45a8ff	774	union {
bogdanm	0:9b334a45a8ff	775	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
bogdanm	0:9b334a45a8ff	776	= 1 */
bogdanm	0:9b334a45a8ff	777	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
bogdanm	0:9b334a45a8ff	778	= 0 */
bogdanm	0:9b334a45a8ff	779	};
bogdanm	0:9b334a45a8ff	780
bogdanm	0:9b334a45a8ff	781	union {
bogdanm	0:9b334a45a8ff	782	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
bogdanm	0:9b334a45a8ff	783	= 1 */
bogdanm	0:9b334a45a8ff	784	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
bogdanm	0:9b334a45a8ff	785	= 0 */
bogdanm	0:9b334a45a8ff	786	};
bogdanm	0:9b334a45a8ff	787
bogdanm	0:9b334a45a8ff	788	union {
bogdanm	0:9b334a45a8ff	789	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
bogdanm	0:9b334a45a8ff	790	= 0 */
bogdanm	0:9b334a45a8ff	791	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
bogdanm	0:9b334a45a8ff	792	= 1 */
bogdanm	0:9b334a45a8ff	793	};
bogdanm	0:9b334a45a8ff	794
bogdanm	0:9b334a45a8ff	795	union {
bogdanm	0:9b334a45a8ff	796	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
bogdanm	0:9b334a45a8ff	797	= 1 */
bogdanm	0:9b334a45a8ff	798	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
bogdanm	0:9b334a45a8ff	799	= 0 */
bogdanm	0:9b334a45a8ff	800	};
bogdanm	0:9b334a45a8ff	801
bogdanm	0:9b334a45a8ff	802	union {
bogdanm	0:9b334a45a8ff	803	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
bogdanm	0:9b334a45a8ff	804	= 0 */
bogdanm	0:9b334a45a8ff	805	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
bogdanm	0:9b334a45a8ff	806	= 1 */
bogdanm	0:9b334a45a8ff	807	};
bogdanm	0:9b334a45a8ff	808
bogdanm	0:9b334a45a8ff	809	union {
bogdanm	0:9b334a45a8ff	810	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
bogdanm	0:9b334a45a8ff	811	= 1 */
bogdanm	0:9b334a45a8ff	812	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
bogdanm	0:9b334a45a8ff	813	= 0 */
bogdanm	0:9b334a45a8ff	814	};
bogdanm	0:9b334a45a8ff	815
bogdanm	0:9b334a45a8ff	816	union {
bogdanm	0:9b334a45a8ff	817	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
bogdanm	0:9b334a45a8ff	818	= 1 */
bogdanm	0:9b334a45a8ff	819	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
bogdanm	0:9b334a45a8ff	820	= 0 */
bogdanm	0:9b334a45a8ff	821	};
bogdanm	0:9b334a45a8ff	822	__I uint32_t RESERVED3[56];
bogdanm	0:9b334a45a8ff	823	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	824	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	825	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	826	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	827	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	828	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	829	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	830	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	831	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	832	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	833	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	834	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	835	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	836	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	837	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	838	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	839	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	840	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	841	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
bogdanm	0:9b334a45a8ff	842	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
bogdanm	0:9b334a45a8ff	843	__I uint32_t RESERVED4[108];
bogdanm	0:9b334a45a8ff	844	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	845	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	846	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	847	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	848	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	849	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	850	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	851	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	852	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	853	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	854	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
bogdanm	0:9b334a45a8ff	855	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
bogdanm	0:9b334a45a8ff	856	} LPC_SCT2_Type;
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	860	/* ================ ADC0 ================ */
bogdanm	0:9b334a45a8ff	861	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	862
bogdanm	0:9b334a45a8ff	863
bogdanm	0:9b334a45a8ff	864	/**
bogdanm	0:9b334a45a8ff	865	* @brief 12-bit ADC controller ADC0/1 (ADC0)
bogdanm	0:9b334a45a8ff	866	*/
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	typedef struct { /!< ADC0 Structure /
bogdanm	0:9b334a45a8ff	869	__IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
bogdanm	0:9b334a45a8ff	870	bits for each sequence and the A/D power-down bit. */
bogdanm	0:9b334a45a8ff	871	__IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
bogdanm	0:9b334a45a8ff	872	internal source for various channels */
bogdanm	0:9b334a45a8ff	873	__IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
bogdanm	0:9b334a45a8ff	874	and channel selection for conversion sequence-A. Also specifies
bogdanm	0:9b334a45a8ff	875	interrupt mode for sequence-A. */
bogdanm	0:9b334a45a8ff	876	__IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
bogdanm	0:9b334a45a8ff	877	and channel selection for conversion sequence-B. Also specifies
bogdanm	0:9b334a45a8ff	878	interrupt mode for sequence-B. */
bogdanm	0:9b334a45a8ff	879	__IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
bogdanm	0:9b334a45a8ff	880	the result of the most recent A/D conversion performed under
bogdanm	0:9b334a45a8ff	881	sequence-A */
bogdanm	0:9b334a45a8ff	882	__IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
bogdanm	0:9b334a45a8ff	883	the result of the most recent A/D conversion performed under
bogdanm	0:9b334a45a8ff	884	sequence-B */
bogdanm	0:9b334a45a8ff	885	__I uint32_t RESERVED0[2];
bogdanm	0:9b334a45a8ff	886	__I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
bogdanm	0:9b334a45a8ff	887	of the most recent conversion completed on channel 0. */
bogdanm	0:9b334a45a8ff	888	__IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
bogdanm	0:9b334a45a8ff	889	level for automatic threshold comparison for any channels linked
bogdanm	0:9b334a45a8ff	890	to threshold pair 0. */
bogdanm	0:9b334a45a8ff	891	__IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
bogdanm	0:9b334a45a8ff	892	level for automatic threshold comparison for any channels linked
bogdanm	0:9b334a45a8ff	893	to threshold pair 1. */
bogdanm	0:9b334a45a8ff	894	__IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
bogdanm	0:9b334a45a8ff	895	level for automatic threshold comparison for any channels linked
bogdanm	0:9b334a45a8ff	896	to threshold pair 0. */
bogdanm	0:9b334a45a8ff	897	__IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
bogdanm	0:9b334a45a8ff	898	level for automatic threshold comparison for any channels linked
bogdanm	0:9b334a45a8ff	899	to threshold pair 1. */
bogdanm	0:9b334a45a8ff	900	__I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
bogdanm	0:9b334a45a8ff	901	threshold compare registers are to be used for each channel */
bogdanm	0:9b334a45a8ff	902	__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
bogdanm	0:9b334a45a8ff	903	bits that enable the sequence-A, sequence-B, threshold compare
bogdanm	0:9b334a45a8ff	904	and data overrun interrupts to be generated. */
bogdanm	0:9b334a45a8ff	905	__I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
bogdanm	0:9b334a45a8ff	906	and the individual component overrun and threshold-compare flags.
bogdanm	0:9b334a45a8ff	907	(The overrun bits replicate information stored in the result
bogdanm	0:9b334a45a8ff	908	registers). */
bogdanm	0:9b334a45a8ff	909	__IO uint32_t TRM; /!< ADC trim register. /
bogdanm	0:9b334a45a8ff	910	} LPC_ADC0_Type;
bogdanm	0:9b334a45a8ff	911
bogdanm	0:9b334a45a8ff	912
bogdanm	0:9b334a45a8ff	913	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	914	/* ================ DAC ================ */
bogdanm	0:9b334a45a8ff	915	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	/**
bogdanm	0:9b334a45a8ff	919	* @brief 12-bit DAC Modification (DAC)
bogdanm	0:9b334a45a8ff	920	*/
bogdanm	0:9b334a45a8ff	921
bogdanm	0:9b334a45a8ff	922	typedef struct { /!< DAC Structure /
bogdanm	0:9b334a45a8ff	923	__IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
bogdanm	0:9b334a45a8ff	924	value to be converted to analog. */
bogdanm	0:9b334a45a8ff	925	__IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
bogdanm	0:9b334a45a8ff	926	DAC operation and the interrupt/dma request flag. */
bogdanm	0:9b334a45a8ff	927	__IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
bogdanm	0:9b334a45a8ff	928	value for the internal DAC DMA/Interrupt timer. */
bogdanm	0:9b334a45a8ff	929	} LPC_DAC_Type;
bogdanm	0:9b334a45a8ff	930
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	933	/* ================ ACMP ================ */
bogdanm	0:9b334a45a8ff	934	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	935
bogdanm	0:9b334a45a8ff	936
bogdanm	0:9b334a45a8ff	937	/**
bogdanm	0:9b334a45a8ff	938	* @brief Analog comparators ACMP0/1/2/3 (ACMP)
bogdanm	0:9b334a45a8ff	939	*/
bogdanm	0:9b334a45a8ff	940
bogdanm	0:9b334a45a8ff	941	typedef struct { /!< ACMP Structure /
bogdanm	0:9b334a45a8ff	942	__IO uint32_t CTRL; /!< Comparator block control register /
bogdanm	0:9b334a45a8ff	943	__IO uint32_t CMP0; /!< Comparator 0 source control /
bogdanm	0:9b334a45a8ff	944	__IO uint32_t CMPFILTR0; /!< Comparator 0 pin filter set-up /
bogdanm	0:9b334a45a8ff	945	__IO uint32_t CMP1; /!< Comparator 1 source control /
bogdanm	0:9b334a45a8ff	946	__IO uint32_t CMPFILTR1; /!< Comparator 0 pin filter set-up /
bogdanm	0:9b334a45a8ff	947	__IO uint32_t CMP2; /!< Comparator 2 source control /
bogdanm	0:9b334a45a8ff	948	__IO uint32_t CMPFILTR2; /!< Comparator 0 pin filter set-up /
bogdanm	0:9b334a45a8ff	949	__IO uint32_t CMP3; /!< Comparator 3 source control /
bogdanm	0:9b334a45a8ff	950	__IO uint32_t CMPFILTR3; /!< Comparator 0 pin filter set-up /
bogdanm	0:9b334a45a8ff	951	} LPC_ACMP_Type;
bogdanm	0:9b334a45a8ff	952
bogdanm	0:9b334a45a8ff	953
bogdanm	0:9b334a45a8ff	954	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	955	/* ================ INMUX ================ */
bogdanm	0:9b334a45a8ff	956	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	/**
bogdanm	0:9b334a45a8ff	960	* @brief Input multiplexing (INMUX) (INMUX)
bogdanm	0:9b334a45a8ff	961	*/
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	typedef struct { /!< INMUX Structure /
bogdanm	0:9b334a45a8ff	964	__IO uint32_t SCT0_INMUX[7]; /!< Pinmux register for SCT0 input 0 /
bogdanm	0:9b334a45a8ff	965	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	966	__IO uint32_t SCT1_INMUX[7]; /!< Pinmux register for SCT1 input 0 /
bogdanm	0:9b334a45a8ff	967	__I uint32_t RESERVED1;
bogdanm	0:9b334a45a8ff	968	__IO uint32_t SCT2_INMUX[3]; /!< Pinmux register for SCT2 input 0 /
bogdanm	0:9b334a45a8ff	969	__I uint32_t RESERVED2[5];
bogdanm	0:9b334a45a8ff	970	__IO uint32_t SCT3_INMUX[3]; /!< Pinmux register for SCT3 input 0 /
bogdanm	0:9b334a45a8ff	971	__I uint32_t RESERVED3[21];
bogdanm	0:9b334a45a8ff	972	__IO uint32_t PINTSEL[8]; /!< Pin interrupt select register 0 /
bogdanm	0:9b334a45a8ff	973	__IO uint32_t DMA_ITRIG_INMUX[18]; /!< Trigger input for DMA channel 0 select register. /
bogdanm	0:9b334a45a8ff	974	__I uint32_t RESERVED4[14];
bogdanm	0:9b334a45a8ff	975	__IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
bogdanm	0:9b334a45a8ff	976	clock */
bogdanm	0:9b334a45a8ff	977	__IO uint32_t FREQMEAS_TARGET; /!< Clock selection for frequency measurement function target clock /
bogdanm	0:9b334a45a8ff	978	} LPC_INMUX_Type;
bogdanm	0:9b334a45a8ff	979
bogdanm	0:9b334a45a8ff	980
bogdanm	0:9b334a45a8ff	981	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	982	/* ================ RTC ================ */
bogdanm	0:9b334a45a8ff	983	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	984
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	/**
bogdanm	0:9b334a45a8ff	987	* @brief Real-Time Clock (RTC) (RTC)
bogdanm	0:9b334a45a8ff	988	*/
bogdanm	0:9b334a45a8ff	989
bogdanm	0:9b334a45a8ff	990	typedef struct { /!< RTC Structure /
bogdanm	0:9b334a45a8ff	991	__IO uint32_t CTRL; /!< RTC control register /
bogdanm	0:9b334a45a8ff	992	__IO uint32_t MATCH; /!< RTC match register /
bogdanm	0:9b334a45a8ff	993	__IO uint32_t COUNT; /!< RTC counter register /
bogdanm	0:9b334a45a8ff	994	__IO uint32_t WAKE; /!< RTC high-resolution/wake-up timer control register /
bogdanm	0:9b334a45a8ff	995	} LPC_RTC_Type;
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	999	/* ================ WWDT ================ */
bogdanm	0:9b334a45a8ff	1000	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1001
bogdanm	0:9b334a45a8ff	1002
bogdanm	0:9b334a45a8ff	1003	/**
bogdanm	0:9b334a45a8ff	1004	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
bogdanm	0:9b334a45a8ff	1005	*/
bogdanm	0:9b334a45a8ff	1006
bogdanm	0:9b334a45a8ff	1007	typedef struct { /!< WWDT Structure /
bogdanm	0:9b334a45a8ff	1008	__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
bogdanm	0:9b334a45a8ff	1009	and status of the Watchdog Timer. */
bogdanm	0:9b334a45a8ff	1010	__IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
bogdanm	0:9b334a45a8ff	1011	the time-out value. */
bogdanm	0:9b334a45a8ff	1012	__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
bogdanm	0:9b334a45a8ff	1013	to this register reloads the Watchdog timer with the value contained
bogdanm	0:9b334a45a8ff	1014	in WDTC. */
bogdanm	0:9b334a45a8ff	1015	__I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
bogdanm	0:9b334a45a8ff	1016	the current value of the Watchdog timer. */
bogdanm	0:9b334a45a8ff	1017	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	1018	__IO uint32_t WARNINT; /!< Watchdog Warning Interrupt compare value. /
bogdanm	0:9b334a45a8ff	1019	__IO uint32_t WINDOW; /!< Watchdog Window compare value. /
bogdanm	0:9b334a45a8ff	1020	} LPC_WWDT_Type;
bogdanm	0:9b334a45a8ff	1021
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1024	/* ================ SWM ================ */
bogdanm	0:9b334a45a8ff	1025	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1026
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	/**
bogdanm	0:9b334a45a8ff	1029	* @brief Switch Matrix (SWM) (SWM)
bogdanm	0:9b334a45a8ff	1030	*/
bogdanm	0:9b334a45a8ff	1031
bogdanm	0:9b334a45a8ff	1032	typedef struct { /!< SWM Structure /
bogdanm	0:9b334a45a8ff	1033	union {
bogdanm	0:9b334a45a8ff	1034	__IO uint32_t PINASSIGN[16];
bogdanm	0:9b334a45a8ff	1035	struct {
bogdanm	0:9b334a45a8ff	1036	__IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
bogdanm	0:9b334a45a8ff	1037	U0_RTS, U0_CTS. */
bogdanm	0:9b334a45a8ff	1038	__IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
bogdanm	0:9b334a45a8ff	1039	U1_RXD, U1_RTS. */
bogdanm	0:9b334a45a8ff	1040	__IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
bogdanm	0:9b334a45a8ff	1041	U2_TXD, U2_RXD. */
bogdanm	0:9b334a45a8ff	1042	__IO uint32_t PINASSIGN3; /!< Pin assign register 3. Assign movable function . /
bogdanm	0:9b334a45a8ff	1043	__IO uint32_t PINASSIGN4; /!< Pin assign register 4. Assign movable functions /
bogdanm	0:9b334a45a8ff	1044	__IO uint32_t PINASSIGN5; /!< Pin assign register 5. Assign movable functions /
bogdanm	0:9b334a45a8ff	1045	__IO uint32_t PINASSIGN6; /!< Pin assign register 6. Assign movable functions /
bogdanm	0:9b334a45a8ff	1046	__IO uint32_t PINASSIGN7; /!< Pin assign register 7. Assign movable functions /
bogdanm	0:9b334a45a8ff	1047	__IO uint32_t PINASSIGN8; /!< Pin assign register 8. Assign movable functions /
bogdanm	0:9b334a45a8ff	1048	__IO uint32_t PINASSIGN9; /!< Pin assign register 9. Assign movable functions /
bogdanm	0:9b334a45a8ff	1049	__IO uint32_t PINASSIGN10; /!< Pin assign register 10. Assign movable functions /
bogdanm	0:9b334a45a8ff	1050	__IO uint32_t PINASSIGN11; /!< Pin assign register 11. Assign movable functions /
bogdanm	0:9b334a45a8ff	1051	__IO uint32_t PINASSIGN12; /!< Pin assign register 12. Assign movable functions /
bogdanm	0:9b334a45a8ff	1052	__IO uint32_t PINASSIGN13; /!< Pin assign register 13. Assign movable functions /
bogdanm	0:9b334a45a8ff	1053	__IO uint32_t PINASSIGN14; /!< Pin assign register 14. Assign movable functions /
bogdanm	0:9b334a45a8ff	1054	__IO uint32_t PINASSIGN15; /!< Pin assign register 15. Assign movable functions /
bogdanm	0:9b334a45a8ff	1055	};
bogdanm	0:9b334a45a8ff	1056	};
bogdanm	0:9b334a45a8ff	1057	__I uint32_t RESERVED0[96];
bogdanm	0:9b334a45a8ff	1058	__IO uint32_t PINENABLE0; /!< Pin enable register 0. Enables fixed-pin functions /
bogdanm	0:9b334a45a8ff	1059	__IO uint32_t PINENABLE1; /!< Pin enable register 0. Enables fixed-pin functions /
bogdanm	0:9b334a45a8ff	1060	} LPC_SWM_Type;
bogdanm	0:9b334a45a8ff	1061
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1064	/* ================ PMU ================ */
bogdanm	0:9b334a45a8ff	1065	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1066
bogdanm	0:9b334a45a8ff	1067
bogdanm	0:9b334a45a8ff	1068	/**
bogdanm	0:9b334a45a8ff	1069	* @brief Power Management Unit (PMU) (PMU)
bogdanm	0:9b334a45a8ff	1070	*/
bogdanm	0:9b334a45a8ff	1071
bogdanm	0:9b334a45a8ff	1072	typedef struct { /!< PMU Structure /
bogdanm	0:9b334a45a8ff	1073	__IO uint32_t PCON; /!< Power control register /
bogdanm	0:9b334a45a8ff	1074	__IO uint32_t GPREG0; /!< General purpose register 0 /
bogdanm	0:9b334a45a8ff	1075	__IO uint32_t GPREG1; /!< General purpose register 0 /
bogdanm	0:9b334a45a8ff	1076	__IO uint32_t GPREG2; /!< General purpose register 0 /
bogdanm	0:9b334a45a8ff	1077	__IO uint32_t GPREG3; /!< General purpose register 0 /
bogdanm	0:9b334a45a8ff	1078	__IO uint32_t DPDCTRL; /!< Deep power-down control register /
bogdanm	0:9b334a45a8ff	1079	} LPC_PMU_Type;
bogdanm	0:9b334a45a8ff	1080
bogdanm	0:9b334a45a8ff	1081
bogdanm	0:9b334a45a8ff	1082	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1083	/* ================ USART0 ================ */
bogdanm	0:9b334a45a8ff	1084	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1085
bogdanm	0:9b334a45a8ff	1086
bogdanm	0:9b334a45a8ff	1087	/**
bogdanm	0:9b334a45a8ff	1088	* @brief USART0 (USART0)
bogdanm	0:9b334a45a8ff	1089	*/
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	typedef struct { /!< USART0 Structure /
bogdanm	0:9b334a45a8ff	1092	__IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
bogdanm	0:9b334a45a8ff	1093	that typically are not changed during operation. */
bogdanm	0:9b334a45a8ff	1094	__IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
bogdanm	0:9b334a45a8ff	1095	likely to change during operation. */
bogdanm	0:9b334a45a8ff	1096	__IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
bogdanm	0:9b334a45a8ff	1097	here. Writing ones clears some bits in the register. Some bits
bogdanm	0:9b334a45a8ff	1098	can be cleared by writing a 1 to them. */
bogdanm	0:9b334a45a8ff	1099	__IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
bogdanm	0:9b334a45a8ff	1100	interrupt enable bit for each potential USART interrupt. A complete
bogdanm	0:9b334a45a8ff	1101	value may be read from this register. Writing a 1 to any implemented
bogdanm	0:9b334a45a8ff	1102	bit position causes that bit to be set. */
bogdanm	0:9b334a45a8ff	1103	__O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
bogdanm	0:9b334a45a8ff	1104	of bits in the INTENSET register. Writing a 1 to any implemented
bogdanm	0:9b334a45a8ff	1105	bit position causes the corresponding bit to be cleared. */
bogdanm	0:9b334a45a8ff	1106	__I uint32_t RXDATA; /!< Receiver Data register. Contains the last character received. /
bogdanm	0:9b334a45a8ff	1107	__I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
bogdanm	0:9b334a45a8ff	1108	received with the current USART receive status. Allows DMA or
bogdanm	0:9b334a45a8ff	1109	software to recover incoming data and status together. */
bogdanm	0:9b334a45a8ff	1110	__IO uint32_t TXDATA; /!< Transmit Data register. Data to be transmitted is written here. /
bogdanm	0:9b334a45a8ff	1111	__IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
bogdanm	0:9b334a45a8ff	1112	value. */
bogdanm	0:9b334a45a8ff	1113	__I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
bogdanm	0:9b334a45a8ff	1114	enabled. */
bogdanm	0:9b334a45a8ff	1115	} LPC_USART0_Type;
bogdanm	0:9b334a45a8ff	1116
bogdanm	0:9b334a45a8ff	1117
bogdanm	0:9b334a45a8ff	1118	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1119	/* ================ SPI0 ================ */
bogdanm	0:9b334a45a8ff	1120	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1121
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	/**
bogdanm	0:9b334a45a8ff	1124	* @brief SPI0 (SPI0)
bogdanm	0:9b334a45a8ff	1125	*/
bogdanm	0:9b334a45a8ff	1126
bogdanm	0:9b334a45a8ff	1127	typedef struct { /!< SPI0 Structure /
bogdanm	0:9b334a45a8ff	1128	__IO uint32_t CFG; /!< SPI Configuration register /
bogdanm	0:9b334a45a8ff	1129	__IO uint32_t DLY; /!< SPI Delay register /
bogdanm	0:9b334a45a8ff	1130	__IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
bogdanm	0:9b334a45a8ff	1131	to that bit position */
bogdanm	0:9b334a45a8ff	1132	__IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
bogdanm	0:9b334a45a8ff	1133	from this register. Writing a 1 to any implemented bit position
bogdanm	0:9b334a45a8ff	1134	causes that bit to be set. */
bogdanm	0:9b334a45a8ff	1135	__O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
bogdanm	0:9b334a45a8ff	1136	position causes the corresponding bit in INTENSET to be cleared. */
bogdanm	0:9b334a45a8ff	1137	__I uint32_t RXDAT; /!< SPI Receive Data /
bogdanm	0:9b334a45a8ff	1138	__IO uint32_t TXDATCTL; /!< SPI Transmit Data with Control /
bogdanm	0:9b334a45a8ff	1139	__IO uint32_t TXDAT; /!< SPI Transmit Data with Control /
bogdanm	0:9b334a45a8ff	1140	__IO uint32_t TXCTL; /!< SPI Transmit Control /
bogdanm	0:9b334a45a8ff	1141	__IO uint32_t DIV; /!< SPI clock Divider /
bogdanm	0:9b334a45a8ff	1142	__I uint32_t INTSTAT; /!< SPI Interrupt Status /
bogdanm	0:9b334a45a8ff	1143	} LPC_SPI0_Type;
bogdanm	0:9b334a45a8ff	1144
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1147	/* ================ I2C0 ================ */
bogdanm	0:9b334a45a8ff	1148	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1149
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	/**
bogdanm	0:9b334a45a8ff	1152	* @brief I2C-bus interface (I2C0)
bogdanm	0:9b334a45a8ff	1153	*/
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	typedef struct { /!< I2C0 Structure /
bogdanm	0:9b334a45a8ff	1156	__IO uint32_t CFG; /!< Configuration for shared functions. /
bogdanm	0:9b334a45a8ff	1157	__IO uint32_t STAT; /!< Status register for Master, Slave, and Monitor functions. /
bogdanm	0:9b334a45a8ff	1158	__IO uint32_t INTENSET; /!< Interrupt Enable Set and read register. /
bogdanm	0:9b334a45a8ff	1159	__O uint32_t INTENCLR; /!< Interrupt Enable Clear register. /
bogdanm	0:9b334a45a8ff	1160	__IO uint32_t TIMEOUT; /!< Time-out value register. /
bogdanm	0:9b334a45a8ff	1161	__IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
bogdanm	0:9b334a45a8ff	1162	what time increments are used for the MSTTIME and SLVTIME registers. */
bogdanm	0:9b334a45a8ff	1163	__I uint32_t INTSTAT; /!< Interrupt Status register for Master, Slave, and Monitor functions. /
bogdanm	0:9b334a45a8ff	1164	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	1165	__IO uint32_t MSTCTL; /!< Master control register. /
bogdanm	0:9b334a45a8ff	1166	__IO uint32_t MSTTIME; /!< Master timing configuration. /
bogdanm	0:9b334a45a8ff	1167	__IO uint32_t MSTDAT; /!< Combined Master receiver and transmitter data register. /
bogdanm	0:9b334a45a8ff	1168	__I uint32_t RESERVED1[5];
bogdanm	0:9b334a45a8ff	1169	__IO uint32_t SLVCTL; /!< Slave control register. /
bogdanm	0:9b334a45a8ff	1170	__IO uint32_t SLVDAT; /!< Combined Slave receiver and transmitter data register. /
bogdanm	0:9b334a45a8ff	1171	__IO uint32_t SLVADR0; /!< Slave address 0. /
bogdanm	0:9b334a45a8ff	1172	__IO uint32_t SLVADR1; /!< Slave address 0. /
bogdanm	0:9b334a45a8ff	1173	__IO uint32_t SLVADR2; /!< Slave address 0. /
bogdanm	0:9b334a45a8ff	1174	__IO uint32_t SLVADR3; /!< Slave address 0. /
bogdanm	0:9b334a45a8ff	1175	__IO uint32_t SLVQUAL0; /!< Slave Qualification for address 0. /
bogdanm	0:9b334a45a8ff	1176	__I uint32_t RESERVED2[9];
bogdanm	0:9b334a45a8ff	1177	__I uint32_t MONRXDAT; /!< Monitor receiver data register. /
bogdanm	0:9b334a45a8ff	1178	} LPC_I2C0_Type;
bogdanm	0:9b334a45a8ff	1179
bogdanm	0:9b334a45a8ff	1180
bogdanm	0:9b334a45a8ff	1181	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1182	/* ================ QEI ================ */
bogdanm	0:9b334a45a8ff	1183	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185
bogdanm	0:9b334a45a8ff	1186	/**
bogdanm	0:9b334a45a8ff	1187	* @brief Quadrature Encoder Interface (QEI) (QEI)
bogdanm	0:9b334a45a8ff	1188	*/
bogdanm	0:9b334a45a8ff	1189
bogdanm	0:9b334a45a8ff	1190	typedef struct { /!< QEI Structure /
bogdanm	0:9b334a45a8ff	1191	__O uint32_t CON; /!< Control register /
bogdanm	0:9b334a45a8ff	1192	__I uint32_t STAT; /!< Encoder status register /
bogdanm	0:9b334a45a8ff	1193	__IO uint32_t CONF; /!< Configuration register /
bogdanm	0:9b334a45a8ff	1194	__I uint32_t POS; /!< Position register /
bogdanm	0:9b334a45a8ff	1195	__IO uint32_t MAXPOS; /!< Maximum position register /
bogdanm	0:9b334a45a8ff	1196	__IO uint32_t CMPOS0; /!< position compare register 0 /
bogdanm	0:9b334a45a8ff	1197	__IO uint32_t CMPOS1; /!< position compare register 1 /
bogdanm	0:9b334a45a8ff	1198	__IO uint32_t CMPOS2; /!< position compare register 2 /
bogdanm	0:9b334a45a8ff	1199	__I uint32_t INXCNT; /!< Index count register /
bogdanm	0:9b334a45a8ff	1200	__IO uint32_t INXCMP0; /!< Index compare register 0 /
bogdanm	0:9b334a45a8ff	1201	__IO uint32_t LOAD; /!< Velocity timer reload register /
bogdanm	0:9b334a45a8ff	1202	__I uint32_t TIME; /!< Velocity timer register /
bogdanm	0:9b334a45a8ff	1203	__I uint32_t VEL; /!< Velocity counter register /
bogdanm	0:9b334a45a8ff	1204	__I uint32_t CAP; /!< Velocity capture register /
bogdanm	0:9b334a45a8ff	1205	__IO uint32_t VELCOMP; /!< Velocity compare register /
bogdanm	0:9b334a45a8ff	1206	__IO uint32_t FILTERPHA; /!< Digital filter register on input phase A (QEI_A) /
bogdanm	0:9b334a45a8ff	1207	__IO uint32_t FILTERPHB; /!< Digital filter register on input phase B (QEI_B) /
bogdanm	0:9b334a45a8ff	1208	__IO uint32_t FILTERINX; /!< Digital filter register on input index (QEI_IDX) /
bogdanm	0:9b334a45a8ff	1209	__IO uint32_t WINDOW; /!< Index acceptance window register /
bogdanm	0:9b334a45a8ff	1210	__IO uint32_t INXCMP1; /!< Index compare register 1 /
bogdanm	0:9b334a45a8ff	1211	__IO uint32_t INXCMP2; /!< Index compare register 2 /
bogdanm	0:9b334a45a8ff	1212	__I uint32_t RESERVED0[993];
bogdanm	0:9b334a45a8ff	1213	__O uint32_t IEC; /!< Interrupt enable clear register /
bogdanm	0:9b334a45a8ff	1214	__O uint32_t IES; /!< Interrupt enable set register /
bogdanm	0:9b334a45a8ff	1215	__I uint32_t INTSTAT; /!< Interrupt status register /
bogdanm	0:9b334a45a8ff	1216	__O uint32_t IE; /!< Interrupt enable clear register /
bogdanm	0:9b334a45a8ff	1217	__O uint32_t CLR; /!< Interrupt status clear register /
bogdanm	0:9b334a45a8ff	1218	__O uint32_t SET; /!< Interrupt status set register /
bogdanm	0:9b334a45a8ff	1219	} LPC_QEI_Type;
bogdanm	0:9b334a45a8ff	1220
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1223	/* ================ SYSCON ================ */
bogdanm	0:9b334a45a8ff	1224	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1225
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227	/**
bogdanm	0:9b334a45a8ff	1228	* @brief System configuration (SYSCON) (SYSCON)
bogdanm	0:9b334a45a8ff	1229	*/
bogdanm	0:9b334a45a8ff	1230
bogdanm	0:9b334a45a8ff	1231	typedef struct { /!< SYSCON Structure /
bogdanm	0:9b334a45a8ff	1232	__IO uint32_t SYSMEMREMAP; /!< System memory remap /
bogdanm	0:9b334a45a8ff	1233	__I uint32_t RESERVED0[4];
bogdanm	0:9b334a45a8ff	1234	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration /
bogdanm	0:9b334a45a8ff	1235	__I uint32_t RESERVED1;
bogdanm	0:9b334a45a8ff	1236	__IO uint32_t NMISRC; /!< NMI Source Control /
bogdanm	0:9b334a45a8ff	1237	__I uint32_t RESERVED2[8];
bogdanm	0:9b334a45a8ff	1238	__IO uint32_t SYSRSTSTAT; /!< System reset status register /
bogdanm	0:9b334a45a8ff	1239	__IO uint32_t PRESETCTRL0; /!< Peripheral reset control 0 /
bogdanm	0:9b334a45a8ff	1240	__IO uint32_t PRESETCTRL1; /!< Peripheral reset control 1 /
bogdanm	0:9b334a45a8ff	1241	__I uint32_t PIOPORCAP0; /!< POR captured PIO status 0 /
bogdanm	0:9b334a45a8ff	1242	__I uint32_t PIOPORCAP1; /!< POR captured PIO status 1 /
bogdanm	0:9b334a45a8ff	1243	__I uint32_t PIOPORCAP2; /!< POR captured PIO status 2 /
bogdanm	0:9b334a45a8ff	1244	__I uint32_t RESERVED3[10];
bogdanm	0:9b334a45a8ff	1245	__IO uint32_t MAINCLKSELA; /!< Main clock source select A /
bogdanm	0:9b334a45a8ff	1246	__IO uint32_t MAINCLKSELB; /!< Main clock source select B /
bogdanm	0:9b334a45a8ff	1247	__IO uint32_t USBCLKSEL; /!< USB clock source select /
bogdanm	0:9b334a45a8ff	1248	__IO uint32_t ADCASYNCCLKSEL; /!< ADC asynchronous clock source select /
bogdanm	0:9b334a45a8ff	1249	__I uint32_t RESERVED4;
bogdanm	0:9b334a45a8ff	1250	__IO uint32_t CLKOUTSELA; /!< CLKOUT clock source select A /
bogdanm	0:9b334a45a8ff	1251	__IO uint32_t CLKOUTSELB; /!< CLKOUT clock source select B /
bogdanm	0:9b334a45a8ff	1252	__I uint32_t RESERVED5;
bogdanm	0:9b334a45a8ff	1253	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select /
bogdanm	0:9b334a45a8ff	1254	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select /
bogdanm	0:9b334a45a8ff	1255	__IO uint32_t SCTPLLCLKSEL; /!< SCT PLL clock source select /
bogdanm	0:9b334a45a8ff	1256	__I uint32_t RESERVED6[5];
bogdanm	0:9b334a45a8ff	1257	__IO uint32_t SYSAHBCLKDIV; /!< System clock divider /
bogdanm	0:9b334a45a8ff	1258	__IO uint32_t SYSAHBCLKCTRL0; /!< System clock control 0 /
bogdanm	0:9b334a45a8ff	1259	__IO uint32_t SYSAHBCLKCTRL1; /!< System clock control 1 /
bogdanm	0:9b334a45a8ff	1260	__IO uint32_t SYSTICKCLKDIV; /!< SYSTICK clock divider /
bogdanm	0:9b334a45a8ff	1261	__IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
bogdanm	0:9b334a45a8ff	1262	baud rate generator. */
bogdanm	0:9b334a45a8ff	1263	__IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
bogdanm	0:9b334a45a8ff	1264	filter */
bogdanm	0:9b334a45a8ff	1265	__IO uint32_t TRACECLKDIV; /!< ARM trace clock divider /
bogdanm	0:9b334a45a8ff	1266	__I uint32_t RESERVED7[4];
bogdanm	0:9b334a45a8ff	1267	__IO uint32_t USBCLKDIV; /!< USB clock divider /
bogdanm	0:9b334a45a8ff	1268	__IO uint32_t ADCASYNCCLKDIV; /!< Asynchronous ADC clock divider /
bogdanm	0:9b334a45a8ff	1269	__I uint32_t RESERVED8;
bogdanm	0:9b334a45a8ff	1270	__IO uint32_t CLKOUTDIV; /!< CLKOUT clock divider /
bogdanm	0:9b334a45a8ff	1271	__I uint32_t RESERVED9[11];
bogdanm	0:9b334a45a8ff	1272	__IO uint32_t FRGCTRL; /!< USART fractional baud rate generator control /
bogdanm	0:9b334a45a8ff	1273	__IO uint32_t USBCLKCTRL; /!< USB clock control /
bogdanm	0:9b334a45a8ff	1274	__IO uint32_t USBCLKST; /!< USB clock status /
bogdanm	0:9b334a45a8ff	1275	__I uint32_t RESERVED10[19];
bogdanm	0:9b334a45a8ff	1276	__IO uint32_t BODCTRL; /!< Brown-Out Detect /
bogdanm	0:9b334a45a8ff	1277	__I uint32_t RESERVED11;
bogdanm	0:9b334a45a8ff	1278	__IO uint32_t SYSOSCCTRL; /!< System oscillator control /
bogdanm	0:9b334a45a8ff	1279	__I uint32_t RESERVED12;
bogdanm	0:9b334a45a8ff	1280	__IO uint32_t RTCOSCCTRL; /!< RTC oscillator control /
bogdanm	0:9b334a45a8ff	1281	__I uint32_t RESERVED13;
bogdanm	0:9b334a45a8ff	1282	__IO uint32_t SYSPLLCTRL; /!< System PLL control /
bogdanm	0:9b334a45a8ff	1283	__I uint32_t SYSPLLSTAT; /!< System PLL status /
bogdanm	0:9b334a45a8ff	1284	__IO uint32_t USBPLLCTRL; /!< USB PLL control /
bogdanm	0:9b334a45a8ff	1285	__I uint32_t USBPLLSTAT; /!< USB PLL status /
bogdanm	0:9b334a45a8ff	1286	__IO uint32_t SCTPLLCTRL; /!< SCT PLL control /
bogdanm	0:9b334a45a8ff	1287	__I uint32_t SCTPLLSTAT; /!< SCT PLL status /
bogdanm	0:9b334a45a8ff	1288	__I uint32_t RESERVED14[21];
bogdanm	0:9b334a45a8ff	1289	__IO uint32_t PDAWAKECFG; /!< Power-down states for wake-up from deep-sleep /
bogdanm	0:9b334a45a8ff	1290	__IO uint32_t PDRUNCFG; /!< Power configuration register /
bogdanm	0:9b334a45a8ff	1291	__I uint32_t RESERVED15[3];
bogdanm	0:9b334a45a8ff	1292	__IO uint32_t STARTERP0; /!< Start logic 0 wake-up enable register /
bogdanm	0:9b334a45a8ff	1293	__IO uint32_t STARTERP1; /!< Start logic 1 wake-up enable register /
bogdanm	0:9b334a45a8ff	1294	} LPC_SYSCON_Type;
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296
bogdanm	0:9b334a45a8ff	1297	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1298	/* ================ MRT ================ */
bogdanm	0:9b334a45a8ff	1299	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1300
bogdanm	0:9b334a45a8ff	1301
bogdanm	0:9b334a45a8ff	1302	/**
bogdanm	0:9b334a45a8ff	1303	* @brief Multi-Rate Timer (MRT) (MRT)
bogdanm	0:9b334a45a8ff	1304	*/
bogdanm	0:9b334a45a8ff	1305
bogdanm	0:9b334a45a8ff	1306	typedef struct { /!< MRT Structure /
bogdanm	0:9b334a45a8ff	1307	__IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
bogdanm	0:9b334a45a8ff	1308	the TIMER0 register. */
bogdanm	0:9b334a45a8ff	1309	__I uint32_t TIMER0; /!< MRT0 Timer register. This register reads the value of the down-counter. /
bogdanm	0:9b334a45a8ff	1310	__IO uint32_t CTRL0; /!< MRT0 Control register. This register controls the MRT0 modes. /
bogdanm	0:9b334a45a8ff	1311	__IO uint32_t STAT0; /!< MRT0 Status register. /
bogdanm	0:9b334a45a8ff	1312	__IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
bogdanm	0:9b334a45a8ff	1313	the TIMER0 register. */
bogdanm	0:9b334a45a8ff	1314	__I uint32_t TIMER1; /!< MRT0 Timer register. This register reads the value of the down-counter. /
bogdanm	0:9b334a45a8ff	1315	__IO uint32_t CTRL1; /!< MRT0 Control register. This register controls the MRT0 modes. /
bogdanm	0:9b334a45a8ff	1316	__IO uint32_t STAT1; /!< MRT0 Status register. /
bogdanm	0:9b334a45a8ff	1317	__IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
bogdanm	0:9b334a45a8ff	1318	the TIMER0 register. */
bogdanm	0:9b334a45a8ff	1319	__I uint32_t TIMER2; /!< MRT0 Timer register. This register reads the value of the down-counter. /
bogdanm	0:9b334a45a8ff	1320	__IO uint32_t CTRL2; /!< MRT0 Control register. This register controls the MRT0 modes. /
bogdanm	0:9b334a45a8ff	1321	__IO uint32_t STAT2; /!< MRT0 Status register. /
bogdanm	0:9b334a45a8ff	1322	__IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
bogdanm	0:9b334a45a8ff	1323	the TIMER0 register. */
bogdanm	0:9b334a45a8ff	1324	__I uint32_t TIMER3; /!< MRT0 Timer register. This register reads the value of the down-counter. /
bogdanm	0:9b334a45a8ff	1325	__IO uint32_t CTRL3; /!< MRT0 Control register. This register controls the MRT0 modes. /
bogdanm	0:9b334a45a8ff	1326	__IO uint32_t STAT3; /!< MRT0 Status register. /
bogdanm	0:9b334a45a8ff	1327	__I uint32_t RESERVED0[45];
bogdanm	0:9b334a45a8ff	1328	__I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
bogdanm	0:9b334a45a8ff	1329	first idle channel. */
bogdanm	0:9b334a45a8ff	1330	__IO uint32_t IRQ_FLAG; /!< Global interrupt flag register /
bogdanm	0:9b334a45a8ff	1331	} LPC_MRT_Type;
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1335	/* ================ PINT ================ */
bogdanm	0:9b334a45a8ff	1336	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1337
bogdanm	0:9b334a45a8ff	1338
bogdanm	0:9b334a45a8ff	1339	/**
bogdanm	0:9b334a45a8ff	1340	* @brief Pin interruptand pattern match (PINT) (PINT)
bogdanm	0:9b334a45a8ff	1341	*/
bogdanm	0:9b334a45a8ff	1342
bogdanm	0:9b334a45a8ff	1343	typedef struct { /!< PINT Structure /
bogdanm	0:9b334a45a8ff	1344	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
bogdanm	0:9b334a45a8ff	1345	__IO uint32_t IENR; /!< Pin interrupt level or rising edge interrupt enable register /
bogdanm	0:9b334a45a8ff	1346	__O uint32_t SIENR; /!< Pin interrupt level or rising edge interrupt set register /
bogdanm	0:9b334a45a8ff	1347	__O uint32_t CIENR; /!< Pin interrupt level (rising edge interrupt) clear register /
bogdanm	0:9b334a45a8ff	1348	__IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
bogdanm	0:9b334a45a8ff	1349	register */
bogdanm	0:9b334a45a8ff	1350	__O uint32_t SIENF; /!< Pin interrupt active level or falling edge interrupt set register /
bogdanm	0:9b334a45a8ff	1351	__O uint32_t CIENF; /!< Pin interrupt active level or falling edge interrupt clear register /
bogdanm	0:9b334a45a8ff	1352	__IO uint32_t RISE; /!< Pin interrupt rising edge register /
bogdanm	0:9b334a45a8ff	1353	__IO uint32_t FALL; /!< Pin interrupt falling edge register /
bogdanm	0:9b334a45a8ff	1354	__IO uint32_t IST; /!< Pin interrupt status register /
bogdanm	0:9b334a45a8ff	1355	__IO uint32_t PMCTRL; /!< Pattern match interrupt control register /
bogdanm	0:9b334a45a8ff	1356	__IO uint32_t PMSRC; /!< Pattern match interrupt bit-slice source register /
bogdanm	0:9b334a45a8ff	1357	__IO uint32_t PMCFG; /!< Pattern match interrupt bit slice configuration register /
bogdanm	0:9b334a45a8ff	1358	} LPC_PINT_Type;
bogdanm	0:9b334a45a8ff	1359
bogdanm	0:9b334a45a8ff	1360
bogdanm	0:9b334a45a8ff	1361	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1362	/* ================ GINT0 ================ */
bogdanm	0:9b334a45a8ff	1363	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1364
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	/**
bogdanm	0:9b334a45a8ff	1367	* @brief Group interrupt 0/1 (GINT0/1) (GINT0)
bogdanm	0:9b334a45a8ff	1368	*/
bogdanm	0:9b334a45a8ff	1369
bogdanm	0:9b334a45a8ff	1370	typedef struct { /!< GINT0 Structure /
bogdanm	0:9b334a45a8ff	1371	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
bogdanm	0:9b334a45a8ff	1372	__I uint32_t RESERVED0[7];
bogdanm	0:9b334a45a8ff	1373	__IO uint32_t PORT_POL[3]; /!< GPIO grouped interrupt port 0 polarity register /
bogdanm	0:9b334a45a8ff	1374	__I uint32_t RESERVED1[5];
bogdanm	0:9b334a45a8ff	1375	__IO uint32_t PORT_ENA[3]; /!< GPIO grouped interrupt port 0 enable register /
bogdanm	0:9b334a45a8ff	1376	} LPC_GINT0_Type;
bogdanm	0:9b334a45a8ff	1377
bogdanm	0:9b334a45a8ff	1378
bogdanm	0:9b334a45a8ff	1379	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1380	/* ================ RIT ================ */
bogdanm	0:9b334a45a8ff	1381	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1382
bogdanm	0:9b334a45a8ff	1383
bogdanm	0:9b334a45a8ff	1384	/**
bogdanm	0:9b334a45a8ff	1385	* @brief Repetitive Interrupt Timer (RIT) (RIT)
bogdanm	0:9b334a45a8ff	1386	*/
bogdanm	0:9b334a45a8ff	1387
bogdanm	0:9b334a45a8ff	1388	typedef struct { /!< RIT Structure /
bogdanm	0:9b334a45a8ff	1389	__IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
bogdanm	0:9b334a45a8ff	1390	value. */
bogdanm	0:9b334a45a8ff	1391	__IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
bogdanm	0:9b334a45a8ff	1392	value. A 1 written to any bit will force a compare on the corresponding
bogdanm	0:9b334a45a8ff	1393	bit of the counter and compare register. */
bogdanm	0:9b334a45a8ff	1394	__IO uint32_t CTRL; /!< Control register. /
bogdanm	0:9b334a45a8ff	1395	__IO uint32_t COUNTER; /!< Counter LSB register. 32 LSBs of the counter. /
bogdanm	0:9b334a45a8ff	1396	__IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
bogdanm	0:9b334a45a8ff	1397	value. */
bogdanm	0:9b334a45a8ff	1398	__IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
bogdanm	0:9b334a45a8ff	1399	value. A 1 written to any bit will force a compare on the corresponding
bogdanm	0:9b334a45a8ff	1400	bit of the counter and compare register. */
bogdanm	0:9b334a45a8ff	1401	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	1402	__IO uint32_t COUNTER_H; /!< Counter MSB register. 16 MSBs of the counter. /
bogdanm	0:9b334a45a8ff	1403	} LPC_RIT_Type;
bogdanm	0:9b334a45a8ff	1404
bogdanm	0:9b334a45a8ff	1405
bogdanm	0:9b334a45a8ff	1406	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1407	/* ================ SCTIPU ================ */
bogdanm	0:9b334a45a8ff	1408	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1409
bogdanm	0:9b334a45a8ff	1410
bogdanm	0:9b334a45a8ff	1411	/**
bogdanm	0:9b334a45a8ff	1412	* @brief SCT Input Processing Unit (IPU) (SCTIPU)
bogdanm	0:9b334a45a8ff	1413	*/
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	typedef struct { /!< SCTIPU Structure /
bogdanm	0:9b334a45a8ff	1416	__IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
bogdanm	0:9b334a45a8ff	1417	latch/sample-enable mux selects, and sample overrride bits for
bogdanm	0:9b334a45a8ff	1418	the SAMPLE module. */
bogdanm	0:9b334a45a8ff	1419	__I uint32_t RESERVED0[7];
bogdanm	0:9b334a45a8ff	1420	__IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
bogdanm	0:9b334a45a8ff	1421	to ORed Abort Output 0. */
bogdanm	0:9b334a45a8ff	1422	__IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
bogdanm	0:9b334a45a8ff	1423	input source caused abort output 0. */
bogdanm	0:9b334a45a8ff	1424	__I uint32_t RESERVED1[6];
bogdanm	0:9b334a45a8ff	1425	__IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
bogdanm	0:9b334a45a8ff	1426	to ORed Abort Output 0. */
bogdanm	0:9b334a45a8ff	1427	__IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
bogdanm	0:9b334a45a8ff	1428	input source caused abort output 0. */
bogdanm	0:9b334a45a8ff	1429	__I uint32_t RESERVED2[6];
bogdanm	0:9b334a45a8ff	1430	__IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
bogdanm	0:9b334a45a8ff	1431	to ORed Abort Output 0. */
bogdanm	0:9b334a45a8ff	1432	__IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
bogdanm	0:9b334a45a8ff	1433	input source caused abort output 0. */
bogdanm	0:9b334a45a8ff	1434	__I uint32_t RESERVED3[6];
bogdanm	0:9b334a45a8ff	1435	__IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
bogdanm	0:9b334a45a8ff	1436	to ORed Abort Output 0. */
bogdanm	0:9b334a45a8ff	1437	__IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
bogdanm	0:9b334a45a8ff	1438	input source caused abort output 0. */
bogdanm	0:9b334a45a8ff	1439	} LPC_SCTIPU_Type;
bogdanm	0:9b334a45a8ff	1440
bogdanm	0:9b334a45a8ff	1441
bogdanm	0:9b334a45a8ff	1442	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1443	/* ================ FLASHCTRL ================ */
bogdanm	0:9b334a45a8ff	1444	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1445
bogdanm	0:9b334a45a8ff	1446
bogdanm	0:9b334a45a8ff	1447	/**
bogdanm	0:9b334a45a8ff	1448	* @brief Flash controller (FLASHCTRL)
bogdanm	0:9b334a45a8ff	1449	*/
bogdanm	0:9b334a45a8ff	1450
bogdanm	0:9b334a45a8ff	1451	typedef struct { /!< FLASHCTRL Structure /
bogdanm	0:9b334a45a8ff	1452	__I uint32_t RESERVED0[8];
bogdanm	0:9b334a45a8ff	1453	__IO uint32_t FMSSTART; /!< Signature start address register /
bogdanm	0:9b334a45a8ff	1454	__IO uint32_t FMSSTOP; /!< Signature stop-address register /
bogdanm	0:9b334a45a8ff	1455	__I uint32_t RESERVED1;
bogdanm	0:9b334a45a8ff	1456	__I uint32_t FMSW0; /!< Signature word /
bogdanm	0:9b334a45a8ff	1457	} LPC_FLASHCTRL_Type;
bogdanm	0:9b334a45a8ff	1458
bogdanm	0:9b334a45a8ff	1459
bogdanm	0:9b334a45a8ff	1460	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1461	/* ================ C_CAN0 ================ */
bogdanm	0:9b334a45a8ff	1462	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1463
bogdanm	0:9b334a45a8ff	1464
bogdanm	0:9b334a45a8ff	1465	/**
bogdanm	0:9b334a45a8ff	1466	* @brief Controller Area Network C_CAN0 (C_CAN0)
bogdanm	0:9b334a45a8ff	1467	*/
bogdanm	0:9b334a45a8ff	1468
bogdanm	0:9b334a45a8ff	1469	typedef struct { /!< C_CAN0 Structure /
bogdanm	0:9b334a45a8ff	1470	__IO uint32_t CANCNTL; /!< CAN control /
bogdanm	0:9b334a45a8ff	1471	__IO uint32_t CANSTAT; /!< Status register /
bogdanm	0:9b334a45a8ff	1472	__I uint32_t CANEC; /!< Error counter /
bogdanm	0:9b334a45a8ff	1473	__IO uint32_t CANBT; /!< Bit timing register /
bogdanm	0:9b334a45a8ff	1474	__I uint32_t CANINT; /!< Interrupt register /
bogdanm	0:9b334a45a8ff	1475	__IO uint32_t CANTEST; /!< Test register /
bogdanm	0:9b334a45a8ff	1476	__IO uint32_t CANBRPE; /!< Baud rate prescaler extension register /
bogdanm	0:9b334a45a8ff	1477	__I uint32_t RESERVED0;
bogdanm	0:9b334a45a8ff	1478	__IO uint32_t CANIF1_CMDREQ; /!< Message interface 1 command request /
bogdanm	0:9b334a45a8ff	1479
bogdanm	0:9b334a45a8ff	1480	union {
bogdanm	0:9b334a45a8ff	1481	__IO uint32_t CANIF1_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
bogdanm	0:9b334a45a8ff	1482	__IO uint32_t CANIF1_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
bogdanm	0:9b334a45a8ff	1483	};
bogdanm	0:9b334a45a8ff	1484	__IO uint32_t CANIF1_MSK1; /!< Message interface 1 mask 1 /
bogdanm	0:9b334a45a8ff	1485	__IO uint32_t CANIF1_MSK2; /!< Message interface 1 mask 2 /
bogdanm	0:9b334a45a8ff	1486	__IO uint32_t CANIF1_ARB1; /!< Message interface 1 arbitration 1 /
bogdanm	0:9b334a45a8ff	1487	__IO uint32_t CANIF1_ARB2; /!< Message interface 1 arbitration 2 /
bogdanm	0:9b334a45a8ff	1488	__IO uint32_t CANIF1_MCTRL; /!< Message interface 1 message control /
bogdanm	0:9b334a45a8ff	1489	__IO uint32_t CANIF1_DA1; /!< Message interface 1 data A1 /
bogdanm	0:9b334a45a8ff	1490	__IO uint32_t CANIF1_DA2; /!< Message interface 1 data A2 /
bogdanm	0:9b334a45a8ff	1491	__IO uint32_t CANIF1_DB1; /!< Message interface 1 data B1 /
bogdanm	0:9b334a45a8ff	1492	__IO uint32_t CANIF1_DB2; /!< Message interface 1 data B2 /
bogdanm	0:9b334a45a8ff	1493	__I uint32_t RESERVED1[13];
bogdanm	0:9b334a45a8ff	1494	__IO uint32_t CANIF2_CMDREQ; /!< Message interface 1 command request /
bogdanm	0:9b334a45a8ff	1495
bogdanm	0:9b334a45a8ff	1496	union {
bogdanm	0:9b334a45a8ff	1497	__IO uint32_t CANIF2_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
bogdanm	0:9b334a45a8ff	1498	__IO uint32_t CANIF2_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
bogdanm	0:9b334a45a8ff	1499	};
bogdanm	0:9b334a45a8ff	1500	__IO uint32_t CANIF2_MSK1; /!< Message interface 1 mask 1 /
bogdanm	0:9b334a45a8ff	1501	__IO uint32_t CANIF2_MSK2; /!< Message interface 1 mask 2 /
bogdanm	0:9b334a45a8ff	1502	__IO uint32_t CANIF2_ARB1; /!< Message interface 1 arbitration 1 /
bogdanm	0:9b334a45a8ff	1503	__IO uint32_t CANIF2_ARB2; /!< Message interface 1 arbitration 2 /
bogdanm	0:9b334a45a8ff	1504	__IO uint32_t CANIF2_MCTRL; /!< Message interface 1 message control /
bogdanm	0:9b334a45a8ff	1505	__IO uint32_t CANIF2_DA1; /!< Message interface 2 data A1 /
bogdanm	0:9b334a45a8ff	1506	__IO uint32_t CANIF2_DA2; /!< Message interface 2 data A2 /
bogdanm	0:9b334a45a8ff	1507	__IO uint32_t CANIF2_DB1; /!< Message interface 2 data B1 /
bogdanm	0:9b334a45a8ff	1508	__IO uint32_t CANIF2_DB2; /!< Message interface 2 data B2 /
bogdanm	0:9b334a45a8ff	1509	__I uint32_t RESERVED2[21];
bogdanm	0:9b334a45a8ff	1510	__I uint32_t CANTXREQ1; /!< Transmission request 1 /
bogdanm	0:9b334a45a8ff	1511	__I uint32_t CANTXREQ2; /!< Transmission request 2 /
bogdanm	0:9b334a45a8ff	1512	__I uint32_t RESERVED3[6];
bogdanm	0:9b334a45a8ff	1513	__I uint32_t CANND1; /!< New data 1 /
bogdanm	0:9b334a45a8ff	1514	__I uint32_t CANND2; /!< New data 2 /
bogdanm	0:9b334a45a8ff	1515	__I uint32_t RESERVED4[6];
bogdanm	0:9b334a45a8ff	1516	__I uint32_t CANIR1; /!< Interrupt pending 1 /
bogdanm	0:9b334a45a8ff	1517	__I uint32_t CANIR2; /!< Interrupt pending 2 /
bogdanm	0:9b334a45a8ff	1518	__I uint32_t RESERVED5[6];
bogdanm	0:9b334a45a8ff	1519	__I uint32_t CANMSGV1; /!< Message valid 1 /
bogdanm	0:9b334a45a8ff	1520	__I uint32_t CANMSGV2; /!< Message valid 2 /
bogdanm	0:9b334a45a8ff	1521	__I uint32_t RESERVED6[6];
bogdanm	0:9b334a45a8ff	1522	__IO uint32_t CANCLKDIV; /!< Can clock divider register /
bogdanm	0:9b334a45a8ff	1523	} LPC_C_CAN0_Type;
bogdanm	0:9b334a45a8ff	1524
bogdanm	0:9b334a45a8ff	1525
bogdanm	0:9b334a45a8ff	1526	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1527	/* ================ IOCON ================ */
bogdanm	0:9b334a45a8ff	1528	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1529
bogdanm	0:9b334a45a8ff	1530
bogdanm	0:9b334a45a8ff	1531	/**
bogdanm	0:9b334a45a8ff	1532	* @brief I/O pin configuration (IOCON) (IOCON)
bogdanm	0:9b334a45a8ff	1533	*/
bogdanm	0:9b334a45a8ff	1534
bogdanm	0:9b334a45a8ff	1535	typedef struct { /!< IOCON Structure /
bogdanm	0:9b334a45a8ff	1536	__IO uint32_t PIO0_0; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1537	__IO uint32_t PIO0_1; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1538	__IO uint32_t PIO0_2; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1539	__IO uint32_t PIO0_3; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1540	__IO uint32_t PIO0_4; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1541	__IO uint32_t PIO0_5; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1542	__IO uint32_t PIO0_6; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1543	__IO uint32_t PIO0_7; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1544	__IO uint32_t PIO0_8; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1545	__IO uint32_t PIO0_9; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1546	__IO uint32_t PIO0_10; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1547	__IO uint32_t PIO0_11; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1548	__IO uint32_t PIO0_12; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1549	__IO uint32_t PIO0_13; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1550	__IO uint32_t PIO0_14; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1551	__IO uint32_t PIO0_15; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1552	__IO uint32_t PIO0_16; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1553	__IO uint32_t PIO0_17; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1554	__IO uint32_t PIO0_18; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1555	__IO uint32_t PIO0_19; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1556	__IO uint32_t PIO0_20; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1557	__IO uint32_t PIO0_21; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
bogdanm	0:9b334a45a8ff	1558	__IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
bogdanm	0:9b334a45a8ff	1559	the I2C-bus SCL function. */
bogdanm	0:9b334a45a8ff	1560	__IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
bogdanm	0:9b334a45a8ff	1561	the I2C-bus SCL function. */
bogdanm	0:9b334a45a8ff	1562	__IO uint32_t PIO0_24; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
bogdanm	0:9b334a45a8ff	1563	__IO uint32_t PIO0_25; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
bogdanm	0:9b334a45a8ff	1564	__IO uint32_t PIO0_26; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
bogdanm	0:9b334a45a8ff	1565	__IO uint32_t PIO0_27; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
bogdanm	0:9b334a45a8ff	1566	__IO uint32_t PIO0_28; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
bogdanm	0:9b334a45a8ff	1567	__IO uint32_t PIO0_29; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
bogdanm	0:9b334a45a8ff	1568	__IO uint32_t PIO0_30; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
bogdanm	0:9b334a45a8ff	1569	__IO uint32_t PIO0_31; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
bogdanm	0:9b334a45a8ff	1570	__IO uint32_t PIO1_0; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1571	__IO uint32_t PIO1_1; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1572	__IO uint32_t PIO1_2; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1573	__IO uint32_t PIO1_3; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1574	__IO uint32_t PIO1_4; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1575	__IO uint32_t PIO1_5; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1576	__IO uint32_t PIO1_6; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1577	__IO uint32_t PIO1_7; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1578	__IO uint32_t PIO1_8; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1579	__IO uint32_t PIO1_9; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1580	__IO uint32_t PIO1_10; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1581	__IO uint32_t PIO1_11; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1582	__IO uint32_t PIO1_12; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1583	__IO uint32_t PIO1_13; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1584	__IO uint32_t PIO1_14; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1585	__IO uint32_t PIO1_15; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1586	__IO uint32_t PIO1_16; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1587	__IO uint32_t PIO1_17; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1588	__IO uint32_t PIO1_18; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1589	__IO uint32_t PIO1_19; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1590	__IO uint32_t PIO1_20; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1591	__IO uint32_t PIO1_21; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1592	__IO uint32_t PIO1_22; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1593	__IO uint32_t PIO1_23; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1594	__IO uint32_t PIO1_24; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1595	__IO uint32_t PIO1_25; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1596	__IO uint32_t PIO1_26; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1597	__IO uint32_t PIO1_27; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1598	__IO uint32_t PIO1_28; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1599	__IO uint32_t PIO1_29; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1600	__IO uint32_t PIO1_30; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1601	__IO uint32_t PIO1_31; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
bogdanm	0:9b334a45a8ff	1602	__IO uint32_t PIO2_0; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
bogdanm	0:9b334a45a8ff	1603	__IO uint32_t PIO2_1; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
bogdanm	0:9b334a45a8ff	1604	__IO uint32_t PIO2_2; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
bogdanm	0:9b334a45a8ff	1605	__IO uint32_t PIO2_3; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
bogdanm	0:9b334a45a8ff	1606	__IO uint32_t PIO2_4; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
bogdanm	0:9b334a45a8ff	1607	__IO uint32_t PIO2_5; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
bogdanm	0:9b334a45a8ff	1608	__IO uint32_t PIO2_6; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
bogdanm	0:9b334a45a8ff	1609	__IO uint32_t PIO2_7; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
bogdanm	0:9b334a45a8ff	1610	__IO uint32_t PIO2_8; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
bogdanm	0:9b334a45a8ff	1611	__IO uint32_t PIO2_9; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
bogdanm	0:9b334a45a8ff	1612	__IO uint32_t PIO2_10; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
bogdanm	0:9b334a45a8ff	1613	__IO uint32_t PIO2_11; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
bogdanm	0:9b334a45a8ff	1614	} LPC_IOCON_Type;
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616
bogdanm	0:9b334a45a8ff	1617	/* -------------------- End of section using anonymous unions ------------------- */
bogdanm	0:9b334a45a8ff	1618	#if defined(__CC_ARM)
bogdanm	0:9b334a45a8ff	1619	#pragma pop
bogdanm	0:9b334a45a8ff	1620	#elif defined(__ICCARM__)
bogdanm	0:9b334a45a8ff	1621	/* leave anonymous unions enabled */
bogdanm	0:9b334a45a8ff	1622	#elif defined(__GNUC__)
bogdanm	0:9b334a45a8ff	1623	/* anonymous unions are enabled by default */
bogdanm	0:9b334a45a8ff	1624	#elif defined(__TMS470__)
bogdanm	0:9b334a45a8ff	1625	/* anonymous unions are enabled by default */
bogdanm	0:9b334a45a8ff	1626	#elif defined(__TASKING__)
bogdanm	0:9b334a45a8ff	1627	#pragma warning restore
bogdanm	0:9b334a45a8ff	1628	#else
bogdanm	0:9b334a45a8ff	1629	#warning Not supported compiler type
bogdanm	0:9b334a45a8ff	1630	#endif
bogdanm	0:9b334a45a8ff	1631
bogdanm	0:9b334a45a8ff	1632
bogdanm	0:9b334a45a8ff	1633
bogdanm	0:9b334a45a8ff	1634
bogdanm	0:9b334a45a8ff	1635	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1636	/* ================ Peripheral memory map ================ */
bogdanm	0:9b334a45a8ff	1637	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1638
bogdanm	0:9b334a45a8ff	1639	#define LPC_GPIO_PORT_BASE 0x1C000000UL
bogdanm	0:9b334a45a8ff	1640	#define LPC_DMA_BASE 0x1C004000UL
bogdanm	0:9b334a45a8ff	1641	#define LPC_USB_BASE 0x1C00C000UL
bogdanm	0:9b334a45a8ff	1642	#define LPC_CRC_BASE 0x1C010000UL
bogdanm	0:9b334a45a8ff	1643	#define LPC_SCT0_BASE 0x1C018000UL
bogdanm	0:9b334a45a8ff	1644	#define LPC_SCT1_BASE 0x1C01C000UL
bogdanm	0:9b334a45a8ff	1645	#define LPC_SCT2_BASE 0x1C020000UL
bogdanm	0:9b334a45a8ff	1646	#define LPC_SCT3_BASE 0x1C024000UL
bogdanm	0:9b334a45a8ff	1647	#define LPC_ADC0_BASE 0x40000000UL
bogdanm	0:9b334a45a8ff	1648	#define LPC_DAC_BASE 0x40004000UL
bogdanm	0:9b334a45a8ff	1649	#define LPC_ACMP_BASE 0x40008000UL
bogdanm	0:9b334a45a8ff	1650	#define LPC_INMUX_BASE 0x40014000UL
bogdanm	0:9b334a45a8ff	1651	#define LPC_RTC_BASE 0x40028000UL
bogdanm	0:9b334a45a8ff	1652	#define LPC_WWDT_BASE 0x4002C000UL
bogdanm	0:9b334a45a8ff	1653	#define LPC_SWM_BASE 0x40038000UL
bogdanm	0:9b334a45a8ff	1654	#define LPC_PMU_BASE 0x4003C000UL
bogdanm	0:9b334a45a8ff	1655	#define LPC_USART0_BASE 0x40040000UL
bogdanm	0:9b334a45a8ff	1656	#define LPC_USART1_BASE 0x40044000UL
bogdanm	0:9b334a45a8ff	1657	#define LPC_SPI0_BASE 0x40048000UL
bogdanm	0:9b334a45a8ff	1658	#define LPC_SPI1_BASE 0x4004C000UL
bogdanm	0:9b334a45a8ff	1659	#define LPC_I2C0_BASE 0x40050000UL
bogdanm	0:9b334a45a8ff	1660	#define LPC_QEI_BASE 0x40058000UL
bogdanm	0:9b334a45a8ff	1661	#define LPC_SYSCON_BASE 0x40074000UL
bogdanm	0:9b334a45a8ff	1662	#define LPC_ADC1_BASE 0x40080000UL
bogdanm	0:9b334a45a8ff	1663	#define LPC_MRT_BASE 0x400A0000UL
bogdanm	0:9b334a45a8ff	1664	#define LPC_PINT_BASE 0x400A4000UL
bogdanm	0:9b334a45a8ff	1665	#define LPC_GINT0_BASE 0x400A8000UL
bogdanm	0:9b334a45a8ff	1666	#define LPC_GINT1_BASE 0x400AC000UL
bogdanm	0:9b334a45a8ff	1667	#define LPC_RIT_BASE 0x400B4000UL
bogdanm	0:9b334a45a8ff	1668	#define LPC_SCTIPU_BASE 0x400B8000UL
bogdanm	0:9b334a45a8ff	1669	#define LPC_FLASHCTRL_BASE 0x400BC000UL
bogdanm	0:9b334a45a8ff	1670	#define LPC_USART2_BASE 0x400C0000UL
bogdanm	0:9b334a45a8ff	1671	#define LPC_C_CAN0_BASE 0x400F0000UL
bogdanm	0:9b334a45a8ff	1672	#define LPC_IOCON_BASE 0x400F8000UL
bogdanm	0:9b334a45a8ff	1673
bogdanm	0:9b334a45a8ff	1674
bogdanm	0:9b334a45a8ff	1675	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1676	/* ================ Peripheral declaration ================ */
bogdanm	0:9b334a45a8ff	1677	/* ================================================================================ */
bogdanm	0:9b334a45a8ff	1678
bogdanm	0:9b334a45a8ff	1679	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
bogdanm	0:9b334a45a8ff	1680	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
bogdanm	0:9b334a45a8ff	1681	#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
bogdanm	0:9b334a45a8ff	1682	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
bogdanm	0:9b334a45a8ff	1683	#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
bogdanm	0:9b334a45a8ff	1684	#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
bogdanm	0:9b334a45a8ff	1685	#define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
bogdanm	0:9b334a45a8ff	1686	#define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
bogdanm	0:9b334a45a8ff	1687	#define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
bogdanm	0:9b334a45a8ff	1688	#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
bogdanm	0:9b334a45a8ff	1689	#define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
bogdanm	0:9b334a45a8ff	1690	#define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
bogdanm	0:9b334a45a8ff	1691	#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
bogdanm	0:9b334a45a8ff	1692	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
bogdanm	0:9b334a45a8ff	1693	#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
bogdanm	0:9b334a45a8ff	1694	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
bogdanm	0:9b334a45a8ff	1695	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
bogdanm	0:9b334a45a8ff	1696	#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
bogdanm	0:9b334a45a8ff	1697	#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
bogdanm	0:9b334a45a8ff	1698	#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
bogdanm	0:9b334a45a8ff	1699	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
bogdanm	0:9b334a45a8ff	1700	#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
bogdanm	0:9b334a45a8ff	1701	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
bogdanm	0:9b334a45a8ff	1702	#define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
bogdanm	0:9b334a45a8ff	1703	#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
bogdanm	0:9b334a45a8ff	1704	#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
bogdanm	0:9b334a45a8ff	1705	#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
bogdanm	0:9b334a45a8ff	1706	#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
bogdanm	0:9b334a45a8ff	1707	#define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
bogdanm	0:9b334a45a8ff	1708	#define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
bogdanm	0:9b334a45a8ff	1709	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
bogdanm	0:9b334a45a8ff	1710	#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
bogdanm	0:9b334a45a8ff	1711	#define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
bogdanm	0:9b334a45a8ff	1712	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
bogdanm	0:9b334a45a8ff	1713
bogdanm	0:9b334a45a8ff	1714
bogdanm	0:9b334a45a8ff	1715	/** @} / / End of group Device_Peripheral_Registers */
bogdanm	0:9b334a45a8ff	1716	/** @} / / End of group LPC15xx */
bogdanm	0:9b334a45a8ff	1717	/** @} / / End of group (null) */
bogdanm	0:9b334a45a8ff	1718
bogdanm	0:9b334a45a8ff	1719	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1720	}
bogdanm	0:9b334a45a8ff	1721	#endif
bogdanm	0:9b334a45a8ff	1722
bogdanm	0:9b334a45a8ff	1723
bogdanm	0:9b334a45a8ff	1724	#endif /* LPC15XX_H */
bogdanm	0:9b334a45a8ff	1725

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Type:	Library
Created:	23 Feb 2016
Imports:	88
Forks:	0
Commits:	71
Dependents:	0
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Followers:	2

targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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