R K / FMOPN

OPN系FM音源チップを制御します

OPN3L(YMF288-M)を制御します。

OPNA(YM2608)やOPN（YM2203)にも使用可能だと思われますがテストしていません。

OPNの場合は拡張FM部を正しく指定してください。

ADPCM系はテストしていません。

読出しも未実装です。コメントアウトしてありますが確認とれていません。

このプログラムは YMF288変換基板+Arduinoで簡易S98プレーヤを作る（その1）（http://d.hatena.ne.jp/m_yanase/20130901/1378020818） を参考にしています。

FMOPN.cpp@2:ea441ce9e405, 2016-01-13 (annotated)

Committer:
netwing
Date:
Wed Jan 13 15:26:27 2016 +0000
Revision:
2:ea441ce9e405
Parent:
1:df099d954a8f 
WR RD???

Who changed what in which revision?

UserRevisionLine numberNew contents of line
netwing 1:df099d954a8f 1 #include "mbed.h"
netwing 1:df099d954a8f 2 #include "FMOPN.h"
netwing 1:df099d954a8f 3 #define bitRead(value, bit) (((value) >> (bit)) & 0x01)
netwing 2:ea441ce9e405 4 FMOPN::FMOPN(
netwing 1:df099d954a8f 5 PinName _D0,
netwing 1:df099d954a8f 6 PinName _D1,
netwing 1:df099d954a8f 7 PinName _D2,
netwing 1:df099d954a8f 8 PinName _D3,
netwing 1:df099d954a8f 9 PinName _D4,
netwing 1:df099d954a8f 10 PinName _D5,
netwing 1:df099d954a8f 11 PinName _D6,
netwing 1:df099d954a8f 12 PinName _D7,
netwing 1:df099d954a8f 13 PinName RST,
netwing 1:df099d954a8f 14 PinName A0,
netwing 1:df099d954a8f 15 PinName A1,
netwing 2:ea441ce9e405 16 PinName CS,
netwing 2:ea441ce9e405 17 PinName WR,
netwing 2:ea441ce9e405 18 PinName RD
netwing 2:ea441ce9e405 19 ) : _BUS(_D0,_D1,_D2,_D3,_D4,_D5,_D6,_D7), _RST(RST), _A0(A0), _A1(A1), _CS(CS), _WR(WR), _RD(RD)
netwing 1:df099d954a8f 20 {
netwing 1:df099d954a8f 21 }
netwing 1:df099d954a8f 22
netwing 1:df099d954a8f 23 // Reset
netwing 2:ea441ce9e405 24 void FMOPN::reset()
netwing 1:df099d954a8f 25 {
netwing 1:df099d954a8f 26 _RST = 0;
netwing 1:df099d954a8f 27 wait_us(100);
netwing 1:df099d954a8f 28 _RST = 1;
netwing 1:df099d954a8f 29 wait_ms(100);
netwing 1:df099d954a8f 30 }
netwing 1:df099d954a8f 31
netwing 1:df099d954a8f 32
netwing 1:df099d954a8f 33 // Register Write
netwing 2:ea441ce9e405 34 void FMOPN::reg_write(unsigned char ifadr, unsigned char adr, unsigned char dat)
netwing 1:df099d954a8f 35 {
netwing 1:df099d954a8f 36 law_write(ifadr, adr, dat);
netwing 1:df099d954a8f 37 switch (adr) { // データライト後のWait
netwing 1:df099d954a8f 38 case 0x28: { // FM Address 0x28
netwing 1:df099d954a8f 39 wait_us(WT_FM_DA); // min: 24us wait
netwing 1:df099d954a8f 40 break;
netwing 1:df099d954a8f 41 }
netwing 1:df099d954a8f 42 case 0x10: { // RHYTHM Address 0x10
netwing 1:df099d954a8f 43 wait_us(WT_RHYTHM_DA); // min: 22us wait
netwing 1:df099d954a8f 44 break;
netwing 1:df099d954a8f 45 }
netwing 1:df099d954a8f 46 default: { // Other Address
netwing 1:df099d954a8f 47 wait_us(2); // min.1.9us wait
netwing 1:df099d954a8f 48 }
netwing 1:df099d954a8f 49 }
netwing 1:df099d954a8f 50 }
netwing 2:ea441ce9e405 51 ////Read
netwing 2:ea441ce9e405 52 //unsigned char FMOPN::reg_read(unsigned char ifadr, unsigned char adr)
netwing 2:ea441ce9e405 53 //{
netwing 2:ea441ce9e405 54 // DigitalOut LED(LED1,1);
netwing 2:ea441ce9e405 55 // _BUS.output();
netwing 2:ea441ce9e405 56 // _WR = 0;
netwing 2:ea441ce9e405 57 // _RD = 1;
netwing 2:ea441ce9e405 58 // adr_write(ifadr,adr);
netwing 2:ea441ce9e405 59 // _BUS.input();
netwing 2:ea441ce9e405 60 // _WR = 1;
netwing 2:ea441ce9e405 61 // _RD = 0;
netwing 2:ea441ce9e405 62 // unsigned char dar=dat_read();
netwing 2:ea441ce9e405 63 // return dar;
netwing 2:ea441ce9e405 64 //}
netwing 1:df099d954a8f 65
netwing 1:df099d954a8f 66 //Write
netwing 2:ea441ce9e405 67 void FMOPN::law_write(unsigned char ifadr, unsigned char adr, unsigned char dat)
netwing 1:df099d954a8f 68 {
netwing 2:ea441ce9e405 69 _BUS.output();
netwing 2:ea441ce9e405 70 _WR = 0;
netwing 2:ea441ce9e405 71 _RD = 1;
netwing 1:df099d954a8f 72 adr_write(ifadr,adr);
netwing 1:df099d954a8f 73 dat_write(dat);
netwing 1:df099d954a8f 74
netwing 1:df099d954a8f 75 }
netwing 1:df099d954a8f 76
netwing 1:df099d954a8f 77 //Write Address
netwing 2:ea441ce9e405 78 void FMOPN::adr_write(unsigned char ifadr, unsigned char adr)
netwing 1:df099d954a8f 79 {
netwing 1:df099d954a8f 80 _A0 = 0; // Address Bus set
netwing 1:df099d954a8f 81 _A1 = bitRead(ifadr, 0);
netwing 2:ea441ce9e405 82 _BUS = adr; // Address set
netwing 1:df099d954a8f 83 _CS = 0;
netwing 1:df099d954a8f 84 wait_us(1); // min: 200ns wait
netwing 1:df099d954a8f 85 _CS = 1;
netwing 1:df099d954a8f 86 wait_us(2); // min: 1.9us wait
netwing 1:df099d954a8f 87 }
netwing 1:df099d954a8f 88
netwing 1:df099d954a8f 89 //Write Data
netwing 2:ea441ce9e405 90 void FMOPN::dat_write(unsigned char dat)
netwing 1:df099d954a8f 91 {
netwing 1:df099d954a8f 92 _A0 = 1; // Address Bus set
netwing 2:ea441ce9e405 93 _BUS = dat; // Data set
netwing 1:df099d954a8f 94 _CS = 0;
netwing 1:df099d954a8f 95 wait_us(1); // min: 200ns wait
netwing 1:df099d954a8f 96 _CS = 1;
netwing 1:df099d954a8f 97 }
netwing 2:ea441ce9e405 98 ////Read Data
netwing 2:ea441ce9e405 99 //unsigned char FMOPN::dat_read()
netwing 2:ea441ce9e405 100 //{
netwing 2:ea441ce9e405 101 // _A0 = 1; // Address Bus set
netwing 2:ea441ce9e405 102 // _CS = 0;
netwing 2:ea441ce9e405 103 // unsigned char d=_BUS;
netwing 2:ea441ce9e405 104 // _CS = 1;
netwing 2:ea441ce9e405 105 // return d;
netwing 2:ea441ce9e405 106 //}