Milen Pavlov / SX1272Lib

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Dependents:   XRangePingPong XRange-LoRaWAN-lmic-app lora-transceiver

Fork of SX1276Lib by Semtech

sx1272/sx1272.cpp@17:a5c9fd1a1ea6, 2015-05-31 (annotated)

Committer:
netblocks
Date:
Sun May 31 12:52:46 2015 +0000
Revision:
17:a5c9fd1a1ea6
Parent:
sx1276/sx1276.cpp@16:d447f8d2d2d6 
XRange SX1272Lib

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 8:0fe3e0e8007b 7 ( C )2014 Semtech
GregCr 0:e6ceb13d2d05 8
netblocks 17:a5c9fd1a1ea6 9 Description: Actual implementation of a SX1272 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
netblocks 17:a5c9fd1a1ea6 13 Maintainers: www.netblocks.eu
netblocks 17:a5c9fd1a1ea6 14 SX1272 LoRa RF module : http://www.netblocks.eu/xrange-sx1272-lora-datasheet/
GregCr 0:e6ceb13d2d05 15 */
netblocks 17:a5c9fd1a1ea6 16 #include "sx1272.h"
GregCr 0:e6ceb13d2d05 17
netblocks 17:a5c9fd1a1ea6 18 const FskBandwidth_t SX1272::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 19 {
GregCr 0:e6ceb13d2d05 20 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 21 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 22 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 23 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 24 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 25 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 26 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 27 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 28 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 29 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 30 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 31 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 32 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 33 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 34 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 35 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 36 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 37 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 38 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 39 { 200000, 0x09 },
mluis 15:04374b1c33fa 40 { 250000, 0x01 },
mluis 16:d447f8d2d2d6 41 { 300000, 0x00 }, // Invalid Badwidth
GregCr 0:e6ceb13d2d05 42 };
GregCr 0:e6ceb13d2d05 43
GregCr 0:e6ceb13d2d05 44
netblocks 17:a5c9fd1a1ea6 45 SX1272::SX1272( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ),
mluis 13:618826a997e2 46 void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ), void ( *cadDone ) ( bool channelActivityDetected ),
mluis 13:618826a997e2 47 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 48 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 13:618826a997e2 49 : Radio( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone ),
mluis 13:618826a997e2 50 spi( mosi, miso, sclk ),
mluis 13:618826a997e2 51 nss( nss ),
mluis 13:618826a997e2 52 reset( reset ),
mluis 13:618826a997e2 53 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 13:618826a997e2 54 isRadioActive( false )
GregCr 0:e6ceb13d2d05 55 {
mluis 13:618826a997e2 56 wait_ms( 10 );
mluis 13:618826a997e2 57 this->rxTx = 0;
mluis 13:618826a997e2 58 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 13:618826a997e2 59 previousOpMode = RF_OPMODE_STANDBY;
mluis 13:618826a997e2 60
mluis 13:618826a997e2 61 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 62
netblocks 17:a5c9fd1a1ea6 63 this->dioIrq[0] = &SX1272::OnDio0Irq;
netblocks 17:a5c9fd1a1ea6 64 this->dioIrq[1] = &SX1272::OnDio1Irq;
netblocks 17:a5c9fd1a1ea6 65 this->dioIrq[2] = &SX1272::OnDio2Irq;
netblocks 17:a5c9fd1a1ea6 66 this->dioIrq[3] = &SX1272::OnDio3Irq;
netblocks 17:a5c9fd1a1ea6 67 this->dioIrq[4] = &SX1272::OnDio4Irq;
mluis 13:618826a997e2 68 this->dioIrq[5] = NULL;
mluis 13:618826a997e2 69
mluis 13:618826a997e2 70 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 71 }
GregCr 0:e6ceb13d2d05 72
netblocks 17:a5c9fd1a1ea6 73 SX1272::~SX1272( )
GregCr 0:e6ceb13d2d05 74 {
mluis 13:618826a997e2 75 delete this->rxBuffer;
mluis 13:618826a997e2 76 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 77 }
GregCr 0:e6ceb13d2d05 78
netblocks 17:a5c9fd1a1ea6 79 void SX1272::RxChainCalibration( void )
GregCr 0:e6ceb13d2d05 80 {
GregCr 0:e6ceb13d2d05 81 }
GregCr 0:e6ceb13d2d05 82
netblocks 17:a5c9fd1a1ea6 83 RadioState SX1272::GetState( void )
GregCr 0:e6ceb13d2d05 84 {
GregCr 0:e6ceb13d2d05 85 return this->settings.State;
GregCr 0:e6ceb13d2d05 86 }
GregCr 0:e6ceb13d2d05 87
netblocks 17:a5c9fd1a1ea6 88 void SX1272::SetChannel( uint32_t freq ) //OK
GregCr 0:e6ceb13d2d05 89 {
GregCr 0:e6ceb13d2d05 90 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 91 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 92 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 93 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 94 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
netblocks 17:a5c9fd1a1ea6 95
GregCr 0:e6ceb13d2d05 96 }
GregCr 0:e6ceb13d2d05 97
netblocks 17:a5c9fd1a1ea6 98 bool SX1272::IsChannelFree( ModemType modem, uint32_t freq, int8_t rssiThresh ) //OK
GregCr 0:e6ceb13d2d05 99 {
netblocks 17:a5c9fd1a1ea6 100 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 101
GregCr 0:e6ceb13d2d05 102 SetModem( modem );
GregCr 0:e6ceb13d2d05 103
GregCr 0:e6ceb13d2d05 104 SetChannel( freq );
GregCr 0:e6ceb13d2d05 105
GregCr 0:e6ceb13d2d05 106 SetOpMode( RF_OPMODE_RECEIVER );
netblocks 17:a5c9fd1a1ea6 107
GregCr 4:f0ce52e94d3f 108 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 109
GregCr 0:e6ceb13d2d05 110 rssi = GetRssi( modem );
GregCr 0:e6ceb13d2d05 111
GregCr 0:e6ceb13d2d05 112 Sleep( );
GregCr 0:e6ceb13d2d05 113
netblocks 17:a5c9fd1a1ea6 114 if( rssi > rssiThresh )
GregCr 0:e6ceb13d2d05 115 {
GregCr 0:e6ceb13d2d05 116 return false;
GregCr 0:e6ceb13d2d05 117 }
GregCr 0:e6ceb13d2d05 118 return true;
netblocks 17:a5c9fd1a1ea6 119
GregCr 0:e6ceb13d2d05 120 }
GregCr 0:e6ceb13d2d05 121
netblocks 17:a5c9fd1a1ea6 122 uint32_t SX1272::Random( void )
GregCr 0:e6ceb13d2d05 123 {
netblocks 17:a5c9fd1a1ea6 124 uint8_t i;
GregCr 0:e6ceb13d2d05 125 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 126
GregCr 0:e6ceb13d2d05 127 /*
GregCr 0:e6ceb13d2d05 128 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 129 */
GregCr 0:e6ceb13d2d05 130 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 131 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 132
GregCr 0:e6ceb13d2d05 133 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 134 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 135 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 136 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 137 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 138 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 139 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 140 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 141 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 142
GregCr 0:e6ceb13d2d05 143 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 144 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 145
GregCr 0:e6ceb13d2d05 146 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 147 {
netblocks 17:a5c9fd1a1ea6 148 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 149 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 150 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 151 }
GregCr 0:e6ceb13d2d05 152
netblocks 17:a5c9fd1a1ea6 153 Sleep( );
GregCr 0:e6ceb13d2d05 154
GregCr 0:e6ceb13d2d05 155 return rnd;
netblocks 17:a5c9fd1a1ea6 156
GregCr 0:e6ceb13d2d05 157 }
GregCr 0:e6ceb13d2d05 158
GregCr 0:e6ceb13d2d05 159 /*!
GregCr 0:e6ceb13d2d05 160 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 161 *
GregCr 0:e6ceb13d2d05 162 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 163 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 164 */
netblocks 17:a5c9fd1a1ea6 165 uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 166 {
netblocks 17:a5c9fd1a1ea6 167 uint8_t i;
GregCr 0:e6ceb13d2d05 168
GregCr 0:e6ceb13d2d05 169 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 170 {
GregCr 0:e6ceb13d2d05 171 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 172 {
GregCr 0:e6ceb13d2d05 173 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 174 }
GregCr 0:e6ceb13d2d05 175 }
GregCr 0:e6ceb13d2d05 176 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 177 while( 1 );
netblocks 17:a5c9fd1a1ea6 178
GregCr 0:e6ceb13d2d05 179 }
GregCr 0:e6ceb13d2d05 180
netblocks 17:a5c9fd1a1ea6 181 void SX1272::SetRxConfig( ModemType modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 182 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 183 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 184 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 185 uint8_t payloadLen,
mluis 13:618826a997e2 186 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 187 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 188 {
GregCr 0:e6ceb13d2d05 189 SetModem( modem );
GregCr 0:e6ceb13d2d05 190
GregCr 0:e6ceb13d2d05 191 switch( modem )
GregCr 0:e6ceb13d2d05 192 {
GregCr 0:e6ceb13d2d05 193 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 194 {
GregCr 0:e6ceb13d2d05 195 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 196 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 197 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 198 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 199 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 200 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 201 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 202 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 203 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 204
GregCr 0:e6ceb13d2d05 205 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 206 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 207 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 208
GregCr 0:e6ceb13d2d05 209 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 210 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 211
mluis 14:8552d0b840be 212 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 213 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 214
GregCr 0:e6ceb13d2d05 215 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 216 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 217 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 218 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 219 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 220 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 221 }
GregCr 0:e6ceb13d2d05 222 break;
GregCr 0:e6ceb13d2d05 223 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 224 {
GregCr 0:e6ceb13d2d05 225 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 226 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 227 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 228 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 229 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 230 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 231 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 232 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 233 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 234 this->settings.LoRa.RxContinuous = rxContinuous;
netblocks 17:a5c9fd1a1ea6 235
GregCr 0:e6ceb13d2d05 236 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 237 {
GregCr 0:e6ceb13d2d05 238 datarate = 12;
GregCr 0:e6ceb13d2d05 239 }
GregCr 0:e6ceb13d2d05 240 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 241 {
GregCr 0:e6ceb13d2d05 242 datarate = 6;
GregCr 0:e6ceb13d2d05 243 }
GregCr 0:e6ceb13d2d05 244
netblocks 17:a5c9fd1a1ea6 245 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
netblocks 17:a5c9fd1a1ea6 246 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 247 {
GregCr 0:e6ceb13d2d05 248 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 249 }
GregCr 0:e6ceb13d2d05 250 else
GregCr 0:e6ceb13d2d05 251 {
GregCr 0:e6ceb13d2d05 252 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 253 }
GregCr 0:e6ceb13d2d05 254
GregCr 0:e6ceb13d2d05 255 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 256 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 257 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 258 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
netblocks 17:a5c9fd1a1ea6 259 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
netblocks 17:a5c9fd1a1ea6 260 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
netblocks 17:a5c9fd1a1ea6 261 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
netblocks 17:a5c9fd1a1ea6 262 ( bandwidth << 6 ) | ( coderate << 3 ) |
netblocks 17:a5c9fd1a1ea6 263 ( fixLen << 2 ) | ( crcOn << 1 ) |
netblocks 17:a5c9fd1a1ea6 264 this->settings.LoRa.LowDatarateOptimize );
netblocks 17:a5c9fd1a1ea6 265
GregCr 0:e6ceb13d2d05 266 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 267 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 268 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 269 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
netblocks 17:a5c9fd1a1ea6 270 ( datarate << 4 ) |
GregCr 0:e6ceb13d2d05 271 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 272
GregCr 0:e6ceb13d2d05 273 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
GregCr 0:e6ceb13d2d05 274
GregCr 0:e6ceb13d2d05 275 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 276 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 277
mluis 13:618826a997e2 278 if( fixLen == 1 )
mluis 13:618826a997e2 279 {
mluis 13:618826a997e2 280 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 281 }
mluis 13:618826a997e2 282
GregCr 6:e7f02929cd3d 283 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 284 {
GregCr 6:e7f02929cd3d 285 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 286 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 287 }
GregCr 6:e7f02929cd3d 288
GregCr 0:e6ceb13d2d05 289 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 290 {
GregCr 0:e6ceb13d2d05 291 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 292 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 293 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 294 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 295 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 296 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 297 }
GregCr 0:e6ceb13d2d05 298 else
GregCr 0:e6ceb13d2d05 299 {
GregCr 0:e6ceb13d2d05 300 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 301 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 302 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 303 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 304 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 305 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 306 }
GregCr 0:e6ceb13d2d05 307 }
GregCr 0:e6ceb13d2d05 308 break;
GregCr 0:e6ceb13d2d05 309 }
GregCr 0:e6ceb13d2d05 310 }
GregCr 0:e6ceb13d2d05 311
netblocks 17:a5c9fd1a1ea6 312
netblocks 17:a5c9fd1a1ea6 313 void SX1272::SetTxConfig( ModemType modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 314 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 315 uint8_t coderate, uint16_t preambleLen,
mluis 13:618826a997e2 316 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 317 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 318 {
GregCr 0:e6ceb13d2d05 319 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 320 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 321
GregCr 0:e6ceb13d2d05 322 SetModem( modem );
GregCr 0:e6ceb13d2d05 323
GregCr 0:e6ceb13d2d05 324 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 325 paDac = Read( REG_PADAC );
netblocks 17:a5c9fd1a1ea6 326
GregCr 0:e6ceb13d2d05 327 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
netblocks 17:a5c9fd1a1ea6 328
GregCr 0:e6ceb13d2d05 329 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 330 {
GregCr 0:e6ceb13d2d05 331 if( power > 17 )
GregCr 0:e6ceb13d2d05 332 {
GregCr 0:e6ceb13d2d05 333 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
GregCr 0:e6ceb13d2d05 334 }
GregCr 0:e6ceb13d2d05 335 else
GregCr 0:e6ceb13d2d05 336 {
GregCr 0:e6ceb13d2d05 337 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
GregCr 0:e6ceb13d2d05 338 }
GregCr 0:e6ceb13d2d05 339 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 340 {
GregCr 0:e6ceb13d2d05 341 if( power < 5 )
GregCr 0:e6ceb13d2d05 342 {
GregCr 0:e6ceb13d2d05 343 power = 5;
GregCr 0:e6ceb13d2d05 344 }
GregCr 0:e6ceb13d2d05 345 if( power > 20 )
GregCr 0:e6ceb13d2d05 346 {
GregCr 0:e6ceb13d2d05 347 power = 20;
GregCr 0:e6ceb13d2d05 348 }
netblocks 17:a5c9fd1a1ea6 349 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 350 }
GregCr 0:e6ceb13d2d05 351 else
GregCr 0:e6ceb13d2d05 352 {
GregCr 0:e6ceb13d2d05 353 if( power < 2 )
GregCr 0:e6ceb13d2d05 354 {
GregCr 0:e6ceb13d2d05 355 power = 2;
GregCr 0:e6ceb13d2d05 356 }
GregCr 0:e6ceb13d2d05 357 if( power > 17 )
GregCr 0:e6ceb13d2d05 358 {
GregCr 0:e6ceb13d2d05 359 power = 17;
GregCr 0:e6ceb13d2d05 360 }
netblocks 17:a5c9fd1a1ea6 361 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 362 }
GregCr 0:e6ceb13d2d05 363 }
GregCr 0:e6ceb13d2d05 364 else
GregCr 0:e6ceb13d2d05 365 {
GregCr 0:e6ceb13d2d05 366 if( power < -1 )
GregCr 0:e6ceb13d2d05 367 {
GregCr 0:e6ceb13d2d05 368 power = -1;
GregCr 0:e6ceb13d2d05 369 }
GregCr 0:e6ceb13d2d05 370 if( power > 14 )
GregCr 0:e6ceb13d2d05 371 {
GregCr 0:e6ceb13d2d05 372 power = 14;
GregCr 0:e6ceb13d2d05 373 }
netblocks 17:a5c9fd1a1ea6 374 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 375 }
GregCr 0:e6ceb13d2d05 376 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 377 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 378
GregCr 0:e6ceb13d2d05 379 switch( modem )
GregCr 0:e6ceb13d2d05 380 {
GregCr 0:e6ceb13d2d05 381 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 382 {
GregCr 0:e6ceb13d2d05 383 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 384 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 385 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 386 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 387 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 388 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 389 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 390 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 391 this->settings.Fsk.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 392
GregCr 0:e6ceb13d2d05 393 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 394 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 395 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 396
GregCr 0:e6ceb13d2d05 397 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 398 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 399 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 400
GregCr 0:e6ceb13d2d05 401 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 402 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 403
GregCr 0:e6ceb13d2d05 404 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 405 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 406 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 407 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 408 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 409 ( crcOn << 4 ) );
netblocks 17:a5c9fd1a1ea6 410
GregCr 0:e6ceb13d2d05 411 }
GregCr 0:e6ceb13d2d05 412 break;
GregCr 0:e6ceb13d2d05 413 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 414 {
GregCr 0:e6ceb13d2d05 415 this->settings.LoRa.Power = power;
GregCr 0:e6ceb13d2d05 416 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 417 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 418 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 419 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 420 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 421 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 422 this->settings.LoRa.HopPeriod = hopPeriod;
netblocks 17:a5c9fd1a1ea6 423 this->settings.LoRa.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 424 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 425 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 426
GregCr 0:e6ceb13d2d05 427 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 428 {
GregCr 0:e6ceb13d2d05 429 datarate = 12;
GregCr 0:e6ceb13d2d05 430 }
GregCr 0:e6ceb13d2d05 431 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 432 {
GregCr 0:e6ceb13d2d05 433 datarate = 6;
GregCr 0:e6ceb13d2d05 434 }
netblocks 17:a5c9fd1a1ea6 435 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
netblocks 17:a5c9fd1a1ea6 436 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 437 {
GregCr 0:e6ceb13d2d05 438 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 439 }
GregCr 0:e6ceb13d2d05 440 else
GregCr 0:e6ceb13d2d05 441 {
GregCr 0:e6ceb13d2d05 442 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 443 }
netblocks 17:a5c9fd1a1ea6 444
GregCr 6:e7f02929cd3d 445 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 446 {
GregCr 6:e7f02929cd3d 447 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 448 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 449 }
netblocks 17:a5c9fd1a1ea6 450
GregCr 0:e6ceb13d2d05 451 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 452 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 453 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 454 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
netblocks 17:a5c9fd1a1ea6 455 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
netblocks 17:a5c9fd1a1ea6 456 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
netblocks 17:a5c9fd1a1ea6 457 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
netblocks 17:a5c9fd1a1ea6 458 ( bandwidth << 6 ) | ( coderate << 3 ) |
netblocks 17:a5c9fd1a1ea6 459 ( fixLen << 2 ) | ( crcOn << 1 ) |
netblocks 17:a5c9fd1a1ea6 460 this->settings.LoRa.LowDatarateOptimize );
GregCr 0:e6ceb13d2d05 461
GregCr 0:e6ceb13d2d05 462 Write( REG_LR_MODEMCONFIG2,
netblocks 17:a5c9fd1a1ea6 463 ( Read( REG_LR_MODEMCONFIG2 ) &
netblocks 17:a5c9fd1a1ea6 464 RFLR_MODEMCONFIG2_SF_MASK ) |
netblocks 17:a5c9fd1a1ea6 465 ( datarate << 4 ) );
GregCr 0:e6ceb13d2d05 466
GregCr 0:e6ceb13d2d05 467
GregCr 0:e6ceb13d2d05 468 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 469 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 470
GregCr 0:e6ceb13d2d05 471 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 472 {
GregCr 0:e6ceb13d2d05 473 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 474 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 475 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 476 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 477 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 478 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 479 }
GregCr 0:e6ceb13d2d05 480 else
GregCr 0:e6ceb13d2d05 481 {
GregCr 0:e6ceb13d2d05 482 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 483 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 484 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 485 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 486 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 487 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 488 }
GregCr 0:e6ceb13d2d05 489 }
GregCr 0:e6ceb13d2d05 490 break;
GregCr 0:e6ceb13d2d05 491 }
GregCr 0:e6ceb13d2d05 492 }
GregCr 0:e6ceb13d2d05 493
netblocks 17:a5c9fd1a1ea6 494
netblocks 17:a5c9fd1a1ea6 495 double SX1272::TimeOnAir( ModemType modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 496 {
netblocks 17:a5c9fd1a1ea6 497 uint32_t airTime = 0;
GregCr 0:e6ceb13d2d05 498
GregCr 0:e6ceb13d2d05 499 switch( modem )
GregCr 0:e6ceb13d2d05 500 {
GregCr 0:e6ceb13d2d05 501 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 502 {
GregCr 4:f0ce52e94d3f 503 airTime = ceil( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 504 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 505 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 506 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 507 pktLen +
GregCr 0:e6ceb13d2d05 508 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 509 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 510 }
GregCr 0:e6ceb13d2d05 511 break;
GregCr 0:e6ceb13d2d05 512 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 513 {
GregCr 0:e6ceb13d2d05 514 double bw = 0.0;
GregCr 0:e6ceb13d2d05 515 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 516 {
netblocks 17:a5c9fd1a1ea6 517 case 0: // 125 kHz
GregCr 0:e6ceb13d2d05 518 bw = 125e3;
GregCr 0:e6ceb13d2d05 519 break;
netblocks 17:a5c9fd1a1ea6 520 case 1: // 250 kHz
GregCr 0:e6ceb13d2d05 521 bw = 250e3;
GregCr 0:e6ceb13d2d05 522 break;
netblocks 17:a5c9fd1a1ea6 523 case 2: // 500 kHz
GregCr 0:e6ceb13d2d05 524 bw = 500e3;
GregCr 0:e6ceb13d2d05 525 break;
GregCr 0:e6ceb13d2d05 526 }
GregCr 0:e6ceb13d2d05 527
GregCr 0:e6ceb13d2d05 528 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 529 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 530 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 531 // time of preamble
GregCr 0:e6ceb13d2d05 532 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 533 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 534 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 535 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 536 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 537 ( double )( 4 * this->settings.LoRa.Datarate -
GregCr 0:e6ceb13d2d05 538 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 8 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 539 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 540 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 541 double tPayload = nPayload * ts;
GregCr 0:e6ceb13d2d05 542 // Time on air
GregCr 0:e6ceb13d2d05 543 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 544 // return us secs
GregCr 0:e6ceb13d2d05 545 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 546 }
GregCr 0:e6ceb13d2d05 547 break;
GregCr 0:e6ceb13d2d05 548 }
GregCr 0:e6ceb13d2d05 549 return airTime;
GregCr 0:e6ceb13d2d05 550 }
netblocks 17:a5c9fd1a1ea6 551
netblocks 17:a5c9fd1a1ea6 552 void SX1272::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 553 {
GregCr 0:e6ceb13d2d05 554 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 555
GregCr 0:e6ceb13d2d05 556 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 557 {
GregCr 0:e6ceb13d2d05 558 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 559 {
GregCr 0:e6ceb13d2d05 560 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 561 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 562
GregCr 0:e6ceb13d2d05 563 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 564 {
GregCr 0:e6ceb13d2d05 565 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 566 }
GregCr 0:e6ceb13d2d05 567 else
GregCr 0:e6ceb13d2d05 568 {
GregCr 0:e6ceb13d2d05 569 Write( REG_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 570 }
GregCr 0:e6ceb13d2d05 571
GregCr 0:e6ceb13d2d05 572 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 573 {
GregCr 0:e6ceb13d2d05 574 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 575 }
GregCr 0:e6ceb13d2d05 576 else
GregCr 0:e6ceb13d2d05 577 {
GregCr 0:e6ceb13d2d05 578 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 579 }
GregCr 0:e6ceb13d2d05 580
GregCr 0:e6ceb13d2d05 581 // Write payload buffer
GregCr 0:e6ceb13d2d05 582 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 583 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 584 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 585 }
GregCr 0:e6ceb13d2d05 586 break;
GregCr 0:e6ceb13d2d05 587 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 588 {
GregCr 0:e6ceb13d2d05 589 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 590 {
GregCr 0:e6ceb13d2d05 591 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
GregCr 0:e6ceb13d2d05 592 }
GregCr 0:e6ceb13d2d05 593 else
GregCr 0:e6ceb13d2d05 594 {
GregCr 0:e6ceb13d2d05 595 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 596 }
GregCr 0:e6ceb13d2d05 597
GregCr 0:e6ceb13d2d05 598 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 599
GregCr 0:e6ceb13d2d05 600 // Initializes the payload size
GregCr 0:e6ceb13d2d05 601 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 602
GregCr 0:e6ceb13d2d05 603 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 604 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 605 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 606
GregCr 0:e6ceb13d2d05 607 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 608 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 609 {
GregCr 0:e6ceb13d2d05 610 Standby( );
GregCr 4:f0ce52e94d3f 611 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 612 }
GregCr 0:e6ceb13d2d05 613 // Write payload buffer
GregCr 0:e6ceb13d2d05 614 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 615 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 616 }
GregCr 0:e6ceb13d2d05 617 break;
GregCr 0:e6ceb13d2d05 618 }
GregCr 0:e6ceb13d2d05 619
GregCr 0:e6ceb13d2d05 620 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 621 }
GregCr 0:e6ceb13d2d05 622
netblocks 17:a5c9fd1a1ea6 623 void SX1272::Sleep( void )
GregCr 0:e6ceb13d2d05 624 {
mluis 13:618826a997e2 625 // Initialize driver timeout timers
mluis 13:618826a997e2 626 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 627 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 628 SetOpMode( RF_OPMODE_SLEEP );
netblocks 17:a5c9fd1a1ea6 629 //SX1272.Settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 630 }
GregCr 0:e6ceb13d2d05 631
netblocks 17:a5c9fd1a1ea6 632 void SX1272::Standby( void )
GregCr 0:e6ceb13d2d05 633 {
GregCr 0:e6ceb13d2d05 634 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 635 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 636 SetOpMode( RF_OPMODE_STANDBY );
netblocks 17:a5c9fd1a1ea6 637 //SX1272.Settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 638 }
GregCr 0:e6ceb13d2d05 639
netblocks 17:a5c9fd1a1ea6 640 void SX1272::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 641 {
GregCr 0:e6ceb13d2d05 642 bool rxContinuous = false;
netblocks 17:a5c9fd1a1ea6 643
GregCr 0:e6ceb13d2d05 644 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 645 {
GregCr 0:e6ceb13d2d05 646 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 647 {
GregCr 0:e6ceb13d2d05 648 rxContinuous = this->settings.Fsk.RxContinuous;
GregCr 0:e6ceb13d2d05 649
GregCr 0:e6ceb13d2d05 650 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 651 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 652 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 653 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 654 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 655 // DIO5=ModeReady
netblocks 17:a5c9fd1a1ea6 656 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
GregCr 0:e6ceb13d2d05 657 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 658 RF_DIOMAPPING1_DIO0_00 |
GregCr 0:e6ceb13d2d05 659 RF_DIOMAPPING1_DIO2_11 );
GregCr 0:e6ceb13d2d05 660
GregCr 0:e6ceb13d2d05 661 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 662 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 663 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 664 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
netblocks 17:a5c9fd1a1ea6 665
GregCr 0:e6ceb13d2d05 666 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
netblocks 17:a5c9fd1a1ea6 667
GregCr 0:e6ceb13d2d05 668 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 669 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 670 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 671 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 672 }
GregCr 0:e6ceb13d2d05 673 break;
GregCr 0:e6ceb13d2d05 674 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 675 {
GregCr 0:e6ceb13d2d05 676 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 677 {
GregCr 0:e6ceb13d2d05 678 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 679 }
GregCr 0:e6ceb13d2d05 680 else
GregCr 0:e6ceb13d2d05 681 {
GregCr 0:e6ceb13d2d05 682 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 683 }
GregCr 0:e6ceb13d2d05 684
GregCr 0:e6ceb13d2d05 685 rxContinuous = this->settings.LoRa.RxContinuous;
netblocks 17:a5c9fd1a1ea6 686
GregCr 6:e7f02929cd3d 687 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 688 {
GregCr 6:e7f02929cd3d 689 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
netblocks 17:a5c9fd1a1ea6 690 //RFLR_IRQFLAGS_RXDONE |
netblocks 17:a5c9fd1a1ea6 691 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
netblocks 17:a5c9fd1a1ea6 692 RFLR_IRQFLAGS_VALIDHEADER |
netblocks 17:a5c9fd1a1ea6 693 RFLR_IRQFLAGS_TXDONE |
netblocks 17:a5c9fd1a1ea6 694 RFLR_IRQFLAGS_CADDONE |
netblocks 17:a5c9fd1a1ea6 695 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
netblocks 17:a5c9fd1a1ea6 696 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 697
mluis 13:618826a997e2 698 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 699 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 700 }
GregCr 6:e7f02929cd3d 701 else
GregCr 6:e7f02929cd3d 702 {
GregCr 6:e7f02929cd3d 703 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
netblocks 17:a5c9fd1a1ea6 704 //RFLR_IRQFLAGS_RXDONE |
netblocks 17:a5c9fd1a1ea6 705 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
netblocks 17:a5c9fd1a1ea6 706 RFLR_IRQFLAGS_VALIDHEADER |
netblocks 17:a5c9fd1a1ea6 707 RFLR_IRQFLAGS_TXDONE |
netblocks 17:a5c9fd1a1ea6 708 RFLR_IRQFLAGS_CADDONE |
netblocks 17:a5c9fd1a1ea6 709 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
netblocks 17:a5c9fd1a1ea6 710 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 711
GregCr 6:e7f02929cd3d 712 // DIO0=RxDone
GregCr 6:e7f02929cd3d 713 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 714 }
GregCr 0:e6ceb13d2d05 715 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 716 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 717 }
GregCr 0:e6ceb13d2d05 718 break;
GregCr 0:e6ceb13d2d05 719 }
GregCr 0:e6ceb13d2d05 720
netblocks 17:a5c9fd1a1ea6 721 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 722
GregCr 0:e6ceb13d2d05 723 this->settings.State = RX;
GregCr 0:e6ceb13d2d05 724 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 725 {
netblocks 17:a5c9fd1a1ea6 726 rxTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 727 }
GregCr 0:e6ceb13d2d05 728
GregCr 0:e6ceb13d2d05 729 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 730 {
GregCr 0:e6ceb13d2d05 731 SetOpMode( RF_OPMODE_RECEIVER );
netblocks 17:a5c9fd1a1ea6 732
GregCr 0:e6ceb13d2d05 733 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 734 {
netblocks 17:a5c9fd1a1ea6 735 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 736 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 737 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 738 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 739 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 740 }
netblocks 17:a5c9fd1a1ea6 741
GregCr 0:e6ceb13d2d05 742 }
GregCr 0:e6ceb13d2d05 743 else
GregCr 0:e6ceb13d2d05 744 {
GregCr 0:e6ceb13d2d05 745 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 746 {
GregCr 0:e6ceb13d2d05 747 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 748 }
GregCr 0:e6ceb13d2d05 749 else
GregCr 0:e6ceb13d2d05 750 {
GregCr 0:e6ceb13d2d05 751 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 752 }
GregCr 0:e6ceb13d2d05 753 }
GregCr 0:e6ceb13d2d05 754 }
GregCr 0:e6ceb13d2d05 755
netblocks 17:a5c9fd1a1ea6 756 void SX1272::Tx( uint32_t timeout )
netblocks 17:a5c9fd1a1ea6 757 {
netblocks 17:a5c9fd1a1ea6 758
GregCr 0:e6ceb13d2d05 759 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 760 {
GregCr 0:e6ceb13d2d05 761 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 762 {
GregCr 0:e6ceb13d2d05 763 // DIO0=PacketSent
GregCr 0:e6ceb13d2d05 764 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 765 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 766 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 767 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 768 // DIO5=ModeReady
netblocks 17:a5c9fd1a1ea6 769 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
GregCr 0:e6ceb13d2d05 770 RF_DIOMAPPING1_DIO2_MASK ) );
GregCr 0:e6ceb13d2d05 771
GregCr 0:e6ceb13d2d05 772 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 773 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 774 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 775 }
GregCr 0:e6ceb13d2d05 776 break;
GregCr 0:e6ceb13d2d05 777 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 778 {
GregCr 6:e7f02929cd3d 779 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 780 {
GregCr 6:e7f02929cd3d 781 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
netblocks 17:a5c9fd1a1ea6 782 RFLR_IRQFLAGS_RXDONE |
netblocks 17:a5c9fd1a1ea6 783 RFLR_IRQFLAGS_PAYLOADCRCERROR |
netblocks 17:a5c9fd1a1ea6 784 RFLR_IRQFLAGS_VALIDHEADER |
netblocks 17:a5c9fd1a1ea6 785 //RFLR_IRQFLAGS_TXDONE |
netblocks 17:a5c9fd1a1ea6 786 RFLR_IRQFLAGS_CADDONE |
netblocks 17:a5c9fd1a1ea6 787 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
netblocks 17:a5c9fd1a1ea6 788 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 789
netblocks 17:a5c9fd1a1ea6 790 // DIO0=TxDone, DIO2=FhssChangeChannel
netblocks 17:a5c9fd1a1ea6 791 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 792 }
GregCr 6:e7f02929cd3d 793 else
GregCr 6:e7f02929cd3d 794 {
GregCr 6:e7f02929cd3d 795 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
netblocks 17:a5c9fd1a1ea6 796 RFLR_IRQFLAGS_RXDONE |
netblocks 17:a5c9fd1a1ea6 797 RFLR_IRQFLAGS_PAYLOADCRCERROR |
netblocks 17:a5c9fd1a1ea6 798 RFLR_IRQFLAGS_VALIDHEADER |
netblocks 17:a5c9fd1a1ea6 799 //RFLR_IRQFLAGS_TXDONE |
netblocks 17:a5c9fd1a1ea6 800 RFLR_IRQFLAGS_CADDONE |
netblocks 17:a5c9fd1a1ea6 801 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
netblocks 17:a5c9fd1a1ea6 802 RFLR_IRQFLAGS_CADDETECTED );
netblocks 17:a5c9fd1a1ea6 803
GregCr 6:e7f02929cd3d 804 // DIO0=TxDone
netblocks 17:a5c9fd1a1ea6 805 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 806 }
GregCr 0:e6ceb13d2d05 807 }
GregCr 0:e6ceb13d2d05 808 break;
GregCr 0:e6ceb13d2d05 809 }
GregCr 0:e6ceb13d2d05 810
netblocks 17:a5c9fd1a1ea6 811 this->settings.State = TX;
netblocks 17:a5c9fd1a1ea6 812 txTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
netblocks 17:a5c9fd1a1ea6 813 SetOpMode( RF_OPMODE_TRANSMITTER );
netblocks 17:a5c9fd1a1ea6 814
GregCr 0:e6ceb13d2d05 815 }
GregCr 0:e6ceb13d2d05 816
netblocks 17:a5c9fd1a1ea6 817 void SX1272::StartCad( void )
GregCr 0:e6ceb13d2d05 818 {
GregCr 7:2b555111463f 819 switch( this->settings.Modem )
GregCr 7:2b555111463f 820 {
GregCr 7:2b555111463f 821 case MODEM_FSK:
GregCr 7:2b555111463f 822 {
GregCr 7:2b555111463f 823
GregCr 7:2b555111463f 824 }
GregCr 7:2b555111463f 825 break;
GregCr 7:2b555111463f 826 case MODEM_LORA:
GregCr 7:2b555111463f 827 {
GregCr 7:2b555111463f 828 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 829 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 830 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 831 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 832 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 833 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 834 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
GregCr 12:aa5b3bf7fdf4 835 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 836 );
GregCr 7:2b555111463f 837
GregCr 7:2b555111463f 838 // DIO3=CADDone
GregCr 7:2b555111463f 839 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 7:2b555111463f 840
GregCr 7:2b555111463f 841 this->settings.State = CAD;
GregCr 7:2b555111463f 842 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 843 }
GregCr 7:2b555111463f 844 break;
GregCr 7:2b555111463f 845 default:
GregCr 7:2b555111463f 846 break;
GregCr 7:2b555111463f 847 }
GregCr 7:2b555111463f 848 }
GregCr 7:2b555111463f 849
netblocks 17:a5c9fd1a1ea6 850
netblocks 17:a5c9fd1a1ea6 851 int16_t SX1272::GetRssi( ModemType modem )
GregCr 7:2b555111463f 852 {
netblocks 17:a5c9fd1a1ea6 853 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 854
GregCr 0:e6ceb13d2d05 855 switch( modem )
GregCr 0:e6ceb13d2d05 856 {
GregCr 0:e6ceb13d2d05 857 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 858 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 859 break;
GregCr 0:e6ceb13d2d05 860 case MODEM_LORA:
netblocks 17:a5c9fd1a1ea6 861 rssi = RSSI_OFFSET + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 862 break;
GregCr 0:e6ceb13d2d05 863 default:
GregCr 0:e6ceb13d2d05 864 rssi = -1;
GregCr 0:e6ceb13d2d05 865 break;
GregCr 0:e6ceb13d2d05 866 }
GregCr 0:e6ceb13d2d05 867 return rssi;
netblocks 17:a5c9fd1a1ea6 868
GregCr 0:e6ceb13d2d05 869 }
GregCr 0:e6ceb13d2d05 870
netblocks 17:a5c9fd1a1ea6 871 void SX1272::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 872 {
GregCr 0:e6ceb13d2d05 873 if( opMode != previousOpMode )
GregCr 0:e6ceb13d2d05 874 {
GregCr 0:e6ceb13d2d05 875 previousOpMode = opMode;
GregCr 0:e6ceb13d2d05 876 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 877 {
GregCr 0:e6ceb13d2d05 878 SetAntSwLowPower( true );
GregCr 0:e6ceb13d2d05 879 }
GregCr 0:e6ceb13d2d05 880 else
GregCr 0:e6ceb13d2d05 881 {
GregCr 0:e6ceb13d2d05 882 SetAntSwLowPower( false );
GregCr 0:e6ceb13d2d05 883 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 884 {
GregCr 0:e6ceb13d2d05 885 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 886 }
GregCr 0:e6ceb13d2d05 887 else
GregCr 0:e6ceb13d2d05 888 {
GregCr 0:e6ceb13d2d05 889 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 890 }
GregCr 0:e6ceb13d2d05 891 }
GregCr 0:e6ceb13d2d05 892 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 893 }
GregCr 0:e6ceb13d2d05 894 }
GregCr 0:e6ceb13d2d05 895
netblocks 17:a5c9fd1a1ea6 896 void SX1272::SetModem( ModemType modem )
GregCr 0:e6ceb13d2d05 897 {
netblocks 17:a5c9fd1a1ea6 898 if( this->settings.Modem == modem )
netblocks 17:a5c9fd1a1ea6 899 {
netblocks 17:a5c9fd1a1ea6 900 return;
netblocks 17:a5c9fd1a1ea6 901 }
netblocks 17:a5c9fd1a1ea6 902
netblocks 17:a5c9fd1a1ea6 903 this->settings.Modem = modem;
netblocks 17:a5c9fd1a1ea6 904 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 905 {
netblocks 17:a5c9fd1a1ea6 906 default:
netblocks 17:a5c9fd1a1ea6 907 case MODEM_FSK:
netblocks 17:a5c9fd1a1ea6 908 SetOpMode( RF_OPMODE_SLEEP );
netblocks 17:a5c9fd1a1ea6 909 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
netblocks 17:a5c9fd1a1ea6 910
netblocks 17:a5c9fd1a1ea6 911 Write( REG_DIOMAPPING1, 0x00 );
netblocks 17:a5c9fd1a1ea6 912 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
netblocks 17:a5c9fd1a1ea6 913 break;
netblocks 17:a5c9fd1a1ea6 914 case MODEM_LORA:
netblocks 17:a5c9fd1a1ea6 915 SetOpMode( RF_OPMODE_SLEEP );
netblocks 17:a5c9fd1a1ea6 916 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
netblocks 17:a5c9fd1a1ea6 917
netblocks 17:a5c9fd1a1ea6 918 Write( REG_DIOMAPPING1, 0x00 );
netblocks 17:a5c9fd1a1ea6 919 Write( REG_DIOMAPPING2, 0x00 );
netblocks 17:a5c9fd1a1ea6 920 break;
GregCr 0:e6ceb13d2d05 921 }
GregCr 0:e6ceb13d2d05 922 }
GregCr 0:e6ceb13d2d05 923
netblocks 17:a5c9fd1a1ea6 924 void SX1272::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 925 {
GregCr 0:e6ceb13d2d05 926 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 927 {
GregCr 0:e6ceb13d2d05 928 case RX:
GregCr 0:e6ceb13d2d05 929 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 930 {
GregCr 0:e6ceb13d2d05 931 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 932 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 933 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 934 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 935
GregCr 0:e6ceb13d2d05 936 // Clear Irqs
GregCr 0:e6ceb13d2d05 937 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 938 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 939 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 940 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 941
GregCr 0:e6ceb13d2d05 942 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 943 {
GregCr 0:e6ceb13d2d05 944 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 945 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 946 }
GregCr 0:e6ceb13d2d05 947 else
GregCr 0:e6ceb13d2d05 948 {
GregCr 5:11ec8a6ba4f0 949 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 950 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 951 }
GregCr 0:e6ceb13d2d05 952 }
GregCr 0:e6ceb13d2d05 953 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 954 {
GregCr 0:e6ceb13d2d05 955 rxTimeout( );
GregCr 0:e6ceb13d2d05 956 }
GregCr 0:e6ceb13d2d05 957 break;
GregCr 0:e6ceb13d2d05 958 case TX:
mluis 13:618826a997e2 959 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 960 if( ( txTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 961 {
GregCr 0:e6ceb13d2d05 962 txTimeout( );
GregCr 0:e6ceb13d2d05 963 }
GregCr 0:e6ceb13d2d05 964 break;
GregCr 0:e6ceb13d2d05 965 default:
GregCr 0:e6ceb13d2d05 966 break;
GregCr 0:e6ceb13d2d05 967 }
GregCr 0:e6ceb13d2d05 968 }
GregCr 0:e6ceb13d2d05 969
netblocks 17:a5c9fd1a1ea6 970 void SX1272::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 971 {
GregCr 0:e6ceb13d2d05 972 __IO uint8_t irqFlags = 0;
netblocks 17:a5c9fd1a1ea6 973
GregCr 0:e6ceb13d2d05 974 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 975 {
GregCr 0:e6ceb13d2d05 976 case RX:
GregCr 0:e6ceb13d2d05 977 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 978 // RxDone interrupt
GregCr 0:e6ceb13d2d05 979 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 980 {
GregCr 0:e6ceb13d2d05 981 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 982 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 0:e6ceb13d2d05 983 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 984 {
GregCr 0:e6ceb13d2d05 985 // Clear Irqs
GregCr 0:e6ceb13d2d05 986 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 987 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 988 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 989 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 990
GregCr 0:e6ceb13d2d05 991 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 992 {
netblocks 17:a5c9fd1a1ea6 993 //this->settings.State = RF_IDLE;
netblocks 17:a5c9fd1a1ea6 994 //TimerStart( &RxTimeoutSyncWord );
netblocks 17:a5c9fd1a1ea6 995 this->settings.State = IDLE;
netblocks 17:a5c9fd1a1ea6 996 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 997 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 998 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 999 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1000 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
netblocks 17:a5c9fd1a1ea6 1001
GregCr 0:e6ceb13d2d05 1002 }
GregCr 0:e6ceb13d2d05 1003 else
GregCr 0:e6ceb13d2d05 1004 {
GregCr 0:e6ceb13d2d05 1005 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1006 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1007 }
netblocks 17:a5c9fd1a1ea6 1008
netblocks 17:a5c9fd1a1ea6 1009 //TimerStop( &RxTimeoutTimer );
netblocks 17:a5c9fd1a1ea6 1010 rxTimeoutTimer.detach( );
netblocks 17:a5c9fd1a1ea6 1011
GregCr 0:e6ceb13d2d05 1012 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1013 {
GregCr 0:e6ceb13d2d05 1014 rxError( );
GregCr 0:e6ceb13d2d05 1015 }
netblocks 17:a5c9fd1a1ea6 1016
GregCr 0:e6ceb13d2d05 1017 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1018 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1019 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1020 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1021 break;
GregCr 0:e6ceb13d2d05 1022 }
GregCr 0:e6ceb13d2d05 1023
GregCr 0:e6ceb13d2d05 1024 // Read received packet size
GregCr 0:e6ceb13d2d05 1025 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1026 {
GregCr 0:e6ceb13d2d05 1027 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1028 {
GregCr 0:e6ceb13d2d05 1029 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1030 }
GregCr 0:e6ceb13d2d05 1031 else
GregCr 0:e6ceb13d2d05 1032 {
GregCr 0:e6ceb13d2d05 1033 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1034 }
GregCr 0:e6ceb13d2d05 1035 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1036 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1037 }
GregCr 0:e6ceb13d2d05 1038 else
GregCr 0:e6ceb13d2d05 1039 {
GregCr 0:e6ceb13d2d05 1040 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1041 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1042 }
GregCr 0:e6ceb13d2d05 1043
GregCr 0:e6ceb13d2d05 1044 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1045 {
GregCr 0:e6ceb13d2d05 1046 this->settings.State = IDLE;
netblocks 17:a5c9fd1a1ea6 1047 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1048 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1049 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1050 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1051 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1052 }
GregCr 0:e6ceb13d2d05 1053 else
GregCr 0:e6ceb13d2d05 1054 {
GregCr 0:e6ceb13d2d05 1055 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1056 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1057 }
GregCr 0:e6ceb13d2d05 1058 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1059
GregCr 0:e6ceb13d2d05 1060 if( (rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1061 {
GregCr 0:e6ceb13d2d05 1062 rxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
GregCr 0:e6ceb13d2d05 1063 }
GregCr 0:e6ceb13d2d05 1064 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1065 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1066 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1067 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1068 break;
netblocks 17:a5c9fd1a1ea6 1069
GregCr 0:e6ceb13d2d05 1070 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1071 {
netblocks 17:a5c9fd1a1ea6 1072 int8_t snr = 0;
GregCr 0:e6ceb13d2d05 1073
GregCr 0:e6ceb13d2d05 1074 // Clear Irq
GregCr 0:e6ceb13d2d05 1075 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1076
GregCr 0:e6ceb13d2d05 1077 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1078 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1079 {
GregCr 0:e6ceb13d2d05 1080 // Clear Irq
GregCr 0:e6ceb13d2d05 1081 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
netblocks 17:a5c9fd1a1ea6 1082
GregCr 0:e6ceb13d2d05 1083 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1084 {
GregCr 0:e6ceb13d2d05 1085 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1086 }
GregCr 0:e6ceb13d2d05 1087 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1088
GregCr 4:f0ce52e94d3f 1089 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1090 {
GregCr 0:e6ceb13d2d05 1091 rxError( );
GregCr 0:e6ceb13d2d05 1092 }
netblocks 17:a5c9fd1a1ea6 1093
GregCr 0:e6ceb13d2d05 1094 break;
GregCr 0:e6ceb13d2d05 1095 }
GregCr 0:e6ceb13d2d05 1096
GregCr 0:e6ceb13d2d05 1097 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1098 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1099 {
GregCr 0:e6ceb13d2d05 1100 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1101 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1102 snr = -snr;
GregCr 0:e6ceb13d2d05 1103 }
GregCr 0:e6ceb13d2d05 1104 else
GregCr 0:e6ceb13d2d05 1105 {
GregCr 0:e6ceb13d2d05 1106 // Divide by 4
GregCr 0:e6ceb13d2d05 1107 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1108 }
GregCr 0:e6ceb13d2d05 1109
GregCr 7:2b555111463f 1110 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
netblocks 17:a5c9fd1a1ea6 1111 if( snr < 0 )
GregCr 0:e6ceb13d2d05 1112 {
netblocks 17:a5c9fd1a1ea6 1113 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ) +
netblocks 17:a5c9fd1a1ea6 1114 snr;
GregCr 0:e6ceb13d2d05 1115 }
GregCr 0:e6ceb13d2d05 1116 else
GregCr 0:e6ceb13d2d05 1117 {
netblocks 17:a5c9fd1a1ea6 1118 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1119 }
GregCr 0:e6ceb13d2d05 1120
GregCr 0:e6ceb13d2d05 1121 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 0:e6ceb13d2d05 1122 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
GregCr 0:e6ceb13d2d05 1123
netblocks 17:a5c9fd1a1ea6 1124
GregCr 0:e6ceb13d2d05 1125 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1126 {
GregCr 0:e6ceb13d2d05 1127 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1128 }
GregCr 0:e6ceb13d2d05 1129 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1130
GregCr 0:e6ceb13d2d05 1131 if( ( rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1132 {
GregCr 0:e6ceb13d2d05 1133 rxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
netblocks 17:a5c9fd1a1ea6 1134 }
GregCr 0:e6ceb13d2d05 1135 }
GregCr 0:e6ceb13d2d05 1136 break;
GregCr 0:e6ceb13d2d05 1137 default:
GregCr 0:e6ceb13d2d05 1138 break;
GregCr 0:e6ceb13d2d05 1139 }
GregCr 0:e6ceb13d2d05 1140 break;
netblocks 17:a5c9fd1a1ea6 1141 case TX:
GregCr 0:e6ceb13d2d05 1142 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1143 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1144 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1145 {
GregCr 0:e6ceb13d2d05 1146 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1147 // Clear Irq
GregCr 0:e6ceb13d2d05 1148 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1149 // Intentional fall through
GregCr 0:e6ceb13d2d05 1150 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1151 default:
GregCr 0:e6ceb13d2d05 1152 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1153 if( ( txDone != NULL ) )
GregCr 0:e6ceb13d2d05 1154 {
GregCr 0:e6ceb13d2d05 1155 txDone( );
GregCr 0:e6ceb13d2d05 1156 }
GregCr 0:e6ceb13d2d05 1157 break;
GregCr 0:e6ceb13d2d05 1158 }
netblocks 17:a5c9fd1a1ea6 1159
GregCr 0:e6ceb13d2d05 1160 break;
GregCr 0:e6ceb13d2d05 1161 default:
GregCr 0:e6ceb13d2d05 1162 break;
GregCr 0:e6ceb13d2d05 1163 }
GregCr 0:e6ceb13d2d05 1164 }
GregCr 0:e6ceb13d2d05 1165
netblocks 17:a5c9fd1a1ea6 1166 void SX1272::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1167 {
GregCr 0:e6ceb13d2d05 1168 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1169 {
GregCr 0:e6ceb13d2d05 1170 case RX:
GregCr 0:e6ceb13d2d05 1171 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1172 {
GregCr 0:e6ceb13d2d05 1173 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1174 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1175 // Read received packet size
GregCr 0:e6ceb13d2d05 1176 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1177 {
GregCr 0:e6ceb13d2d05 1178 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1179 {
GregCr 0:e6ceb13d2d05 1180 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1181 }
GregCr 0:e6ceb13d2d05 1182 else
GregCr 0:e6ceb13d2d05 1183 {
GregCr 0:e6ceb13d2d05 1184 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1185 }
GregCr 0:e6ceb13d2d05 1186 }
GregCr 0:e6ceb13d2d05 1187
GregCr 0:e6ceb13d2d05 1188 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1189 {
GregCr 0:e6ceb13d2d05 1190 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1191 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1192 }
GregCr 0:e6ceb13d2d05 1193 else
GregCr 0:e6ceb13d2d05 1194 {
GregCr 0:e6ceb13d2d05 1195 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1196 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1197 }
GregCr 0:e6ceb13d2d05 1198 break;
GregCr 0:e6ceb13d2d05 1199 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1200 // Sync time out
GregCr 0:e6ceb13d2d05 1201 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1202 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1203 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1204 {
GregCr 0:e6ceb13d2d05 1205 rxTimeout( );
GregCr 0:e6ceb13d2d05 1206 }
GregCr 0:e6ceb13d2d05 1207 break;
GregCr 0:e6ceb13d2d05 1208 default:
GregCr 0:e6ceb13d2d05 1209 break;
GregCr 0:e6ceb13d2d05 1210 }
GregCr 0:e6ceb13d2d05 1211 break;
GregCr 0:e6ceb13d2d05 1212 case TX:
GregCr 0:e6ceb13d2d05 1213 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1214 {
GregCr 0:e6ceb13d2d05 1215 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1216 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1217 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1218 {
GregCr 0:e6ceb13d2d05 1219 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1220 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1221 }
GregCr 0:e6ceb13d2d05 1222 else
GregCr 0:e6ceb13d2d05 1223 {
GregCr 0:e6ceb13d2d05 1224 // Write the last chunk of data
GregCr 0:e6ceb13d2d05 1225 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1226 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1227 }
GregCr 0:e6ceb13d2d05 1228 break;
GregCr 0:e6ceb13d2d05 1229 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1230 break;
GregCr 0:e6ceb13d2d05 1231 default:
GregCr 0:e6ceb13d2d05 1232 break;
GregCr 0:e6ceb13d2d05 1233 }
GregCr 0:e6ceb13d2d05 1234 break;
GregCr 0:e6ceb13d2d05 1235 default:
GregCr 0:e6ceb13d2d05 1236 break;
GregCr 0:e6ceb13d2d05 1237 }
GregCr 0:e6ceb13d2d05 1238 }
GregCr 0:e6ceb13d2d05 1239
netblocks 17:a5c9fd1a1ea6 1240 void SX1272::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1241 {
GregCr 0:e6ceb13d2d05 1242 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1243 {
GregCr 0:e6ceb13d2d05 1244 case RX:
GregCr 0:e6ceb13d2d05 1245 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1246 {
GregCr 0:e6ceb13d2d05 1247 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1248 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1249 {
GregCr 0:e6ceb13d2d05 1250 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1251
GregCr 0:e6ceb13d2d05 1252 this->settings.FskPacketHandler.SyncWordDetected = true;
GregCr 0:e6ceb13d2d05 1253
GregCr 0:e6ceb13d2d05 1254 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1255
GregCr 0:e6ceb13d2d05 1256 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1257 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1258 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1259 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1260 }
GregCr 0:e6ceb13d2d05 1261 break;
GregCr 0:e6ceb13d2d05 1262 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1263 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1264 {
GregCr 6:e7f02929cd3d 1265 // Clear Irq
GregCr 6:e7f02929cd3d 1266 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1267
mluis 13:618826a997e2 1268 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1269 {
mluis 13:618826a997e2 1270 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1271 }
GregCr 6:e7f02929cd3d 1272 }
GregCr 0:e6ceb13d2d05 1273 break;
GregCr 0:e6ceb13d2d05 1274 default:
GregCr 0:e6ceb13d2d05 1275 break;
GregCr 0:e6ceb13d2d05 1276 }
GregCr 0:e6ceb13d2d05 1277 break;
GregCr 0:e6ceb13d2d05 1278 case TX:
GregCr 0:e6ceb13d2d05 1279 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1280 {
GregCr 0:e6ceb13d2d05 1281 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1282 break;
GregCr 0:e6ceb13d2d05 1283 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1284 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1285 {
GregCr 6:e7f02929cd3d 1286 // Clear Irq
GregCr 6:e7f02929cd3d 1287 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1288
mluis 13:618826a997e2 1289 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1290 {
mluis 13:618826a997e2 1291 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1292 }
GregCr 6:e7f02929cd3d 1293 }
GregCr 0:e6ceb13d2d05 1294 break;
GregCr 0:e6ceb13d2d05 1295 default:
GregCr 0:e6ceb13d2d05 1296 break;
GregCr 0:e6ceb13d2d05 1297 }
GregCr 0:e6ceb13d2d05 1298 break;
GregCr 0:e6ceb13d2d05 1299 default:
GregCr 0:e6ceb13d2d05 1300 break;
GregCr 0:e6ceb13d2d05 1301 }
GregCr 0:e6ceb13d2d05 1302 }
GregCr 0:e6ceb13d2d05 1303
netblocks 17:a5c9fd1a1ea6 1304 void SX1272::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1305 {
GregCr 0:e6ceb13d2d05 1306 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1307 {
GregCr 0:e6ceb13d2d05 1308 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1309 break;
GregCr 0:e6ceb13d2d05 1310 case MODEM_LORA:
mluis 13:618826a997e2 1311 if( ( Read( REG_LR_IRQFLAGS ) & 0x01 ) == 0x01 )
mluis 13:618826a997e2 1312 {
mluis 13:618826a997e2 1313 // Clear Irq
mluis 13:618826a997e2 1314 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED_MASK | RFLR_IRQFLAGS_CADDONE);
mluis 13:618826a997e2 1315 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1316 {
mluis 13:618826a997e2 1317 cadDone( true );
mluis 13:618826a997e2 1318 }
GregCr 12:aa5b3bf7fdf4 1319 }
GregCr 12:aa5b3bf7fdf4 1320 else
mluis 13:618826a997e2 1321 {
mluis 13:618826a997e2 1322 // Clear Irq
mluis 13:618826a997e2 1323 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 13:618826a997e2 1324 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1325 {
mluis 13:618826a997e2 1326 cadDone( false );
mluis 13:618826a997e2 1327 }
GregCr 7:2b555111463f 1328 }
GregCr 0:e6ceb13d2d05 1329 break;
GregCr 0:e6ceb13d2d05 1330 default:
GregCr 0:e6ceb13d2d05 1331 break;
GregCr 0:e6ceb13d2d05 1332 }
GregCr 0:e6ceb13d2d05 1333 }
GregCr 0:e6ceb13d2d05 1334
netblocks 17:a5c9fd1a1ea6 1335 void SX1272::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1336 {
GregCr 0:e6ceb13d2d05 1337 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1338 {
GregCr 0:e6ceb13d2d05 1339 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1340 {
GregCr 0:e6ceb13d2d05 1341 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1342 {
GregCr 0:e6ceb13d2d05 1343 this->settings.FskPacketHandler.PreambleDetected = true;
GregCr 0:e6ceb13d2d05 1344 }
GregCr 0:e6ceb13d2d05 1345 }
GregCr 0:e6ceb13d2d05 1346 break;
GregCr 0:e6ceb13d2d05 1347 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1348 break;
GregCr 0:e6ceb13d2d05 1349 default:
GregCr 0:e6ceb13d2d05 1350 break;
GregCr 0:e6ceb13d2d05 1351 }
GregCr 0:e6ceb13d2d05 1352 }
GregCr 0:e6ceb13d2d05 1353
netblocks 17:a5c9fd1a1ea6 1354 void SX1272::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1355 {
GregCr 0:e6ceb13d2d05 1356 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1357 {
GregCr 0:e6ceb13d2d05 1358 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1359 break;
GregCr 0:e6ceb13d2d05 1360 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1361 break;
GregCr 0:e6ceb13d2d05 1362 default:
GregCr 0:e6ceb13d2d05 1363 break;
GregCr 0:e6ceb13d2d05 1364 }
mluis 13:618826a997e2 1365 }