Neri Tiziano / X_NUCLEO_IHM03A1_for

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Dependencies:   X_NUCLEO_COMMON ST_INTERFACES

Components/powerstep01/powerstep01.h@0:00a3c3f5a8f0, 2016-04-05 (annotated)

Committer:
nucleosam
Date:
Tue Apr 05 15:18:56 2016 +0000
Revision:
0:00a3c3f5a8f0
Child:
1:8ce2a5d6fbf8
Initial version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nucleosam 0:00a3c3f5a8f0 1 /**
nucleosam 0:00a3c3f5a8f0 2 ******************************************************************************
nucleosam 0:00a3c3f5a8f0 3 * @file powerstep01.h
nucleosam 0:00a3c3f5a8f0 4 * @author IPC Rennes
nucleosam 0:00a3c3f5a8f0 5 * @version V1.2.0
nucleosam 0:00a3c3f5a8f0 6 * @date January 25th, 2016
nucleosam 0:00a3c3f5a8f0 7 * @brief Header for Powerstep01 motor driver (Microstepping controller with power MOSFETs)
nucleosam 0:00a3c3f5a8f0 8 * @note (C) COPYRIGHT 2016 STMicroelectronics
nucleosam 0:00a3c3f5a8f0 9 ******************************************************************************
nucleosam 0:00a3c3f5a8f0 10 * @attention
nucleosam 0:00a3c3f5a8f0 11 *
nucleosam 0:00a3c3f5a8f0 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
nucleosam 0:00a3c3f5a8f0 13 *
nucleosam 0:00a3c3f5a8f0 14 * Redistribution and use in source and binary forms, with or without modification,
nucleosam 0:00a3c3f5a8f0 15 * are permitted provided that the following conditions are met:
nucleosam 0:00a3c3f5a8f0 16 * 1. Redistributions of source code must retain the above copyright notice,
nucleosam 0:00a3c3f5a8f0 17 * this list of conditions and the following disclaimer.
nucleosam 0:00a3c3f5a8f0 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
nucleosam 0:00a3c3f5a8f0 19 * this list of conditions and the following disclaimer in the documentation
nucleosam 0:00a3c3f5a8f0 20 * and/or other materials provided with the distribution.
nucleosam 0:00a3c3f5a8f0 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
nucleosam 0:00a3c3f5a8f0 22 * may be used to endorse or promote products derived from this software
nucleosam 0:00a3c3f5a8f0 23 * without specific prior written permission.
nucleosam 0:00a3c3f5a8f0 24 *
nucleosam 0:00a3c3f5a8f0 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
nucleosam 0:00a3c3f5a8f0 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
nucleosam 0:00a3c3f5a8f0 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
nucleosam 0:00a3c3f5a8f0 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
nucleosam 0:00a3c3f5a8f0 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
nucleosam 0:00a3c3f5a8f0 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
nucleosam 0:00a3c3f5a8f0 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
nucleosam 0:00a3c3f5a8f0 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
nucleosam 0:00a3c3f5a8f0 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
nucleosam 0:00a3c3f5a8f0 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
nucleosam 0:00a3c3f5a8f0 35 *
nucleosam 0:00a3c3f5a8f0 36 ******************************************************************************
nucleosam 0:00a3c3f5a8f0 37 */
nucleosam 0:00a3c3f5a8f0 38
nucleosam 0:00a3c3f5a8f0 39 /* Define to prevent recursive inclusion -------------------------------------*/
nucleosam 0:00a3c3f5a8f0 40 #ifndef _POWERSTEP01_H_INCLUDED
nucleosam 0:00a3c3f5a8f0 41 #define _POWERSTEP01_H_INCLUDED
nucleosam 0:00a3c3f5a8f0 42
nucleosam 0:00a3c3f5a8f0 43 #ifdef __cplusplus
nucleosam 0:00a3c3f5a8f0 44 extern "C" {
nucleosam 0:00a3c3f5a8f0 45 #endif
nucleosam 0:00a3c3f5a8f0 46
nucleosam 0:00a3c3f5a8f0 47 /* Includes ------------------------------------------------------------------*/
nucleosam 0:00a3c3f5a8f0 48 #include "powerstep01_target_config.h"
nucleosam 0:00a3c3f5a8f0 49 #include "stdint.h"
nucleosam 0:00a3c3f5a8f0 50 #include "motor.h"
nucleosam 0:00a3c3f5a8f0 51
nucleosam 0:00a3c3f5a8f0 52 /* Definitions ---------------------------------------------------------------*/
nucleosam 0:00a3c3f5a8f0 53
nucleosam 0:00a3c3f5a8f0 54 /** @addtogroup Components
nucleosam 0:00a3c3f5a8f0 55 * @{
nucleosam 0:00a3c3f5a8f0 56 */
nucleosam 0:00a3c3f5a8f0 57
nucleosam 0:00a3c3f5a8f0 58 /** @defgroup POWERSTEP01 POWERSTEP01
nucleosam 0:00a3c3f5a8f0 59 * @{
nucleosam 0:00a3c3f5a8f0 60 */
nucleosam 0:00a3c3f5a8f0 61
nucleosam 0:00a3c3f5a8f0 62 /** @defgroup Powerstep01_Exported_Defines Powerstep01_Exported_Defines
nucleosam 0:00a3c3f5a8f0 63 * @{
nucleosam 0:00a3c3f5a8f0 64 */
nucleosam 0:00a3c3f5a8f0 65 /// Current FW version
nucleosam 0:00a3c3f5a8f0 66 #define POWERSTEP01_FW_VERSION (2)
nucleosam 0:00a3c3f5a8f0 67
nucleosam 0:00a3c3f5a8f0 68 /// Powerstep01 max number of bytes of command & arguments to set a parameter
nucleosam 0:00a3c3f5a8f0 69 #define POWERSTEP01_CMD_ARG_MAX_NB_BYTES (4)
nucleosam 0:00a3c3f5a8f0 70
nucleosam 0:00a3c3f5a8f0 71 /// Powerstep01 command + argument bytes number for NOP command
nucleosam 0:00a3c3f5a8f0 72 #define POWERSTEP01_CMD_ARG_NB_BYTES_NOP (1)
nucleosam 0:00a3c3f5a8f0 73 /// Powerstep01 command + argument bytes number for RUN command
nucleosam 0:00a3c3f5a8f0 74 #define POWERSTEP01_CMD_ARG_NB_BYTES_RUN (4)
nucleosam 0:00a3c3f5a8f0 75 /// Powerstep01 command + argument bytes number for STEP_CLOCK command
nucleosam 0:00a3c3f5a8f0 76 #define POWERSTEP01_CMD_ARG_NB_BYTES_STEP_CLOCK (1)
nucleosam 0:00a3c3f5a8f0 77 /// Powerstep01 command + argument bytes number for MOVE command
nucleosam 0:00a3c3f5a8f0 78 #define POWERSTEP01_CMD_ARG_NB_BYTES_MOVE (4)
nucleosam 0:00a3c3f5a8f0 79 /// Powerstep01 command + argument bytes number for GO_TO command
nucleosam 0:00a3c3f5a8f0 80 #define POWERSTEP01_CMD_ARG_NB_BYTES_GO_TO (4)
nucleosam 0:00a3c3f5a8f0 81 /// Powerstep01 command + argument bytes number for GO_TO_DIR command
nucleosam 0:00a3c3f5a8f0 82 #define POWERSTEP01_CMD_ARG_NB_BYTES_GO_TO_DIR (4)
nucleosam 0:00a3c3f5a8f0 83 /// Powerstep01 command + argument bytes number for GO_UNTIL command
nucleosam 0:00a3c3f5a8f0 84 #define POWERSTEP01_CMD_ARG_NB_BYTES_GO_UNTIL (4)
nucleosam 0:00a3c3f5a8f0 85 /// Powerstep01 command + argument bytes number for RELEASE_SW command
nucleosam 0:00a3c3f5a8f0 86 #define POWERSTEP01_CMD_ARG_NB_BYTES_RELEASE_SW (1)
nucleosam 0:00a3c3f5a8f0 87 /// Powerstep01 command + argument bytes number for GO_HOME command
nucleosam 0:00a3c3f5a8f0 88 #define POWERSTEP01_CMD_ARG_NB_BYTES_GO_HOME (1)
nucleosam 0:00a3c3f5a8f0 89 /// Powerstep01 command + argument bytes number for GO_MARK command
nucleosam 0:00a3c3f5a8f0 90 #define POWERSTEP01_CMD_ARG_NB_BYTES_GO_MARK (1)
nucleosam 0:00a3c3f5a8f0 91 /// Powerstep01 command + argument bytes number for RESET_POS command
nucleosam 0:00a3c3f5a8f0 92 #define POWERSTEP01_CMD_ARG_NB_BYTES_RESET_POS (1)
nucleosam 0:00a3c3f5a8f0 93 /// Powerstep01 command + argument bytes number for RESET_DEVICE command
nucleosam 0:00a3c3f5a8f0 94 #define POWERSTEP01_CMD_ARG_NB_BYTES_RESET_DEVICE (1)
nucleosam 0:00a3c3f5a8f0 95 /// Powerstep01 command + argument bytes number for NOP command
nucleosam 0:00a3c3f5a8f0 96 #define POWERSTEP01_CMD_ARG_NB_BYTES_SOFT_STOP (1)
nucleosam 0:00a3c3f5a8f0 97 /// Powerstep01 command + argument bytes number for HARD_STOP command
nucleosam 0:00a3c3f5a8f0 98 #define POWERSTEP01_CMD_ARG_NB_BYTES_HARD_STOP (1)
nucleosam 0:00a3c3f5a8f0 99 /// Powerstep01 command + argument bytes number for SOFT_HIZ command
nucleosam 0:00a3c3f5a8f0 100 #define POWERSTEP01_CMD_ARG_NB_BYTES_SOFT_HIZ (1)
nucleosam 0:00a3c3f5a8f0 101 /// Powerstep01 command + argument bytes number for ARD_HIZ command
nucleosam 0:00a3c3f5a8f0 102 #define POWERSTEP01_CMD_ARG_NB_BYTES_HARD_HIZ (1)
nucleosam 0:00a3c3f5a8f0 103 /// Powerstep01 command + argument bytes number for GET_STATUS command
nucleosam 0:00a3c3f5a8f0 104 #define POWERSTEP01_CMD_ARG_NB_BYTES_GET_STATUS (1)
nucleosam 0:00a3c3f5a8f0 105
nucleosam 0:00a3c3f5a8f0 106 /// Powerstep01 response bytes number
nucleosam 0:00a3c3f5a8f0 107 #define POWERSTEP01_RSP_NB_BYTES_GET_STATUS (2)
nucleosam 0:00a3c3f5a8f0 108
nucleosam 0:00a3c3f5a8f0 109 /// Daisy chain command mask
nucleosam 0:00a3c3f5a8f0 110 #define DAISY_CHAIN_COMMAND_MASK (0xFA)
nucleosam 0:00a3c3f5a8f0 111
nucleosam 0:00a3c3f5a8f0 112 /// powerSTEP01 max absolute position
nucleosam 0:00a3c3f5a8f0 113 #define POWERSTEP01_MAX_POSITION (int32_t)(0x001FFFFF)
nucleosam 0:00a3c3f5a8f0 114
nucleosam 0:00a3c3f5a8f0 115 /// powerSTEP01 min absolute position
nucleosam 0:00a3c3f5a8f0 116 #define POWERSTEP01_MIN_POSITION (int32_t)(0xFFE00000)
nucleosam 0:00a3c3f5a8f0 117
nucleosam 0:00a3c3f5a8f0 118 /// powerSTEP01 error base number
nucleosam 0:00a3c3f5a8f0 119 #define POWERSTEP01_ERROR_BASE (0x7000)
nucleosam 0:00a3c3f5a8f0 120
nucleosam 0:00a3c3f5a8f0 121 /// powerSTEP01 acceleration and deceleration max value
nucleosam 0:00a3c3f5a8f0 122 #define POWERSTEP01_ACC_DEC_MAX_VALUE (float)(59590)
nucleosam 0:00a3c3f5a8f0 123 /// powerSTEP01 max speed max value
nucleosam 0:00a3c3f5a8f0 124 #define POWERSTEP01_MAX_SPEED_MAX_VALUE (float)(15610)
nucleosam 0:00a3c3f5a8f0 125 /// powerSTEP01 min speed max value
nucleosam 0:00a3c3f5a8f0 126 #define POWERSTEP01_MIN_SPEED_MAX_VALUE (float)(976.3)
nucleosam 0:00a3c3f5a8f0 127 /// powerSTEP01 full step speed max value
nucleosam 0:00a3c3f5a8f0 128 #define POWERSTEP01_FS_SPD_MAX_VALUE (float)(15625)
nucleosam 0:00a3c3f5a8f0 129 /// powerSTEP01 intersect speed max value
nucleosam 0:00a3c3f5a8f0 130 #define POWERSTEP01_INT_SPD_MAX_VALUE (float)(976.5)
nucleosam 0:00a3c3f5a8f0 131 /// powerSTEP01 thermal compensation max value
nucleosam 0:00a3c3f5a8f0 132 #define POWERSTEP01_K_THERM_MAX_VALUE (float)(1.46875)
nucleosam 0:00a3c3f5a8f0 133 /// powerSTEP01 thermal compensation min value
nucleosam 0:00a3c3f5a8f0 134 #define POWERSTEP01_K_THERM_MIN_VALUE (float)(1)
nucleosam 0:00a3c3f5a8f0 135 /// powerSTEP01 thermal compensation max value
nucleosam 0:00a3c3f5a8f0 136 #define POWERSTEP01_STALL_OCD_TH_MAX_VALUE (float)(1000)
nucleosam 0:00a3c3f5a8f0 137 /// powerSTEP01 thermal compensation max value
nucleosam 0:00a3c3f5a8f0 138 #define POWERSTEP01_K_THERM_MAX_VALUE (float)(1.46875)
nucleosam 0:00a3c3f5a8f0 139 /// powerSTEP01 voltage amplitude regulation max value
nucleosam 0:00a3c3f5a8f0 140 #define POWERSTEP01_KVAL_MAX_VALUE (float)(255/256)
nucleosam 0:00a3c3f5a8f0 141 /// powerSTEP01 BEMF compensation curve slope max value
nucleosam 0:00a3c3f5a8f0 142 #define POWERSTEP01_SLP_MAX_VALUE (float)(0.4)
nucleosam 0:00a3c3f5a8f0 143 /// powerSTEP01 torque regulation DAC reference voltage max value
nucleosam 0:00a3c3f5a8f0 144 #define POWERSTEP01_TVAL_MAX_VALUE (float)(1000)
nucleosam 0:00a3c3f5a8f0 145 /// powerSTEP01 minimum off and on time max value
nucleosam 0:00a3c3f5a8f0 146 #define POWERSTEP01_TOFF_TON_MIN_MAX_VALUE (float)(64)
nucleosam 0:00a3c3f5a8f0 147
nucleosam 0:00a3c3f5a8f0 148 ///Shift of the low speed optimization bit in MIN_SPEED register
nucleosam 0:00a3c3f5a8f0 149 #define POWERSTEP01_LSPD_OPT_SHIFT (12)
nucleosam 0:00a3c3f5a8f0 150 ///Shift of the boost mode bit in FS_SPD register
nucleosam 0:00a3c3f5a8f0 151 #define POWERSTEP01_BOOST_MODE_SHIFT (10)
nucleosam 0:00a3c3f5a8f0 152 ///Maximum fast decay time (TOFF_FAST) unit
nucleosam 0:00a3c3f5a8f0 153 #define POWERSTEP01_TOFF_FAST_UNIT_US (2)
nucleosam 0:00a3c3f5a8f0 154 ///Shift of the maximum fast decay time (TOFF_FAST) in T_FAST register
nucleosam 0:00a3c3f5a8f0 155 #define POWERSTEP01_TOFF_FAST_SHIFT (4)
nucleosam 0:00a3c3f5a8f0 156 ///Maximum fall step time (FAST_STEP) unit
nucleosam 0:00a3c3f5a8f0 157 #define POWERSTEP01_FAST_STEP_UNIT_US (2)
nucleosam 0:00a3c3f5a8f0 158 ///Shift of the maximum fall step time (FAST_STEP) in T_FAST register
nucleosam 0:00a3c3f5a8f0 159 #define POWERSTEP01_FAST_STEP_SHIFT (0)
nucleosam 0:00a3c3f5a8f0 160 ///Duration unit of constant current phase during gate turn-on and turn-off (TCC)
nucleosam 0:00a3c3f5a8f0 161 #define POWERSTEP01_TCC_UNIT_NS (125)
nucleosam 0:00a3c3f5a8f0 162 ///Shift of TCC field in GATECFG1 register
nucleosam 0:00a3c3f5a8f0 163 #define POWERSTEP01_TCC_SHIFT (0)
nucleosam 0:00a3c3f5a8f0 164 ///Shift of IGATE field in GATECFG1 register
nucleosam 0:00a3c3f5a8f0 165 #define POWERSTEP01_IGATE_SHIFT (5)
nucleosam 0:00a3c3f5a8f0 166 ///Shift of TBOOST field in GATECFG1 register
nucleosam 0:00a3c3f5a8f0 167 #define POWERSTEP01_TBOOST_SHIFT (8)
nucleosam 0:00a3c3f5a8f0 168 ///Duration unit of the blanking of the current sensing comparators (TBLANK)
nucleosam 0:00a3c3f5a8f0 169 #define POWERSTEP01_TBLANK_UNIT_NS (125)
nucleosam 0:00a3c3f5a8f0 170 ///Shift of TBLANK field in GATECFG2 register
nucleosam 0:00a3c3f5a8f0 171 #define POWERSTEP01_TBLANK_SHIFT (5)
nucleosam 0:00a3c3f5a8f0 172 ///Deadtime duration unit between gate turn-off and opposite gate turn-on (TDT)
nucleosam 0:00a3c3f5a8f0 173 #define POWERSTEP01_TDT_UNIT_NS (125)
nucleosam 0:00a3c3f5a8f0 174 ///Shift of TDT field in GATECFG2 register
nucleosam 0:00a3c3f5a8f0 175 #define POWERSTEP01_TDT_SHIFT (0)
nucleosam 0:00a3c3f5a8f0 176 ///Shift of F_PWM_INT field in CONFIG register for voltage mode
nucleosam 0:00a3c3f5a8f0 177 #define POWERSTEP01_CONFIG_PWM_DIV_SHIFT (13)
nucleosam 0:00a3c3f5a8f0 178 ///Shift of F_PWM_DEC field in CONFIG register for voltage mode
nucleosam 0:00a3c3f5a8f0 179 #define POWERSTEP01_CONFIG_PWM_MUL_SHIFT (10)
nucleosam 0:00a3c3f5a8f0 180 ///Target switching period (TSW) unit
nucleosam 0:00a3c3f5a8f0 181 #define POWERSTEP01_CONFIG_TSW_UNIT_US (4)
nucleosam 0:00a3c3f5a8f0 182 ///Shift of TSW field in CONFIG register for current mode
nucleosam 0:00a3c3f5a8f0 183 #define POWERSTEP01_CONFIG_TSW_SHIFT (10)
nucleosam 0:00a3c3f5a8f0 184 ///Shift of MOT_STATUS field in STATUS register
nucleosam 0:00a3c3f5a8f0 185 #define POWERSTEP01_STATUS_MOT_STATUS_SHIFT (5)
nucleosam 0:00a3c3f5a8f0 186 /**
nucleosam 0:00a3c3f5a8f0 187 * @}
nucleosam 0:00a3c3f5a8f0 188 */
nucleosam 0:00a3c3f5a8f0 189
nucleosam 0:00a3c3f5a8f0 190 /* Types ---------------------------------------------------------------------*/
nucleosam 0:00a3c3f5a8f0 191
nucleosam 0:00a3c3f5a8f0 192 /** @defgroup Powerstep01_Exported_Types Powerstep01 Exported Types
nucleosam 0:00a3c3f5a8f0 193 * @{
nucleosam 0:00a3c3f5a8f0 194 */
nucleosam 0:00a3c3f5a8f0 195 /// masks for ABS_POS register of PowerStep01
nucleosam 0:00a3c3f5a8f0 196 typedef enum {
nucleosam 0:00a3c3f5a8f0 197 POWERSTEP01_ABS_POS_VALUE_MASK = ((uint32_t)0x003FFFFF),
nucleosam 0:00a3c3f5a8f0 198 POWERSTEP01_ABS_POS_SIGN_BIT_MASK = ((uint32_t)0x00200000)
nucleosam 0:00a3c3f5a8f0 199 } powerstep01_AbsPosMasks_t;
nucleosam 0:00a3c3f5a8f0 200
nucleosam 0:00a3c3f5a8f0 201 /// masks for EL_POS register of PowerStep01
nucleosam 0:00a3c3f5a8f0 202 typedef enum {
nucleosam 0:00a3c3f5a8f0 203 POWERSTEP01_ELPOS_STEP_MASK = ((uint16_t)0x180),
nucleosam 0:00a3c3f5a8f0 204 POWERSTEP01_ELPOS_MICROSTEP_MASK = ((uint16_t)0x07F)
nucleosam 0:00a3c3f5a8f0 205 } powerstep01_ElPosMasks_t;
nucleosam 0:00a3c3f5a8f0 206
nucleosam 0:00a3c3f5a8f0 207 /// masks for MIN_SPEED register of PowerStep01
nucleosam 0:00a3c3f5a8f0 208 typedef enum {
nucleosam 0:00a3c3f5a8f0 209 POWERSTEP01_LSPD_OPT = ((uint16_t)((0x1)<<POWERSTEP01_LSPD_OPT_SHIFT)),
nucleosam 0:00a3c3f5a8f0 210 POWERSTEP01_MIN_SPEED_MASK = ((uint16_t)0x0FFF)
nucleosam 0:00a3c3f5a8f0 211 } powerstep01_MinSpeedMasks_t;
nucleosam 0:00a3c3f5a8f0 212
nucleosam 0:00a3c3f5a8f0 213 /// Low speed optimization (MIN_SPEED register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 214 typedef enum {
nucleosam 0:00a3c3f5a8f0 215 POWERSTEP01_LSPD_OPT_OFF = ((uint16_t)0x0000),
nucleosam 0:00a3c3f5a8f0 216 POWERSTEP01_LSPD_OPT_ON = ((uint16_t)POWERSTEP01_LSPD_OPT)
nucleosam 0:00a3c3f5a8f0 217 } powerstep01_LspdOpt_t;
nucleosam 0:00a3c3f5a8f0 218
nucleosam 0:00a3c3f5a8f0 219 /// masks for FS_SPD register of PowerStep01
nucleosam 0:00a3c3f5a8f0 220 typedef enum {
nucleosam 0:00a3c3f5a8f0 221 POWERSTEP01_BOOST_MODE = ((uint16_t)((0x1)<<POWERSTEP01_BOOST_MODE_SHIFT)),
nucleosam 0:00a3c3f5a8f0 222 POWERSTEP01_FS_SPD_MASK = ((uint16_t)0x03FF)
nucleosam 0:00a3c3f5a8f0 223 } powerstep01_FsSpdMasks_t;
nucleosam 0:00a3c3f5a8f0 224
nucleosam 0:00a3c3f5a8f0 225 /// Full step boost (FS_SPD register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 226 typedef enum {
nucleosam 0:00a3c3f5a8f0 227 POWERSTEP01_BOOST_MODE_OFF = ((uint16_t)0x0000),
nucleosam 0:00a3c3f5a8f0 228 POWERSTEP01_BOOST_MODE_ON = ((uint16_t)POWERSTEP01_BOOST_MODE)
nucleosam 0:00a3c3f5a8f0 229 } powerstep01_BoostMode_t;
nucleosam 0:00a3c3f5a8f0 230
nucleosam 0:00a3c3f5a8f0 231 /// masks for T_FAST register of PowerStep01
nucleosam 0:00a3c3f5a8f0 232 typedef enum {
nucleosam 0:00a3c3f5a8f0 233 POWERSTEP01_FAST_STEP_MASK = ((uint16_t) ((0xF)<<POWERSTEP01_FAST_STEP_SHIFT)),
nucleosam 0:00a3c3f5a8f0 234 POWERSTEP01_TOFF_FAST_MASK = ((uint16_t) ((0xF)<<POWERSTEP01_TOFF_FAST_SHIFT))
nucleosam 0:00a3c3f5a8f0 235 } powerstep01_TFastMasks_t;
nucleosam 0:00a3c3f5a8f0 236
nucleosam 0:00a3c3f5a8f0 237 /// Maximum fall step times (T_FAST register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 238 typedef enum {
nucleosam 0:00a3c3f5a8f0 239 POWERSTEP01_FAST_STEP_2us = (((uint8_t)0x00)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 240 POWERSTEP01_FAST_STEP_4us = (((uint8_t)0x01)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 241 POWERSTEP01_FAST_STEP_6us = (((uint8_t)0x02)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 242 POWERSTEP01_FAST_STEP_8us = (((uint8_t)0x03)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 243 POWERSTEP01_FAST_STEP_10us = (((uint8_t)0x04)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 244 POWERSTEP01_FAST_STEP_12us = (((uint8_t)0x05)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 245 POWERSTEP01_FAST_STEP_14us = (((uint8_t)0x06)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 246 POWERSTEP01_FAST_STEP_16us = (((uint8_t)0x07)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 247 POWERSTEP01_FAST_STEP_18us = (((uint8_t)0x08)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 248 POWERSTEP01_FAST_STEP_20us = (((uint8_t)0x09)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 249 POWERSTEP01_FAST_STEP_22us = (((uint8_t)0x0A)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 250 POWERSTEP01_FAST_STEP_24s = (((uint8_t)0x0B)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 251 POWERSTEP01_FAST_STEP_26us = (((uint8_t)0x0C)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 252 POWERSTEP01_FAST_STEP_28us = (((uint8_t)0x0D)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 253 POWERSTEP01_FAST_STEP_30us = (((uint8_t)0x0E)<<POWERSTEP01_FAST_STEP_SHIFT),
nucleosam 0:00a3c3f5a8f0 254 POWERSTEP01_FAST_STEP_32us = (((uint8_t)0x0F)<<POWERSTEP01_FAST_STEP_SHIFT)
nucleosam 0:00a3c3f5a8f0 255 } powerstep01_FastStep_t;
nucleosam 0:00a3c3f5a8f0 256
nucleosam 0:00a3c3f5a8f0 257 /// Maximum fast decay times (T_FAST register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 258 typedef enum {
nucleosam 0:00a3c3f5a8f0 259 POWERSTEP01_TOFF_FAST_2us = (((uint8_t)0x00)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 260 POWERSTEP01_TOFF_FAST_4us = (((uint8_t)0x01)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 261 POWERSTEP01_TOFF_FAST_6us = (((uint8_t)0x02)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 262 POWERSTEP01_TOFF_FAST_8us = (((uint8_t)0x03)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 263 POWERSTEP01_TOFF_FAST_10us = (((uint8_t)0x04)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 264 POWERSTEP01_TOFF_FAST_12us = (((uint8_t)0x05)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 265 POWERSTEP01_TOFF_FAST_14us = (((uint8_t)0x06)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 266 POWERSTEP01_TOFF_FAST_16us = (((uint8_t)0x07)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 267 POWERSTEP01_TOFF_FAST_18us = (((uint8_t)0x08)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 268 POWERSTEP01_TOFF_FAST_20us = (((uint8_t)0x09)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 269 POWERSTEP01_TOFF_FAST_22us = (((uint8_t)0x0A)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 270 POWERSTEP01_TOFF_FAST_24us = (((uint8_t)0x0B)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 271 POWERSTEP01_TOFF_FAST_26us = (((uint8_t)0x0C)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 272 POWERSTEP01_TOFF_FAST_28us = (((uint8_t)0x0D)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 273 POWERSTEP01_TOFF_FAST_30us = (((uint8_t)0x0E)<<POWERSTEP01_TOFF_FAST_SHIFT),
nucleosam 0:00a3c3f5a8f0 274 POWERSTEP01_TOFF_FAST_32us = (((uint8_t)0x0F)<<POWERSTEP01_TOFF_FAST_SHIFT)
nucleosam 0:00a3c3f5a8f0 275 } powerstep01_ToffFast_t;
nucleosam 0:00a3c3f5a8f0 276
nucleosam 0:00a3c3f5a8f0 277 /// Overcurrent threshold options (OCD register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 278 typedef enum {
nucleosam 0:00a3c3f5a8f0 279 POWERSTEP01_OCD_TH_31_25mV = ((uint8_t)0x00),
nucleosam 0:00a3c3f5a8f0 280 POWERSTEP01_OCD_TH_62_5mV = ((uint8_t)0x01),
nucleosam 0:00a3c3f5a8f0 281 POWERSTEP01_OCD_TH_93_75mV = ((uint8_t)0x02),
nucleosam 0:00a3c3f5a8f0 282 POWERSTEP01_OCD_TH_125mV = ((uint8_t)0x03),
nucleosam 0:00a3c3f5a8f0 283 POWERSTEP01_OCD_TH_156_25mV = ((uint8_t)0x04),
nucleosam 0:00a3c3f5a8f0 284 POWERSTEP01_OCD_TH_187_50mV = ((uint8_t)0x05),
nucleosam 0:00a3c3f5a8f0 285 POWERSTEP01_OCD_TH_218_75mV = ((uint8_t)0x06),
nucleosam 0:00a3c3f5a8f0 286 POWERSTEP01_OCD_TH_250mV = ((uint8_t)0x07),
nucleosam 0:00a3c3f5a8f0 287 POWERSTEP01_OCD_TH_281_25mV = ((uint8_t)0x08),
nucleosam 0:00a3c3f5a8f0 288 POWERSTEP01_OCD_TH_312_5mV = ((uint8_t)0x09),
nucleosam 0:00a3c3f5a8f0 289 POWERSTEP01_OCD_TH_343_75mV = ((uint8_t)0x0A),
nucleosam 0:00a3c3f5a8f0 290 POWERSTEP01_OCD_TH_375mV = ((uint8_t)0x0B),
nucleosam 0:00a3c3f5a8f0 291 POWERSTEP01_OCD_TH_406_25mV = ((uint8_t)0x0C),
nucleosam 0:00a3c3f5a8f0 292 POWERSTEP01_OCD_TH_437_5mV = ((uint8_t)0x0D),
nucleosam 0:00a3c3f5a8f0 293 POWERSTEP01_OCD_TH_468_75mV = ((uint8_t)0x0E),
nucleosam 0:00a3c3f5a8f0 294 POWERSTEP01_OCD_TH_500mV = ((uint8_t)0x0F),
nucleosam 0:00a3c3f5a8f0 295 POWERSTEP01_OCD_TH_531_25mV = ((uint8_t)0x10),
nucleosam 0:00a3c3f5a8f0 296 POWERSTEP01_OCD_TH_562_5mV = ((uint8_t)0x11),
nucleosam 0:00a3c3f5a8f0 297 POWERSTEP01_OCD_TH_593_75mV = ((uint8_t)0x12),
nucleosam 0:00a3c3f5a8f0 298 POWERSTEP01_OCD_TH_625mV = ((uint8_t)0x13),
nucleosam 0:00a3c3f5a8f0 299 POWERSTEP01_OCD_TH_656_25mV = ((uint8_t)0x14),
nucleosam 0:00a3c3f5a8f0 300 POWERSTEP01_OCD_TH_687_5mV = ((uint8_t)0x15),
nucleosam 0:00a3c3f5a8f0 301 POWERSTEP01_OCD_TH_718_75mV = ((uint8_t)0x16),
nucleosam 0:00a3c3f5a8f0 302 POWERSTEP01_OCD_TH_750mV = ((uint8_t)0x17),
nucleosam 0:00a3c3f5a8f0 303 POWERSTEP01_OCD_TH_781_25mV = ((uint8_t)0x18),
nucleosam 0:00a3c3f5a8f0 304 POWERSTEP01_OCD_TH_812_5mV = ((uint8_t)0x19),
nucleosam 0:00a3c3f5a8f0 305 POWERSTEP01_OCD_TH_843_75mV = ((uint8_t)0x1A),
nucleosam 0:00a3c3f5a8f0 306 POWERSTEP01_OCD_TH_875mV = ((uint8_t)0x1B),
nucleosam 0:00a3c3f5a8f0 307 POWERSTEP01_OCD_TH_906_25mV = ((uint8_t)0x1C),
nucleosam 0:00a3c3f5a8f0 308 POWERSTEP01_OCD_TH_937_75mV = ((uint8_t)0x1D),
nucleosam 0:00a3c3f5a8f0 309 POWERSTEP01_OCD_TH_968_75mV = ((uint8_t)0x1E),
nucleosam 0:00a3c3f5a8f0 310 POWERSTEP01_OCD_TH_1V = ((uint8_t)0x1F)
nucleosam 0:00a3c3f5a8f0 311 } powerstep01_OcdTh_t;
nucleosam 0:00a3c3f5a8f0 312
nucleosam 0:00a3c3f5a8f0 313 /// masks for STEP_MODE register of PowerStep01
nucleosam 0:00a3c3f5a8f0 314 typedef enum {
nucleosam 0:00a3c3f5a8f0 315 POWERSTEP01_STEP_MODE_STEP_SEL = ((uint8_t)0x07),
nucleosam 0:00a3c3f5a8f0 316 POWERSTEP01_STEP_MODE_CM_VM = ((uint8_t)0x08),
nucleosam 0:00a3c3f5a8f0 317 POWERSTEP01_STEP_MODE_SYNC_SEL = ((uint8_t)0x70),
nucleosam 0:00a3c3f5a8f0 318 POWERSTEP01_STEP_MODE_SYNC_EN = ((uint8_t)0x80)
nucleosam 0:00a3c3f5a8f0 319 } powerstep01_StepModeMasks_t;
nucleosam 0:00a3c3f5a8f0 320
nucleosam 0:00a3c3f5a8f0 321 /// Voltage or Current mode selection (CM_VM field of STEP_MODE register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 322 typedef enum {
nucleosam 0:00a3c3f5a8f0 323 POWERSTEP01_CM_VM_VOLTAGE = ((uint8_t)0x00),
nucleosam 0:00a3c3f5a8f0 324 POWERSTEP01_CM_VM_CURRENT = ((uint8_t)0x08)
nucleosam 0:00a3c3f5a8f0 325 } powerstep01_CmVm_t;
nucleosam 0:00a3c3f5a8f0 326
nucleosam 0:00a3c3f5a8f0 327 /// Stepping options (field STEP_SEL of STEP_MODE register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 328 typedef enum {
nucleosam 0:00a3c3f5a8f0 329 POWERSTEP01_STEP_SEL_1 = ((uint8_t)0x00),
nucleosam 0:00a3c3f5a8f0 330 POWERSTEP01_STEP_SEL_1_2 = ((uint8_t)0x01),
nucleosam 0:00a3c3f5a8f0 331 POWERSTEP01_STEP_SEL_1_4 = ((uint8_t)0x02),
nucleosam 0:00a3c3f5a8f0 332 POWERSTEP01_STEP_SEL_1_8 = ((uint8_t)0x03),
nucleosam 0:00a3c3f5a8f0 333 POWERSTEP01_STEP_SEL_1_16 = ((uint8_t)0x04),
nucleosam 0:00a3c3f5a8f0 334 POWERSTEP01_STEP_SEL_1_32 = ((uint8_t)0x05),
nucleosam 0:00a3c3f5a8f0 335 POWERSTEP01_STEP_SEL_1_64 = ((uint8_t)0x06),
nucleosam 0:00a3c3f5a8f0 336 POWERSTEP01_STEP_SEL_1_128 = ((uint8_t)0x07)
nucleosam 0:00a3c3f5a8f0 337 } powerstep01_StepSel_t;
nucleosam 0:00a3c3f5a8f0 338
nucleosam 0:00a3c3f5a8f0 339 /// Powerstep01 Sync Output frequency enabling bitw
nucleosam 0:00a3c3f5a8f0 340 #define POWERSTEP01_SYNC_EN ((0x1) << 7)
nucleosam 0:00a3c3f5a8f0 341
nucleosam 0:00a3c3f5a8f0 342 /// SYNC_SEL options (STEP_MODE register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 343 typedef enum {
nucleosam 0:00a3c3f5a8f0 344 POWERSTEP01_SYNC_SEL_DISABLED = ((uint8_t)0x00),
nucleosam 0:00a3c3f5a8f0 345 POWERSTEP01_SYNC_SEL_1_2 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x00)),
nucleosam 0:00a3c3f5a8f0 346 POWERSTEP01_SYNC_SEL_1 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x10)),
nucleosam 0:00a3c3f5a8f0 347 POWERSTEP01_SYNC_SEL_2 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x20)),
nucleosam 0:00a3c3f5a8f0 348 POWERSTEP01_SYNC_SEL_4 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x30)),
nucleosam 0:00a3c3f5a8f0 349 POWERSTEP01_SYNC_SEL_8 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x40)),
nucleosam 0:00a3c3f5a8f0 350 POWERSTEP01_SYNC_SEL_16 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x50)),
nucleosam 0:00a3c3f5a8f0 351 POWERSTEP01_SYNC_SEL_32 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x60)),
nucleosam 0:00a3c3f5a8f0 352 POWERSTEP01_SYNC_SEL_64 = ((uint8_t)(POWERSTEP01_SYNC_EN|0x70))
nucleosam 0:00a3c3f5a8f0 353 } powerstep01_SyncSel_t;
nucleosam 0:00a3c3f5a8f0 354
nucleosam 0:00a3c3f5a8f0 355 /// Alarms conditions (ALARM_EN register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 356 typedef enum {
nucleosam 0:00a3c3f5a8f0 357 POWERSTEP01_ALARM_EN_OVERCURRENT = ((uint8_t)0x01),
nucleosam 0:00a3c3f5a8f0 358 POWERSTEP01_ALARM_EN_THERMAL_SHUTDOWN = ((uint8_t)0x02),
nucleosam 0:00a3c3f5a8f0 359 POWERSTEP01_ALARM_EN_THERMAL_WARNING = ((uint8_t)0x04),
nucleosam 0:00a3c3f5a8f0 360 POWERSTEP01_ALARM_EN_UVLO = ((uint8_t)0x08),
nucleosam 0:00a3c3f5a8f0 361 POWERSTEP01_ALARM_EN_ADC_UVLO = ((uint8_t)0x10),
nucleosam 0:00a3c3f5a8f0 362 POWERSTEP01_ALARM_EN_STALL_DETECTION = ((uint8_t)0x20),
nucleosam 0:00a3c3f5a8f0 363 POWERSTEP01_ALARM_EN_SW_TURN_ON = ((uint8_t)0x40),
nucleosam 0:00a3c3f5a8f0 364 POWERSTEP01_ALARM_EN_WRONG_NPERF_CMD = ((uint8_t)0x80)
nucleosam 0:00a3c3f5a8f0 365 } powerstep01_AlarmEn_t;
nucleosam 0:00a3c3f5a8f0 366
nucleosam 0:00a3c3f5a8f0 367
nucleosam 0:00a3c3f5a8f0 368 /// masks for GATECFG1 register of PowerStep01
nucleosam 0:00a3c3f5a8f0 369 typedef enum {
nucleosam 0:00a3c3f5a8f0 370 POWERSTEP01_GATECFG1_TCC_MASK = ((uint16_t)0x001F),
nucleosam 0:00a3c3f5a8f0 371 POWERSTEP01_GATECFG1_IGATE_MASK = ((uint16_t)0x00E0),
nucleosam 0:00a3c3f5a8f0 372 POWERSTEP01_GATECFG1_TBOOST_MASK = ((uint16_t)0x0700),
nucleosam 0:00a3c3f5a8f0 373 POWERSTEP01_GATECFG1_WD_EN = ((uint16_t)0x0800)
nucleosam 0:00a3c3f5a8f0 374 } powerstep01_GateCfg1Masks_t;
nucleosam 0:00a3c3f5a8f0 375
nucleosam 0:00a3c3f5a8f0 376 /// Control current Time (field TCC of GATECFG1 register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 377 typedef enum {
nucleosam 0:00a3c3f5a8f0 378 POWERSTEP01_TCC_125ns = (((uint8_t)0x00)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 379 POWERSTEP01_TCC_250ns = (((uint8_t)0x01)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 380 POWERSTEP01_TCC_375ns = (((uint8_t)0x02)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 381 POWERSTEP01_TCC_500ns = (((uint8_t)0x03)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 382 POWERSTEP01_TCC_625ns = (((uint8_t)0x04)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 383 POWERSTEP01_TCC_750ns = (((uint8_t)0x05)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 384 POWERSTEP01_TCC_875ns = (((uint8_t)0x06)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 385 POWERSTEP01_TCC_1000ns = (((uint8_t)0x07)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 386 POWERSTEP01_TCC_1125ns = (((uint8_t)0x08)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 387 POWERSTEP01_TCC_1250ns = (((uint8_t)0x09)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 388 POWERSTEP01_TCC_1375ns = (((uint8_t)0x0A)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 389 POWERSTEP01_TCC_1500ns = (((uint8_t)0x0B)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 390 POWERSTEP01_TCC_1625ns = (((uint8_t)0x0C)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 391 POWERSTEP01_TCC_1750ns = (((uint8_t)0x0D)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 392 POWERSTEP01_TCC_1875ns = (((uint8_t)0x0E)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 393 POWERSTEP01_TCC_2000ns = (((uint8_t)0x0F)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 394 POWERSTEP01_TCC_2125ns = (((uint8_t)0x10)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 395 POWERSTEP01_TCC_2250ns = (((uint8_t)0x11)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 396 POWERSTEP01_TCC_2375ns = (((uint8_t)0x12)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 397 POWERSTEP01_TCC_2500ns = (((uint8_t)0x13)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 398 POWERSTEP01_TCC_2625ns = (((uint8_t)0x14)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 399 POWERSTEP01_TCC_2750ns = (((uint8_t)0x15)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 400 POWERSTEP01_TCC_2875ns = (((uint8_t)0x16)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 401 POWERSTEP01_TCC_3000ns = (((uint8_t)0x17)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 402 POWERSTEP01_TCC_3125ns = (((uint8_t)0x18)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 403 POWERSTEP01_TCC_3250ns = (((uint8_t)0x19)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 404 POWERSTEP01_TCC_3375ns = (((uint8_t)0x1A)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 405 POWERSTEP01_TCC_3500ns = (((uint8_t)0x1B)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 406 POWERSTEP01_TCC_3625ns = (((uint8_t)0x1C)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 407 POWERSTEP01_TCC_3750ns = (((uint8_t)0x1D)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 408 POWERSTEP01_TCC_3750ns_bis = (((uint8_t)0x1E)<<POWERSTEP01_TCC_SHIFT),
nucleosam 0:00a3c3f5a8f0 409 POWERSTEP01_TCC_3750ns_ter = (((uint8_t)0x1F)<<POWERSTEP01_TCC_SHIFT)
nucleosam 0:00a3c3f5a8f0 410 } powerstep01_Tcc_t;
nucleosam 0:00a3c3f5a8f0 411
nucleosam 0:00a3c3f5a8f0 412 /// Igate options (GATECFG1 register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 413 typedef enum {
nucleosam 0:00a3c3f5a8f0 414 POWERSTEP01_IGATE_4mA = (((uint8_t)0x00)<<POWERSTEP01_IGATE_SHIFT),
nucleosam 0:00a3c3f5a8f0 415 POWERSTEP01_IGATE_4mA_Bis = (((uint8_t)0x01)<<POWERSTEP01_IGATE_SHIFT),
nucleosam 0:00a3c3f5a8f0 416 POWERSTEP01_IGATE_8mA = (((uint8_t)0x02)<<POWERSTEP01_IGATE_SHIFT),
nucleosam 0:00a3c3f5a8f0 417 POWERSTEP01_IGATE_16mA = (((uint8_t)0x03)<<POWERSTEP01_IGATE_SHIFT),
nucleosam 0:00a3c3f5a8f0 418 POWERSTEP01_IGATE_24mA = (((uint8_t)0x04)<<POWERSTEP01_IGATE_SHIFT),
nucleosam 0:00a3c3f5a8f0 419 POWERSTEP01_IGATE_32mA = (((uint8_t)0x05)<<POWERSTEP01_IGATE_SHIFT),
nucleosam 0:00a3c3f5a8f0 420 POWERSTEP01_IGATE_64mA = (((uint8_t)0x06)<<POWERSTEP01_IGATE_SHIFT),
nucleosam 0:00a3c3f5a8f0 421 POWERSTEP01_IGATE_96mA = (((uint8_t)0x07)<<POWERSTEP01_IGATE_SHIFT),
nucleosam 0:00a3c3f5a8f0 422 } powerstep01_Igate_t;
nucleosam 0:00a3c3f5a8f0 423
nucleosam 0:00a3c3f5a8f0 424 /// Turn off boost time (TBOOST field of GATECFG1 register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 425 typedef enum {
nucleosam 0:00a3c3f5a8f0 426 POWERSTEP01_TBOOST_0ns = (((uint8_t)0x00)<<POWERSTEP01_TBOOST_SHIFT),
nucleosam 0:00a3c3f5a8f0 427 POWERSTEP01_TBOOST_62_5__83_3__125ns = (((uint8_t)0x01)<<POWERSTEP01_TBOOST_SHIFT),
nucleosam 0:00a3c3f5a8f0 428 POWERSTEP01_TBOOST_125ns = (((uint8_t)0x02)<<POWERSTEP01_TBOOST_SHIFT),
nucleosam 0:00a3c3f5a8f0 429 POWERSTEP01_TBOOST_250ns = (((uint8_t)0x03)<<POWERSTEP01_TBOOST_SHIFT),
nucleosam 0:00a3c3f5a8f0 430 POWERSTEP01_TBOOST_375ns = (((uint8_t)0x04)<<POWERSTEP01_TBOOST_SHIFT),
nucleosam 0:00a3c3f5a8f0 431 POWERSTEP01_TBOOST_500ns = (((uint8_t)0x05)<<POWERSTEP01_TBOOST_SHIFT),
nucleosam 0:00a3c3f5a8f0 432 POWERSTEP01_TBOOST_750ns = (((uint8_t)0x06)<<POWERSTEP01_TBOOST_SHIFT),
nucleosam 0:00a3c3f5a8f0 433 POWERSTEP01_TBOOST_1000ns = (((uint8_t)0x07)<<POWERSTEP01_TBOOST_SHIFT),
nucleosam 0:00a3c3f5a8f0 434 } powerstep01_Tboost_t;
nucleosam 0:00a3c3f5a8f0 435
nucleosam 0:00a3c3f5a8f0 436 /// External clock watchdog (WD_EN field of GATECFG1 register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 437 typedef enum {
nucleosam 0:00a3c3f5a8f0 438 POWERSTEP01_WD_EN_DISABLE = ((uint16_t)0x0000),
nucleosam 0:00a3c3f5a8f0 439 POWERSTEP01_WD_EN_ENABLE = ((uint16_t) ((0x1) << 11))
nucleosam 0:00a3c3f5a8f0 440 } powerstep01_WdEn_t;
nucleosam 0:00a3c3f5a8f0 441
nucleosam 0:00a3c3f5a8f0 442
nucleosam 0:00a3c3f5a8f0 443 /// masks for GATECFG2 register of PowerStep01
nucleosam 0:00a3c3f5a8f0 444 typedef enum {
nucleosam 0:00a3c3f5a8f0 445 POWERSTEP01_GATECFG2_TDT = ((uint8_t)0x1F),
nucleosam 0:00a3c3f5a8f0 446 POWERSTEP01_GATECFG2_TBLANK = ((uint8_t)0xE0)
nucleosam 0:00a3c3f5a8f0 447 } powerstep01_GateCfg2Masks_t;
nucleosam 0:00a3c3f5a8f0 448
nucleosam 0:00a3c3f5a8f0 449 /// Blanking time (TBLANK field of GATECFG2 register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 450 typedef enum {
nucleosam 0:00a3c3f5a8f0 451 POWERSTEP01_TBLANK_125ns = (((uint8_t)0x00)<<POWERSTEP01_TBLANK_SHIFT),
nucleosam 0:00a3c3f5a8f0 452 POWERSTEP01_TBLANK_250ns = (((uint8_t)0x01)<<POWERSTEP01_TBLANK_SHIFT),
nucleosam 0:00a3c3f5a8f0 453 POWERSTEP01_TBLANK_375ns = (((uint8_t)0x02)<<POWERSTEP01_TBLANK_SHIFT),
nucleosam 0:00a3c3f5a8f0 454 POWERSTEP01_TBLANK_500ns = (((uint8_t)0x03)<<POWERSTEP01_TBLANK_SHIFT),
nucleosam 0:00a3c3f5a8f0 455 POWERSTEP01_TBLANK_625ns = (((uint8_t)0x04)<<POWERSTEP01_TBLANK_SHIFT),
nucleosam 0:00a3c3f5a8f0 456 POWERSTEP01_TBLANK_750ns = (((uint8_t)0x05)<<POWERSTEP01_TBLANK_SHIFT),
nucleosam 0:00a3c3f5a8f0 457 POWERSTEP01_TBLANK_875ns = (((uint8_t)0x06)<<POWERSTEP01_TBLANK_SHIFT),
nucleosam 0:00a3c3f5a8f0 458 POWERSTEP01_TBLANK_1000ns = (((uint8_t)0x07)<<POWERSTEP01_TBLANK_SHIFT),
nucleosam 0:00a3c3f5a8f0 459 } powerstep01_TBlank_t;
nucleosam 0:00a3c3f5a8f0 460
nucleosam 0:00a3c3f5a8f0 461 /// Dead time (TDT field of GATECFG2 register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 462 typedef enum {
nucleosam 0:00a3c3f5a8f0 463 POWERSTEP01_TDT_125ns = (((uint8_t)0x00)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 464 POWERSTEP01_TDT_250ns = (((uint8_t)0x01)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 465 POWERSTEP01_TDT_375ns = (((uint8_t)0x02)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 466 POWERSTEP01_TDT_500ns = (((uint8_t)0x03)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 467 POWERSTEP01_TDT_625ns = (((uint8_t)0x04)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 468 POWERSTEP01_TDT_750ns = (((uint8_t)0x05)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 469 POWERSTEP01_TDT_875ns = (((uint8_t)0x06)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 470 POWERSTEP01_TDT_1000ns = (((uint8_t)0x07)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 471 POWERSTEP01_TDT_1125ns = (((uint8_t)0x08)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 472 POWERSTEP01_TDT_1250ns = (((uint8_t)0x09)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 473 POWERSTEP01_TDT_1375ns = (((uint8_t)0x0A)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 474 POWERSTEP01_TDT_1500ns = (((uint8_t)0x0B)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 475 POWERSTEP01_TDT_1625ns = (((uint8_t)0x0C)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 476 POWERSTEP01_TDT_1750ns = (((uint8_t)0x0D)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 477 POWERSTEP01_TDT_1875ns = (((uint8_t)0x0E)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 478 POWERSTEP01_TDT_2000ns = (((uint8_t)0x0F)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 479 POWERSTEP01_TDT_2125ns = (((uint8_t)0x10)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 480 POWERSTEP01_TDT_2250ns = (((uint8_t)0x11)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 481 POWERSTEP01_TDT_2375ns = (((uint8_t)0x12)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 482 POWERSTEP01_TDT_2500ns = (((uint8_t)0x13)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 483 POWERSTEP01_TDT_2625ns = (((uint8_t)0x14)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 484 POWERSTEP01_TDT_2750ns = (((uint8_t)0x15)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 485 POWERSTEP01_TDT_2875ns = (((uint8_t)0x16)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 486 POWERSTEP01_TDT_3000ns = (((uint8_t)0x17)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 487 POWERSTEP01_TDT_3125ns = (((uint8_t)0x18)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 488 POWERSTEP01_TDT_3250ns = (((uint8_t)0x19)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 489 POWERSTEP01_TDT_3375ns = (((uint8_t)0x1A)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 490 POWERSTEP01_TDT_3500ns = (((uint8_t)0x1B)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 491 POWERSTEP01_TDT_3625ns = (((uint8_t)0x1C)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 492 POWERSTEP01_TDT_3750ns = (((uint8_t)0x1D)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 493 POWERSTEP01_TDT_3875ns = (((uint8_t)0x1E)<<POWERSTEP01_TDT_SHIFT),
nucleosam 0:00a3c3f5a8f0 494 POWERSTEP01_TDT_4000ns = (((uint8_t)0x1F)<<POWERSTEP01_TDT_SHIFT)
nucleosam 0:00a3c3f5a8f0 495 } powerstep01_Tdt_t;
nucleosam 0:00a3c3f5a8f0 496
nucleosam 0:00a3c3f5a8f0 497 /// Masks for CONFIG register of Powerstep01
nucleosam 0:00a3c3f5a8f0 498 typedef enum {
nucleosam 0:00a3c3f5a8f0 499 POWERSTEP01_CONFIG_OSC_SEL = ((uint16_t)0x0007),
nucleosam 0:00a3c3f5a8f0 500 POWERSTEP01_CONFIG_EXT_CLK = ((uint16_t)0x0008),
nucleosam 0:00a3c3f5a8f0 501 POWERSTEP01_CONFIG_SW_MODE = ((uint16_t)0x0010),
nucleosam 0:00a3c3f5a8f0 502 POWERSTEP01_CONFIG_OC_SD = ((uint16_t)0x0080),
nucleosam 0:00a3c3f5a8f0 503 POWERSTEP01_CONFIG_UVLOVAL = ((uint16_t)0x0100),
nucleosam 0:00a3c3f5a8f0 504 POWERSTEP01_CONFIG_VCCVAL = ((uint16_t)0x0200),
nucleosam 0:00a3c3f5a8f0 505 // Masks specific for voltage mode
nucleosam 0:00a3c3f5a8f0 506 POWERSTEP01_CONFIG_EN_VSCOMP = ((uint16_t)0x0020),
nucleosam 0:00a3c3f5a8f0 507 POWERSTEP01_CONFIG_F_PWM_DEC = ((uint16_t)0x1C00),
nucleosam 0:00a3c3f5a8f0 508 POWERSTEP01_CONFIG_F_PWM_INT = ((uint16_t)0xE000),
nucleosam 0:00a3c3f5a8f0 509 // Masks specific for current mode
nucleosam 0:00a3c3f5a8f0 510 POWERSTEP01_CONFIG_TSW = ((uint16_t)0x7C00),
nucleosam 0:00a3c3f5a8f0 511 POWERSTEP01_CONFIG_PRED_EN = ((uint16_t)0x8000)
nucleosam 0:00a3c3f5a8f0 512 } powerstep01_ConfigMasks_t;
nucleosam 0:00a3c3f5a8f0 513
nucleosam 0:00a3c3f5a8f0 514 /// Masks for CONFIG register of Powerstep01 (specific for current mode)
nucleosam 0:00a3c3f5a8f0 515 #define POWERSTEP01_CONFIG_EN_TQREG (POWERSTEP01_CONFIG_EN_VSCOMP)
nucleosam 0:00a3c3f5a8f0 516
nucleosam 0:00a3c3f5a8f0 517 /// Oscillator management (EXT_CLK and OSC_SEL fields of CONFIG register of Powerstep01)
nucleosam 0:00a3c3f5a8f0 518 typedef enum {
nucleosam 0:00a3c3f5a8f0 519 POWERSTEP01_CONFIG_INT_16MHZ = ((uint16_t)0x0000),
nucleosam 0:00a3c3f5a8f0 520 POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_2MHZ = ((uint16_t)0x0008),
nucleosam 0:00a3c3f5a8f0 521 POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_4MHZ = ((uint16_t)0x0009),
nucleosam 0:00a3c3f5a8f0 522 POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_8MHZ = ((uint16_t)0x000A),
nucleosam 0:00a3c3f5a8f0 523 POWERSTEP01_CONFIG_INT_16MHZ_OSCOUT_16MHZ = ((uint16_t)0x000B),
nucleosam 0:00a3c3f5a8f0 524 POWERSTEP01_CONFIG_EXT_8MHZ_XTAL_DRIVE = ((uint16_t)0x0004),
nucleosam 0:00a3c3f5a8f0 525 POWERSTEP01_CONFIG_EXT_16MHZ_XTAL_DRIVE = ((uint16_t)0x0005),
nucleosam 0:00a3c3f5a8f0 526 POWERSTEP01_CONFIG_EXT_24MHZ_XTAL_DRIVE = ((uint16_t)0x0006),
nucleosam 0:00a3c3f5a8f0 527 POWERSTEP01_CONFIG_EXT_32MHZ_XTAL_DRIVE = ((uint16_t)0x0007),
nucleosam 0:00a3c3f5a8f0 528 POWERSTEP01_CONFIG_EXT_8MHZ_OSCOUT_INVERT = ((uint16_t)0x000C),
nucleosam 0:00a3c3f5a8f0 529 POWERSTEP01_CONFIG_EXT_16MHZ_OSCOUT_INVERT = ((uint16_t)0x000D),
nucleosam 0:00a3c3f5a8f0 530 POWERSTEP01_CONFIG_EXT_24MHZ_OSCOUT_INVERT = ((uint16_t)0x000E),
nucleosam 0:00a3c3f5a8f0 531 POWERSTEP01_CONFIG_EXT_32MHZ_OSCOUT_INVERT = ((uint16_t)0x000F)
nucleosam 0:00a3c3f5a8f0 532 } powerstep01_ConfigOscMgmt_t;
nucleosam 0:00a3c3f5a8f0 533
nucleosam 0:00a3c3f5a8f0 534 /// Oscillator management (EXT_CLK and OSC_SEL fields of CONFIG register of Powerstep01)
nucleosam 0:00a3c3f5a8f0 535 typedef enum {
nucleosam 0:00a3c3f5a8f0 536 POWERSTEP01_CONFIG_SW_HARD_STOP = ((uint16_t)0x0000),
nucleosam 0:00a3c3f5a8f0 537 POWERSTEP01_CONFIG_SW_USER = ((uint16_t)0x0010)
nucleosam 0:00a3c3f5a8f0 538 } powerstep01_ConfigSwMode_t;
nucleosam 0:00a3c3f5a8f0 539
nucleosam 0:00a3c3f5a8f0 540 /// Voltage supply compensation enabling for voltage mode (EN_VSCOMP field of CONFIG register of Powerstep01)
nucleosam 0:00a3c3f5a8f0 541 typedef enum {
nucleosam 0:00a3c3f5a8f0 542 POWERSTEP01_CONFIG_VS_COMP_DISABLE = ((uint16_t)0x0000),
nucleosam 0:00a3c3f5a8f0 543 POWERSTEP01_CONFIG_VS_COMP_ENABLE = ((uint16_t)0x0020)
nucleosam 0:00a3c3f5a8f0 544 } powerstep01_ConfigEnVscomp_t;
nucleosam 0:00a3c3f5a8f0 545
nucleosam 0:00a3c3f5a8f0 546 /// External torque regulation enabling (EN_TQREG field of CONFIG register of Powerstep01)
nucleosam 0:00a3c3f5a8f0 547 typedef enum {
nucleosam 0:00a3c3f5a8f0 548 POWERSTEP01_CONFIG_TQ_REG_TVAL_USED = ((uint16_t)0x0000),
nucleosam 0:00a3c3f5a8f0 549 POWERSTEP01_CONFIG_TQ_REG_ADC_OUT = ((uint16_t)0x0020)
nucleosam 0:00a3c3f5a8f0 550 } powerstep01_ConfigEnTqReg_t;
nucleosam 0:00a3c3f5a8f0 551
nucleosam 0:00a3c3f5a8f0 552 /// Overcurrent shutdown (OC_SD field of CONFIG register of Powerstep01)
nucleosam 0:00a3c3f5a8f0 553 typedef enum {
nucleosam 0:00a3c3f5a8f0 554 POWERSTEP01_CONFIG_OC_SD_DISABLE = ((uint16_t)0x0000),
nucleosam 0:00a3c3f5a8f0 555 POWERSTEP01_CONFIG_OC_SD_ENABLE = ((uint16_t)0x0080)
nucleosam 0:00a3c3f5a8f0 556 } powerstep01_ConfigOcSd_t;
nucleosam 0:00a3c3f5a8f0 557
nucleosam 0:00a3c3f5a8f0 558 /// UVLO thresholds (UVLOVAL field of CONFIG register of Powerstep01)
nucleosam 0:00a3c3f5a8f0 559 typedef enum {
nucleosam 0:00a3c3f5a8f0 560 POWERSTEP01_CONFIG_UVLOVAL_LOW = ((uint16_t)0x0000),
nucleosam 0:00a3c3f5a8f0 561 POWERSTEP01_CONFIG_UVLOVAL_HIGH = ((uint16_t)0x0100),
nucleosam 0:00a3c3f5a8f0 562 } powerstep01_ConfigUvLoVal_t;
nucleosam 0:00a3c3f5a8f0 563
nucleosam 0:00a3c3f5a8f0 564 /// Vcc voltage (VCCVAL field of CONFIG register of Powerstep01)
nucleosam 0:00a3c3f5a8f0 565 typedef enum {
nucleosam 0:00a3c3f5a8f0 566 POWERSTEP01_CONFIG_VCCVAL_7_5V = ((uint16_t)0x0000),
nucleosam 0:00a3c3f5a8f0 567 POWERSTEP01_CONFIG_VCCVAL_15V = ((uint16_t)0x0200)
nucleosam 0:00a3c3f5a8f0 568 } powerstep01_ConfigVccVal_t;
nucleosam 0:00a3c3f5a8f0 569
nucleosam 0:00a3c3f5a8f0 570 /// PWM frequency division factor (F_PWM_INT field of CONFIG register of Powerstep01)
nucleosam 0:00a3c3f5a8f0 571 typedef enum {
nucleosam 0:00a3c3f5a8f0 572 POWERSTEP01_CONFIG_PWM_DIV_1 = (((uint16_t)0x00)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT),
nucleosam 0:00a3c3f5a8f0 573 POWERSTEP01_CONFIG_PWM_DIV_2 = (((uint16_t)0x01)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT),
nucleosam 0:00a3c3f5a8f0 574 POWERSTEP01_CONFIG_PWM_DIV_3 = (((uint16_t)0x02)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT),
nucleosam 0:00a3c3f5a8f0 575 POWERSTEP01_CONFIG_PWM_DIV_4 = (((uint16_t)0x03)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT),
nucleosam 0:00a3c3f5a8f0 576 POWERSTEP01_CONFIG_PWM_DIV_5 = (((uint16_t)0x04)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT),
nucleosam 0:00a3c3f5a8f0 577 POWERSTEP01_CONFIG_PWM_DIV_6 = (((uint16_t)0x05)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT),
nucleosam 0:00a3c3f5a8f0 578 POWERSTEP01_CONFIG_PWM_DIV_7 = (((uint16_t)0x06)<<POWERSTEP01_CONFIG_PWM_DIV_SHIFT)
nucleosam 0:00a3c3f5a8f0 579 } powerstep01_ConfigFPwmInt_t;
nucleosam 0:00a3c3f5a8f0 580
nucleosam 0:00a3c3f5a8f0 581 /// PWM frequency multiplication factor (F_PWM_DEC field of CONFIG register of Powerstep01)
nucleosam 0:00a3c3f5a8f0 582 typedef enum {
nucleosam 0:00a3c3f5a8f0 583 POWERSTEP01_CONFIG_PWM_MUL_0_625 = (((uint16_t)0x00)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
nucleosam 0:00a3c3f5a8f0 584 POWERSTEP01_CONFIG_PWM_MUL_0_75 = (((uint16_t)0x01)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
nucleosam 0:00a3c3f5a8f0 585 POWERSTEP01_CONFIG_PWM_MUL_0_875 = (((uint16_t)0x02)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
nucleosam 0:00a3c3f5a8f0 586 POWERSTEP01_CONFIG_PWM_MUL_1 = (((uint16_t)0x03)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
nucleosam 0:00a3c3f5a8f0 587 POWERSTEP01_CONFIG_PWM_MUL_1_25 = (((uint16_t)0x04)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
nucleosam 0:00a3c3f5a8f0 588 POWERSTEP01_CONFIG_PWM_MUL_1_5 = (((uint16_t)0x05)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
nucleosam 0:00a3c3f5a8f0 589 POWERSTEP01_CONFIG_PWM_MUL_1_75 = (((uint16_t)0x06)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT),
nucleosam 0:00a3c3f5a8f0 590 POWERSTEP01_CONFIG_PWM_MUL_2 = (((uint16_t)0x07)<<POWERSTEP01_CONFIG_PWM_MUL_SHIFT)
nucleosam 0:00a3c3f5a8f0 591 } powerstep01_ConfigFPwmDec_t;
nucleosam 0:00a3c3f5a8f0 592
nucleosam 0:00a3c3f5a8f0 593 /// Switching period (TSW field of CONFIG register of Powerstep01)
nucleosam 0:00a3c3f5a8f0 594 typedef enum {
nucleosam 0:00a3c3f5a8f0 595 POWERSTEP01_CONFIG_TSW_004us =(((uint16_t)0x01)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 596 POWERSTEP01_CONFIG_TSW_008us =(((uint16_t)0x02)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 597 POWERSTEP01_CONFIG_TSW_012us =(((uint16_t)0x03)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 598 POWERSTEP01_CONFIG_TSW_016us =(((uint16_t)0x04)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 599 POWERSTEP01_CONFIG_TSW_020us =(((uint16_t)0x05)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 600 POWERSTEP01_CONFIG_TSW_024us =(((uint16_t)0x06)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 601 POWERSTEP01_CONFIG_TSW_028us =(((uint16_t)0x07)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 602 POWERSTEP01_CONFIG_TSW_032us =(((uint16_t)0x08)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 603 POWERSTEP01_CONFIG_TSW_036us =(((uint16_t)0x09)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 604 POWERSTEP01_CONFIG_TSW_040us =(((uint16_t)0x0A)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 605 POWERSTEP01_CONFIG_TSW_044us =(((uint16_t)0x0B)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 606 POWERSTEP01_CONFIG_TSW_048us =(((uint16_t)0x0C)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 607 POWERSTEP01_CONFIG_TSW_052us =(((uint16_t)0x0D)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 608 POWERSTEP01_CONFIG_TSW_056us =(((uint16_t)0x0E)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 609 POWERSTEP01_CONFIG_TSW_060us =(((uint16_t)0x0F)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 610 POWERSTEP01_CONFIG_TSW_064us =(((uint16_t)0x10)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 611 POWERSTEP01_CONFIG_TSW_068us =(((uint16_t)0x11)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 612 POWERSTEP01_CONFIG_TSW_072us =(((uint16_t)0x12)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 613 POWERSTEP01_CONFIG_TSW_076us =(((uint16_t)0x13)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 614 POWERSTEP01_CONFIG_TSW_080us =(((uint16_t)0x14)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 615 POWERSTEP01_CONFIG_TSW_084us =(((uint16_t)0x15)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 616 POWERSTEP01_CONFIG_TSW_088us =(((uint16_t)0x16)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 617 POWERSTEP01_CONFIG_TSW_092us =(((uint16_t)0x17)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 618 POWERSTEP01_CONFIG_TSW_096us =(((uint16_t)0x18)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 619 POWERSTEP01_CONFIG_TSW_100us =(((uint16_t)0x19)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 620 POWERSTEP01_CONFIG_TSW_104us =(((uint16_t)0x1A)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 621 POWERSTEP01_CONFIG_TSW_108us =(((uint16_t)0x1B)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 622 POWERSTEP01_CONFIG_TSW_112us =(((uint16_t)0x1C)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 623 POWERSTEP01_CONFIG_TSW_116us =(((uint16_t)0x1D)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 624 POWERSTEP01_CONFIG_TSW_120us =(((uint16_t)0x1E)<<POWERSTEP01_CONFIG_TSW_SHIFT),
nucleosam 0:00a3c3f5a8f0 625 POWERSTEP01_CONFIG_TSW_124us =(((uint16_t)0x1F)<<POWERSTEP01_CONFIG_TSW_SHIFT)
nucleosam 0:00a3c3f5a8f0 626 } powerstep01_ConfigTsw_t;
nucleosam 0:00a3c3f5a8f0 627
nucleosam 0:00a3c3f5a8f0 628 /// Voltage supply compensation enabling for current mode(EN_PRED field of CONFIG register of Powerstep01)
nucleosam 0:00a3c3f5a8f0 629 typedef enum {
nucleosam 0:00a3c3f5a8f0 630 POWERSTEP01_CONFIG_PRED_DISABLE =((uint16_t)0x0000),
nucleosam 0:00a3c3f5a8f0 631 POWERSTEP01_CONFIG_PRED_ENABLE =((uint16_t)0x8000)
nucleosam 0:00a3c3f5a8f0 632 } powerstep01_ConfigPredEn_t;
nucleosam 0:00a3c3f5a8f0 633
nucleosam 0:00a3c3f5a8f0 634 /// Bit mask for STATUS Register of PowerStep01²
nucleosam 0:00a3c3f5a8f0 635 typedef enum {
nucleosam 0:00a3c3f5a8f0 636 POWERSTEP01_STATUS_HIZ = (((uint16_t)0x0001)),
nucleosam 0:00a3c3f5a8f0 637 POWERSTEP01_STATUS_BUSY = (((uint16_t)0x0002)),
nucleosam 0:00a3c3f5a8f0 638 POWERSTEP01_STATUS_SW_F = (((uint16_t)0x0004)),
nucleosam 0:00a3c3f5a8f0 639 POWERSTEP01_STATUS_SW_EVN = (((uint16_t)0x0008)),
nucleosam 0:00a3c3f5a8f0 640 POWERSTEP01_STATUS_DIR = (((uint16_t)0x0010)),
nucleosam 0:00a3c3f5a8f0 641 POWERSTEP01_STATUS_MOT_STATUS = (((uint16_t)0x0060)),
nucleosam 0:00a3c3f5a8f0 642 POWERSTEP01_STATUS_CMD_ERROR = (((uint16_t)0x0080)),
nucleosam 0:00a3c3f5a8f0 643 POWERSTEP01_STATUS_STCK_MOD = (((uint16_t)0x0100)),
nucleosam 0:00a3c3f5a8f0 644 POWERSTEP01_STATUS_UVLO = (((uint16_t)0x0200)),
nucleosam 0:00a3c3f5a8f0 645 POWERSTEP01_STATUS_UVLO_ADC = (((uint16_t)0x0400)),
nucleosam 0:00a3c3f5a8f0 646 POWERSTEP01_STATUS_TH_STATUS = (((uint16_t)0x1800)),
nucleosam 0:00a3c3f5a8f0 647 POWERSTEP01_STATUS_OCD = (((uint16_t)0x2000)),
nucleosam 0:00a3c3f5a8f0 648 POWERSTEP01_STATUS_STALL_A = (((uint16_t)0x4000)),
nucleosam 0:00a3c3f5a8f0 649 POWERSTEP01_STATUS_STALL_B = (((uint16_t)0x8000))
nucleosam 0:00a3c3f5a8f0 650 } powerstep01_StatusMasks_t;
nucleosam 0:00a3c3f5a8f0 651
nucleosam 0:00a3c3f5a8f0 652 /// Motor state (MOT_STATUS filed of STATUS register of PowerStep01)
nucleosam 0:00a3c3f5a8f0 653 typedef enum {
nucleosam 0:00a3c3f5a8f0 654 POWERSTEP01_STATUS_MOT_STATUS_STOPPED = (((uint16_t)0x0000)<<POWERSTEP01_STATUS_MOT_STATUS_SHIFT),
nucleosam 0:00a3c3f5a8f0 655 POWERSTEP01_STATUS_MOT_STATUS_ACCELERATION = (((uint16_t)0x0001)<<POWERSTEP01_STATUS_MOT_STATUS_SHIFT),
nucleosam 0:00a3c3f5a8f0 656 POWERSTEP01_STATUS_MOT_STATUS_DECELERATION = (((uint16_t)0x0002)<<POWERSTEP01_STATUS_MOT_STATUS_SHIFT),
nucleosam 0:00a3c3f5a8f0 657 POWERSTEP01_STATUS_MOT_STATUS_CONST_SPD = (((uint16_t)0x0003)<<POWERSTEP01_STATUS_MOT_STATUS_SHIFT)
nucleosam 0:00a3c3f5a8f0 658 } powerstep01_Status_t;
nucleosam 0:00a3c3f5a8f0 659
nucleosam 0:00a3c3f5a8f0 660 /// Powerstep01 internal register addresses
nucleosam 0:00a3c3f5a8f0 661 typedef enum {
nucleosam 0:00a3c3f5a8f0 662 POWERSTEP01_ABS_POS = ((uint8_t)0x01),
nucleosam 0:00a3c3f5a8f0 663 POWERSTEP01_EL_POS = ((uint8_t)0x02),
nucleosam 0:00a3c3f5a8f0 664 POWERSTEP01_MARK = ((uint8_t)0x03),
nucleosam 0:00a3c3f5a8f0 665 POWERSTEP01_SPEED = ((uint8_t)0x04),
nucleosam 0:00a3c3f5a8f0 666 POWERSTEP01_ACC = ((uint8_t)0x05),
nucleosam 0:00a3c3f5a8f0 667 POWERSTEP01_DEC = ((uint8_t)0x06),
nucleosam 0:00a3c3f5a8f0 668 POWERSTEP01_MAX_SPEED = ((uint8_t)0x07),
nucleosam 0:00a3c3f5a8f0 669 POWERSTEP01_MIN_SPEED = ((uint8_t)0x08),
nucleosam 0:00a3c3f5a8f0 670 POWERSTEP01_FS_SPD = ((uint8_t)0x15),
nucleosam 0:00a3c3f5a8f0 671 POWERSTEP01_KVAL_HOLD = ((uint8_t)0x09),
nucleosam 0:00a3c3f5a8f0 672 POWERSTEP01_KVAL_RUN = ((uint8_t)0x0A),
nucleosam 0:00a3c3f5a8f0 673 POWERSTEP01_KVAL_ACC = ((uint8_t)0x0B),
nucleosam 0:00a3c3f5a8f0 674 POWERSTEP01_KVAL_DEC = ((uint8_t)0x0C),
nucleosam 0:00a3c3f5a8f0 675 POWERSTEP01_INT_SPD = ((uint8_t)0x0D),
nucleosam 0:00a3c3f5a8f0 676 POWERSTEP01_ST_SLP = ((uint8_t)0x0E),
nucleosam 0:00a3c3f5a8f0 677 POWERSTEP01_FN_SLP_ACC = ((uint8_t)0x0F),
nucleosam 0:00a3c3f5a8f0 678 POWERSTEP01_FN_SLP_DEC = ((uint8_t)0x10),
nucleosam 0:00a3c3f5a8f0 679 POWERSTEP01_K_THERM = ((uint8_t)0x11),
nucleosam 0:00a3c3f5a8f0 680 POWERSTEP01_ADC_OUT = ((uint8_t)0x12),
nucleosam 0:00a3c3f5a8f0 681 POWERSTEP01_OCD_TH = ((uint8_t)0x13),
nucleosam 0:00a3c3f5a8f0 682 POWERSTEP01_STALL_TH = ((uint8_t)0x14),
nucleosam 0:00a3c3f5a8f0 683 POWERSTEP01_STEP_MODE = ((uint8_t)0x16),
nucleosam 0:00a3c3f5a8f0 684 POWERSTEP01_ALARM_EN = ((uint8_t)0x17),
nucleosam 0:00a3c3f5a8f0 685 POWERSTEP01_GATECFG1 = ((uint8_t)0x18),
nucleosam 0:00a3c3f5a8f0 686 POWERSTEP01_GATECFG2 = ((uint8_t)0x19),
nucleosam 0:00a3c3f5a8f0 687 POWERSTEP01_CONFIG = ((uint8_t)0x1A),
nucleosam 0:00a3c3f5a8f0 688 POWERSTEP01_STATUS = ((uint8_t)0x1B)
nucleosam 0:00a3c3f5a8f0 689 } powerstep01_Registers_t;
nucleosam 0:00a3c3f5a8f0 690
nucleosam 0:00a3c3f5a8f0 691 /// Powerstep01 address of register TVAL_HOLD (Current mode only)
nucleosam 0:00a3c3f5a8f0 692 #define POWERSTEP01_TVAL_HOLD (POWERSTEP01_KVAL_HOLD )
nucleosam 0:00a3c3f5a8f0 693 /// Powerstep01 address of register TVAL_RUN (Current mode only)
nucleosam 0:00a3c3f5a8f0 694 #define POWERSTEP01_TVAL_RUN (POWERSTEP01_KVAL_RUN)
nucleosam 0:00a3c3f5a8f0 695 /// Powerstep01 address of register TVAL_HOLD (Current mode only)
nucleosam 0:00a3c3f5a8f0 696 #define POWERSTEP01_TVAL_ACC (POWERSTEP01_KVAL_ACC)
nucleosam 0:00a3c3f5a8f0 697 /// Powerstep01 address of register TVAL_DEC (Current mode only)
nucleosam 0:00a3c3f5a8f0 698 #define POWERSTEP01_TVAL_DEC (POWERSTEP01_KVAL_DEC)
nucleosam 0:00a3c3f5a8f0 699 /// Powerstep01 address of register T_FAST (Current mode only)
nucleosam 0:00a3c3f5a8f0 700 #define POWERSTEP01_T_FAST (POWERSTEP01_ST_SLP)
nucleosam 0:00a3c3f5a8f0 701 /// Powerstep01 address of register TON_MIN (Current mode only)
nucleosam 0:00a3c3f5a8f0 702 #define POWERSTEP01_TON_MIN (POWERSTEP01_FN_SLP_ACC)
nucleosam 0:00a3c3f5a8f0 703 /// Powerstep01 address of register TOFF_MIN (Current mode only)
nucleosam 0:00a3c3f5a8f0 704 #define POWERSTEP01_TOFF_MIN (POWERSTEP01_FN_SLP_DEC)
nucleosam 0:00a3c3f5a8f0 705
nucleosam 0:00a3c3f5a8f0 706 /// Powerstep01 application commands
nucleosam 0:00a3c3f5a8f0 707 typedef enum {
nucleosam 0:00a3c3f5a8f0 708 POWERSTEP01_NOP = ((uint8_t)0x00),
nucleosam 0:00a3c3f5a8f0 709 POWERSTEP01_SET_PARAM = ((uint8_t)0x00),
nucleosam 0:00a3c3f5a8f0 710 POWERSTEP01_GET_PARAM = ((uint8_t)0x20),
nucleosam 0:00a3c3f5a8f0 711 POWERSTEP01_RUN = ((uint8_t)0x50),
nucleosam 0:00a3c3f5a8f0 712 POWERSTEP01_STEP_CLOCK = ((uint8_t)0x58),
nucleosam 0:00a3c3f5a8f0 713 POWERSTEP01_MOVE = ((uint8_t)0x40),
nucleosam 0:00a3c3f5a8f0 714 POWERSTEP01_GO_TO = ((uint8_t)0x60),
nucleosam 0:00a3c3f5a8f0 715 POWERSTEP01_GO_TO_DIR = ((uint8_t)0x68),
nucleosam 0:00a3c3f5a8f0 716 POWERSTEP01_GO_UNTIL = ((uint8_t)0x82),
nucleosam 0:00a3c3f5a8f0 717 POWERSTEP01_GO_UNTIL_ACT_CPY = ((uint8_t)0x8A),
nucleosam 0:00a3c3f5a8f0 718 POWERSTEP01_RELEASE_SW = ((uint8_t)0x92),
nucleosam 0:00a3c3f5a8f0 719 POWERSTEP01_GO_HOME = ((uint8_t)0x70),
nucleosam 0:00a3c3f5a8f0 720 POWERSTEP01_GO_MARK = ((uint8_t)0x78),
nucleosam 0:00a3c3f5a8f0 721 POWERSTEP01_RESET_POS = ((uint8_t)0xD8),
nucleosam 0:00a3c3f5a8f0 722 POWERSTEP01_RESET_DEVICE = ((uint8_t)0xC0),
nucleosam 0:00a3c3f5a8f0 723 POWERSTEP01_SOFT_STOP = ((uint8_t)0xB0),
nucleosam 0:00a3c3f5a8f0 724 POWERSTEP01_HARD_STOP = ((uint8_t)0xB8),
nucleosam 0:00a3c3f5a8f0 725 POWERSTEP01_SOFT_HIZ = ((uint8_t)0xA0),
nucleosam 0:00a3c3f5a8f0 726 POWERSTEP01_HARD_HIZ = ((uint8_t)0xA8),
nucleosam 0:00a3c3f5a8f0 727 POWERSTEP01_GET_STATUS = ((uint8_t)0xD0),
nucleosam 0:00a3c3f5a8f0 728 POWERSTEP01_RESERVED_CMD1 = ((uint8_t)0xEB),
nucleosam 0:00a3c3f5a8f0 729 POWERSTEP01_RESERVED_CMD2 = ((uint8_t)0xF8)
nucleosam 0:00a3c3f5a8f0 730 } powerstep01_Commands_t;
nucleosam 0:00a3c3f5a8f0 731
nucleosam 0:00a3c3f5a8f0 732 /** @defgroup Motor_Driver_Initialization_Structure Motor Driver Initialization Structure
nucleosam 0:00a3c3f5a8f0 733 * @{
nucleosam 0:00a3c3f5a8f0 734 */
nucleosam 0:00a3c3f5a8f0 735 /* ACTION --------------------------------------------------------------------*
nucleosam 0:00a3c3f5a8f0 736 * Declare here the component's initialization structure, if any, one *
nucleosam 0:00a3c3f5a8f0 737 * variable per line without initialization. *
nucleosam 0:00a3c3f5a8f0 738 * *
nucleosam 0:00a3c3f5a8f0 739 * Example: *
nucleosam 0:00a3c3f5a8f0 740 * typedef struct *
nucleosam 0:00a3c3f5a8f0 741 * { *
nucleosam 0:00a3c3f5a8f0 742 * int frequency; *
nucleosam 0:00a3c3f5a8f0 743 * int update_mode; *
nucleosam 0:00a3c3f5a8f0 744 * } COMPONENT_Init_t; *
nucleosam 0:00a3c3f5a8f0 745 *----------------------------------------------------------------------------*/
nucleosam 0:00a3c3f5a8f0 746 ///Initialization parameters structure common to current and voltage modes
nucleosam 0:00a3c3f5a8f0 747 typedef struct
nucleosam 0:00a3c3f5a8f0 748 {
nucleosam 0:00a3c3f5a8f0 749 ///Current or voltage mode selection
nucleosam 0:00a3c3f5a8f0 750 powerstep01_CmVm_t cmVmSelection;
nucleosam 0:00a3c3f5a8f0 751 ///Acceleration
nucleosam 0:00a3c3f5a8f0 752 float acceleration;
nucleosam 0:00a3c3f5a8f0 753 ///Deceleration
nucleosam 0:00a3c3f5a8f0 754 float deceleration;
nucleosam 0:00a3c3f5a8f0 755 ///Maximum speed
nucleosam 0:00a3c3f5a8f0 756 float maxSpeed;
nucleosam 0:00a3c3f5a8f0 757 ///Minimum speed
nucleosam 0:00a3c3f5a8f0 758 float minSpeed;
nucleosam 0:00a3c3f5a8f0 759 ///Low speed optimization bit
nucleosam 0:00a3c3f5a8f0 760 powerstep01_LspdOpt_t lowSpeedOptimization;
nucleosam 0:00a3c3f5a8f0 761 ///Full step speed
nucleosam 0:00a3c3f5a8f0 762 float fullStepSpeed;
nucleosam 0:00a3c3f5a8f0 763 ///Boost mode bit
nucleosam 0:00a3c3f5a8f0 764 powerstep01_BoostMode_t boostMode;
nucleosam 0:00a3c3f5a8f0 765 ///Over current detection threshold
nucleosam 0:00a3c3f5a8f0 766 float ocdThreshold;
nucleosam 0:00a3c3f5a8f0 767 ///Step mode
nucleosam 0:00a3c3f5a8f0 768 motorStepMode_t stepMode;
nucleosam 0:00a3c3f5a8f0 769 ///Sync clock selection
nucleosam 0:00a3c3f5a8f0 770 powerstep01_SyncSel_t syncClockSelection;
nucleosam 0:00a3c3f5a8f0 771 ///Alarm selection
nucleosam 0:00a3c3f5a8f0 772 uint8_t alarmsSelection;
nucleosam 0:00a3c3f5a8f0 773 ///Sink or source current used by gate driving circuitry
nucleosam 0:00a3c3f5a8f0 774 powerstep01_Igate_t iGate;
nucleosam 0:00a3c3f5a8f0 775 ///Duration of the overboost phase during gate turn-off
nucleosam 0:00a3c3f5a8f0 776 powerstep01_Tboost_t tBoost;
nucleosam 0:00a3c3f5a8f0 777 ///Duration of constant current phase during gate turn-on and turn-off
nucleosam 0:00a3c3f5a8f0 778 powerstep01_Tcc_t tcc;
nucleosam 0:00a3c3f5a8f0 779 ///Clock source monitoring enable bit
nucleosam 0:00a3c3f5a8f0 780 powerstep01_WdEn_t wdEn;
nucleosam 0:00a3c3f5a8f0 781 ///Duration of the blanking of the current sensing comparators
nucleosam 0:00a3c3f5a8f0 782 powerstep01_TBlank_t tBlank;
nucleosam 0:00a3c3f5a8f0 783 ///Deadtime duration between gate turn-off and opposite gate turn-on
nucleosam 0:00a3c3f5a8f0 784 powerstep01_Tdt_t tdt;
nucleosam 0:00a3c3f5a8f0 785 } commonParameters_t;
nucleosam 0:00a3c3f5a8f0 786
nucleosam 0:00a3c3f5a8f0 787 ///Initialization parameters structure for voltage mode
nucleosam 0:00a3c3f5a8f0 788 typedef struct
nucleosam 0:00a3c3f5a8f0 789 {
nucleosam 0:00a3c3f5a8f0 790 ///Parameters common to current and voltage modes
nucleosam 0:00a3c3f5a8f0 791 commonParameters_t cp;
nucleosam 0:00a3c3f5a8f0 792 ///Voltage amplitude regulation when the motor is stopped
nucleosam 0:00a3c3f5a8f0 793 float kvalHold;
nucleosam 0:00a3c3f5a8f0 794 ///Voltage amplitude regulation when the motor is running at constant speed
nucleosam 0:00a3c3f5a8f0 795 float kvalRun;
nucleosam 0:00a3c3f5a8f0 796 ///Voltage amplitude regulation during motor acceleration
nucleosam 0:00a3c3f5a8f0 797 float kvalAcc;
nucleosam 0:00a3c3f5a8f0 798 ///Voltage amplitude regulation during motor deceleration
nucleosam 0:00a3c3f5a8f0 799 float kvalDec;
nucleosam 0:00a3c3f5a8f0 800 ///Speed value at which the BEMF compensation curve changes slope
nucleosam 0:00a3c3f5a8f0 801 float intersectSpeed;
nucleosam 0:00a3c3f5a8f0 802 ///BEMF compensation curve slope when speed is lower than intersect speed
nucleosam 0:00a3c3f5a8f0 803 float startSlope;
nucleosam 0:00a3c3f5a8f0 804 ///BEMF compensation curve slope when speed is greater than intersect speed during acceleration
nucleosam 0:00a3c3f5a8f0 805 float accelerationFinalSlope;
nucleosam 0:00a3c3f5a8f0 806 ///BEMF compensation curve slope when speed is greater than intersect speed during deceleration
nucleosam 0:00a3c3f5a8f0 807 float decelerationFinalSlope;
nucleosam 0:00a3c3f5a8f0 808 ///Winding resistance thermal drift compensation coefficient
nucleosam 0:00a3c3f5a8f0 809 float thermalCompensationFactor;
nucleosam 0:00a3c3f5a8f0 810 ///Stall detection threshold
nucleosam 0:00a3c3f5a8f0 811 float stallThreshold;
nucleosam 0:00a3c3f5a8f0 812 ///System clock source management
nucleosam 0:00a3c3f5a8f0 813 powerstep01_ConfigOscMgmt_t oscClkSel;
nucleosam 0:00a3c3f5a8f0 814 ///External switch to act as HardStop interrupt or not
nucleosam 0:00a3c3f5a8f0 815 powerstep01_ConfigSwMode_t swMode;
nucleosam 0:00a3c3f5a8f0 816 ///Motor supply voltage compensation enable bit
nucleosam 0:00a3c3f5a8f0 817 powerstep01_ConfigEnVscomp_t enVsComp;
nucleosam 0:00a3c3f5a8f0 818 ///Overcurrent event causes or not the bridges to turn-off
nucleosam 0:00a3c3f5a8f0 819 powerstep01_ConfigOcSd_t ocSd;
nucleosam 0:00a3c3f5a8f0 820 ///UVLO protection thresholds
nucleosam 0:00a3c3f5a8f0 821 powerstep01_ConfigUvLoVal_t uvloVal;
nucleosam 0:00a3c3f5a8f0 822 ///Internal VCC regulator output voltage
nucleosam 0:00a3c3f5a8f0 823 powerstep01_ConfigVccVal_t vccVal;
nucleosam 0:00a3c3f5a8f0 824 ///Integer division factor of PWM frequency generation
nucleosam 0:00a3c3f5a8f0 825 powerstep01_ConfigFPwmInt_t fPwmInt;
nucleosam 0:00a3c3f5a8f0 826 ///Multiplication factor of PWM frequency generation
nucleosam 0:00a3c3f5a8f0 827 powerstep01_ConfigFPwmDec_t fPwmDec;
nucleosam 0:00a3c3f5a8f0 828 } powerstep01_VoltageMode_Init_t;
nucleosam 0:00a3c3f5a8f0 829
nucleosam 0:00a3c3f5a8f0 830 ///Initialization parameters structure for current mode
nucleosam 0:00a3c3f5a8f0 831 typedef struct
nucleosam 0:00a3c3f5a8f0 832 {
nucleosam 0:00a3c3f5a8f0 833 ///Parameters common to current and voltage modes
nucleosam 0:00a3c3f5a8f0 834 commonParameters_t cp;
nucleosam 0:00a3c3f5a8f0 835 ///Torque regulation DAC reference voltage when motor is stopped
nucleosam 0:00a3c3f5a8f0 836 float tvalHold;
nucleosam 0:00a3c3f5a8f0 837 ///Torque regulation DAC reference voltage when motor is runnig at constant speed
nucleosam 0:00a3c3f5a8f0 838 float tvalRun;
nucleosam 0:00a3c3f5a8f0 839 ///Torque regulation DAC reference voltage during motor acceleration
nucleosam 0:00a3c3f5a8f0 840 float tvalAcc;
nucleosam 0:00a3c3f5a8f0 841 ///Torque regulation DAC reference voltage during motor deceleration
nucleosam 0:00a3c3f5a8f0 842 float tvalDec;
nucleosam 0:00a3c3f5a8f0 843 ///Maximum fast decay time
nucleosam 0:00a3c3f5a8f0 844 powerstep01_ToffFast_t toffFast;
nucleosam 0:00a3c3f5a8f0 845 ///Maximum fall step time
nucleosam 0:00a3c3f5a8f0 846 powerstep01_FastStep_t fastStep;
nucleosam 0:00a3c3f5a8f0 847 ///Minimum on-time
nucleosam 0:00a3c3f5a8f0 848 float tonMin;
nucleosam 0:00a3c3f5a8f0 849 ///Minimum off-time
nucleosam 0:00a3c3f5a8f0 850 float toffMin;
nucleosam 0:00a3c3f5a8f0 851 ///System clock source management
nucleosam 0:00a3c3f5a8f0 852 powerstep01_ConfigOscMgmt_t oscClkSel;
nucleosam 0:00a3c3f5a8f0 853 ///External switch to act as HardStop interrupt or not
nucleosam 0:00a3c3f5a8f0 854 powerstep01_ConfigSwMode_t swMode;
nucleosam 0:00a3c3f5a8f0 855 ///Peak current is adjusted through the ADCIN input or not
nucleosam 0:00a3c3f5a8f0 856 powerstep01_ConfigEnTqReg_t tqReg;
nucleosam 0:00a3c3f5a8f0 857 ///Motor supply voltage compensation enable bit
nucleosam 0:00a3c3f5a8f0 858 powerstep01_ConfigEnVscomp_t enVsComp;
nucleosam 0:00a3c3f5a8f0 859 ///Overcurrent event causes or not the bridges to turn-off
nucleosam 0:00a3c3f5a8f0 860 powerstep01_ConfigOcSd_t ocSd;
nucleosam 0:00a3c3f5a8f0 861 ///UVLO protection thresholds
nucleosam 0:00a3c3f5a8f0 862 powerstep01_ConfigUvLoVal_t uvloVal;
nucleosam 0:00a3c3f5a8f0 863 ///Internal VCC regulator output voltage
nucleosam 0:00a3c3f5a8f0 864 powerstep01_ConfigVccVal_t vccVal;
nucleosam 0:00a3c3f5a8f0 865 ///target switching period
nucleosam 0:00a3c3f5a8f0 866 powerstep01_ConfigTsw_t tsw;
nucleosam 0:00a3c3f5a8f0 867 ///predictive current control method enable bit
nucleosam 0:00a3c3f5a8f0 868 powerstep01_ConfigPredEn_t predEn;
nucleosam 0:00a3c3f5a8f0 869
nucleosam 0:00a3c3f5a8f0 870 } powerstep01_CurrentMode_Init_t;
nucleosam 0:00a3c3f5a8f0 871
nucleosam 0:00a3c3f5a8f0 872 ///Union of current and volatge modes initialization parameters structures
nucleosam 0:00a3c3f5a8f0 873 typedef union powerstep01_Init_u powerstep01_Init_u_t;
nucleosam 0:00a3c3f5a8f0 874 union powerstep01_Init_u
nucleosam 0:00a3c3f5a8f0 875 {
nucleosam 0:00a3c3f5a8f0 876 ///Initialization parameters structure for current mode
nucleosam 0:00a3c3f5a8f0 877 powerstep01_CurrentMode_Init_t cm;
nucleosam 0:00a3c3f5a8f0 878 ///Initialization parameters structure for voltage mode
nucleosam 0:00a3c3f5a8f0 879 powerstep01_VoltageMode_Init_t vm;
nucleosam 0:00a3c3f5a8f0 880 };
nucleosam 0:00a3c3f5a8f0 881 /**
nucleosam 0:00a3c3f5a8f0 882 * @}
nucleosam 0:00a3c3f5a8f0 883 */
nucleosam 0:00a3c3f5a8f0 884
nucleosam 0:00a3c3f5a8f0 885 /**
nucleosam 0:00a3c3f5a8f0 886 * @brief Powerstep01 driver data structure definition.
nucleosam 0:00a3c3f5a8f0 887 */
nucleosam 0:00a3c3f5a8f0 888 /* ACTION --------------------------------------------------------------------*
nucleosam 0:00a3c3f5a8f0 889 * Declare here the structure of component's data, if any, one variable per *
nucleosam 0:00a3c3f5a8f0 890 * line without initialization. *
nucleosam 0:00a3c3f5a8f0 891 * *
nucleosam 0:00a3c3f5a8f0 892 * Example: *
nucleosam 0:00a3c3f5a8f0 893 * typedef struct *
nucleosam 0:00a3c3f5a8f0 894 * { *
nucleosam 0:00a3c3f5a8f0 895 * int T0_out; *
nucleosam 0:00a3c3f5a8f0 896 * int T1_out; *
nucleosam 0:00a3c3f5a8f0 897 * float T0_degC; *
nucleosam 0:00a3c3f5a8f0 898 * float T1_degC; *
nucleosam 0:00a3c3f5a8f0 899 * } COMPONENT_Data_t; *
nucleosam 0:00a3c3f5a8f0 900 *----------------------------------------------------------------------------*/
nucleosam 0:00a3c3f5a8f0 901
nucleosam 0:00a3c3f5a8f0 902 /**
nucleosam 0:00a3c3f5a8f0 903 * @}
nucleosam 0:00a3c3f5a8f0 904 */
nucleosam 0:00a3c3f5a8f0 905
nucleosam 0:00a3c3f5a8f0 906 /* Functions -----------------------------------------------------------------*/
nucleosam 0:00a3c3f5a8f0 907
nucleosam 0:00a3c3f5a8f0 908 /** @defgroup Powerstep01_Board_Linked_Functions Powerstep01 Board Linked Functions
nucleosam 0:00a3c3f5a8f0 909 * @{
nucleosam 0:00a3c3f5a8f0 910 */
nucleosam 0:00a3c3f5a8f0 911
nucleosam 0:00a3c3f5a8f0 912 /* ACTION --------------------------------------------------------------------*
nucleosam 0:00a3c3f5a8f0 913 * Declare here extern platform-dependent APIs you might need (e.g.: I/O and *
nucleosam 0:00a3c3f5a8f0 914 * interrupt related functions), and implement them in a glue-logic file on *
nucleosam 0:00a3c3f5a8f0 915 * the target environment, for example within the "x_nucleo_board.c" file. *
nucleosam 0:00a3c3f5a8f0 916 * E.g.: *
nucleosam 0:00a3c3f5a8f0 917 * extern Status_t COMPONENT_IO_Init (void *handle); *
nucleosam 0:00a3c3f5a8f0 918 * extern Status_t COMPONENT_IO_Read (handle, buf, regadd, bytes); *
nucleosam 0:00a3c3f5a8f0 919 * extern Status_t COMPONENT_IO_Write(handle, buf, regadd, bytes); *
nucleosam 0:00a3c3f5a8f0 920 * extern void COMPONENT_IO_ITConfig(void); *
nucleosam 0:00a3c3f5a8f0 921 *----------------------------------------------------------------------------*/
nucleosam 0:00a3c3f5a8f0 922 ///Delay of the requested number of milliseconds
nucleosam 0:00a3c3f5a8f0 923 extern void Powerstep01_Board_Delay(void *handle, uint32_t delay);
nucleosam 0:00a3c3f5a8f0 924 ///Enable Irq
nucleosam 0:00a3c3f5a8f0 925 extern void Powerstep01_Board_EnableIrq(void *handle);
nucleosam 0:00a3c3f5a8f0 926 ///Disable Irq
nucleosam 0:00a3c3f5a8f0 927 extern void Powerstep01_Board_DisableIrq(void *handle);
nucleosam 0:00a3c3f5a8f0 928 ///Init the timer for the step clock
nucleosam 0:00a3c3f5a8f0 929 extern void Powerstep01_Board_StepClockInit(void *handle);
nucleosam 0:00a3c3f5a8f0 930 ///Set the Powerstep01 reset pin (high logic level)
nucleosam 0:00a3c3f5a8f0 931 extern void Powerstep01_Board_ReleaseReset(void *handle);
nucleosam 0:00a3c3f5a8f0 932 ///Reset the Powerstep01 reset pin (low logic level)
nucleosam 0:00a3c3f5a8f0 933 extern void Powerstep01_Board_Reset(void *handle);
nucleosam 0:00a3c3f5a8f0 934 ///Write bytes to the Powerstep01s via SPI
nucleosam 0:00a3c3f5a8f0 935 extern uint8_t Powerstep01_Board_SpiWriteBytes(void *handle, uint8_t *pByteToTransmit, uint8_t *pReceivedByte);
nucleosam 0:00a3c3f5a8f0 936
nucleosam 0:00a3c3f5a8f0 937
nucleosam 0:00a3c3f5a8f0 938 /**
nucleosam 0:00a3c3f5a8f0 939 * @}
nucleosam 0:00a3c3f5a8f0 940 */
nucleosam 0:00a3c3f5a8f0 941
nucleosam 0:00a3c3f5a8f0 942 /**
nucleosam 0:00a3c3f5a8f0 943 * @}
nucleosam 0:00a3c3f5a8f0 944 */
nucleosam 0:00a3c3f5a8f0 945
nucleosam 0:00a3c3f5a8f0 946 /**
nucleosam 0:00a3c3f5a8f0 947 * @}
nucleosam 0:00a3c3f5a8f0 948 */
nucleosam 0:00a3c3f5a8f0 949
nucleosam 0:00a3c3f5a8f0 950 #ifdef __cplusplus
nucleosam 0:00a3c3f5a8f0 951 }
nucleosam 0:00a3c3f5a8f0 952 #endif
nucleosam 0:00a3c3f5a8f0 953
nucleosam 0:00a3c3f5a8f0 954 #endif /* #ifndef _POWERSTEP01_H_INCLUDED */
nucleosam 0:00a3c3f5a8f0 955
nucleosam 0:00a3c3f5a8f0 956 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/