This library lets you connect an MRF24J40 tranceiver to your mbed. The MRF24J40 is intended for use as a zigbee or 6LowPan tranciever. However, it can also be used to simply send data from one tranceiver to another. The tranceiver is also available as a module on a small PCB with antenna etc. It requires no other components and can be connected to the mbed using 6 or 7 pins: MISO, MOSI, CLK, CS, WAKE, INT, RESET (optional). New: Added support for INT and WAKE pins. Added PrintBuffer function Added DebugDump function
Fork of MRF24J40 by
MRF24J40.cpp@3:f8a30ff66793, 2015-01-07 (annotated)
- Committer:
- nbremond
- Date:
- Wed Jan 07 22:03:56 2015 +0000
- Revision:
- 3:f8a30ff66793
- Parent:
- 2:d1e104b6ce31
Add support for INT and WAKE pins
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
hilgo | 0:0630ffe718d3 | 1 | /* mbed MRF24J40 (IEEE 802.15.4 tranceiver) Library |
hilgo | 0:0630ffe718d3 | 2 | * Copyright (c) 2011 Jeroen Hilgers |
hilgo | 0:0630ffe718d3 | 3 | * |
hilgo | 0:0630ffe718d3 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
hilgo | 0:0630ffe718d3 | 5 | * of this software and associated documentation files (the "Software"), to deal |
hilgo | 0:0630ffe718d3 | 6 | * in the Software without restriction, including without limitation the rights |
hilgo | 0:0630ffe718d3 | 7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
hilgo | 0:0630ffe718d3 | 8 | * copies of the Software, and to permit persons to whom the Software is |
hilgo | 0:0630ffe718d3 | 9 | * furnished to do so, subject to the following conditions: |
hilgo | 0:0630ffe718d3 | 10 | * |
hilgo | 0:0630ffe718d3 | 11 | * The above copyright notice and this permission notice shall be included in |
hilgo | 0:0630ffe718d3 | 12 | * all copies or substantial portions of the Software. |
hilgo | 0:0630ffe718d3 | 13 | * |
hilgo | 0:0630ffe718d3 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
hilgo | 0:0630ffe718d3 | 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
hilgo | 0:0630ffe718d3 | 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
hilgo | 0:0630ffe718d3 | 17 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
hilgo | 0:0630ffe718d3 | 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
hilgo | 0:0630ffe718d3 | 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
hilgo | 0:0630ffe718d3 | 20 | * THE SOFTWARE. |
hilgo | 0:0630ffe718d3 | 21 | */ |
hilgo | 0:0630ffe718d3 | 22 | |
hilgo | 0:0630ffe718d3 | 23 | #include "MRF24J40.h" |
hilgo | 0:0630ffe718d3 | 24 | |
hilgo | 0:0630ffe718d3 | 25 | // MRF20J40 Short address control register mapping. |
hilgo | 0:0630ffe718d3 | 26 | #define RXMCR 0x00 |
hilgo | 0:0630ffe718d3 | 27 | #define PANIDL 0x01 |
hilgo | 0:0630ffe718d3 | 28 | #define PANIDH 0x02 |
hilgo | 0:0630ffe718d3 | 29 | #define SADRL 0x03 |
hilgo | 0:0630ffe718d3 | 30 | #define SADRH 0x04 |
hilgo | 0:0630ffe718d3 | 31 | #define EADR0 0x05 |
hilgo | 0:0630ffe718d3 | 32 | #define EADR1 0x06 |
hilgo | 0:0630ffe718d3 | 33 | #define EADR2 0x07 |
hilgo | 0:0630ffe718d3 | 34 | #define EADR3 0x08 |
hilgo | 0:0630ffe718d3 | 35 | #define EADR4 0x09 |
hilgo | 0:0630ffe718d3 | 36 | #define EADR5 0x0a |
hilgo | 0:0630ffe718d3 | 37 | #define EADR6 0x0b |
hilgo | 0:0630ffe718d3 | 38 | #define EADR7 0x0c |
hilgo | 0:0630ffe718d3 | 39 | #define RXFLUSH 0x0d |
hilgo | 0:0630ffe718d3 | 40 | |
hilgo | 0:0630ffe718d3 | 41 | #define TXNMTRIG 0x1b |
hilgo | 0:0630ffe718d3 | 42 | #define TXSR 0x24 |
hilgo | 0:0630ffe718d3 | 43 | |
hilgo | 0:0630ffe718d3 | 44 | #define ISRSTS 0x31 |
hilgo | 0:0630ffe718d3 | 45 | #define INTMSK 0x32 |
hilgo | 0:0630ffe718d3 | 46 | #define GPIO 0x33 |
hilgo | 0:0630ffe718d3 | 47 | #define TRISGPIO 0x34 |
hilgo | 0:0630ffe718d3 | 48 | |
hilgo | 0:0630ffe718d3 | 49 | #define RFCTL 0x36 |
hilgo | 0:0630ffe718d3 | 50 | |
hilgo | 0:0630ffe718d3 | 51 | #define BBREG2 0x3A |
hilgo | 0:0630ffe718d3 | 52 | |
hilgo | 0:0630ffe718d3 | 53 | #define BBREG6 0x3E |
hilgo | 0:0630ffe718d3 | 54 | #define RSSITHCCA 0x3F |
hilgo | 0:0630ffe718d3 | 55 | |
hilgo | 0:0630ffe718d3 | 56 | // MRF20J40 Long address control register mapping. |
hilgo | 0:0630ffe718d3 | 57 | #define RFCTRL0 0x200 |
hilgo | 0:0630ffe718d3 | 58 | |
hilgo | 0:0630ffe718d3 | 59 | #define RFCTRL2 0x202 |
hilgo | 0:0630ffe718d3 | 60 | #define RFCTRL3 0x203 |
hilgo | 0:0630ffe718d3 | 61 | |
hilgo | 0:0630ffe718d3 | 62 | #define RFCTRL6 0x206 |
hilgo | 0:0630ffe718d3 | 63 | #define RFCTRL7 0x207 |
hilgo | 0:0630ffe718d3 | 64 | #define RFCTRL8 0x208 |
hilgo | 0:0630ffe718d3 | 65 | |
hilgo | 0:0630ffe718d3 | 66 | #define CLKINTCR 0x211 |
hilgo | 0:0630ffe718d3 | 67 | #define CLCCTRL 0x220 |
hilgo | 0:0630ffe718d3 | 68 | |
nbremond | 3:f8a30ff66793 | 69 | MRF24J40::MRF24J40(PinName mosi, PinName miso, PinName sck, PinName cs, PinName reset, PinName irq, PinName wake) : |
hilgo | 0:0630ffe718d3 | 70 | mSpi(mosi, miso, sck), // mosi, miso, sclk |
hilgo | 0:0630ffe718d3 | 71 | mCs(cs), |
nbremond | 3:f8a30ff66793 | 72 | mReset(reset), |
nbremond | 3:f8a30ff66793 | 73 | mIrq(irq), |
nbremond | 3:f8a30ff66793 | 74 | mWake(wake) |
hilgo | 0:0630ffe718d3 | 75 | { |
hilgo | 0:0630ffe718d3 | 76 | mSpi.format(8, 0); // 8 bits, cpol=0; cpha=0 |
hilgo | 0:0630ffe718d3 | 77 | mSpi.frequency(500000); |
hilgo | 0:0630ffe718d3 | 78 | Reset(); |
hilgo | 0:0630ffe718d3 | 79 | } |
hilgo | 0:0630ffe718d3 | 80 | |
nbremond | 2:d1e104b6ce31 | 81 | |
hilgo | 0:0630ffe718d3 | 82 | void MRF24J40::DebugDump(Serial &ser) |
hilgo | 0:0630ffe718d3 | 83 | { |
hilgo | 0:0630ffe718d3 | 84 | ser.printf("MRF24J40 registers:\r"); |
nbremond | 3:f8a30ff66793 | 85 | ser.printf("RXMCR=0x%X\r", ReadShort(RXMCR)); |
nbremond | 3:f8a30ff66793 | 86 | ser.printf("RXFLUSH=0x%X\r", ReadShort(RXFLUSH)); |
nbremond | 3:f8a30ff66793 | 87 | ser.printf("TXNMTRIG=0x%X\r", ReadShort(TXNMTRIG)); |
nbremond | 3:f8a30ff66793 | 88 | ser.printf("TXSR=0x%X\r", ReadShort(TXSR)); |
nbremond | 3:f8a30ff66793 | 89 | ser.printf("ISRSTS=0x%X\r", ReadShort(ISRSTS)); |
nbremond | 3:f8a30ff66793 | 90 | ser.printf("INTMSK=0x%X\r", ReadShort(INTMSK)); |
nbremond | 3:f8a30ff66793 | 91 | ser.printf("GPIO=0x%X\r", ReadShort(GPIO)); |
nbremond | 3:f8a30ff66793 | 92 | ser.printf("TRISGPIO=0x%X\r", ReadShort(TRISGPIO)); |
nbremond | 3:f8a30ff66793 | 93 | ser.printf("RFCTL=0x%X\r", ReadShort(RFCTL)); |
nbremond | 3:f8a30ff66793 | 94 | ser.printf("BBREG2=0x%X\r", ReadShort(BBREG2)); |
nbremond | 3:f8a30ff66793 | 95 | ser.printf("BBREG6=0x%X\r", ReadShort(BBREG6)); |
nbremond | 3:f8a30ff66793 | 96 | ser.printf("RSSITHCCA=0x%X\r", ReadShort(RSSITHCCA)); |
hilgo | 0:0630ffe718d3 | 97 | |
hilgo | 0:0630ffe718d3 | 98 | |
nbremond | 3:f8a30ff66793 | 99 | ser.printf("RFCTRL0=0x%X\r", ReadLong(RFCTRL0)); |
nbremond | 3:f8a30ff66793 | 100 | ser.printf("RFCTRL2=0x%X\r", ReadLong(RFCTRL2)); |
nbremond | 3:f8a30ff66793 | 101 | ser.printf("RFCTRL3=0x%X\r", ReadLong(RFCTRL3)); |
nbremond | 3:f8a30ff66793 | 102 | ser.printf("RFCTRL6=0x%X\r", ReadLong(RFCTRL6)); |
nbremond | 3:f8a30ff66793 | 103 | ser.printf("RFCTRL7=0x%X\r", ReadLong(RFCTRL7)); |
nbremond | 3:f8a30ff66793 | 104 | ser.printf("RFCTRL8=0x%X\r", ReadLong(RFCTRL8)); |
nbremond | 3:f8a30ff66793 | 105 | ser.printf("CLKINTCR=0x%X\r", ReadLong(CLKINTCR)); |
nbremond | 3:f8a30ff66793 | 106 | ser.printf("CLCCTRL=0x%X\r", ReadLong(CLCCTRL)); |
hilgo | 0:0630ffe718d3 | 107 | ser.printf("\r"); |
hilgo | 0:0630ffe718d3 | 108 | } |
nbremond | 2:d1e104b6ce31 | 109 | |
hilgo | 0:0630ffe718d3 | 110 | |
hilgo | 0:0630ffe718d3 | 111 | void MRF24J40::Reset(void) |
hilgo | 0:0630ffe718d3 | 112 | { |
nbremond | 3:f8a30ff66793 | 113 | mWake = 1; |
hilgo | 0:0630ffe718d3 | 114 | mCs = 1; |
hilgo | 0:0630ffe718d3 | 115 | // Pulse hardware reset. |
hilgo | 0:0630ffe718d3 | 116 | mReset = 0; |
hilgo | 0:0630ffe718d3 | 117 | wait_us(100); |
hilgo | 0:0630ffe718d3 | 118 | mReset = 1; |
hilgo | 0:0630ffe718d3 | 119 | wait_us(100); |
hilgo | 0:0630ffe718d3 | 120 | |
hilgo | 0:0630ffe718d3 | 121 | // Reset RF module. |
hilgo | 0:0630ffe718d3 | 122 | WriteShort(RFCTL, 0x04); |
hilgo | 0:0630ffe718d3 | 123 | WriteShort(RFCTL, 0x00); |
hilgo | 0:0630ffe718d3 | 124 | |
hilgo | 0:0630ffe718d3 | 125 | WriteShort(RFCTL, 0x00); |
hilgo | 0:0630ffe718d3 | 126 | |
hilgo | 0:0630ffe718d3 | 127 | WriteShort(PANIDL, 0xAA); |
hilgo | 0:0630ffe718d3 | 128 | WriteShort(PANIDH, 0xAA); |
hilgo | 0:0630ffe718d3 | 129 | WriteShort(SADRL, 0xAA); |
hilgo | 0:0630ffe718d3 | 130 | WriteShort(SADRH, 0xAA); |
hilgo | 0:0630ffe718d3 | 131 | |
hilgo | 0:0630ffe718d3 | 132 | // Flush RX fifo. |
hilgo | 0:0630ffe718d3 | 133 | WriteShort(RXFLUSH, 0x01); |
hilgo | 0:0630ffe718d3 | 134 | |
hilgo | 0:0630ffe718d3 | 135 | // Write MAC addresses here. We don't care. |
hilgo | 0:0630ffe718d3 | 136 | |
hilgo | 0:0630ffe718d3 | 137 | WriteLong(RFCTRL2, 0x80); // Enable RF PLL. |
hilgo | 0:0630ffe718d3 | 138 | |
hilgo | 0:0630ffe718d3 | 139 | WriteLong(RFCTRL3, 0x00); // Full power. |
hilgo | 0:0630ffe718d3 | 140 | WriteLong(RFCTRL6, 0x80); // Enable TX filter (recommended) |
hilgo | 0:0630ffe718d3 | 141 | WriteLong(RFCTRL8, 0x10); // Enhanced VCO (recommended) |
hilgo | 0:0630ffe718d3 | 142 | |
hilgo | 0:0630ffe718d3 | 143 | WriteShort(BBREG2,0x78); // Clear Channel Assesment use carrier sense. |
hilgo | 0:0630ffe718d3 | 144 | WriteShort(BBREG6,0x40); // Calculate RSSI for Rx packet. |
hilgo | 0:0630ffe718d3 | 145 | WriteShort(RSSITHCCA,0x00);// RSSI threshold for CCA. |
hilgo | 0:0630ffe718d3 | 146 | |
hilgo | 0:0630ffe718d3 | 147 | WriteLong(RFCTRL0, 0x00); // Channel 11. |
hilgo | 0:0630ffe718d3 | 148 | |
hilgo | 0:0630ffe718d3 | 149 | WriteShort(RXMCR, 0x01); // Don't check address upon reception. |
hilgo | 0:0630ffe718d3 | 150 | // MrfWriteShort(RXMCR, 0x00); // Check address upon reception. |
hilgo | 0:0630ffe718d3 | 151 | |
hilgo | 0:0630ffe718d3 | 152 | // Reset RF module with new settings. |
hilgo | 0:0630ffe718d3 | 153 | WriteShort(RFCTL, 0x04); |
hilgo | 0:0630ffe718d3 | 154 | WriteShort(RFCTL, 0x00); |
hilgo | 0:0630ffe718d3 | 155 | } |
hilgo | 0:0630ffe718d3 | 156 | |
hilgo | 0:0630ffe718d3 | 157 | void MRF24J40::Send(uint8_t *data, uint8_t length) |
hilgo | 0:0630ffe718d3 | 158 | { |
hilgo | 0:0630ffe718d3 | 159 | uint8_t i; |
hilgo | 0:0630ffe718d3 | 160 | |
nbremond | 3:f8a30ff66793 | 161 | mWake = 1; |
nbremond | 3:f8a30ff66793 | 162 | |
hilgo | 0:0630ffe718d3 | 163 | WriteLong(0x000, 0); // No addresses in header. |
hilgo | 0:0630ffe718d3 | 164 | WriteLong(0x001, length); // 11 bytes |
hilgo | 0:0630ffe718d3 | 165 | for(i=0; i<length; i++) |
hilgo | 0:0630ffe718d3 | 166 | WriteLong(0x002+i, data[i]); |
hilgo | 0:0630ffe718d3 | 167 | |
hilgo | 0:0630ffe718d3 | 168 | WriteShort(TXNMTRIG, 0x01); |
hilgo | 0:0630ffe718d3 | 169 | } |
hilgo | 0:0630ffe718d3 | 170 | |
hilgo | 0:0630ffe718d3 | 171 | uint8_t MRF24J40::Receive(uint8_t *data, uint8_t maxLength) |
hilgo | 0:0630ffe718d3 | 172 | { |
hilgo | 0:0630ffe718d3 | 173 | uint8_t i, length; |
hilgo | 0:0630ffe718d3 | 174 | uint8_t lqi, rssi; |
hilgo | 0:0630ffe718d3 | 175 | |
nbremond | 3:f8a30ff66793 | 176 | mWake = 1; |
nbremond | 3:f8a30ff66793 | 177 | |
hilgo | 0:0630ffe718d3 | 178 | if(ReadShort(ISRSTS)& 0x08) |
hilgo | 0:0630ffe718d3 | 179 | { |
hilgo | 0:0630ffe718d3 | 180 | length = ReadLong(0x300); |
hilgo | 0:0630ffe718d3 | 181 | lqi = ReadLong(0x301 + length); |
hilgo | 0:0630ffe718d3 | 182 | rssi = ReadLong(0x302 + length); |
hilgo | 0:0630ffe718d3 | 183 | for(i=0; i<length; i++) |
hilgo | 0:0630ffe718d3 | 184 | if(i<maxLength) |
hilgo | 0:0630ffe718d3 | 185 | *data++ = ReadLong(0x301 + (uint16_t)i); |
hilgo | 0:0630ffe718d3 | 186 | else |
hilgo | 0:0630ffe718d3 | 187 | ReadLong(0x301 + (uint16_t)i); |
hilgo | 0:0630ffe718d3 | 188 | if(length < maxLength) |
hilgo | 0:0630ffe718d3 | 189 | return length; |
hilgo | 0:0630ffe718d3 | 190 | } |
hilgo | 0:0630ffe718d3 | 191 | return 0; |
hilgo | 0:0630ffe718d3 | 192 | } |
hilgo | 0:0630ffe718d3 | 193 | |
hilgo | 0:0630ffe718d3 | 194 | uint8_t MRF24J40::ReadShort (uint8_t address) |
hilgo | 0:0630ffe718d3 | 195 | { |
hilgo | 0:0630ffe718d3 | 196 | uint8_t value; |
hilgo | 0:0630ffe718d3 | 197 | mCs = 0; |
hilgo | 0:0630ffe718d3 | 198 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 199 | mSpi.write((address<<1) & 0x7E); |
hilgo | 0:0630ffe718d3 | 200 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 201 | value = mSpi.write(0xFF); |
hilgo | 0:0630ffe718d3 | 202 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 203 | mCs = 1; |
hilgo | 0:0630ffe718d3 | 204 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 205 | return value; |
hilgo | 0:0630ffe718d3 | 206 | } |
hilgo | 0:0630ffe718d3 | 207 | |
hilgo | 0:0630ffe718d3 | 208 | void MRF24J40::WriteShort (uint8_t address, uint8_t data) |
hilgo | 0:0630ffe718d3 | 209 | { |
hilgo | 0:0630ffe718d3 | 210 | mCs = 0; |
hilgo | 0:0630ffe718d3 | 211 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 212 | mSpi.write(((address<<1) & 0x7E) | 0x01); |
hilgo | 0:0630ffe718d3 | 213 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 214 | mSpi.write(data); |
hilgo | 0:0630ffe718d3 | 215 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 216 | mCs = 1; |
hilgo | 0:0630ffe718d3 | 217 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 218 | } |
hilgo | 0:0630ffe718d3 | 219 | |
hilgo | 0:0630ffe718d3 | 220 | uint8_t MRF24J40::ReadLong (uint16_t address) |
hilgo | 0:0630ffe718d3 | 221 | { |
hilgo | 0:0630ffe718d3 | 222 | uint8_t value; |
hilgo | 0:0630ffe718d3 | 223 | mCs = 0; |
hilgo | 0:0630ffe718d3 | 224 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 225 | mSpi.write((address>>3) | 0x80); |
hilgo | 0:0630ffe718d3 | 226 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 227 | mSpi.write((address<<5) & 0xE0); |
hilgo | 0:0630ffe718d3 | 228 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 229 | value = mSpi.write(0xFF); |
hilgo | 0:0630ffe718d3 | 230 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 231 | mCs = 1; |
hilgo | 0:0630ffe718d3 | 232 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 233 | return value; |
hilgo | 0:0630ffe718d3 | 234 | } |
hilgo | 0:0630ffe718d3 | 235 | |
hilgo | 0:0630ffe718d3 | 236 | void MRF24J40::WriteLong (uint16_t address, uint8_t data) |
hilgo | 0:0630ffe718d3 | 237 | { |
hilgo | 0:0630ffe718d3 | 238 | mCs = 0; |
hilgo | 0:0630ffe718d3 | 239 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 240 | mSpi.write((address>>3) | 0x80); |
hilgo | 0:0630ffe718d3 | 241 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 242 | mSpi.write(((address<<5) & 0xE0) | 0x10); |
hilgo | 0:0630ffe718d3 | 243 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 244 | mSpi.write(data); |
hilgo | 0:0630ffe718d3 | 245 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 246 | mCs = 1; |
hilgo | 0:0630ffe718d3 | 247 | wait_us(1); |
hilgo | 0:0630ffe718d3 | 248 | } |
nbremond | 3:f8a30ff66793 | 249 | |
nbremond | 3:f8a30ff66793 | 250 | |
nbremond | 3:f8a30ff66793 | 251 | void MRF24J40::PrintBuffer(Serial &ser, uint8_t *buffer, uint8_t bufferSize) |
nbremond | 3:f8a30ff66793 | 252 | { |
nbremond | 3:f8a30ff66793 | 253 | for(uint8_t i=0; i<bufferSize; i++) |
nbremond | 3:f8a30ff66793 | 254 | { |
nbremond | 3:f8a30ff66793 | 255 | ser.printf("0x%02X ", buffer[i]); |
nbremond | 3:f8a30ff66793 | 256 | } |
nbremond | 3:f8a30ff66793 | 257 | ser.printf("\r\n"); |
nbremond | 3:f8a30ff66793 | 258 | } |