Diff: targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c

Revision:

19:112740acecfa

Parent:

0:9b334a45a8ff

diff -r da299f395b9e -r 112740acecfa targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c	Mon Nov 09 13:30:11 2015 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c	Tue Nov 10 09:30:11 2015 +0000
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_rcc.c
   * @author  MCD Application Team
-  * @version V1.3.2
-  * @date    26-June-2015
+  * @version V1.4.1
+  * @date    09-October-2015
   * @brief   RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -214,6 +214,12 @@
              PCLK2 84 MHz and PCLK1 42 MHz. 
              Depending on the device voltage range, the maximum frequency should
              be adapted accordingly (refer to the product datasheets for more details).
+             
+         (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
+             PCLK2 100 MHz and PCLK1 50 MHz. 
+             Depending on the device voltage range, the maximum frequency should
+             be adapted accordingly (refer to the product datasheets for more details).
+             
 @endverbatim
   * @{
   */
@@ -222,7 +228,7 @@
   * @brief  Resets the RCC clock configuration to the default reset state.
   * @note   The default reset state of the clock configuration is given below:
   *            - HSI ON and used as system clock source
-  *            - HSE, PLL and PLLI2S OFF
+  *            - HSE and PLL OFF
   *            - AHB, APB1 and APB2 prescaler set to 1.
   *            - CSS, MCO1 and MCO2 OFF
   *            - All interrupts disabled
@@ -231,31 +237,8 @@
   *            - LSI, LSE and RTC clocks 
   * @retval None
   */
-void HAL_RCC_DeInit(void)
-{
-  /* Set HSION bit */
-  SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); 
-  
-  /* Reset CFGR register */
-  CLEAR_REG(RCC->CFGR);
-  
-  /* Reset HSEON, CSSON, PLLON, PLLI2S */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON); 
-  
-  /* Reset PLLCFGR register */
-  CLEAR_REG(RCC->PLLCFGR);
-  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); 
-  
-  /* Reset PLLI2SCFGR register */
-  CLEAR_REG(RCC->PLLI2SCFGR);
-  SET_BIT(RCC->PLLI2SCFGR,  RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
-  
-  /* Reset HSEBYP bit */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-  
-  /* Disable all interrupts */
-  CLEAR_REG(RCC->CIR); 
-}
+__weak void HAL_RCC_DeInit(void)
+{}
 
 /**
   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
@@ -882,7 +865,8 @@
   *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
   *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
   *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx 
+  *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices   
   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
   *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
   * @param  RCC_MCODiv: specifies the MCOx prescaler.
@@ -892,6 +876,8 @@
   *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
   *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
   *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  * @note  For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
+  *        at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
   * @retval None
   */
 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
@@ -918,6 +904,11 @@
     
     /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
+    
+   /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
+#if defined(RCC_CFGR_MCO1EN)
+    __HAL_RCC_MCO1_ENABLE();
+#endif /* RCC_CFGR_MCO1EN */    
   }
   else
   {
@@ -936,6 +927,11 @@
     
     /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
+
+   /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
+#if defined(RCC_CFGR_MCO2EN)
+    __HAL_RCC_MCO2_ENABLE();
+#endif /* RCC_CFGR_MCO2EN */
   }
 }