fix LPC812 PWM
Fork of mbed-dev by
targets/cmsis/core_caFunc.h@66:fdb3f9f9a72f, 2016-02-18 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Feb 18 09:45:10 2016 +0000
- Revision:
- 66:fdb3f9f9a72f
- Parent:
- 0:9b334a45a8ff
Synchronized with git revision b57f7d56840134d072ca567460a86b77fb7adcf8
Full URL: https://github.com/mbedmicro/mbed/commit/b57f7d56840134d072ca567460a86b77fb7adcf8/
Support of export function to the IAR.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /**************************************************************************//** |
bogdanm | 0:9b334a45a8ff | 2 | * @file core_caFunc.h |
bogdanm | 0:9b334a45a8ff | 3 | * @brief CMSIS Cortex-A Core Function Access Header File |
bogdanm | 0:9b334a45a8ff | 4 | * @version V3.10 |
bogdanm | 0:9b334a45a8ff | 5 | * @date 30 Oct 2013 |
bogdanm | 0:9b334a45a8ff | 6 | * |
bogdanm | 0:9b334a45a8ff | 7 | * @note |
bogdanm | 0:9b334a45a8ff | 8 | * |
bogdanm | 0:9b334a45a8ff | 9 | ******************************************************************************/ |
bogdanm | 0:9b334a45a8ff | 10 | /* Copyright (c) 2009 - 2013 ARM LIMITED |
bogdanm | 0:9b334a45a8ff | 11 | |
bogdanm | 0:9b334a45a8ff | 12 | All rights reserved. |
bogdanm | 0:9b334a45a8ff | 13 | Redistribution and use in source and binary forms, with or without |
bogdanm | 0:9b334a45a8ff | 14 | modification, are permitted provided that the following conditions are met: |
bogdanm | 0:9b334a45a8ff | 15 | - Redistributions of source code must retain the above copyright |
bogdanm | 0:9b334a45a8ff | 16 | notice, this list of conditions and the following disclaimer. |
bogdanm | 0:9b334a45a8ff | 17 | - Redistributions in binary form must reproduce the above copyright |
bogdanm | 0:9b334a45a8ff | 18 | notice, this list of conditions and the following disclaimer in the |
bogdanm | 0:9b334a45a8ff | 19 | documentation and/or other materials provided with the distribution. |
bogdanm | 0:9b334a45a8ff | 20 | - Neither the name of ARM nor the names of its contributors may be used |
bogdanm | 0:9b334a45a8ff | 21 | to endorse or promote products derived from this software without |
bogdanm | 0:9b334a45a8ff | 22 | specific prior written permission. |
bogdanm | 0:9b334a45a8ff | 23 | * |
bogdanm | 0:9b334a45a8ff | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 0:9b334a45a8ff | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 0:9b334a45a8ff | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
bogdanm | 0:9b334a45a8ff | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
bogdanm | 0:9b334a45a8ff | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
bogdanm | 0:9b334a45a8ff | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
bogdanm | 0:9b334a45a8ff | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
bogdanm | 0:9b334a45a8ff | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
bogdanm | 0:9b334a45a8ff | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
bogdanm | 0:9b334a45a8ff | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
bogdanm | 0:9b334a45a8ff | 34 | POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 0:9b334a45a8ff | 35 | ---------------------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 36 | |
bogdanm | 0:9b334a45a8ff | 37 | |
bogdanm | 0:9b334a45a8ff | 38 | #ifndef __CORE_CAFUNC_H__ |
bogdanm | 0:9b334a45a8ff | 39 | #define __CORE_CAFUNC_H__ |
bogdanm | 0:9b334a45a8ff | 40 | |
bogdanm | 0:9b334a45a8ff | 41 | |
bogdanm | 0:9b334a45a8ff | 42 | /* ########################### Core Function Access ########################### */ |
bogdanm | 0:9b334a45a8ff | 43 | /** \ingroup CMSIS_Core_FunctionInterface |
bogdanm | 0:9b334a45a8ff | 44 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
bogdanm | 0:9b334a45a8ff | 45 | @{ |
bogdanm | 0:9b334a45a8ff | 46 | */ |
bogdanm | 0:9b334a45a8ff | 47 | |
bogdanm | 0:9b334a45a8ff | 48 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
bogdanm | 0:9b334a45a8ff | 49 | /* ARM armcc specific functions */ |
bogdanm | 0:9b334a45a8ff | 50 | |
bogdanm | 0:9b334a45a8ff | 51 | #if (__ARMCC_VERSION < 400677) |
bogdanm | 0:9b334a45a8ff | 52 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
bogdanm | 0:9b334a45a8ff | 53 | #endif |
bogdanm | 0:9b334a45a8ff | 54 | |
bogdanm | 0:9b334a45a8ff | 55 | #define MODE_USR 0x10 |
bogdanm | 0:9b334a45a8ff | 56 | #define MODE_FIQ 0x11 |
bogdanm | 0:9b334a45a8ff | 57 | #define MODE_IRQ 0x12 |
bogdanm | 0:9b334a45a8ff | 58 | #define MODE_SVC 0x13 |
bogdanm | 0:9b334a45a8ff | 59 | #define MODE_MON 0x16 |
bogdanm | 0:9b334a45a8ff | 60 | #define MODE_ABT 0x17 |
bogdanm | 0:9b334a45a8ff | 61 | #define MODE_HYP 0x1A |
bogdanm | 0:9b334a45a8ff | 62 | #define MODE_UND 0x1B |
bogdanm | 0:9b334a45a8ff | 63 | #define MODE_SYS 0x1F |
bogdanm | 0:9b334a45a8ff | 64 | |
bogdanm | 0:9b334a45a8ff | 65 | /** \brief Get APSR Register |
bogdanm | 0:9b334a45a8ff | 66 | |
bogdanm | 0:9b334a45a8ff | 67 | This function returns the content of the APSR Register. |
bogdanm | 0:9b334a45a8ff | 68 | |
bogdanm | 0:9b334a45a8ff | 69 | \return APSR Register value |
bogdanm | 0:9b334a45a8ff | 70 | */ |
bogdanm | 0:9b334a45a8ff | 71 | __STATIC_INLINE uint32_t __get_APSR(void) |
bogdanm | 0:9b334a45a8ff | 72 | { |
bogdanm | 0:9b334a45a8ff | 73 | register uint32_t __regAPSR __ASM("apsr"); |
bogdanm | 0:9b334a45a8ff | 74 | return(__regAPSR); |
bogdanm | 0:9b334a45a8ff | 75 | } |
bogdanm | 0:9b334a45a8ff | 76 | |
bogdanm | 0:9b334a45a8ff | 77 | |
bogdanm | 0:9b334a45a8ff | 78 | /** \brief Get CPSR Register |
bogdanm | 0:9b334a45a8ff | 79 | |
bogdanm | 0:9b334a45a8ff | 80 | This function returns the content of the CPSR Register. |
bogdanm | 0:9b334a45a8ff | 81 | |
bogdanm | 0:9b334a45a8ff | 82 | \return CPSR Register value |
bogdanm | 0:9b334a45a8ff | 83 | */ |
bogdanm | 0:9b334a45a8ff | 84 | __STATIC_INLINE uint32_t __get_CPSR(void) |
bogdanm | 0:9b334a45a8ff | 85 | { |
bogdanm | 0:9b334a45a8ff | 86 | register uint32_t __regCPSR __ASM("cpsr"); |
bogdanm | 0:9b334a45a8ff | 87 | return(__regCPSR); |
bogdanm | 0:9b334a45a8ff | 88 | } |
bogdanm | 0:9b334a45a8ff | 89 | |
bogdanm | 0:9b334a45a8ff | 90 | /** \brief Set Stack Pointer |
bogdanm | 0:9b334a45a8ff | 91 | |
bogdanm | 0:9b334a45a8ff | 92 | This function assigns the given value to the current stack pointer. |
bogdanm | 0:9b334a45a8ff | 93 | |
bogdanm | 0:9b334a45a8ff | 94 | \param [in] topOfStack Stack Pointer value to set |
bogdanm | 0:9b334a45a8ff | 95 | */ |
bogdanm | 0:9b334a45a8ff | 96 | register uint32_t __regSP __ASM("sp"); |
bogdanm | 0:9b334a45a8ff | 97 | __STATIC_INLINE void __set_SP(uint32_t topOfStack) |
bogdanm | 0:9b334a45a8ff | 98 | { |
bogdanm | 0:9b334a45a8ff | 99 | __regSP = topOfStack; |
bogdanm | 0:9b334a45a8ff | 100 | } |
bogdanm | 0:9b334a45a8ff | 101 | |
bogdanm | 0:9b334a45a8ff | 102 | |
bogdanm | 0:9b334a45a8ff | 103 | /** \brief Get link register |
bogdanm | 0:9b334a45a8ff | 104 | |
bogdanm | 0:9b334a45a8ff | 105 | This function returns the value of the link register |
bogdanm | 0:9b334a45a8ff | 106 | |
bogdanm | 0:9b334a45a8ff | 107 | \return Value of link register |
bogdanm | 0:9b334a45a8ff | 108 | */ |
bogdanm | 0:9b334a45a8ff | 109 | register uint32_t __reglr __ASM("lr"); |
bogdanm | 0:9b334a45a8ff | 110 | __STATIC_INLINE uint32_t __get_LR(void) |
bogdanm | 0:9b334a45a8ff | 111 | { |
bogdanm | 0:9b334a45a8ff | 112 | return(__reglr); |
bogdanm | 0:9b334a45a8ff | 113 | } |
bogdanm | 0:9b334a45a8ff | 114 | |
bogdanm | 0:9b334a45a8ff | 115 | /** \brief Set link register |
bogdanm | 0:9b334a45a8ff | 116 | |
bogdanm | 0:9b334a45a8ff | 117 | This function sets the value of the link register |
bogdanm | 0:9b334a45a8ff | 118 | |
bogdanm | 0:9b334a45a8ff | 119 | \param [in] lr LR value to set |
bogdanm | 0:9b334a45a8ff | 120 | */ |
bogdanm | 0:9b334a45a8ff | 121 | __STATIC_INLINE void __set_LR(uint32_t lr) |
bogdanm | 0:9b334a45a8ff | 122 | { |
bogdanm | 0:9b334a45a8ff | 123 | __reglr = lr; |
bogdanm | 0:9b334a45a8ff | 124 | } |
bogdanm | 0:9b334a45a8ff | 125 | |
bogdanm | 0:9b334a45a8ff | 126 | /** \brief Set Process Stack Pointer |
bogdanm | 0:9b334a45a8ff | 127 | |
bogdanm | 0:9b334a45a8ff | 128 | This function assigns the given value to the USR/SYS Stack Pointer (PSP). |
bogdanm | 0:9b334a45a8ff | 129 | |
bogdanm | 0:9b334a45a8ff | 130 | \param [in] topOfProcStack USR/SYS Stack Pointer value to set |
bogdanm | 0:9b334a45a8ff | 131 | */ |
bogdanm | 0:9b334a45a8ff | 132 | __STATIC_ASM void __set_PSP(uint32_t topOfProcStack) |
bogdanm | 0:9b334a45a8ff | 133 | { |
bogdanm | 0:9b334a45a8ff | 134 | ARM |
bogdanm | 0:9b334a45a8ff | 135 | PRESERVE8 |
bogdanm | 0:9b334a45a8ff | 136 | |
bogdanm | 0:9b334a45a8ff | 137 | BIC R0, R0, #7 ;ensure stack is 8-byte aligned |
bogdanm | 0:9b334a45a8ff | 138 | MRS R1, CPSR |
bogdanm | 0:9b334a45a8ff | 139 | CPS #MODE_SYS ;no effect in USR mode |
bogdanm | 0:9b334a45a8ff | 140 | MOV SP, R0 |
bogdanm | 0:9b334a45a8ff | 141 | MSR CPSR_c, R1 ;no effect in USR mode |
bogdanm | 0:9b334a45a8ff | 142 | ISB |
bogdanm | 0:9b334a45a8ff | 143 | BX LR |
bogdanm | 0:9b334a45a8ff | 144 | |
bogdanm | 0:9b334a45a8ff | 145 | } |
bogdanm | 0:9b334a45a8ff | 146 | |
bogdanm | 0:9b334a45a8ff | 147 | /** \brief Set User Mode |
bogdanm | 0:9b334a45a8ff | 148 | |
bogdanm | 0:9b334a45a8ff | 149 | This function changes the processor state to User Mode |
bogdanm | 0:9b334a45a8ff | 150 | */ |
bogdanm | 0:9b334a45a8ff | 151 | __STATIC_ASM void __set_CPS_USR(void) |
bogdanm | 0:9b334a45a8ff | 152 | { |
bogdanm | 0:9b334a45a8ff | 153 | ARM |
bogdanm | 0:9b334a45a8ff | 154 | |
bogdanm | 0:9b334a45a8ff | 155 | CPS #MODE_USR |
bogdanm | 0:9b334a45a8ff | 156 | BX LR |
bogdanm | 0:9b334a45a8ff | 157 | } |
bogdanm | 0:9b334a45a8ff | 158 | |
bogdanm | 0:9b334a45a8ff | 159 | |
bogdanm | 0:9b334a45a8ff | 160 | /** \brief Enable FIQ |
bogdanm | 0:9b334a45a8ff | 161 | |
bogdanm | 0:9b334a45a8ff | 162 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
bogdanm | 0:9b334a45a8ff | 163 | Can only be executed in Privileged modes. |
bogdanm | 0:9b334a45a8ff | 164 | */ |
bogdanm | 0:9b334a45a8ff | 165 | #define __enable_fault_irq __enable_fiq |
bogdanm | 0:9b334a45a8ff | 166 | |
bogdanm | 0:9b334a45a8ff | 167 | |
bogdanm | 0:9b334a45a8ff | 168 | /** \brief Disable FIQ |
bogdanm | 0:9b334a45a8ff | 169 | |
bogdanm | 0:9b334a45a8ff | 170 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
bogdanm | 0:9b334a45a8ff | 171 | Can only be executed in Privileged modes. |
bogdanm | 0:9b334a45a8ff | 172 | */ |
bogdanm | 0:9b334a45a8ff | 173 | #define __disable_fault_irq __disable_fiq |
bogdanm | 0:9b334a45a8ff | 174 | |
bogdanm | 0:9b334a45a8ff | 175 | |
bogdanm | 0:9b334a45a8ff | 176 | /** \brief Get FPSCR |
bogdanm | 0:9b334a45a8ff | 177 | |
bogdanm | 0:9b334a45a8ff | 178 | This function returns the current value of the Floating Point Status/Control register. |
bogdanm | 0:9b334a45a8ff | 179 | |
bogdanm | 0:9b334a45a8ff | 180 | \return Floating Point Status/Control register value |
bogdanm | 0:9b334a45a8ff | 181 | */ |
bogdanm | 0:9b334a45a8ff | 182 | __STATIC_INLINE uint32_t __get_FPSCR(void) |
bogdanm | 0:9b334a45a8ff | 183 | { |
bogdanm | 0:9b334a45a8ff | 184 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
bogdanm | 0:9b334a45a8ff | 185 | register uint32_t __regfpscr __ASM("fpscr"); |
bogdanm | 0:9b334a45a8ff | 186 | return(__regfpscr); |
bogdanm | 0:9b334a45a8ff | 187 | #else |
bogdanm | 0:9b334a45a8ff | 188 | return(0); |
bogdanm | 0:9b334a45a8ff | 189 | #endif |
bogdanm | 0:9b334a45a8ff | 190 | } |
bogdanm | 0:9b334a45a8ff | 191 | |
bogdanm | 0:9b334a45a8ff | 192 | |
bogdanm | 0:9b334a45a8ff | 193 | /** \brief Set FPSCR |
bogdanm | 0:9b334a45a8ff | 194 | |
bogdanm | 0:9b334a45a8ff | 195 | This function assigns the given value to the Floating Point Status/Control register. |
bogdanm | 0:9b334a45a8ff | 196 | |
bogdanm | 0:9b334a45a8ff | 197 | \param [in] fpscr Floating Point Status/Control value to set |
bogdanm | 0:9b334a45a8ff | 198 | */ |
bogdanm | 0:9b334a45a8ff | 199 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
bogdanm | 0:9b334a45a8ff | 200 | { |
bogdanm | 0:9b334a45a8ff | 201 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
bogdanm | 0:9b334a45a8ff | 202 | register uint32_t __regfpscr __ASM("fpscr"); |
bogdanm | 0:9b334a45a8ff | 203 | __regfpscr = (fpscr); |
bogdanm | 0:9b334a45a8ff | 204 | #endif |
bogdanm | 0:9b334a45a8ff | 205 | } |
bogdanm | 0:9b334a45a8ff | 206 | |
bogdanm | 0:9b334a45a8ff | 207 | /** \brief Get FPEXC |
bogdanm | 0:9b334a45a8ff | 208 | |
bogdanm | 0:9b334a45a8ff | 209 | This function returns the current value of the Floating Point Exception Control register. |
bogdanm | 0:9b334a45a8ff | 210 | |
bogdanm | 0:9b334a45a8ff | 211 | \return Floating Point Exception Control register value |
bogdanm | 0:9b334a45a8ff | 212 | */ |
bogdanm | 0:9b334a45a8ff | 213 | __STATIC_INLINE uint32_t __get_FPEXC(void) |
bogdanm | 0:9b334a45a8ff | 214 | { |
bogdanm | 0:9b334a45a8ff | 215 | #if (__FPU_PRESENT == 1) |
bogdanm | 0:9b334a45a8ff | 216 | register uint32_t __regfpexc __ASM("fpexc"); |
bogdanm | 0:9b334a45a8ff | 217 | return(__regfpexc); |
bogdanm | 0:9b334a45a8ff | 218 | #else |
bogdanm | 0:9b334a45a8ff | 219 | return(0); |
bogdanm | 0:9b334a45a8ff | 220 | #endif |
bogdanm | 0:9b334a45a8ff | 221 | } |
bogdanm | 0:9b334a45a8ff | 222 | |
bogdanm | 0:9b334a45a8ff | 223 | |
bogdanm | 0:9b334a45a8ff | 224 | /** \brief Set FPEXC |
bogdanm | 0:9b334a45a8ff | 225 | |
bogdanm | 0:9b334a45a8ff | 226 | This function assigns the given value to the Floating Point Exception Control register. |
bogdanm | 0:9b334a45a8ff | 227 | |
bogdanm | 0:9b334a45a8ff | 228 | \param [in] fpscr Floating Point Exception Control value to set |
bogdanm | 0:9b334a45a8ff | 229 | */ |
bogdanm | 0:9b334a45a8ff | 230 | __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) |
bogdanm | 0:9b334a45a8ff | 231 | { |
bogdanm | 0:9b334a45a8ff | 232 | #if (__FPU_PRESENT == 1) |
bogdanm | 0:9b334a45a8ff | 233 | register uint32_t __regfpexc __ASM("fpexc"); |
bogdanm | 0:9b334a45a8ff | 234 | __regfpexc = (fpexc); |
bogdanm | 0:9b334a45a8ff | 235 | #endif |
bogdanm | 0:9b334a45a8ff | 236 | } |
bogdanm | 0:9b334a45a8ff | 237 | |
bogdanm | 0:9b334a45a8ff | 238 | /** \brief Get CPACR |
bogdanm | 0:9b334a45a8ff | 239 | |
bogdanm | 0:9b334a45a8ff | 240 | This function returns the current value of the Coprocessor Access Control register. |
bogdanm | 0:9b334a45a8ff | 241 | |
bogdanm | 0:9b334a45a8ff | 242 | \return Coprocessor Access Control register value |
bogdanm | 0:9b334a45a8ff | 243 | */ |
bogdanm | 0:9b334a45a8ff | 244 | __STATIC_INLINE uint32_t __get_CPACR(void) |
bogdanm | 0:9b334a45a8ff | 245 | { |
bogdanm | 0:9b334a45a8ff | 246 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
bogdanm | 0:9b334a45a8ff | 247 | return __regCPACR; |
bogdanm | 0:9b334a45a8ff | 248 | } |
bogdanm | 0:9b334a45a8ff | 249 | |
bogdanm | 0:9b334a45a8ff | 250 | /** \brief Set CPACR |
bogdanm | 0:9b334a45a8ff | 251 | |
bogdanm | 0:9b334a45a8ff | 252 | This function assigns the given value to the Coprocessor Access Control register. |
bogdanm | 0:9b334a45a8ff | 253 | |
bogdanm | 0:9b334a45a8ff | 254 | \param [in] cpacr Coprocessor Acccess Control value to set |
bogdanm | 0:9b334a45a8ff | 255 | */ |
bogdanm | 0:9b334a45a8ff | 256 | __STATIC_INLINE void __set_CPACR(uint32_t cpacr) |
bogdanm | 0:9b334a45a8ff | 257 | { |
bogdanm | 0:9b334a45a8ff | 258 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
bogdanm | 0:9b334a45a8ff | 259 | __regCPACR = cpacr; |
bogdanm | 0:9b334a45a8ff | 260 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 261 | } |
bogdanm | 0:9b334a45a8ff | 262 | |
bogdanm | 0:9b334a45a8ff | 263 | /** \brief Get CBAR |
bogdanm | 0:9b334a45a8ff | 264 | |
bogdanm | 0:9b334a45a8ff | 265 | This function returns the value of the Configuration Base Address register. |
bogdanm | 0:9b334a45a8ff | 266 | |
bogdanm | 0:9b334a45a8ff | 267 | \return Configuration Base Address register value |
bogdanm | 0:9b334a45a8ff | 268 | */ |
bogdanm | 0:9b334a45a8ff | 269 | __STATIC_INLINE uint32_t __get_CBAR() { |
bogdanm | 0:9b334a45a8ff | 270 | register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0"); |
bogdanm | 0:9b334a45a8ff | 271 | return(__regCBAR); |
bogdanm | 0:9b334a45a8ff | 272 | } |
bogdanm | 0:9b334a45a8ff | 273 | |
bogdanm | 0:9b334a45a8ff | 274 | /** \brief Get TTBR0 |
bogdanm | 0:9b334a45a8ff | 275 | |
bogdanm | 0:9b334a45a8ff | 276 | This function returns the value of the Translation Table Base Register 0. |
bogdanm | 0:9b334a45a8ff | 277 | |
bogdanm | 0:9b334a45a8ff | 278 | \return Translation Table Base Register 0 value |
bogdanm | 0:9b334a45a8ff | 279 | */ |
bogdanm | 0:9b334a45a8ff | 280 | __STATIC_INLINE uint32_t __get_TTBR0() { |
bogdanm | 0:9b334a45a8ff | 281 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
bogdanm | 0:9b334a45a8ff | 282 | return(__regTTBR0); |
bogdanm | 0:9b334a45a8ff | 283 | } |
bogdanm | 0:9b334a45a8ff | 284 | |
bogdanm | 0:9b334a45a8ff | 285 | /** \brief Set TTBR0 |
bogdanm | 0:9b334a45a8ff | 286 | |
bogdanm | 0:9b334a45a8ff | 287 | This function assigns the given value to the Translation Table Base Register 0. |
bogdanm | 0:9b334a45a8ff | 288 | |
bogdanm | 0:9b334a45a8ff | 289 | \param [in] ttbr0 Translation Table Base Register 0 value to set |
bogdanm | 0:9b334a45a8ff | 290 | */ |
bogdanm | 0:9b334a45a8ff | 291 | __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { |
bogdanm | 0:9b334a45a8ff | 292 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
bogdanm | 0:9b334a45a8ff | 293 | __regTTBR0 = ttbr0; |
bogdanm | 0:9b334a45a8ff | 294 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 295 | } |
bogdanm | 0:9b334a45a8ff | 296 | |
bogdanm | 0:9b334a45a8ff | 297 | /** \brief Get DACR |
bogdanm | 0:9b334a45a8ff | 298 | |
bogdanm | 0:9b334a45a8ff | 299 | This function returns the value of the Domain Access Control Register. |
bogdanm | 0:9b334a45a8ff | 300 | |
bogdanm | 0:9b334a45a8ff | 301 | \return Domain Access Control Register value |
bogdanm | 0:9b334a45a8ff | 302 | */ |
bogdanm | 0:9b334a45a8ff | 303 | __STATIC_INLINE uint32_t __get_DACR() { |
bogdanm | 0:9b334a45a8ff | 304 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
bogdanm | 0:9b334a45a8ff | 305 | return(__regDACR); |
bogdanm | 0:9b334a45a8ff | 306 | } |
bogdanm | 0:9b334a45a8ff | 307 | |
bogdanm | 0:9b334a45a8ff | 308 | /** \brief Set DACR |
bogdanm | 0:9b334a45a8ff | 309 | |
bogdanm | 0:9b334a45a8ff | 310 | This function assigns the given value to the Domain Access Control Register. |
bogdanm | 0:9b334a45a8ff | 311 | |
bogdanm | 0:9b334a45a8ff | 312 | \param [in] dacr Domain Access Control Register value to set |
bogdanm | 0:9b334a45a8ff | 313 | */ |
bogdanm | 0:9b334a45a8ff | 314 | __STATIC_INLINE void __set_DACR(uint32_t dacr) { |
bogdanm | 0:9b334a45a8ff | 315 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
bogdanm | 0:9b334a45a8ff | 316 | __regDACR = dacr; |
bogdanm | 0:9b334a45a8ff | 317 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 318 | } |
bogdanm | 0:9b334a45a8ff | 319 | |
bogdanm | 0:9b334a45a8ff | 320 | /******************************** Cache and BTAC enable ****************************************************/ |
bogdanm | 0:9b334a45a8ff | 321 | |
bogdanm | 0:9b334a45a8ff | 322 | /** \brief Set SCTLR |
bogdanm | 0:9b334a45a8ff | 323 | |
bogdanm | 0:9b334a45a8ff | 324 | This function assigns the given value to the System Control Register. |
bogdanm | 0:9b334a45a8ff | 325 | |
bogdanm | 0:9b334a45a8ff | 326 | \param [in] sctlr System Control Register value to set |
bogdanm | 0:9b334a45a8ff | 327 | */ |
bogdanm | 0:9b334a45a8ff | 328 | __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) |
bogdanm | 0:9b334a45a8ff | 329 | { |
bogdanm | 0:9b334a45a8ff | 330 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
bogdanm | 0:9b334a45a8ff | 331 | __regSCTLR = sctlr; |
bogdanm | 0:9b334a45a8ff | 332 | } |
bogdanm | 0:9b334a45a8ff | 333 | |
bogdanm | 0:9b334a45a8ff | 334 | /** \brief Get SCTLR |
bogdanm | 0:9b334a45a8ff | 335 | |
bogdanm | 0:9b334a45a8ff | 336 | This function returns the value of the System Control Register. |
bogdanm | 0:9b334a45a8ff | 337 | |
bogdanm | 0:9b334a45a8ff | 338 | \return System Control Register value |
bogdanm | 0:9b334a45a8ff | 339 | */ |
bogdanm | 0:9b334a45a8ff | 340 | __STATIC_INLINE uint32_t __get_SCTLR() { |
bogdanm | 0:9b334a45a8ff | 341 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
bogdanm | 0:9b334a45a8ff | 342 | return(__regSCTLR); |
bogdanm | 0:9b334a45a8ff | 343 | } |
bogdanm | 0:9b334a45a8ff | 344 | |
bogdanm | 0:9b334a45a8ff | 345 | /** \brief Enable Caches |
bogdanm | 0:9b334a45a8ff | 346 | |
bogdanm | 0:9b334a45a8ff | 347 | Enable Caches |
bogdanm | 0:9b334a45a8ff | 348 | */ |
bogdanm | 0:9b334a45a8ff | 349 | __STATIC_INLINE void __enable_caches(void) { |
bogdanm | 0:9b334a45a8ff | 350 | // Set I bit 12 to enable I Cache |
bogdanm | 0:9b334a45a8ff | 351 | // Set C bit 2 to enable D Cache |
bogdanm | 0:9b334a45a8ff | 352 | __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); |
bogdanm | 0:9b334a45a8ff | 353 | } |
bogdanm | 0:9b334a45a8ff | 354 | |
bogdanm | 0:9b334a45a8ff | 355 | /** \brief Disable Caches |
bogdanm | 0:9b334a45a8ff | 356 | |
bogdanm | 0:9b334a45a8ff | 357 | Disable Caches |
bogdanm | 0:9b334a45a8ff | 358 | */ |
bogdanm | 0:9b334a45a8ff | 359 | __STATIC_INLINE void __disable_caches(void) { |
bogdanm | 0:9b334a45a8ff | 360 | // Clear I bit 12 to disable I Cache |
bogdanm | 0:9b334a45a8ff | 361 | // Clear C bit 2 to disable D Cache |
bogdanm | 0:9b334a45a8ff | 362 | __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2)); |
bogdanm | 0:9b334a45a8ff | 363 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 364 | } |
bogdanm | 0:9b334a45a8ff | 365 | |
bogdanm | 0:9b334a45a8ff | 366 | /** \brief Enable BTAC |
bogdanm | 0:9b334a45a8ff | 367 | |
bogdanm | 0:9b334a45a8ff | 368 | Enable BTAC |
bogdanm | 0:9b334a45a8ff | 369 | */ |
bogdanm | 0:9b334a45a8ff | 370 | __STATIC_INLINE void __enable_btac(void) { |
bogdanm | 0:9b334a45a8ff | 371 | // Set Z bit 11 to enable branch prediction |
bogdanm | 0:9b334a45a8ff | 372 | __set_SCTLR( __get_SCTLR() | (1 << 11)); |
bogdanm | 0:9b334a45a8ff | 373 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 374 | } |
bogdanm | 0:9b334a45a8ff | 375 | |
bogdanm | 0:9b334a45a8ff | 376 | /** \brief Disable BTAC |
bogdanm | 0:9b334a45a8ff | 377 | |
bogdanm | 0:9b334a45a8ff | 378 | Disable BTAC |
bogdanm | 0:9b334a45a8ff | 379 | */ |
bogdanm | 0:9b334a45a8ff | 380 | __STATIC_INLINE void __disable_btac(void) { |
bogdanm | 0:9b334a45a8ff | 381 | // Clear Z bit 11 to disable branch prediction |
bogdanm | 0:9b334a45a8ff | 382 | __set_SCTLR( __get_SCTLR() & ~(1 << 11)); |
bogdanm | 0:9b334a45a8ff | 383 | } |
bogdanm | 0:9b334a45a8ff | 384 | |
bogdanm | 0:9b334a45a8ff | 385 | |
bogdanm | 0:9b334a45a8ff | 386 | /** \brief Enable MMU |
bogdanm | 0:9b334a45a8ff | 387 | |
bogdanm | 0:9b334a45a8ff | 388 | Enable MMU |
bogdanm | 0:9b334a45a8ff | 389 | */ |
bogdanm | 0:9b334a45a8ff | 390 | __STATIC_INLINE void __enable_mmu(void) { |
bogdanm | 0:9b334a45a8ff | 391 | // Set M bit 0 to enable the MMU |
bogdanm | 0:9b334a45a8ff | 392 | // Set AFE bit to enable simplified access permissions model |
bogdanm | 0:9b334a45a8ff | 393 | // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking |
bogdanm | 0:9b334a45a8ff | 394 | __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); |
bogdanm | 0:9b334a45a8ff | 395 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 396 | } |
bogdanm | 0:9b334a45a8ff | 397 | |
bogdanm | 0:9b334a45a8ff | 398 | /** \brief Disable MMU |
bogdanm | 0:9b334a45a8ff | 399 | |
bogdanm | 0:9b334a45a8ff | 400 | Disable MMU |
bogdanm | 0:9b334a45a8ff | 401 | */ |
bogdanm | 0:9b334a45a8ff | 402 | __STATIC_INLINE void __disable_mmu(void) { |
bogdanm | 0:9b334a45a8ff | 403 | // Clear M bit 0 to disable the MMU |
bogdanm | 0:9b334a45a8ff | 404 | __set_SCTLR( __get_SCTLR() & ~1); |
bogdanm | 0:9b334a45a8ff | 405 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 406 | } |
bogdanm | 0:9b334a45a8ff | 407 | |
bogdanm | 0:9b334a45a8ff | 408 | /******************************** TLB maintenance operations ************************************************/ |
bogdanm | 0:9b334a45a8ff | 409 | /** \brief Invalidate the whole tlb |
bogdanm | 0:9b334a45a8ff | 410 | |
bogdanm | 0:9b334a45a8ff | 411 | TLBIALL. Invalidate the whole tlb |
bogdanm | 0:9b334a45a8ff | 412 | */ |
bogdanm | 0:9b334a45a8ff | 413 | |
bogdanm | 0:9b334a45a8ff | 414 | __STATIC_INLINE void __ca9u_inv_tlb_all(void) { |
bogdanm | 0:9b334a45a8ff | 415 | register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0"); |
bogdanm | 0:9b334a45a8ff | 416 | __TLBIALL = 0; |
bogdanm | 0:9b334a45a8ff | 417 | __DSB(); |
bogdanm | 0:9b334a45a8ff | 418 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 419 | } |
bogdanm | 0:9b334a45a8ff | 420 | |
bogdanm | 0:9b334a45a8ff | 421 | /******************************** BTB maintenance operations ************************************************/ |
bogdanm | 0:9b334a45a8ff | 422 | /** \brief Invalidate entire branch predictor array |
bogdanm | 0:9b334a45a8ff | 423 | |
bogdanm | 0:9b334a45a8ff | 424 | BPIALL. Branch Predictor Invalidate All. |
bogdanm | 0:9b334a45a8ff | 425 | */ |
bogdanm | 0:9b334a45a8ff | 426 | |
bogdanm | 0:9b334a45a8ff | 427 | __STATIC_INLINE void __v7_inv_btac(void) { |
bogdanm | 0:9b334a45a8ff | 428 | register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6"); |
bogdanm | 0:9b334a45a8ff | 429 | __BPIALL = 0; |
bogdanm | 0:9b334a45a8ff | 430 | __DSB(); //ensure completion of the invalidation |
bogdanm | 0:9b334a45a8ff | 431 | __ISB(); //ensure instruction fetch path sees new state |
bogdanm | 0:9b334a45a8ff | 432 | } |
bogdanm | 0:9b334a45a8ff | 433 | |
bogdanm | 0:9b334a45a8ff | 434 | |
bogdanm | 0:9b334a45a8ff | 435 | /******************************** L1 cache operations ******************************************************/ |
bogdanm | 0:9b334a45a8ff | 436 | |
bogdanm | 0:9b334a45a8ff | 437 | /** \brief Invalidate the whole I$ |
bogdanm | 0:9b334a45a8ff | 438 | |
bogdanm | 0:9b334a45a8ff | 439 | ICIALLU. Instruction Cache Invalidate All to PoU |
bogdanm | 0:9b334a45a8ff | 440 | */ |
bogdanm | 0:9b334a45a8ff | 441 | __STATIC_INLINE void __v7_inv_icache_all(void) { |
bogdanm | 0:9b334a45a8ff | 442 | register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0"); |
bogdanm | 0:9b334a45a8ff | 443 | __ICIALLU = 0; |
bogdanm | 0:9b334a45a8ff | 444 | __DSB(); //ensure completion of the invalidation |
bogdanm | 0:9b334a45a8ff | 445 | __ISB(); //ensure instruction fetch path sees new I cache state |
bogdanm | 0:9b334a45a8ff | 446 | } |
bogdanm | 0:9b334a45a8ff | 447 | |
bogdanm | 0:9b334a45a8ff | 448 | /** \brief Clean D$ by MVA |
bogdanm | 0:9b334a45a8ff | 449 | |
bogdanm | 0:9b334a45a8ff | 450 | DCCMVAC. Data cache clean by MVA to PoC |
bogdanm | 0:9b334a45a8ff | 451 | */ |
bogdanm | 0:9b334a45a8ff | 452 | __STATIC_INLINE void __v7_clean_dcache_mva(void *va) { |
bogdanm | 0:9b334a45a8ff | 453 | register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1"); |
bogdanm | 0:9b334a45a8ff | 454 | __DCCMVAC = (uint32_t)va; |
bogdanm | 0:9b334a45a8ff | 455 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
bogdanm | 0:9b334a45a8ff | 456 | } |
bogdanm | 0:9b334a45a8ff | 457 | |
bogdanm | 0:9b334a45a8ff | 458 | /** \brief Invalidate D$ by MVA |
bogdanm | 0:9b334a45a8ff | 459 | |
bogdanm | 0:9b334a45a8ff | 460 | DCIMVAC. Data cache invalidate by MVA to PoC |
bogdanm | 0:9b334a45a8ff | 461 | */ |
bogdanm | 0:9b334a45a8ff | 462 | __STATIC_INLINE void __v7_inv_dcache_mva(void *va) { |
bogdanm | 0:9b334a45a8ff | 463 | register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1"); |
bogdanm | 0:9b334a45a8ff | 464 | __DCIMVAC = (uint32_t)va; |
bogdanm | 0:9b334a45a8ff | 465 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
bogdanm | 0:9b334a45a8ff | 466 | } |
bogdanm | 0:9b334a45a8ff | 467 | |
bogdanm | 0:9b334a45a8ff | 468 | /** \brief Clean and Invalidate D$ by MVA |
bogdanm | 0:9b334a45a8ff | 469 | |
bogdanm | 0:9b334a45a8ff | 470 | DCCIMVAC. Data cache clean and invalidate by MVA to PoC |
bogdanm | 0:9b334a45a8ff | 471 | */ |
bogdanm | 0:9b334a45a8ff | 472 | __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) { |
bogdanm | 0:9b334a45a8ff | 473 | register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1"); |
bogdanm | 0:9b334a45a8ff | 474 | __DCCIMVAC = (uint32_t)va; |
bogdanm | 0:9b334a45a8ff | 475 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
bogdanm | 0:9b334a45a8ff | 476 | } |
bogdanm | 0:9b334a45a8ff | 477 | |
bogdanm | 0:9b334a45a8ff | 478 | /** \brief Clean and Invalidate the entire data or unified cache |
bogdanm | 0:9b334a45a8ff | 479 | |
bogdanm | 0:9b334a45a8ff | 480 | Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. |
bogdanm | 0:9b334a45a8ff | 481 | */ |
bogdanm | 0:9b334a45a8ff | 482 | #pragma push |
bogdanm | 0:9b334a45a8ff | 483 | #pragma arm |
bogdanm | 0:9b334a45a8ff | 484 | __STATIC_ASM void __v7_all_cache(uint32_t op) { |
bogdanm | 0:9b334a45a8ff | 485 | ARM |
bogdanm | 0:9b334a45a8ff | 486 | |
bogdanm | 0:9b334a45a8ff | 487 | PUSH {R4-R11} |
bogdanm | 0:9b334a45a8ff | 488 | |
bogdanm | 0:9b334a45a8ff | 489 | MRC p15, 1, R6, c0, c0, 1 // Read CLIDR |
bogdanm | 0:9b334a45a8ff | 490 | ANDS R3, R6, #0x07000000 // Extract coherency level |
bogdanm | 0:9b334a45a8ff | 491 | MOV R3, R3, LSR #23 // Total cache levels << 1 |
bogdanm | 0:9b334a45a8ff | 492 | BEQ Finished // If 0, no need to clean |
bogdanm | 0:9b334a45a8ff | 493 | |
bogdanm | 0:9b334a45a8ff | 494 | MOV R10, #0 // R10 holds current cache level << 1 |
bogdanm | 0:9b334a45a8ff | 495 | Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position |
bogdanm | 0:9b334a45a8ff | 496 | MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level |
bogdanm | 0:9b334a45a8ff | 497 | AND R1, R1, #7 // Isolate those lower 3 bits |
bogdanm | 0:9b334a45a8ff | 498 | CMP R1, #2 |
bogdanm | 0:9b334a45a8ff | 499 | BLT Skip // No cache or only instruction cache at this level |
bogdanm | 0:9b334a45a8ff | 500 | |
bogdanm | 0:9b334a45a8ff | 501 | MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register |
bogdanm | 0:9b334a45a8ff | 502 | ISB // ISB to sync the change to the CacheSizeID reg |
bogdanm | 0:9b334a45a8ff | 503 | MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register |
bogdanm | 0:9b334a45a8ff | 504 | AND R2, R1, #7 // Extract the line length field |
bogdanm | 0:9b334a45a8ff | 505 | ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes) |
bogdanm | 0:9b334a45a8ff | 506 | LDR R4, =0x3FF |
bogdanm | 0:9b334a45a8ff | 507 | ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned) |
bogdanm | 0:9b334a45a8ff | 508 | CLZ R5, R4 // R5 is the bit position of the way size increment |
bogdanm | 0:9b334a45a8ff | 509 | LDR R7, =0x7FFF |
bogdanm | 0:9b334a45a8ff | 510 | ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned) |
bogdanm | 0:9b334a45a8ff | 511 | |
bogdanm | 0:9b334a45a8ff | 512 | Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned) |
bogdanm | 0:9b334a45a8ff | 513 | |
bogdanm | 0:9b334a45a8ff | 514 | Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11 |
bogdanm | 0:9b334a45a8ff | 515 | ORR R11, R11, R7, LSL R2 // Factor in the Set number |
bogdanm | 0:9b334a45a8ff | 516 | CMP R0, #0 |
bogdanm | 0:9b334a45a8ff | 517 | BNE Dccsw |
bogdanm | 0:9b334a45a8ff | 518 | MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way |
bogdanm | 0:9b334a45a8ff | 519 | B cont |
bogdanm | 0:9b334a45a8ff | 520 | Dccsw CMP R0, #1 |
bogdanm | 0:9b334a45a8ff | 521 | BNE Dccisw |
bogdanm | 0:9b334a45a8ff | 522 | MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way |
bogdanm | 0:9b334a45a8ff | 523 | B cont |
bogdanm | 0:9b334a45a8ff | 524 | Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way |
bogdanm | 0:9b334a45a8ff | 525 | cont SUBS R9, R9, #1 // Decrement the Way number |
bogdanm | 0:9b334a45a8ff | 526 | BGE Loop3 |
bogdanm | 0:9b334a45a8ff | 527 | SUBS R7, R7, #1 // Decrement the Set number |
bogdanm | 0:9b334a45a8ff | 528 | BGE Loop2 |
bogdanm | 0:9b334a45a8ff | 529 | Skip ADD R10, R10, #2 // Increment the cache number |
bogdanm | 0:9b334a45a8ff | 530 | CMP R3, R10 |
bogdanm | 0:9b334a45a8ff | 531 | BGT Loop1 |
bogdanm | 0:9b334a45a8ff | 532 | |
bogdanm | 0:9b334a45a8ff | 533 | Finished |
bogdanm | 0:9b334a45a8ff | 534 | DSB |
bogdanm | 0:9b334a45a8ff | 535 | POP {R4-R11} |
bogdanm | 0:9b334a45a8ff | 536 | BX lr |
bogdanm | 0:9b334a45a8ff | 537 | |
bogdanm | 0:9b334a45a8ff | 538 | } |
bogdanm | 0:9b334a45a8ff | 539 | #pragma pop |
bogdanm | 0:9b334a45a8ff | 540 | |
bogdanm | 0:9b334a45a8ff | 541 | |
bogdanm | 0:9b334a45a8ff | 542 | /** \brief Invalidate the whole D$ |
bogdanm | 0:9b334a45a8ff | 543 | |
bogdanm | 0:9b334a45a8ff | 544 | DCISW. Invalidate by Set/Way |
bogdanm | 0:9b334a45a8ff | 545 | */ |
bogdanm | 0:9b334a45a8ff | 546 | |
bogdanm | 0:9b334a45a8ff | 547 | __STATIC_INLINE void __v7_inv_dcache_all(void) { |
bogdanm | 0:9b334a45a8ff | 548 | __v7_all_cache(0); |
bogdanm | 0:9b334a45a8ff | 549 | } |
bogdanm | 0:9b334a45a8ff | 550 | |
bogdanm | 0:9b334a45a8ff | 551 | /** \brief Clean the whole D$ |
bogdanm | 0:9b334a45a8ff | 552 | |
bogdanm | 0:9b334a45a8ff | 553 | DCCSW. Clean by Set/Way |
bogdanm | 0:9b334a45a8ff | 554 | */ |
bogdanm | 0:9b334a45a8ff | 555 | |
bogdanm | 0:9b334a45a8ff | 556 | __STATIC_INLINE void __v7_clean_dcache_all(void) { |
bogdanm | 0:9b334a45a8ff | 557 | __v7_all_cache(1); |
bogdanm | 0:9b334a45a8ff | 558 | } |
bogdanm | 0:9b334a45a8ff | 559 | |
bogdanm | 0:9b334a45a8ff | 560 | /** \brief Clean and invalidate the whole D$ |
bogdanm | 0:9b334a45a8ff | 561 | |
bogdanm | 0:9b334a45a8ff | 562 | DCCISW. Clean and Invalidate by Set/Way |
bogdanm | 0:9b334a45a8ff | 563 | */ |
bogdanm | 0:9b334a45a8ff | 564 | |
bogdanm | 0:9b334a45a8ff | 565 | __STATIC_INLINE void __v7_clean_inv_dcache_all(void) { |
bogdanm | 0:9b334a45a8ff | 566 | __v7_all_cache(2); |
bogdanm | 0:9b334a45a8ff | 567 | } |
bogdanm | 0:9b334a45a8ff | 568 | |
bogdanm | 0:9b334a45a8ff | 569 | #include "core_ca_mmu.h" |
bogdanm | 0:9b334a45a8ff | 570 | |
bogdanm | 0:9b334a45a8ff | 571 | #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ |
bogdanm | 0:9b334a45a8ff | 572 | |
mbed_official | 66:fdb3f9f9a72f | 573 | #define __inline inline |
mbed_official | 66:fdb3f9f9a72f | 574 | |
mbed_official | 66:fdb3f9f9a72f | 575 | inline static uint32_t __disable_irq_iar() { |
mbed_official | 66:fdb3f9f9a72f | 576 | int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I |
mbed_official | 66:fdb3f9f9a72f | 577 | __disable_irq(); |
mbed_official | 66:fdb3f9f9a72f | 578 | return irq_dis; |
mbed_official | 66:fdb3f9f9a72f | 579 | } |
mbed_official | 66:fdb3f9f9a72f | 580 | |
mbed_official | 66:fdb3f9f9a72f | 581 | #define MODE_USR 0x10 |
mbed_official | 66:fdb3f9f9a72f | 582 | #define MODE_FIQ 0x11 |
mbed_official | 66:fdb3f9f9a72f | 583 | #define MODE_IRQ 0x12 |
mbed_official | 66:fdb3f9f9a72f | 584 | #define MODE_SVC 0x13 |
mbed_official | 66:fdb3f9f9a72f | 585 | #define MODE_MON 0x16 |
mbed_official | 66:fdb3f9f9a72f | 586 | #define MODE_ABT 0x17 |
mbed_official | 66:fdb3f9f9a72f | 587 | #define MODE_HYP 0x1A |
mbed_official | 66:fdb3f9f9a72f | 588 | #define MODE_UND 0x1B |
mbed_official | 66:fdb3f9f9a72f | 589 | #define MODE_SYS 0x1F |
mbed_official | 66:fdb3f9f9a72f | 590 | |
mbed_official | 66:fdb3f9f9a72f | 591 | /** \brief Set Process Stack Pointer |
mbed_official | 66:fdb3f9f9a72f | 592 | |
mbed_official | 66:fdb3f9f9a72f | 593 | This function assigns the given value to the USR/SYS Stack Pointer (PSP). |
mbed_official | 66:fdb3f9f9a72f | 594 | |
mbed_official | 66:fdb3f9f9a72f | 595 | \param [in] topOfProcStack USR/SYS Stack Pointer value to set |
mbed_official | 66:fdb3f9f9a72f | 596 | */ |
mbed_official | 66:fdb3f9f9a72f | 597 | // from rt_CMSIS.c |
mbed_official | 66:fdb3f9f9a72f | 598 | __arm static inline void __set_PSP(uint32_t topOfProcStack) { |
mbed_official | 66:fdb3f9f9a72f | 599 | __asm( |
mbed_official | 66:fdb3f9f9a72f | 600 | " ARM\n" |
mbed_official | 66:fdb3f9f9a72f | 601 | // " PRESERVE8\n" |
mbed_official | 66:fdb3f9f9a72f | 602 | |
mbed_official | 66:fdb3f9f9a72f | 603 | " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n" |
mbed_official | 66:fdb3f9f9a72f | 604 | " MRS R1, CPSR \n" |
mbed_official | 66:fdb3f9f9a72f | 605 | " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS |
mbed_official | 66:fdb3f9f9a72f | 606 | " MOV SP, R0 \n" |
mbed_official | 66:fdb3f9f9a72f | 607 | " MSR CPSR_c, R1 ;no effect in USR mode \n" |
mbed_official | 66:fdb3f9f9a72f | 608 | " ISB \n" |
mbed_official | 66:fdb3f9f9a72f | 609 | " BX LR \n"); |
mbed_official | 66:fdb3f9f9a72f | 610 | } |
mbed_official | 66:fdb3f9f9a72f | 611 | |
mbed_official | 66:fdb3f9f9a72f | 612 | /** \brief Set User Mode |
mbed_official | 66:fdb3f9f9a72f | 613 | |
mbed_official | 66:fdb3f9f9a72f | 614 | This function changes the processor state to User Mode |
mbed_official | 66:fdb3f9f9a72f | 615 | */ |
mbed_official | 66:fdb3f9f9a72f | 616 | // from rt_CMSIS.c |
mbed_official | 66:fdb3f9f9a72f | 617 | __arm static inline void __set_CPS_USR(void) { |
mbed_official | 66:fdb3f9f9a72f | 618 | __asm( |
mbed_official | 66:fdb3f9f9a72f | 619 | " ARM \n" |
mbed_official | 66:fdb3f9f9a72f | 620 | |
mbed_official | 66:fdb3f9f9a72f | 621 | " CPS #0x10 \n" // MODE_USR |
mbed_official | 66:fdb3f9f9a72f | 622 | " BX LR\n"); |
mbed_official | 66:fdb3f9f9a72f | 623 | } |
mbed_official | 66:fdb3f9f9a72f | 624 | |
mbed_official | 66:fdb3f9f9a72f | 625 | /** \brief Set TTBR0 |
mbed_official | 66:fdb3f9f9a72f | 626 | |
mbed_official | 66:fdb3f9f9a72f | 627 | This function assigns the given value to the Translation Table Base Register 0. |
mbed_official | 66:fdb3f9f9a72f | 628 | |
mbed_official | 66:fdb3f9f9a72f | 629 | \param [in] ttbr0 Translation Table Base Register 0 value to set |
mbed_official | 66:fdb3f9f9a72f | 630 | */ |
mbed_official | 66:fdb3f9f9a72f | 631 | // from mmu_Renesas_RZ_A1.c |
mbed_official | 66:fdb3f9f9a72f | 632 | __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { |
mbed_official | 66:fdb3f9f9a72f | 633 | __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15 |
mbed_official | 66:fdb3f9f9a72f | 634 | __ISB(); |
mbed_official | 66:fdb3f9f9a72f | 635 | } |
mbed_official | 66:fdb3f9f9a72f | 636 | |
mbed_official | 66:fdb3f9f9a72f | 637 | /** \brief Set DACR |
mbed_official | 66:fdb3f9f9a72f | 638 | |
mbed_official | 66:fdb3f9f9a72f | 639 | This function assigns the given value to the Domain Access Control Register. |
mbed_official | 66:fdb3f9f9a72f | 640 | |
mbed_official | 66:fdb3f9f9a72f | 641 | \param [in] dacr Domain Access Control Register value to set |
mbed_official | 66:fdb3f9f9a72f | 642 | */ |
mbed_official | 66:fdb3f9f9a72f | 643 | // from mmu_Renesas_RZ_A1.c |
mbed_official | 66:fdb3f9f9a72f | 644 | __STATIC_INLINE void __set_DACR(uint32_t dacr) { |
mbed_official | 66:fdb3f9f9a72f | 645 | __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15 |
mbed_official | 66:fdb3f9f9a72f | 646 | __ISB(); |
mbed_official | 66:fdb3f9f9a72f | 647 | } |
mbed_official | 66:fdb3f9f9a72f | 648 | |
mbed_official | 66:fdb3f9f9a72f | 649 | |
mbed_official | 66:fdb3f9f9a72f | 650 | /******************************** Cache and BTAC enable ****************************************************/ |
mbed_official | 66:fdb3f9f9a72f | 651 | /** \brief Set SCTLR |
mbed_official | 66:fdb3f9f9a72f | 652 | |
mbed_official | 66:fdb3f9f9a72f | 653 | This function assigns the given value to the System Control Register. |
mbed_official | 66:fdb3f9f9a72f | 654 | |
mbed_official | 66:fdb3f9f9a72f | 655 | \param [in] sctlr System Control Register value to set |
mbed_official | 66:fdb3f9f9a72f | 656 | */ |
mbed_official | 66:fdb3f9f9a72f | 657 | // from __enable_mmu() |
mbed_official | 66:fdb3f9f9a72f | 658 | __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) { |
mbed_official | 66:fdb3f9f9a72f | 659 | __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15 |
mbed_official | 66:fdb3f9f9a72f | 660 | } |
mbed_official | 66:fdb3f9f9a72f | 661 | |
mbed_official | 66:fdb3f9f9a72f | 662 | /** \brief Get SCTLR |
mbed_official | 66:fdb3f9f9a72f | 663 | |
mbed_official | 66:fdb3f9f9a72f | 664 | This function returns the value of the System Control Register. |
mbed_official | 66:fdb3f9f9a72f | 665 | |
mbed_official | 66:fdb3f9f9a72f | 666 | \return System Control Register value |
mbed_official | 66:fdb3f9f9a72f | 667 | */ |
mbed_official | 66:fdb3f9f9a72f | 668 | // from __enable_mmu() |
mbed_official | 66:fdb3f9f9a72f | 669 | __STATIC_INLINE uint32_t __get_SCTLR() { |
mbed_official | 66:fdb3f9f9a72f | 670 | uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0); |
mbed_official | 66:fdb3f9f9a72f | 671 | return __regSCTLR; |
mbed_official | 66:fdb3f9f9a72f | 672 | } |
mbed_official | 66:fdb3f9f9a72f | 673 | |
mbed_official | 66:fdb3f9f9a72f | 674 | /** \brief Enable Caches |
mbed_official | 66:fdb3f9f9a72f | 675 | |
mbed_official | 66:fdb3f9f9a72f | 676 | Enable Caches |
mbed_official | 66:fdb3f9f9a72f | 677 | */ |
mbed_official | 66:fdb3f9f9a72f | 678 | // from system_Renesas_RZ_A1.c |
mbed_official | 66:fdb3f9f9a72f | 679 | __STATIC_INLINE void __enable_caches(void) { |
mbed_official | 66:fdb3f9f9a72f | 680 | __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); |
mbed_official | 66:fdb3f9f9a72f | 681 | } |
mbed_official | 66:fdb3f9f9a72f | 682 | |
mbed_official | 66:fdb3f9f9a72f | 683 | /** \brief Enable BTAC |
mbed_official | 66:fdb3f9f9a72f | 684 | |
mbed_official | 66:fdb3f9f9a72f | 685 | Enable BTAC |
mbed_official | 66:fdb3f9f9a72f | 686 | */ |
mbed_official | 66:fdb3f9f9a72f | 687 | // from system_Renesas_RZ_A1.c |
mbed_official | 66:fdb3f9f9a72f | 688 | __STATIC_INLINE void __enable_btac(void) { |
mbed_official | 66:fdb3f9f9a72f | 689 | __set_SCTLR( __get_SCTLR() | (1 << 11)); |
mbed_official | 66:fdb3f9f9a72f | 690 | __ISB(); |
mbed_official | 66:fdb3f9f9a72f | 691 | } |
mbed_official | 66:fdb3f9f9a72f | 692 | |
mbed_official | 66:fdb3f9f9a72f | 693 | /** \brief Enable MMU |
mbed_official | 66:fdb3f9f9a72f | 694 | |
mbed_official | 66:fdb3f9f9a72f | 695 | Enable MMU |
mbed_official | 66:fdb3f9f9a72f | 696 | */ |
mbed_official | 66:fdb3f9f9a72f | 697 | // from system_Renesas_RZ_A1.c |
mbed_official | 66:fdb3f9f9a72f | 698 | __STATIC_INLINE void __enable_mmu(void) { |
mbed_official | 66:fdb3f9f9a72f | 699 | // Set M bit 0 to enable the MMU |
mbed_official | 66:fdb3f9f9a72f | 700 | // Set AFE bit to enable simplified access permissions model |
mbed_official | 66:fdb3f9f9a72f | 701 | // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking |
mbed_official | 66:fdb3f9f9a72f | 702 | __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); |
mbed_official | 66:fdb3f9f9a72f | 703 | __ISB(); |
mbed_official | 66:fdb3f9f9a72f | 704 | } |
mbed_official | 66:fdb3f9f9a72f | 705 | |
mbed_official | 66:fdb3f9f9a72f | 706 | /******************************** TLB maintenance operations ************************************************/ |
mbed_official | 66:fdb3f9f9a72f | 707 | /** \brief Invalidate the whole tlb |
mbed_official | 66:fdb3f9f9a72f | 708 | |
mbed_official | 66:fdb3f9f9a72f | 709 | TLBIALL. Invalidate the whole tlb |
mbed_official | 66:fdb3f9f9a72f | 710 | */ |
mbed_official | 66:fdb3f9f9a72f | 711 | // from system_Renesas_RZ_A1.c |
mbed_official | 66:fdb3f9f9a72f | 712 | __STATIC_INLINE void __ca9u_inv_tlb_all(void) { |
mbed_official | 66:fdb3f9f9a72f | 713 | uint32_t val = 0; |
mbed_official | 66:fdb3f9f9a72f | 714 | __MCR(15, 0, val, 8, 7, 0); // reg to cp15 |
mbed_official | 66:fdb3f9f9a72f | 715 | __MCR(15, 0, val, 8, 6, 0); // reg to cp15 |
mbed_official | 66:fdb3f9f9a72f | 716 | __MCR(15, 0, val, 8, 5, 0); // reg to cp15 |
mbed_official | 66:fdb3f9f9a72f | 717 | __DSB(); |
mbed_official | 66:fdb3f9f9a72f | 718 | __ISB(); |
mbed_official | 66:fdb3f9f9a72f | 719 | } |
mbed_official | 66:fdb3f9f9a72f | 720 | |
mbed_official | 66:fdb3f9f9a72f | 721 | /******************************** BTB maintenance operations ************************************************/ |
mbed_official | 66:fdb3f9f9a72f | 722 | /** \brief Invalidate entire branch predictor array |
mbed_official | 66:fdb3f9f9a72f | 723 | |
mbed_official | 66:fdb3f9f9a72f | 724 | BPIALL. Branch Predictor Invalidate All. |
mbed_official | 66:fdb3f9f9a72f | 725 | */ |
mbed_official | 66:fdb3f9f9a72f | 726 | // from system_Renesas_RZ_A1.c |
mbed_official | 66:fdb3f9f9a72f | 727 | __STATIC_INLINE void __v7_inv_btac(void) { |
mbed_official | 66:fdb3f9f9a72f | 728 | uint32_t val = 0; |
mbed_official | 66:fdb3f9f9a72f | 729 | __MCR(15, 0, val, 7, 5, 6); // reg to cp15 |
mbed_official | 66:fdb3f9f9a72f | 730 | __DSB(); //ensure completion of the invalidation |
mbed_official | 66:fdb3f9f9a72f | 731 | __ISB(); //ensure instruction fetch path sees new state |
mbed_official | 66:fdb3f9f9a72f | 732 | } |
mbed_official | 66:fdb3f9f9a72f | 733 | |
mbed_official | 66:fdb3f9f9a72f | 734 | |
mbed_official | 66:fdb3f9f9a72f | 735 | /******************************** L1 cache operations ******************************************************/ |
mbed_official | 66:fdb3f9f9a72f | 736 | |
mbed_official | 66:fdb3f9f9a72f | 737 | /** \brief Invalidate the whole I$ |
mbed_official | 66:fdb3f9f9a72f | 738 | |
mbed_official | 66:fdb3f9f9a72f | 739 | ICIALLU. Instruction Cache Invalidate All to PoU |
mbed_official | 66:fdb3f9f9a72f | 740 | */ |
mbed_official | 66:fdb3f9f9a72f | 741 | // from system_Renesas_RZ_A1.c |
mbed_official | 66:fdb3f9f9a72f | 742 | __STATIC_INLINE void __v7_inv_icache_all(void) { |
mbed_official | 66:fdb3f9f9a72f | 743 | uint32_t val = 0; |
mbed_official | 66:fdb3f9f9a72f | 744 | __MCR(15, 0, val, 7, 5, 0); // reg to cp15 |
mbed_official | 66:fdb3f9f9a72f | 745 | __DSB(); //ensure completion of the invalidation |
mbed_official | 66:fdb3f9f9a72f | 746 | __ISB(); //ensure instruction fetch path sees new I cache state |
mbed_official | 66:fdb3f9f9a72f | 747 | } |
mbed_official | 66:fdb3f9f9a72f | 748 | |
mbed_official | 66:fdb3f9f9a72f | 749 | // from __v7_inv_dcache_all() |
mbed_official | 66:fdb3f9f9a72f | 750 | __arm static inline void __v7_all_cache(uint32_t op) { |
mbed_official | 66:fdb3f9f9a72f | 751 | __asm( |
mbed_official | 66:fdb3f9f9a72f | 752 | " ARM \n" |
mbed_official | 66:fdb3f9f9a72f | 753 | |
mbed_official | 66:fdb3f9f9a72f | 754 | " PUSH {R4-R11} \n" |
mbed_official | 66:fdb3f9f9a72f | 755 | |
mbed_official | 66:fdb3f9f9a72f | 756 | " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR |
mbed_official | 66:fdb3f9f9a72f | 757 | " ANDS R3, R6, #0x07000000\n" // Extract coherency level |
mbed_official | 66:fdb3f9f9a72f | 758 | " MOV R3, R3, LSR #23\n" // Total cache levels << 1 |
mbed_official | 66:fdb3f9f9a72f | 759 | " BEQ Finished\n" // If 0, no need to clean |
mbed_official | 66:fdb3f9f9a72f | 760 | |
mbed_official | 66:fdb3f9f9a72f | 761 | " MOV R10, #0\n" // R10 holds current cache level << 1 |
mbed_official | 66:fdb3f9f9a72f | 762 | "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position |
mbed_official | 66:fdb3f9f9a72f | 763 | " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level |
mbed_official | 66:fdb3f9f9a72f | 764 | " AND R1, R1, #7 \n" // Isolate those lower 3 bits |
mbed_official | 66:fdb3f9f9a72f | 765 | " CMP R1, #2 \n" |
mbed_official | 66:fdb3f9f9a72f | 766 | " BLT Skip \n" // No cache or only instruction cache at this level |
mbed_official | 66:fdb3f9f9a72f | 767 | |
mbed_official | 66:fdb3f9f9a72f | 768 | " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register |
mbed_official | 66:fdb3f9f9a72f | 769 | " ISB \n" // ISB to sync the change to the CacheSizeID reg |
mbed_official | 66:fdb3f9f9a72f | 770 | " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register |
mbed_official | 66:fdb3f9f9a72f | 771 | " AND R2, R1, #7 \n" // Extract the line length field |
mbed_official | 66:fdb3f9f9a72f | 772 | " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes) |
mbed_official | 66:fdb3f9f9a72f | 773 | " movw R4, #0x3FF \n" |
mbed_official | 66:fdb3f9f9a72f | 774 | " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned) |
mbed_official | 66:fdb3f9f9a72f | 775 | " CLZ R5, R4 \n" // R5 is the bit position of the way size increment |
mbed_official | 66:fdb3f9f9a72f | 776 | " movw R7, #0x7FFF \n" |
mbed_official | 66:fdb3f9f9a72f | 777 | " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned) |
mbed_official | 66:fdb3f9f9a72f | 778 | |
mbed_official | 66:fdb3f9f9a72f | 779 | "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned) |
mbed_official | 66:fdb3f9f9a72f | 780 | |
mbed_official | 66:fdb3f9f9a72f | 781 | "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11 |
mbed_official | 66:fdb3f9f9a72f | 782 | " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number |
mbed_official | 66:fdb3f9f9a72f | 783 | " CMP R0, #0 \n" |
mbed_official | 66:fdb3f9f9a72f | 784 | " BNE Dccsw \n" |
mbed_official | 66:fdb3f9f9a72f | 785 | " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way |
mbed_official | 66:fdb3f9f9a72f | 786 | " B cont \n" |
mbed_official | 66:fdb3f9f9a72f | 787 | "Dccsw: CMP R0, #1 \n" |
mbed_official | 66:fdb3f9f9a72f | 788 | " BNE Dccisw \n" |
mbed_official | 66:fdb3f9f9a72f | 789 | " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way |
mbed_official | 66:fdb3f9f9a72f | 790 | " B cont \n" |
mbed_official | 66:fdb3f9f9a72f | 791 | "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way |
mbed_official | 66:fdb3f9f9a72f | 792 | "cont: SUBS R9, R9, #1 \n" // Decrement the Way number |
mbed_official | 66:fdb3f9f9a72f | 793 | " BGE Loop3 \n" |
mbed_official | 66:fdb3f9f9a72f | 794 | " SUBS R7, R7, #1 \n" // Decrement the Set number |
mbed_official | 66:fdb3f9f9a72f | 795 | " BGE Loop2 \n" |
mbed_official | 66:fdb3f9f9a72f | 796 | "Skip: ADD R10, R10, #2 \n" // increment the cache number |
mbed_official | 66:fdb3f9f9a72f | 797 | " CMP R3, R10 \n" |
mbed_official | 66:fdb3f9f9a72f | 798 | " BGT Loop1 \n" |
mbed_official | 66:fdb3f9f9a72f | 799 | |
mbed_official | 66:fdb3f9f9a72f | 800 | "Finished: \n" |
mbed_official | 66:fdb3f9f9a72f | 801 | " DSB \n" |
mbed_official | 66:fdb3f9f9a72f | 802 | " POP {R4-R11} \n" |
mbed_official | 66:fdb3f9f9a72f | 803 | " BX lr \n" ); |
mbed_official | 66:fdb3f9f9a72f | 804 | } |
mbed_official | 66:fdb3f9f9a72f | 805 | |
mbed_official | 66:fdb3f9f9a72f | 806 | /** \brief Invalidate the whole D$ |
mbed_official | 66:fdb3f9f9a72f | 807 | |
mbed_official | 66:fdb3f9f9a72f | 808 | DCISW. Invalidate by Set/Way |
mbed_official | 66:fdb3f9f9a72f | 809 | */ |
mbed_official | 66:fdb3f9f9a72f | 810 | // from system_Renesas_RZ_A1.c |
mbed_official | 66:fdb3f9f9a72f | 811 | __STATIC_INLINE void __v7_inv_dcache_all(void) { |
mbed_official | 66:fdb3f9f9a72f | 812 | __v7_all_cache(0); |
mbed_official | 66:fdb3f9f9a72f | 813 | } |
mbed_official | 66:fdb3f9f9a72f | 814 | #include "core_ca_mmu.h" |
bogdanm | 0:9b334a45a8ff | 815 | |
bogdanm | 0:9b334a45a8ff | 816 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
bogdanm | 0:9b334a45a8ff | 817 | /* GNU gcc specific functions */ |
bogdanm | 0:9b334a45a8ff | 818 | |
bogdanm | 0:9b334a45a8ff | 819 | #define MODE_USR 0x10 |
bogdanm | 0:9b334a45a8ff | 820 | #define MODE_FIQ 0x11 |
bogdanm | 0:9b334a45a8ff | 821 | #define MODE_IRQ 0x12 |
bogdanm | 0:9b334a45a8ff | 822 | #define MODE_SVC 0x13 |
bogdanm | 0:9b334a45a8ff | 823 | #define MODE_MON 0x16 |
bogdanm | 0:9b334a45a8ff | 824 | #define MODE_ABT 0x17 |
bogdanm | 0:9b334a45a8ff | 825 | #define MODE_HYP 0x1A |
bogdanm | 0:9b334a45a8ff | 826 | #define MODE_UND 0x1B |
bogdanm | 0:9b334a45a8ff | 827 | #define MODE_SYS 0x1F |
bogdanm | 0:9b334a45a8ff | 828 | |
bogdanm | 0:9b334a45a8ff | 829 | |
bogdanm | 0:9b334a45a8ff | 830 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) |
bogdanm | 0:9b334a45a8ff | 831 | { |
bogdanm | 0:9b334a45a8ff | 832 | __ASM volatile ("cpsie i"); |
bogdanm | 0:9b334a45a8ff | 833 | } |
bogdanm | 0:9b334a45a8ff | 834 | |
bogdanm | 0:9b334a45a8ff | 835 | /** \brief Disable IRQ Interrupts |
bogdanm | 0:9b334a45a8ff | 836 | |
bogdanm | 0:9b334a45a8ff | 837 | This function disables IRQ interrupts by setting the I-bit in the CPSR. |
bogdanm | 0:9b334a45a8ff | 838 | Can only be executed in Privileged modes. |
bogdanm | 0:9b334a45a8ff | 839 | */ |
bogdanm | 0:9b334a45a8ff | 840 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void) |
bogdanm | 0:9b334a45a8ff | 841 | { |
bogdanm | 0:9b334a45a8ff | 842 | uint32_t result; |
bogdanm | 0:9b334a45a8ff | 843 | |
bogdanm | 0:9b334a45a8ff | 844 | __ASM volatile ("mrs %0, cpsr" : "=r" (result)); |
bogdanm | 0:9b334a45a8ff | 845 | __ASM volatile ("cpsid i"); |
bogdanm | 0:9b334a45a8ff | 846 | return(result & 0x80); |
bogdanm | 0:9b334a45a8ff | 847 | } |
bogdanm | 0:9b334a45a8ff | 848 | |
bogdanm | 0:9b334a45a8ff | 849 | |
bogdanm | 0:9b334a45a8ff | 850 | /** \brief Get APSR Register |
bogdanm | 0:9b334a45a8ff | 851 | |
bogdanm | 0:9b334a45a8ff | 852 | This function returns the content of the APSR Register. |
bogdanm | 0:9b334a45a8ff | 853 | |
bogdanm | 0:9b334a45a8ff | 854 | \return APSR Register value |
bogdanm | 0:9b334a45a8ff | 855 | */ |
bogdanm | 0:9b334a45a8ff | 856 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) |
bogdanm | 0:9b334a45a8ff | 857 | { |
bogdanm | 0:9b334a45a8ff | 858 | #if 1 |
bogdanm | 0:9b334a45a8ff | 859 | register uint32_t __regAPSR; |
bogdanm | 0:9b334a45a8ff | 860 | __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) ); |
bogdanm | 0:9b334a45a8ff | 861 | #else |
bogdanm | 0:9b334a45a8ff | 862 | register uint32_t __regAPSR __ASM("apsr"); |
bogdanm | 0:9b334a45a8ff | 863 | #endif |
bogdanm | 0:9b334a45a8ff | 864 | return(__regAPSR); |
bogdanm | 0:9b334a45a8ff | 865 | } |
bogdanm | 0:9b334a45a8ff | 866 | |
bogdanm | 0:9b334a45a8ff | 867 | |
bogdanm | 0:9b334a45a8ff | 868 | /** \brief Get CPSR Register |
bogdanm | 0:9b334a45a8ff | 869 | |
bogdanm | 0:9b334a45a8ff | 870 | This function returns the content of the CPSR Register. |
bogdanm | 0:9b334a45a8ff | 871 | |
bogdanm | 0:9b334a45a8ff | 872 | \return CPSR Register value |
bogdanm | 0:9b334a45a8ff | 873 | */ |
bogdanm | 0:9b334a45a8ff | 874 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void) |
bogdanm | 0:9b334a45a8ff | 875 | { |
bogdanm | 0:9b334a45a8ff | 876 | #if 1 |
bogdanm | 0:9b334a45a8ff | 877 | register uint32_t __regCPSR; |
bogdanm | 0:9b334a45a8ff | 878 | __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR)); |
bogdanm | 0:9b334a45a8ff | 879 | #else |
bogdanm | 0:9b334a45a8ff | 880 | register uint32_t __regCPSR __ASM("cpsr"); |
bogdanm | 0:9b334a45a8ff | 881 | #endif |
bogdanm | 0:9b334a45a8ff | 882 | return(__regCPSR); |
bogdanm | 0:9b334a45a8ff | 883 | } |
bogdanm | 0:9b334a45a8ff | 884 | |
bogdanm | 0:9b334a45a8ff | 885 | #if 0 |
bogdanm | 0:9b334a45a8ff | 886 | /** \brief Set Stack Pointer |
bogdanm | 0:9b334a45a8ff | 887 | |
bogdanm | 0:9b334a45a8ff | 888 | This function assigns the given value to the current stack pointer. |
bogdanm | 0:9b334a45a8ff | 889 | |
bogdanm | 0:9b334a45a8ff | 890 | \param [in] topOfStack Stack Pointer value to set |
bogdanm | 0:9b334a45a8ff | 891 | */ |
bogdanm | 0:9b334a45a8ff | 892 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack) |
bogdanm | 0:9b334a45a8ff | 893 | { |
bogdanm | 0:9b334a45a8ff | 894 | register uint32_t __regSP __ASM("sp"); |
bogdanm | 0:9b334a45a8ff | 895 | __regSP = topOfStack; |
bogdanm | 0:9b334a45a8ff | 896 | } |
bogdanm | 0:9b334a45a8ff | 897 | #endif |
bogdanm | 0:9b334a45a8ff | 898 | |
bogdanm | 0:9b334a45a8ff | 899 | /** \brief Get link register |
bogdanm | 0:9b334a45a8ff | 900 | |
bogdanm | 0:9b334a45a8ff | 901 | This function returns the value of the link register |
bogdanm | 0:9b334a45a8ff | 902 | |
bogdanm | 0:9b334a45a8ff | 903 | \return Value of link register |
bogdanm | 0:9b334a45a8ff | 904 | */ |
bogdanm | 0:9b334a45a8ff | 905 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void) |
bogdanm | 0:9b334a45a8ff | 906 | { |
bogdanm | 0:9b334a45a8ff | 907 | register uint32_t __reglr __ASM("lr"); |
bogdanm | 0:9b334a45a8ff | 908 | return(__reglr); |
bogdanm | 0:9b334a45a8ff | 909 | } |
bogdanm | 0:9b334a45a8ff | 910 | |
bogdanm | 0:9b334a45a8ff | 911 | #if 0 |
bogdanm | 0:9b334a45a8ff | 912 | /** \brief Set link register |
bogdanm | 0:9b334a45a8ff | 913 | |
bogdanm | 0:9b334a45a8ff | 914 | This function sets the value of the link register |
bogdanm | 0:9b334a45a8ff | 915 | |
bogdanm | 0:9b334a45a8ff | 916 | \param [in] lr LR value to set |
bogdanm | 0:9b334a45a8ff | 917 | */ |
bogdanm | 0:9b334a45a8ff | 918 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr) |
bogdanm | 0:9b334a45a8ff | 919 | { |
bogdanm | 0:9b334a45a8ff | 920 | register uint32_t __reglr __ASM("lr"); |
bogdanm | 0:9b334a45a8ff | 921 | __reglr = lr; |
bogdanm | 0:9b334a45a8ff | 922 | } |
bogdanm | 0:9b334a45a8ff | 923 | #endif |
bogdanm | 0:9b334a45a8ff | 924 | |
bogdanm | 0:9b334a45a8ff | 925 | /** \brief Set Process Stack Pointer |
bogdanm | 0:9b334a45a8ff | 926 | |
bogdanm | 0:9b334a45a8ff | 927 | This function assigns the given value to the USR/SYS Stack Pointer (PSP). |
bogdanm | 0:9b334a45a8ff | 928 | |
bogdanm | 0:9b334a45a8ff | 929 | \param [in] topOfProcStack USR/SYS Stack Pointer value to set |
bogdanm | 0:9b334a45a8ff | 930 | */ |
bogdanm | 0:9b334a45a8ff | 931 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
bogdanm | 0:9b334a45a8ff | 932 | { |
bogdanm | 0:9b334a45a8ff | 933 | __asm__ volatile ( |
bogdanm | 0:9b334a45a8ff | 934 | ".ARM;" |
bogdanm | 0:9b334a45a8ff | 935 | ".eabi_attribute Tag_ABI_align8_preserved,1;" |
bogdanm | 0:9b334a45a8ff | 936 | |
bogdanm | 0:9b334a45a8ff | 937 | "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */ |
bogdanm | 0:9b334a45a8ff | 938 | "MRS R1, CPSR;" |
bogdanm | 0:9b334a45a8ff | 939 | "CPS %0;" /* ;no effect in USR mode */ |
bogdanm | 0:9b334a45a8ff | 940 | "MOV SP, R0;" |
bogdanm | 0:9b334a45a8ff | 941 | "MSR CPSR_c, R1;" /* ;no effect in USR mode */ |
bogdanm | 0:9b334a45a8ff | 942 | "ISB;" |
bogdanm | 0:9b334a45a8ff | 943 | //"BX LR;" |
bogdanm | 0:9b334a45a8ff | 944 | : |
bogdanm | 0:9b334a45a8ff | 945 | : "i"(MODE_SYS) |
bogdanm | 0:9b334a45a8ff | 946 | : "r0", "r1"); |
bogdanm | 0:9b334a45a8ff | 947 | return; |
bogdanm | 0:9b334a45a8ff | 948 | } |
bogdanm | 0:9b334a45a8ff | 949 | |
bogdanm | 0:9b334a45a8ff | 950 | /** \brief Set User Mode |
bogdanm | 0:9b334a45a8ff | 951 | |
bogdanm | 0:9b334a45a8ff | 952 | This function changes the processor state to User Mode |
bogdanm | 0:9b334a45a8ff | 953 | */ |
bogdanm | 0:9b334a45a8ff | 954 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void) |
bogdanm | 0:9b334a45a8ff | 955 | { |
bogdanm | 0:9b334a45a8ff | 956 | __asm__ volatile ( |
bogdanm | 0:9b334a45a8ff | 957 | ".ARM;" |
bogdanm | 0:9b334a45a8ff | 958 | |
bogdanm | 0:9b334a45a8ff | 959 | "CPS %0;" |
bogdanm | 0:9b334a45a8ff | 960 | //"BX LR;" |
bogdanm | 0:9b334a45a8ff | 961 | : |
bogdanm | 0:9b334a45a8ff | 962 | : "i"(MODE_USR) |
bogdanm | 0:9b334a45a8ff | 963 | : ); |
bogdanm | 0:9b334a45a8ff | 964 | return; |
bogdanm | 0:9b334a45a8ff | 965 | } |
bogdanm | 0:9b334a45a8ff | 966 | |
bogdanm | 0:9b334a45a8ff | 967 | |
bogdanm | 0:9b334a45a8ff | 968 | /** \brief Enable FIQ |
bogdanm | 0:9b334a45a8ff | 969 | |
bogdanm | 0:9b334a45a8ff | 970 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
bogdanm | 0:9b334a45a8ff | 971 | Can only be executed in Privileged modes. |
bogdanm | 0:9b334a45a8ff | 972 | */ |
bogdanm | 0:9b334a45a8ff | 973 | #define __enable_fault_irq() __asm__ volatile ("cpsie f") |
bogdanm | 0:9b334a45a8ff | 974 | |
bogdanm | 0:9b334a45a8ff | 975 | |
bogdanm | 0:9b334a45a8ff | 976 | /** \brief Disable FIQ |
bogdanm | 0:9b334a45a8ff | 977 | |
bogdanm | 0:9b334a45a8ff | 978 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
bogdanm | 0:9b334a45a8ff | 979 | Can only be executed in Privileged modes. |
bogdanm | 0:9b334a45a8ff | 980 | */ |
bogdanm | 0:9b334a45a8ff | 981 | #define __disable_fault_irq() __asm__ volatile ("cpsid f") |
bogdanm | 0:9b334a45a8ff | 982 | |
bogdanm | 0:9b334a45a8ff | 983 | |
bogdanm | 0:9b334a45a8ff | 984 | /** \brief Get FPSCR |
bogdanm | 0:9b334a45a8ff | 985 | |
bogdanm | 0:9b334a45a8ff | 986 | This function returns the current value of the Floating Point Status/Control register. |
bogdanm | 0:9b334a45a8ff | 987 | |
bogdanm | 0:9b334a45a8ff | 988 | \return Floating Point Status/Control register value |
bogdanm | 0:9b334a45a8ff | 989 | */ |
bogdanm | 0:9b334a45a8ff | 990 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) |
bogdanm | 0:9b334a45a8ff | 991 | { |
bogdanm | 0:9b334a45a8ff | 992 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
bogdanm | 0:9b334a45a8ff | 993 | #if 1 |
bogdanm | 0:9b334a45a8ff | 994 | uint32_t result; |
bogdanm | 0:9b334a45a8ff | 995 | |
bogdanm | 0:9b334a45a8ff | 996 | __ASM volatile ("vmrs %0, fpscr" : "=r" (result) ); |
bogdanm | 0:9b334a45a8ff | 997 | return (result); |
bogdanm | 0:9b334a45a8ff | 998 | #else |
bogdanm | 0:9b334a45a8ff | 999 | register uint32_t __regfpscr __ASM("fpscr"); |
bogdanm | 0:9b334a45a8ff | 1000 | return(__regfpscr); |
bogdanm | 0:9b334a45a8ff | 1001 | #endif |
bogdanm | 0:9b334a45a8ff | 1002 | #else |
bogdanm | 0:9b334a45a8ff | 1003 | return(0); |
bogdanm | 0:9b334a45a8ff | 1004 | #endif |
bogdanm | 0:9b334a45a8ff | 1005 | } |
bogdanm | 0:9b334a45a8ff | 1006 | |
bogdanm | 0:9b334a45a8ff | 1007 | |
bogdanm | 0:9b334a45a8ff | 1008 | /** \brief Set FPSCR |
bogdanm | 0:9b334a45a8ff | 1009 | |
bogdanm | 0:9b334a45a8ff | 1010 | This function assigns the given value to the Floating Point Status/Control register. |
bogdanm | 0:9b334a45a8ff | 1011 | |
bogdanm | 0:9b334a45a8ff | 1012 | \param [in] fpscr Floating Point Status/Control value to set |
bogdanm | 0:9b334a45a8ff | 1013 | */ |
bogdanm | 0:9b334a45a8ff | 1014 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
bogdanm | 0:9b334a45a8ff | 1015 | { |
bogdanm | 0:9b334a45a8ff | 1016 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
bogdanm | 0:9b334a45a8ff | 1017 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1018 | __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) ); |
bogdanm | 0:9b334a45a8ff | 1019 | #else |
bogdanm | 0:9b334a45a8ff | 1020 | register uint32_t __regfpscr __ASM("fpscr"); |
bogdanm | 0:9b334a45a8ff | 1021 | __regfpscr = (fpscr); |
bogdanm | 0:9b334a45a8ff | 1022 | #endif |
bogdanm | 0:9b334a45a8ff | 1023 | #endif |
bogdanm | 0:9b334a45a8ff | 1024 | } |
bogdanm | 0:9b334a45a8ff | 1025 | |
bogdanm | 0:9b334a45a8ff | 1026 | /** \brief Get FPEXC |
bogdanm | 0:9b334a45a8ff | 1027 | |
bogdanm | 0:9b334a45a8ff | 1028 | This function returns the current value of the Floating Point Exception Control register. |
bogdanm | 0:9b334a45a8ff | 1029 | |
bogdanm | 0:9b334a45a8ff | 1030 | \return Floating Point Exception Control register value |
bogdanm | 0:9b334a45a8ff | 1031 | */ |
bogdanm | 0:9b334a45a8ff | 1032 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void) |
bogdanm | 0:9b334a45a8ff | 1033 | { |
bogdanm | 0:9b334a45a8ff | 1034 | #if (__FPU_PRESENT == 1) |
bogdanm | 0:9b334a45a8ff | 1035 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1036 | uint32_t result; |
bogdanm | 0:9b334a45a8ff | 1037 | |
bogdanm | 0:9b334a45a8ff | 1038 | __ASM volatile ("vmrs %0, fpexc" : "=r" (result)); |
bogdanm | 0:9b334a45a8ff | 1039 | return (result); |
bogdanm | 0:9b334a45a8ff | 1040 | #else |
bogdanm | 0:9b334a45a8ff | 1041 | register uint32_t __regfpexc __ASM("fpexc"); |
bogdanm | 0:9b334a45a8ff | 1042 | return(__regfpexc); |
bogdanm | 0:9b334a45a8ff | 1043 | #endif |
bogdanm | 0:9b334a45a8ff | 1044 | #else |
bogdanm | 0:9b334a45a8ff | 1045 | return(0); |
bogdanm | 0:9b334a45a8ff | 1046 | #endif |
bogdanm | 0:9b334a45a8ff | 1047 | } |
bogdanm | 0:9b334a45a8ff | 1048 | |
bogdanm | 0:9b334a45a8ff | 1049 | |
bogdanm | 0:9b334a45a8ff | 1050 | /** \brief Set FPEXC |
bogdanm | 0:9b334a45a8ff | 1051 | |
bogdanm | 0:9b334a45a8ff | 1052 | This function assigns the given value to the Floating Point Exception Control register. |
bogdanm | 0:9b334a45a8ff | 1053 | |
bogdanm | 0:9b334a45a8ff | 1054 | \param [in] fpscr Floating Point Exception Control value to set |
bogdanm | 0:9b334a45a8ff | 1055 | */ |
bogdanm | 0:9b334a45a8ff | 1056 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) |
bogdanm | 0:9b334a45a8ff | 1057 | { |
bogdanm | 0:9b334a45a8ff | 1058 | #if (__FPU_PRESENT == 1) |
bogdanm | 0:9b334a45a8ff | 1059 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1060 | __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc)); |
bogdanm | 0:9b334a45a8ff | 1061 | #else |
bogdanm | 0:9b334a45a8ff | 1062 | register uint32_t __regfpexc __ASM("fpexc"); |
bogdanm | 0:9b334a45a8ff | 1063 | __regfpexc = (fpexc); |
bogdanm | 0:9b334a45a8ff | 1064 | #endif |
bogdanm | 0:9b334a45a8ff | 1065 | #endif |
bogdanm | 0:9b334a45a8ff | 1066 | } |
bogdanm | 0:9b334a45a8ff | 1067 | |
bogdanm | 0:9b334a45a8ff | 1068 | /** \brief Get CPACR |
bogdanm | 0:9b334a45a8ff | 1069 | |
bogdanm | 0:9b334a45a8ff | 1070 | This function returns the current value of the Coprocessor Access Control register. |
bogdanm | 0:9b334a45a8ff | 1071 | |
bogdanm | 0:9b334a45a8ff | 1072 | \return Coprocessor Access Control register value |
bogdanm | 0:9b334a45a8ff | 1073 | */ |
bogdanm | 0:9b334a45a8ff | 1074 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void) |
bogdanm | 0:9b334a45a8ff | 1075 | { |
bogdanm | 0:9b334a45a8ff | 1076 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1077 | register uint32_t __regCPACR; |
bogdanm | 0:9b334a45a8ff | 1078 | __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR)); |
bogdanm | 0:9b334a45a8ff | 1079 | #else |
bogdanm | 0:9b334a45a8ff | 1080 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
bogdanm | 0:9b334a45a8ff | 1081 | #endif |
bogdanm | 0:9b334a45a8ff | 1082 | return __regCPACR; |
bogdanm | 0:9b334a45a8ff | 1083 | } |
bogdanm | 0:9b334a45a8ff | 1084 | |
bogdanm | 0:9b334a45a8ff | 1085 | /** \brief Set CPACR |
bogdanm | 0:9b334a45a8ff | 1086 | |
bogdanm | 0:9b334a45a8ff | 1087 | This function assigns the given value to the Coprocessor Access Control register. |
bogdanm | 0:9b334a45a8ff | 1088 | |
bogdanm | 0:9b334a45a8ff | 1089 | \param [in] cpacr Coprocessor Acccess Control value to set |
bogdanm | 0:9b334a45a8ff | 1090 | */ |
bogdanm | 0:9b334a45a8ff | 1091 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr) |
bogdanm | 0:9b334a45a8ff | 1092 | { |
bogdanm | 0:9b334a45a8ff | 1093 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1094 | __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr)); |
bogdanm | 0:9b334a45a8ff | 1095 | #else |
bogdanm | 0:9b334a45a8ff | 1096 | register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); |
bogdanm | 0:9b334a45a8ff | 1097 | __regCPACR = cpacr; |
bogdanm | 0:9b334a45a8ff | 1098 | #endif |
bogdanm | 0:9b334a45a8ff | 1099 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 1100 | } |
bogdanm | 0:9b334a45a8ff | 1101 | |
bogdanm | 0:9b334a45a8ff | 1102 | /** \brief Get CBAR |
bogdanm | 0:9b334a45a8ff | 1103 | |
bogdanm | 0:9b334a45a8ff | 1104 | This function returns the value of the Configuration Base Address register. |
bogdanm | 0:9b334a45a8ff | 1105 | |
bogdanm | 0:9b334a45a8ff | 1106 | \return Configuration Base Address register value |
bogdanm | 0:9b334a45a8ff | 1107 | */ |
bogdanm | 0:9b334a45a8ff | 1108 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() { |
bogdanm | 0:9b334a45a8ff | 1109 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1110 | register uint32_t __regCBAR; |
bogdanm | 0:9b334a45a8ff | 1111 | __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR)); |
bogdanm | 0:9b334a45a8ff | 1112 | #else |
bogdanm | 0:9b334a45a8ff | 1113 | register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0"); |
bogdanm | 0:9b334a45a8ff | 1114 | #endif |
bogdanm | 0:9b334a45a8ff | 1115 | return(__regCBAR); |
bogdanm | 0:9b334a45a8ff | 1116 | } |
bogdanm | 0:9b334a45a8ff | 1117 | |
bogdanm | 0:9b334a45a8ff | 1118 | /** \brief Get TTBR0 |
bogdanm | 0:9b334a45a8ff | 1119 | |
bogdanm | 0:9b334a45a8ff | 1120 | This function returns the value of the Translation Table Base Register 0. |
bogdanm | 0:9b334a45a8ff | 1121 | |
bogdanm | 0:9b334a45a8ff | 1122 | \return Translation Table Base Register 0 value |
bogdanm | 0:9b334a45a8ff | 1123 | */ |
bogdanm | 0:9b334a45a8ff | 1124 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() { |
bogdanm | 0:9b334a45a8ff | 1125 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1126 | register uint32_t __regTTBR0; |
bogdanm | 0:9b334a45a8ff | 1127 | __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0)); |
bogdanm | 0:9b334a45a8ff | 1128 | #else |
bogdanm | 0:9b334a45a8ff | 1129 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
bogdanm | 0:9b334a45a8ff | 1130 | #endif |
bogdanm | 0:9b334a45a8ff | 1131 | return(__regTTBR0); |
bogdanm | 0:9b334a45a8ff | 1132 | } |
bogdanm | 0:9b334a45a8ff | 1133 | |
bogdanm | 0:9b334a45a8ff | 1134 | /** \brief Set TTBR0 |
bogdanm | 0:9b334a45a8ff | 1135 | |
bogdanm | 0:9b334a45a8ff | 1136 | This function assigns the given value to the Translation Table Base Register 0. |
bogdanm | 0:9b334a45a8ff | 1137 | |
bogdanm | 0:9b334a45a8ff | 1138 | \param [in] ttbr0 Translation Table Base Register 0 value to set |
bogdanm | 0:9b334a45a8ff | 1139 | */ |
bogdanm | 0:9b334a45a8ff | 1140 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { |
bogdanm | 0:9b334a45a8ff | 1141 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1142 | __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0)); |
bogdanm | 0:9b334a45a8ff | 1143 | #else |
bogdanm | 0:9b334a45a8ff | 1144 | register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); |
bogdanm | 0:9b334a45a8ff | 1145 | __regTTBR0 = ttbr0; |
bogdanm | 0:9b334a45a8ff | 1146 | #endif |
bogdanm | 0:9b334a45a8ff | 1147 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 1148 | } |
bogdanm | 0:9b334a45a8ff | 1149 | |
bogdanm | 0:9b334a45a8ff | 1150 | /** \brief Get DACR |
bogdanm | 0:9b334a45a8ff | 1151 | |
bogdanm | 0:9b334a45a8ff | 1152 | This function returns the value of the Domain Access Control Register. |
bogdanm | 0:9b334a45a8ff | 1153 | |
bogdanm | 0:9b334a45a8ff | 1154 | \return Domain Access Control Register value |
bogdanm | 0:9b334a45a8ff | 1155 | */ |
bogdanm | 0:9b334a45a8ff | 1156 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() { |
bogdanm | 0:9b334a45a8ff | 1157 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1158 | register uint32_t __regDACR; |
bogdanm | 0:9b334a45a8ff | 1159 | __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR)); |
bogdanm | 0:9b334a45a8ff | 1160 | #else |
bogdanm | 0:9b334a45a8ff | 1161 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
bogdanm | 0:9b334a45a8ff | 1162 | #endif |
bogdanm | 0:9b334a45a8ff | 1163 | return(__regDACR); |
bogdanm | 0:9b334a45a8ff | 1164 | } |
bogdanm | 0:9b334a45a8ff | 1165 | |
bogdanm | 0:9b334a45a8ff | 1166 | /** \brief Set DACR |
bogdanm | 0:9b334a45a8ff | 1167 | |
bogdanm | 0:9b334a45a8ff | 1168 | This function assigns the given value to the Domain Access Control Register. |
bogdanm | 0:9b334a45a8ff | 1169 | |
bogdanm | 0:9b334a45a8ff | 1170 | \param [in] dacr Domain Access Control Register value to set |
bogdanm | 0:9b334a45a8ff | 1171 | */ |
bogdanm | 0:9b334a45a8ff | 1172 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) { |
bogdanm | 0:9b334a45a8ff | 1173 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1174 | __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr)); |
bogdanm | 0:9b334a45a8ff | 1175 | #else |
bogdanm | 0:9b334a45a8ff | 1176 | register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); |
bogdanm | 0:9b334a45a8ff | 1177 | __regDACR = dacr; |
bogdanm | 0:9b334a45a8ff | 1178 | #endif |
bogdanm | 0:9b334a45a8ff | 1179 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 1180 | } |
bogdanm | 0:9b334a45a8ff | 1181 | |
bogdanm | 0:9b334a45a8ff | 1182 | /******************************** Cache and BTAC enable ****************************************************/ |
bogdanm | 0:9b334a45a8ff | 1183 | |
bogdanm | 0:9b334a45a8ff | 1184 | /** \brief Set SCTLR |
bogdanm | 0:9b334a45a8ff | 1185 | |
bogdanm | 0:9b334a45a8ff | 1186 | This function assigns the given value to the System Control Register. |
bogdanm | 0:9b334a45a8ff | 1187 | |
bogdanm | 0:9b334a45a8ff | 1188 | \param [in] sctlr System Control Register value to set |
bogdanm | 0:9b334a45a8ff | 1189 | */ |
bogdanm | 0:9b334a45a8ff | 1190 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) |
bogdanm | 0:9b334a45a8ff | 1191 | { |
bogdanm | 0:9b334a45a8ff | 1192 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1193 | __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr)); |
bogdanm | 0:9b334a45a8ff | 1194 | #else |
bogdanm | 0:9b334a45a8ff | 1195 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
bogdanm | 0:9b334a45a8ff | 1196 | __regSCTLR = sctlr; |
bogdanm | 0:9b334a45a8ff | 1197 | #endif |
bogdanm | 0:9b334a45a8ff | 1198 | } |
bogdanm | 0:9b334a45a8ff | 1199 | |
bogdanm | 0:9b334a45a8ff | 1200 | /** \brief Get SCTLR |
bogdanm | 0:9b334a45a8ff | 1201 | |
bogdanm | 0:9b334a45a8ff | 1202 | This function returns the value of the System Control Register. |
bogdanm | 0:9b334a45a8ff | 1203 | |
bogdanm | 0:9b334a45a8ff | 1204 | \return System Control Register value |
bogdanm | 0:9b334a45a8ff | 1205 | */ |
bogdanm | 0:9b334a45a8ff | 1206 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() { |
bogdanm | 0:9b334a45a8ff | 1207 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1208 | register uint32_t __regSCTLR; |
bogdanm | 0:9b334a45a8ff | 1209 | __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR)); |
bogdanm | 0:9b334a45a8ff | 1210 | #else |
bogdanm | 0:9b334a45a8ff | 1211 | register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); |
bogdanm | 0:9b334a45a8ff | 1212 | #endif |
bogdanm | 0:9b334a45a8ff | 1213 | return(__regSCTLR); |
bogdanm | 0:9b334a45a8ff | 1214 | } |
bogdanm | 0:9b334a45a8ff | 1215 | |
bogdanm | 0:9b334a45a8ff | 1216 | /** \brief Enable Caches |
bogdanm | 0:9b334a45a8ff | 1217 | |
bogdanm | 0:9b334a45a8ff | 1218 | Enable Caches |
bogdanm | 0:9b334a45a8ff | 1219 | */ |
bogdanm | 0:9b334a45a8ff | 1220 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) { |
bogdanm | 0:9b334a45a8ff | 1221 | // Set I bit 12 to enable I Cache |
bogdanm | 0:9b334a45a8ff | 1222 | // Set C bit 2 to enable D Cache |
bogdanm | 0:9b334a45a8ff | 1223 | __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); |
bogdanm | 0:9b334a45a8ff | 1224 | } |
bogdanm | 0:9b334a45a8ff | 1225 | |
bogdanm | 0:9b334a45a8ff | 1226 | /** \brief Disable Caches |
bogdanm | 0:9b334a45a8ff | 1227 | |
bogdanm | 0:9b334a45a8ff | 1228 | Disable Caches |
bogdanm | 0:9b334a45a8ff | 1229 | */ |
bogdanm | 0:9b334a45a8ff | 1230 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) { |
bogdanm | 0:9b334a45a8ff | 1231 | // Clear I bit 12 to disable I Cache |
bogdanm | 0:9b334a45a8ff | 1232 | // Clear C bit 2 to disable D Cache |
bogdanm | 0:9b334a45a8ff | 1233 | __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2)); |
bogdanm | 0:9b334a45a8ff | 1234 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 1235 | } |
bogdanm | 0:9b334a45a8ff | 1236 | |
bogdanm | 0:9b334a45a8ff | 1237 | /** \brief Enable BTAC |
bogdanm | 0:9b334a45a8ff | 1238 | |
bogdanm | 0:9b334a45a8ff | 1239 | Enable BTAC |
bogdanm | 0:9b334a45a8ff | 1240 | */ |
bogdanm | 0:9b334a45a8ff | 1241 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) { |
bogdanm | 0:9b334a45a8ff | 1242 | // Set Z bit 11 to enable branch prediction |
bogdanm | 0:9b334a45a8ff | 1243 | __set_SCTLR( __get_SCTLR() | (1 << 11)); |
bogdanm | 0:9b334a45a8ff | 1244 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 1245 | } |
bogdanm | 0:9b334a45a8ff | 1246 | |
bogdanm | 0:9b334a45a8ff | 1247 | /** \brief Disable BTAC |
bogdanm | 0:9b334a45a8ff | 1248 | |
bogdanm | 0:9b334a45a8ff | 1249 | Disable BTAC |
bogdanm | 0:9b334a45a8ff | 1250 | */ |
bogdanm | 0:9b334a45a8ff | 1251 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) { |
bogdanm | 0:9b334a45a8ff | 1252 | // Clear Z bit 11 to disable branch prediction |
bogdanm | 0:9b334a45a8ff | 1253 | __set_SCTLR( __get_SCTLR() & ~(1 << 11)); |
bogdanm | 0:9b334a45a8ff | 1254 | } |
bogdanm | 0:9b334a45a8ff | 1255 | |
bogdanm | 0:9b334a45a8ff | 1256 | |
bogdanm | 0:9b334a45a8ff | 1257 | /** \brief Enable MMU |
bogdanm | 0:9b334a45a8ff | 1258 | |
bogdanm | 0:9b334a45a8ff | 1259 | Enable MMU |
bogdanm | 0:9b334a45a8ff | 1260 | */ |
bogdanm | 0:9b334a45a8ff | 1261 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) { |
bogdanm | 0:9b334a45a8ff | 1262 | // Set M bit 0 to enable the MMU |
bogdanm | 0:9b334a45a8ff | 1263 | // Set AFE bit to enable simplified access permissions model |
bogdanm | 0:9b334a45a8ff | 1264 | // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking |
bogdanm | 0:9b334a45a8ff | 1265 | __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); |
bogdanm | 0:9b334a45a8ff | 1266 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 1267 | } |
bogdanm | 0:9b334a45a8ff | 1268 | |
bogdanm | 0:9b334a45a8ff | 1269 | /** \brief Disable MMU |
bogdanm | 0:9b334a45a8ff | 1270 | |
bogdanm | 0:9b334a45a8ff | 1271 | Disable MMU |
bogdanm | 0:9b334a45a8ff | 1272 | */ |
bogdanm | 0:9b334a45a8ff | 1273 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) { |
bogdanm | 0:9b334a45a8ff | 1274 | // Clear M bit 0 to disable the MMU |
bogdanm | 0:9b334a45a8ff | 1275 | __set_SCTLR( __get_SCTLR() & ~1); |
bogdanm | 0:9b334a45a8ff | 1276 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 1277 | } |
bogdanm | 0:9b334a45a8ff | 1278 | |
bogdanm | 0:9b334a45a8ff | 1279 | /******************************** TLB maintenance operations ************************************************/ |
bogdanm | 0:9b334a45a8ff | 1280 | /** \brief Invalidate the whole tlb |
bogdanm | 0:9b334a45a8ff | 1281 | |
bogdanm | 0:9b334a45a8ff | 1282 | TLBIALL. Invalidate the whole tlb |
bogdanm | 0:9b334a45a8ff | 1283 | */ |
bogdanm | 0:9b334a45a8ff | 1284 | |
bogdanm | 0:9b334a45a8ff | 1285 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) { |
bogdanm | 0:9b334a45a8ff | 1286 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1287 | __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); |
bogdanm | 0:9b334a45a8ff | 1288 | #else |
bogdanm | 0:9b334a45a8ff | 1289 | register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0"); |
bogdanm | 0:9b334a45a8ff | 1290 | __TLBIALL = 0; |
bogdanm | 0:9b334a45a8ff | 1291 | #endif |
bogdanm | 0:9b334a45a8ff | 1292 | __DSB(); |
bogdanm | 0:9b334a45a8ff | 1293 | __ISB(); |
bogdanm | 0:9b334a45a8ff | 1294 | } |
bogdanm | 0:9b334a45a8ff | 1295 | |
bogdanm | 0:9b334a45a8ff | 1296 | /******************************** BTB maintenance operations ************************************************/ |
bogdanm | 0:9b334a45a8ff | 1297 | /** \brief Invalidate entire branch predictor array |
bogdanm | 0:9b334a45a8ff | 1298 | |
bogdanm | 0:9b334a45a8ff | 1299 | BPIALL. Branch Predictor Invalidate All. |
bogdanm | 0:9b334a45a8ff | 1300 | */ |
bogdanm | 0:9b334a45a8ff | 1301 | |
bogdanm | 0:9b334a45a8ff | 1302 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) { |
bogdanm | 0:9b334a45a8ff | 1303 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1304 | __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); |
bogdanm | 0:9b334a45a8ff | 1305 | #else |
bogdanm | 0:9b334a45a8ff | 1306 | register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6"); |
bogdanm | 0:9b334a45a8ff | 1307 | __BPIALL = 0; |
bogdanm | 0:9b334a45a8ff | 1308 | #endif |
bogdanm | 0:9b334a45a8ff | 1309 | __DSB(); //ensure completion of the invalidation |
bogdanm | 0:9b334a45a8ff | 1310 | __ISB(); //ensure instruction fetch path sees new state |
bogdanm | 0:9b334a45a8ff | 1311 | } |
bogdanm | 0:9b334a45a8ff | 1312 | |
bogdanm | 0:9b334a45a8ff | 1313 | |
bogdanm | 0:9b334a45a8ff | 1314 | /******************************** L1 cache operations ******************************************************/ |
bogdanm | 0:9b334a45a8ff | 1315 | |
bogdanm | 0:9b334a45a8ff | 1316 | /** \brief Invalidate the whole I$ |
bogdanm | 0:9b334a45a8ff | 1317 | |
bogdanm | 0:9b334a45a8ff | 1318 | ICIALLU. Instruction Cache Invalidate All to PoU |
bogdanm | 0:9b334a45a8ff | 1319 | */ |
bogdanm | 0:9b334a45a8ff | 1320 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) { |
bogdanm | 0:9b334a45a8ff | 1321 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1322 | __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); |
bogdanm | 0:9b334a45a8ff | 1323 | #else |
bogdanm | 0:9b334a45a8ff | 1324 | register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0"); |
bogdanm | 0:9b334a45a8ff | 1325 | __ICIALLU = 0; |
bogdanm | 0:9b334a45a8ff | 1326 | #endif |
bogdanm | 0:9b334a45a8ff | 1327 | __DSB(); //ensure completion of the invalidation |
bogdanm | 0:9b334a45a8ff | 1328 | __ISB(); //ensure instruction fetch path sees new I cache state |
bogdanm | 0:9b334a45a8ff | 1329 | } |
bogdanm | 0:9b334a45a8ff | 1330 | |
bogdanm | 0:9b334a45a8ff | 1331 | /** \brief Clean D$ by MVA |
bogdanm | 0:9b334a45a8ff | 1332 | |
bogdanm | 0:9b334a45a8ff | 1333 | DCCMVAC. Data cache clean by MVA to PoC |
bogdanm | 0:9b334a45a8ff | 1334 | */ |
bogdanm | 0:9b334a45a8ff | 1335 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) { |
bogdanm | 0:9b334a45a8ff | 1336 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1337 | __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va)); |
bogdanm | 0:9b334a45a8ff | 1338 | #else |
bogdanm | 0:9b334a45a8ff | 1339 | register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1"); |
bogdanm | 0:9b334a45a8ff | 1340 | __DCCMVAC = (uint32_t)va; |
bogdanm | 0:9b334a45a8ff | 1341 | #endif |
bogdanm | 0:9b334a45a8ff | 1342 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
bogdanm | 0:9b334a45a8ff | 1343 | } |
bogdanm | 0:9b334a45a8ff | 1344 | |
bogdanm | 0:9b334a45a8ff | 1345 | /** \brief Invalidate D$ by MVA |
bogdanm | 0:9b334a45a8ff | 1346 | |
bogdanm | 0:9b334a45a8ff | 1347 | DCIMVAC. Data cache invalidate by MVA to PoC |
bogdanm | 0:9b334a45a8ff | 1348 | */ |
bogdanm | 0:9b334a45a8ff | 1349 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) { |
bogdanm | 0:9b334a45a8ff | 1350 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1351 | __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va)); |
bogdanm | 0:9b334a45a8ff | 1352 | #else |
bogdanm | 0:9b334a45a8ff | 1353 | register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1"); |
bogdanm | 0:9b334a45a8ff | 1354 | __DCIMVAC = (uint32_t)va; |
bogdanm | 0:9b334a45a8ff | 1355 | #endif |
bogdanm | 0:9b334a45a8ff | 1356 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
bogdanm | 0:9b334a45a8ff | 1357 | } |
bogdanm | 0:9b334a45a8ff | 1358 | |
bogdanm | 0:9b334a45a8ff | 1359 | /** \brief Clean and Invalidate D$ by MVA |
bogdanm | 0:9b334a45a8ff | 1360 | |
bogdanm | 0:9b334a45a8ff | 1361 | DCCIMVAC. Data cache clean and invalidate by MVA to PoC |
bogdanm | 0:9b334a45a8ff | 1362 | */ |
bogdanm | 0:9b334a45a8ff | 1363 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) { |
bogdanm | 0:9b334a45a8ff | 1364 | #if 1 |
bogdanm | 0:9b334a45a8ff | 1365 | __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va)); |
bogdanm | 0:9b334a45a8ff | 1366 | #else |
bogdanm | 0:9b334a45a8ff | 1367 | register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1"); |
bogdanm | 0:9b334a45a8ff | 1368 | __DCCIMVAC = (uint32_t)va; |
bogdanm | 0:9b334a45a8ff | 1369 | #endif |
bogdanm | 0:9b334a45a8ff | 1370 | __DMB(); //ensure the ordering of data cache maintenance operations and their effects |
bogdanm | 0:9b334a45a8ff | 1371 | } |
bogdanm | 0:9b334a45a8ff | 1372 | |
bogdanm | 0:9b334a45a8ff | 1373 | /** \brief Clean and Invalidate the entire data or unified cache |
bogdanm | 0:9b334a45a8ff | 1374 | |
bogdanm | 0:9b334a45a8ff | 1375 | Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. |
bogdanm | 0:9b334a45a8ff | 1376 | */ |
bogdanm | 0:9b334a45a8ff | 1377 | extern void __v7_all_cache(uint32_t op); |
bogdanm | 0:9b334a45a8ff | 1378 | |
bogdanm | 0:9b334a45a8ff | 1379 | |
bogdanm | 0:9b334a45a8ff | 1380 | /** \brief Invalidate the whole D$ |
bogdanm | 0:9b334a45a8ff | 1381 | |
bogdanm | 0:9b334a45a8ff | 1382 | DCISW. Invalidate by Set/Way |
bogdanm | 0:9b334a45a8ff | 1383 | */ |
bogdanm | 0:9b334a45a8ff | 1384 | |
bogdanm | 0:9b334a45a8ff | 1385 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) { |
bogdanm | 0:9b334a45a8ff | 1386 | __v7_all_cache(0); |
bogdanm | 0:9b334a45a8ff | 1387 | } |
bogdanm | 0:9b334a45a8ff | 1388 | |
bogdanm | 0:9b334a45a8ff | 1389 | /** \brief Clean the whole D$ |
bogdanm | 0:9b334a45a8ff | 1390 | |
bogdanm | 0:9b334a45a8ff | 1391 | DCCSW. Clean by Set/Way |
bogdanm | 0:9b334a45a8ff | 1392 | */ |
bogdanm | 0:9b334a45a8ff | 1393 | |
bogdanm | 0:9b334a45a8ff | 1394 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) { |
bogdanm | 0:9b334a45a8ff | 1395 | __v7_all_cache(1); |
bogdanm | 0:9b334a45a8ff | 1396 | } |
bogdanm | 0:9b334a45a8ff | 1397 | |
bogdanm | 0:9b334a45a8ff | 1398 | /** \brief Clean and invalidate the whole D$ |
bogdanm | 0:9b334a45a8ff | 1399 | |
bogdanm | 0:9b334a45a8ff | 1400 | DCCISW. Clean and Invalidate by Set/Way |
bogdanm | 0:9b334a45a8ff | 1401 | */ |
bogdanm | 0:9b334a45a8ff | 1402 | |
bogdanm | 0:9b334a45a8ff | 1403 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) { |
bogdanm | 0:9b334a45a8ff | 1404 | __v7_all_cache(2); |
bogdanm | 0:9b334a45a8ff | 1405 | } |
bogdanm | 0:9b334a45a8ff | 1406 | |
bogdanm | 0:9b334a45a8ff | 1407 | #include "core_ca_mmu.h" |
bogdanm | 0:9b334a45a8ff | 1408 | |
bogdanm | 0:9b334a45a8ff | 1409 | #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ |
bogdanm | 0:9b334a45a8ff | 1410 | |
bogdanm | 0:9b334a45a8ff | 1411 | #error TASKING Compiler support not implemented for Cortex-A |
bogdanm | 0:9b334a45a8ff | 1412 | |
bogdanm | 0:9b334a45a8ff | 1413 | #endif |
bogdanm | 0:9b334a45a8ff | 1414 | |
bogdanm | 0:9b334a45a8ff | 1415 | /*@} end of CMSIS_Core_RegAccFunctions */ |
bogdanm | 0:9b334a45a8ff | 1416 | |
bogdanm | 0:9b334a45a8ff | 1417 | |
bogdanm | 0:9b334a45a8ff | 1418 | #endif /* __CORE_CAFUNC_H__ */ |