mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c@83:a036322b8637, 2016-03-07 (annotated)

Committer:: mbed_official
Date:: Mon Mar 07 10:00:14 2016 +0000
Revision:: 83:a036322b8637
Parent:: 0:9b334a45a8ff

Synchronized with git revision ee20d03969aa5c570152f88e8f3d8a4739eed40b



Full URL: https://github.com/mbedmicro/mbed/commit/ee20d03969aa5c570152f88e8f3d8a4739eed40b/



[STM32F7] Update STM32F7Cube_FW version

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f7xx_hal_spi.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	83:a036322b8637	5	* @version V1.0.4
mbed_official	83:a036322b8637	6	* @date 09-December-2015
bogdanm	0:9b334a45a8ff	7	* @brief SPI HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + IO operation functions
bogdanm	0:9b334a45a8ff	12	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	13	* + Peripheral State functions
bogdanm	0:9b334a45a8ff	14	@verbatim
bogdanm	0:9b334a45a8ff	15	==============================================================================
bogdanm	0:9b334a45a8ff	16	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	17	==============================================================================
bogdanm	0:9b334a45a8ff	18	[..]
bogdanm	0:9b334a45a8ff	19	The SPI HAL driver can be used as follows:
bogdanm	0:9b334a45a8ff	20
bogdanm	0:9b334a45a8ff	21	(#) Declare a SPI_HandleTypeDef handle structure, for example:
bogdanm	0:9b334a45a8ff	22	SPI_HandleTypeDef hspi;
bogdanm	0:9b334a45a8ff	23
bogdanm	0:9b334a45a8ff	24	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
bogdanm	0:9b334a45a8ff	25	(##) Enable the SPIx interface clock
bogdanm	0:9b334a45a8ff	26	(##) SPI pins configuration
bogdanm	0:9b334a45a8ff	27	(+++) Enable the clock for the SPI GPIOs
bogdanm	0:9b334a45a8ff	28	(+++) Configure these SPI pins as alternate function push-pull
bogdanm	0:9b334a45a8ff	29	(##) NVIC configuration if you need to use interrupt process
bogdanm	0:9b334a45a8ff	30	(+++) Configure the SPIx interrupt priority
bogdanm	0:9b334a45a8ff	31	(+++) Enable the NVIC SPI IRQ handle
bogdanm	0:9b334a45a8ff	32	(##) DMA Configuration if you need to use DMA process
bogdanm	0:9b334a45a8ff	33	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
bogdanm	0:9b334a45a8ff	34	(+++) Enable the DMAx clock
bogdanm	0:9b334a45a8ff	35	(+++) Configure the DMA handle parameters
bogdanm	0:9b334a45a8ff	36	(+++) Configure the DMA Tx or Rx channel
bogdanm	0:9b334a45a8ff	37	(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
bogdanm	0:9b334a45a8ff	38	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
bogdanm	0:9b334a45a8ff	39
bogdanm	0:9b334a45a8ff	40	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
bogdanm	0:9b334a45a8ff	41	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
bogdanm	0:9b334a45a8ff	44	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
bogdanm	0:9b334a45a8ff	45	by calling the customised HAL_SPI_MspInit() API.
bogdanm	0:9b334a45a8ff	46	[..]
bogdanm	0:9b334a45a8ff	47	Circular mode restriction:
bogdanm	0:9b334a45a8ff	48	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
bogdanm	0:9b334a45a8ff	49	(##) Master 2Lines RxOnly
bogdanm	0:9b334a45a8ff	50	(##) Master 1Line Rx
bogdanm	0:9b334a45a8ff	51	(#) The CRC feature is not managed when the DMA circular mode is enabled
bogdanm	0:9b334a45a8ff	52	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
bogdanm	0:9b334a45a8ff	53	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
bogdanm	0:9b334a45a8ff	54
bogdanm	0:9b334a45a8ff	55	@endverbatim
bogdanm	0:9b334a45a8ff	56	******************************************************************************
bogdanm	0:9b334a45a8ff	57	* @attention
bogdanm	0:9b334a45a8ff	58	*
bogdanm	0:9b334a45a8ff	59	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	60	*
bogdanm	0:9b334a45a8ff	61	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	62	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	63	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	64	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	65	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	66	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	67	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	68	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	69	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	70	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	71	*
bogdanm	0:9b334a45a8ff	72	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	73	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	74	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	75	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	76	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	77	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	78	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	79	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	80	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	81	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	82	*
bogdanm	0:9b334a45a8ff	83	******************************************************************************
bogdanm	0:9b334a45a8ff	84	*/
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	87	#include "stm32f7xx_hal.h"
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	/** @addtogroup STM32F7xx_HAL_Driver
bogdanm	0:9b334a45a8ff	90	* @{
bogdanm	0:9b334a45a8ff	91	*/
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	/** @defgroup SPI SPI
bogdanm	0:9b334a45a8ff	94	* @brief SPI HAL module driver
bogdanm	0:9b334a45a8ff	95	* @{
bogdanm	0:9b334a45a8ff	96	*/
bogdanm	0:9b334a45a8ff	97	#ifdef HAL_SPI_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	100	/* Private defines -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	101	/** @defgroup SPI_Private_Constants SPI Private Constants
bogdanm	0:9b334a45a8ff	102	* @{
bogdanm	0:9b334a45a8ff	103	*/
bogdanm	0:9b334a45a8ff	104	#define SPI_DEFAULT_TIMEOUT 50
bogdanm	0:9b334a45a8ff	105	/**
bogdanm	0:9b334a45a8ff	106	* @}
bogdanm	0:9b334a45a8ff	107	*/
bogdanm	0:9b334a45a8ff	108
bogdanm	0:9b334a45a8ff	109	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	110	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	111	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	112	/** @addtogroup SPI_Private_Functions
bogdanm	0:9b334a45a8ff	113	* @{
bogdanm	0:9b334a45a8ff	114	*/
bogdanm	0:9b334a45a8ff	115	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	116	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	117	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	118	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	119	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	120	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	121	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	122	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	123	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	124	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	125	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	126	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	127	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	128	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	129	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	130	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	131	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	132	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	133	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	134	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	135	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	136	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	137	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	138	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	139	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	140	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	141	/**
bogdanm	0:9b334a45a8ff	142	* @}
bogdanm	0:9b334a45a8ff	143	*/
bogdanm	0:9b334a45a8ff	144
bogdanm	0:9b334a45a8ff	145	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	/** @defgroup SPI_Exported_Functions SPI Exported Functions
bogdanm	0:9b334a45a8ff	148	* @{
bogdanm	0:9b334a45a8ff	149	*/
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	152	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	153	*
bogdanm	0:9b334a45a8ff	154	@verbatim
bogdanm	0:9b334a45a8ff	155	===============================================================================
bogdanm	0:9b334a45a8ff	156	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	157	===============================================================================
bogdanm	0:9b334a45a8ff	158	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	159	de-initialize the SPIx peripheral:
bogdanm	0:9b334a45a8ff	160
bogdanm	0:9b334a45a8ff	161	(+) User must implement HAL_SPI_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	162	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	163
bogdanm	0:9b334a45a8ff	164	(+) Call the function HAL_SPI_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	165	the selected configuration:
bogdanm	0:9b334a45a8ff	166	(++) Mode
bogdanm	0:9b334a45a8ff	167	(++) Direction
bogdanm	0:9b334a45a8ff	168	(++) Data Size
bogdanm	0:9b334a45a8ff	169	(++) Clock Polarity and Phase
bogdanm	0:9b334a45a8ff	170	(++) NSS Management
bogdanm	0:9b334a45a8ff	171	(++) BaudRate Prescaler
bogdanm	0:9b334a45a8ff	172	(++) FirstBit
bogdanm	0:9b334a45a8ff	173	(++) TIMode
bogdanm	0:9b334a45a8ff	174	(++) CRC Calculation
bogdanm	0:9b334a45a8ff	175	(++) CRC Polynomial if CRC enabled
bogdanm	0:9b334a45a8ff	176	(++) CRC Length, used only with Data8 and Data16
bogdanm	0:9b334a45a8ff	177	(++) FIFO reception threshold
bogdanm	0:9b334a45a8ff	178
bogdanm	0:9b334a45a8ff	179	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	180	of the selected SPIx peripheral.
bogdanm	0:9b334a45a8ff	181
bogdanm	0:9b334a45a8ff	182	@endverbatim
bogdanm	0:9b334a45a8ff	183	* @{
bogdanm	0:9b334a45a8ff	184	*/
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	/**
bogdanm	0:9b334a45a8ff	187	* @brief Initializes the SPI according to the specified parameters
bogdanm	0:9b334a45a8ff	188	* in the SPI_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	189	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	190	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	191	* @retval HAL status
bogdanm	0:9b334a45a8ff	192	*/
bogdanm	0:9b334a45a8ff	193	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	194	{
bogdanm	0:9b334a45a8ff	195	uint32_t frxth;
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	198	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	199	{
bogdanm	0:9b334a45a8ff	200	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	201	}
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	/* Check the parameters */
bogdanm	0:9b334a45a8ff	204	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
bogdanm	0:9b334a45a8ff	205	assert_param(IS_SPI_MODE(hspi->Init.Mode));
bogdanm	0:9b334a45a8ff	206	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	207	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
bogdanm	0:9b334a45a8ff	208	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
bogdanm	0:9b334a45a8ff	209	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
bogdanm	0:9b334a45a8ff	210	assert_param(IS_SPI_NSS(hspi->Init.NSS));
bogdanm	0:9b334a45a8ff	211	assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
bogdanm	0:9b334a45a8ff	212	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
bogdanm	0:9b334a45a8ff	213	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
bogdanm	0:9b334a45a8ff	214	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
bogdanm	0:9b334a45a8ff	215	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
bogdanm	0:9b334a45a8ff	216	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
bogdanm	0:9b334a45a8ff	217	assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	if(hspi->State == HAL_SPI_STATE_RESET)
bogdanm	0:9b334a45a8ff	220	{
bogdanm	0:9b334a45a8ff	221	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	222	hspi->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	223
bogdanm	0:9b334a45a8ff	224	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	225	HAL_SPI_MspInit(hspi);
bogdanm	0:9b334a45a8ff	226	}
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	229
bogdanm	0:9b334a45a8ff	230	/* Disable the selected SPI peripheral */
bogdanm	0:9b334a45a8ff	231	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	232
bogdanm	0:9b334a45a8ff	233	/* Align by default the rs fifo threshold on the data size */
bogdanm	0:9b334a45a8ff	234	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	235	{
bogdanm	0:9b334a45a8ff	236	frxth = SPI_RXFIFO_THRESHOLD_HF;
bogdanm	0:9b334a45a8ff	237	}
bogdanm	0:9b334a45a8ff	238	else
bogdanm	0:9b334a45a8ff	239	{
bogdanm	0:9b334a45a8ff	240	frxth = SPI_RXFIFO_THRESHOLD_QF;
bogdanm	0:9b334a45a8ff	241	}
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	/* CRC calculation is valid only for 16Bit and 8 Bit */
bogdanm	0:9b334a45a8ff	244	if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
bogdanm	0:9b334a45a8ff	245	{
bogdanm	0:9b334a45a8ff	246	/* CRC must be disabled */
bogdanm	0:9b334a45a8ff	247	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
bogdanm	0:9b334a45a8ff	248	}
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	/* Align the CRC Length on the data size */
bogdanm	0:9b334a45a8ff	251	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
bogdanm	0:9b334a45a8ff	252	{
bogdanm	0:9b334a45a8ff	253	/* CRC Length aligned on the data size : value set by default */
bogdanm	0:9b334a45a8ff	254	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	255	{
bogdanm	0:9b334a45a8ff	256	hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
bogdanm	0:9b334a45a8ff	257	}
bogdanm	0:9b334a45a8ff	258	else
bogdanm	0:9b334a45a8ff	259	{
bogdanm	0:9b334a45a8ff	260	hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
bogdanm	0:9b334a45a8ff	261	}
bogdanm	0:9b334a45a8ff	262	}
bogdanm	0:9b334a45a8ff	263
bogdanm	0:9b334a45a8ff	264	/---------------------------- SPIx CR1 & CR2 Configuration ------------------------/
bogdanm	0:9b334a45a8ff	265	/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
bogdanm	0:9b334a45a8ff	266	Communication speed, First bit, CRC calculation state, CRC Length */
bogdanm	0:9b334a45a8ff	267	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \|
bogdanm	0:9b334a45a8ff	268	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
bogdanm	0:9b334a45a8ff	269	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
bogdanm	0:9b334a45a8ff	270
bogdanm	0:9b334a45a8ff	271	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
bogdanm	0:9b334a45a8ff	272	{
bogdanm	0:9b334a45a8ff	273	hspi->Instance->CR1\|= SPI_CR1_CRCL;
bogdanm	0:9b334a45a8ff	274	}
bogdanm	0:9b334a45a8ff	275
bogdanm	0:9b334a45a8ff	276	/* Configure : NSS management */
bogdanm	0:9b334a45a8ff	277	/* Configure : Rx Fifo Threshold */
bogdanm	0:9b334a45a8ff	278	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode \| hspi->Init.NSSPMode \|
bogdanm	0:9b334a45a8ff	279	hspi->Init.DataSize ) \| frxth;
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	/---------------------------- SPIx CRCPOLY Configuration --------------------/
bogdanm	0:9b334a45a8ff	282	/* Configure : CRC Polynomial */
bogdanm	0:9b334a45a8ff	283	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	286	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	return HAL_OK;
bogdanm	0:9b334a45a8ff	289	}
bogdanm	0:9b334a45a8ff	290
bogdanm	0:9b334a45a8ff	291	/**
bogdanm	0:9b334a45a8ff	292	* @brief DeInitializes the SPI peripheral
bogdanm	0:9b334a45a8ff	293	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	294	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	295	* @retval HAL status
bogdanm	0:9b334a45a8ff	296	*/
bogdanm	0:9b334a45a8ff	297	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	298	{
bogdanm	0:9b334a45a8ff	299	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	300	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	301	{
bogdanm	0:9b334a45a8ff	302	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	303	}
bogdanm	0:9b334a45a8ff	304
bogdanm	0:9b334a45a8ff	305	/* Check the parameters */
bogdanm	0:9b334a45a8ff	306	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
bogdanm	0:9b334a45a8ff	307
bogdanm	0:9b334a45a8ff	308	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	309
bogdanm	0:9b334a45a8ff	310	/* check flag before the SPI disable */
bogdanm	0:9b334a45a8ff	311	SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
bogdanm	0:9b334a45a8ff	312	SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);
bogdanm	0:9b334a45a8ff	313	SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	/* Disable the SPI Peripheral Clock */
bogdanm	0:9b334a45a8ff	316	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	319	HAL_SPI_MspDeInit(hspi);
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	322	hspi->State = HAL_SPI_STATE_RESET;
bogdanm	0:9b334a45a8ff	323
bogdanm	0:9b334a45a8ff	324	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	325
bogdanm	0:9b334a45a8ff	326	return HAL_OK;
bogdanm	0:9b334a45a8ff	327	}
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	/**
bogdanm	0:9b334a45a8ff	330	* @brief SPI MSP Init
bogdanm	0:9b334a45a8ff	331	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	332	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	333	* @retval None
bogdanm	0:9b334a45a8ff	334	*/
bogdanm	0:9b334a45a8ff	335	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	336	{
mbed_official	83:a036322b8637	337	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	338	UNUSED(hspi);
mbed_official	83:a036322b8637	339
bogdanm	0:9b334a45a8ff	340	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	341	the HAL_SPI_MspInit should be implemented in the user file
bogdanm	0:9b334a45a8ff	342	*/
bogdanm	0:9b334a45a8ff	343	}
bogdanm	0:9b334a45a8ff	344
bogdanm	0:9b334a45a8ff	345	/**
bogdanm	0:9b334a45a8ff	346	* @brief SPI MSP DeInit
bogdanm	0:9b334a45a8ff	347	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	348	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	349	* @retval None
bogdanm	0:9b334a45a8ff	350	*/
bogdanm	0:9b334a45a8ff	351	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	352	{
mbed_official	83:a036322b8637	353	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	354	UNUSED(hspi);
mbed_official	83:a036322b8637	355
bogdanm	0:9b334a45a8ff	356	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	357	the HAL_SPI_MspDeInit should be implemented in the user file
bogdanm	0:9b334a45a8ff	358	*/
bogdanm	0:9b334a45a8ff	359	}
bogdanm	0:9b334a45a8ff	360
bogdanm	0:9b334a45a8ff	361	/**
bogdanm	0:9b334a45a8ff	362	* @}
bogdanm	0:9b334a45a8ff	363	*/
bogdanm	0:9b334a45a8ff	364
bogdanm	0:9b334a45a8ff	365	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	366	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	367	*
bogdanm	0:9b334a45a8ff	368	@verbatim
bogdanm	0:9b334a45a8ff	369	==============================================================================
bogdanm	0:9b334a45a8ff	370	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	371	===============================================================================
bogdanm	0:9b334a45a8ff	372	This subsection provides a set of functions allowing to manage the SPI
bogdanm	0:9b334a45a8ff	373	data transfers.
bogdanm	0:9b334a45a8ff	374
bogdanm	0:9b334a45a8ff	375	[..] The SPI supports master and slave mode :
bogdanm	0:9b334a45a8ff	376
bogdanm	0:9b334a45a8ff	377	(#) There are two modes of transfer:
bogdanm	0:9b334a45a8ff	378	(++) Blocking mode: The communication is performed in polling mode.
bogdanm	0:9b334a45a8ff	379	The HAL status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	380	after finishing transfer.
bogdanm	0:9b334a45a8ff	381	(++) No-Blocking mode: The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	382	or DMA, These APIs return the HAL status.
bogdanm	0:9b334a45a8ff	383	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	384	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	385	using DMA mode.
bogdanm	0:9b334a45a8ff	386	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
bogdanm	0:9b334a45a8ff	387	will be executed respectively at the end of the transmit or Receive process
bogdanm	0:9b334a45a8ff	388	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
bogdanm	0:9b334a45a8ff	389
bogdanm	0:9b334a45a8ff	390	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
bogdanm	0:9b334a45a8ff	391	exist for 1Line (simplex) and 2Lines (full duplex) modes.
bogdanm	0:9b334a45a8ff	392
bogdanm	0:9b334a45a8ff	393	@endverbatim
bogdanm	0:9b334a45a8ff	394	* @{
bogdanm	0:9b334a45a8ff	395	*/
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397	/**
bogdanm	0:9b334a45a8ff	398	* @brief Transmit an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	399	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	400	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	401	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	402	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	403	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	404	* @retval HAL status
bogdanm	0:9b334a45a8ff	405	*/
bogdanm	0:9b334a45a8ff	406	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	407	{
bogdanm	0:9b334a45a8ff	408	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410	/* Process Locked */
bogdanm	0:9b334a45a8ff	411	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	412
bogdanm	0:9b334a45a8ff	413	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	414	{
bogdanm	0:9b334a45a8ff	415	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	416	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	417	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	418	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	419	}
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	422	{
bogdanm	0:9b334a45a8ff	423	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	424	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	425	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	426	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	427	}
bogdanm	0:9b334a45a8ff	428
bogdanm	0:9b334a45a8ff	429	/* Set the transaction information */
bogdanm	0:9b334a45a8ff	430	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	431	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	432	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	433	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	434	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	435	hspi->pRxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	436	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	437	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	440	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	441	{
bogdanm	0:9b334a45a8ff	442	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	443	}
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	446	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	447	{
bogdanm	0:9b334a45a8ff	448	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	449	}
bogdanm	0:9b334a45a8ff	450
bogdanm	0:9b334a45a8ff	451	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	452	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	453	{
bogdanm	0:9b334a45a8ff	454	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	455	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	456	}
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	459	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	460	{
bogdanm	0:9b334a45a8ff	461	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	462	while (hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	463	{
bogdanm	0:9b334a45a8ff	464	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	465	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	466	{
bogdanm	0:9b334a45a8ff	467	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	468	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	469	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	470	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	471	}
bogdanm	0:9b334a45a8ff	472	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	473	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	474	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	475	}
bogdanm	0:9b334a45a8ff	476	}
bogdanm	0:9b334a45a8ff	477	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	478	else
bogdanm	0:9b334a45a8ff	479	{
bogdanm	0:9b334a45a8ff	480	while (hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	481	{
bogdanm	0:9b334a45a8ff	482	if(hspi->TxXferCount != 0x1)
bogdanm	0:9b334a45a8ff	483	{
bogdanm	0:9b334a45a8ff	484	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	485	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	486	{
bogdanm	0:9b334a45a8ff	487	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	488	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	489	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	490	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	491	}
bogdanm	0:9b334a45a8ff	492	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	493	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	494	hspi->TxXferCount -= 2;
bogdanm	0:9b334a45a8ff	495	}
bogdanm	0:9b334a45a8ff	496	else
bogdanm	0:9b334a45a8ff	497	{
bogdanm	0:9b334a45a8ff	498	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	499	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	500	{
bogdanm	0:9b334a45a8ff	501	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	502	}
bogdanm	0:9b334a45a8ff	503	((__IO uint8_t)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	504	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	505	}
bogdanm	0:9b334a45a8ff	506	}
bogdanm	0:9b334a45a8ff	507	}
bogdanm	0:9b334a45a8ff	508
bogdanm	0:9b334a45a8ff	509	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	510	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	511	{
bogdanm	0:9b334a45a8ff	512	hspi->Instance->CR1\|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	513	}
bogdanm	0:9b334a45a8ff	514
bogdanm	0:9b334a45a8ff	515	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	516	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	517	{
bogdanm	0:9b334a45a8ff	518	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	519	}
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	522	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	523	{
bogdanm	0:9b334a45a8ff	524	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	525	}
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	530	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	533	{
bogdanm	0:9b334a45a8ff	534	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	535	}
bogdanm	0:9b334a45a8ff	536	else
bogdanm	0:9b334a45a8ff	537	{
bogdanm	0:9b334a45a8ff	538	return HAL_OK;
bogdanm	0:9b334a45a8ff	539	}
bogdanm	0:9b334a45a8ff	540	}
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	/**
bogdanm	0:9b334a45a8ff	543	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	544	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	545	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	546	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	547	* @param Size: amount of data to be received
bogdanm	0:9b334a45a8ff	548	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	549	* @retval HAL status
bogdanm	0:9b334a45a8ff	550	*/
bogdanm	0:9b334a45a8ff	551	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	552	{
bogdanm	0:9b334a45a8ff	553	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	554
bogdanm	0:9b334a45a8ff	555	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	556	{
bogdanm	0:9b334a45a8ff	557	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	558	}
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	561	{
bogdanm	0:9b334a45a8ff	562	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	563	}
bogdanm	0:9b334a45a8ff	564
bogdanm	0:9b334a45a8ff	565	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	566	{
bogdanm	0:9b334a45a8ff	567	/* the receive process is not supported in 2Lines direction master mode */
bogdanm	0:9b334a45a8ff	568	/* in this case we call the transmitReceive process */
bogdanm	0:9b334a45a8ff	569	return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
bogdanm	0:9b334a45a8ff	570	}
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	/* Process Locked */
bogdanm	0:9b334a45a8ff	573	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	576	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	577	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	578	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	579	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	580	hspi->pTxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	581	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	582	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	583
bogdanm	0:9b334a45a8ff	584	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	585	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	586	{
bogdanm	0:9b334a45a8ff	587	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	588	/* this is done to handle the CRCNEXT before the latest data */
bogdanm	0:9b334a45a8ff	589	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	590	}
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	/* Set the Rx Fido threshold */
bogdanm	0:9b334a45a8ff	593	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	594	{
bogdanm	0:9b334a45a8ff	595	/* set fiforxthreshold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	596	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	597	}
bogdanm	0:9b334a45a8ff	598	else
bogdanm	0:9b334a45a8ff	599	{
bogdanm	0:9b334a45a8ff	600	/* set fiforxthreshold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	601	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	602	}
bogdanm	0:9b334a45a8ff	603
bogdanm	0:9b334a45a8ff	604	/* Configure communication direction 1Line and enabled SPI if needed */
bogdanm	0:9b334a45a8ff	605	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	606	{
bogdanm	0:9b334a45a8ff	607	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	608	}
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	611	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	612	{
bogdanm	0:9b334a45a8ff	613	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	614	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	615	}
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	618	if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	619	{
bogdanm	0:9b334a45a8ff	620	while(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	621	{
bogdanm	0:9b334a45a8ff	622	/* Wait until the RXNE flag */
bogdanm	0:9b334a45a8ff	623	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	624	{
bogdanm	0:9b334a45a8ff	625	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	626	}
bogdanm	0:9b334a45a8ff	627	(hspi->pRxBuffPtr++)= (__IO uint8_t *)&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	628	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	629	}
bogdanm	0:9b334a45a8ff	630	}
bogdanm	0:9b334a45a8ff	631	else /* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	632	{
bogdanm	0:9b334a45a8ff	633	while(hspi->RxXferCount > 1 )
bogdanm	0:9b334a45a8ff	634	{
bogdanm	0:9b334a45a8ff	635	/* Wait until RXNE flag is reset to read data */
bogdanm	0:9b334a45a8ff	636	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	637	{
bogdanm	0:9b334a45a8ff	638	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	639	}
bogdanm	0:9b334a45a8ff	640	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	641	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	642	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	643	}
bogdanm	0:9b334a45a8ff	644	}
bogdanm	0:9b334a45a8ff	645
bogdanm	0:9b334a45a8ff	646	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	647	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	648	{
bogdanm	0:9b334a45a8ff	649	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	650	}
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	653	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	654	{
bogdanm	0:9b334a45a8ff	655	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	656	}
bogdanm	0:9b334a45a8ff	657
bogdanm	0:9b334a45a8ff	658	/* Receive last data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	659	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	660	{
bogdanm	0:9b334a45a8ff	661	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	662	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	663	}
bogdanm	0:9b334a45a8ff	664	/* Receive last data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	665	else
bogdanm	0:9b334a45a8ff	666	{
bogdanm	0:9b334a45a8ff	667	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	668	}
bogdanm	0:9b334a45a8ff	669	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	/* Read CRC from DR to close CRC calculation process */
bogdanm	0:9b334a45a8ff	672	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	673	{
bogdanm	0:9b334a45a8ff	674	/* Wait until TXE flag */
bogdanm	0:9b334a45a8ff	675	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	676	{
bogdanm	0:9b334a45a8ff	677	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	678	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	679	}
bogdanm	0:9b334a45a8ff	680	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	681	{
bogdanm	0:9b334a45a8ff	682	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	683	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	684	}
bogdanm	0:9b334a45a8ff	685	else
bogdanm	0:9b334a45a8ff	686	{
bogdanm	0:9b334a45a8ff	687	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	688	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
bogdanm	0:9b334a45a8ff	691	{
bogdanm	0:9b334a45a8ff	692	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	693	{
bogdanm	0:9b334a45a8ff	694	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	695	hspi->ErrorCode\|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	696	}
bogdanm	0:9b334a45a8ff	697	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	698	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	699	}
bogdanm	0:9b334a45a8ff	700	}
bogdanm	0:9b334a45a8ff	701	}
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	704	if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	705	{
bogdanm	0:9b334a45a8ff	706	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	707	}
bogdanm	0:9b334a45a8ff	708
bogdanm	0:9b334a45a8ff	709	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	710
bogdanm	0:9b334a45a8ff	711	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	712	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	713	{
bogdanm	0:9b334a45a8ff	714	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	715	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	716
bogdanm	0:9b334a45a8ff	717	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	718	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	719	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	720	}
bogdanm	0:9b334a45a8ff	721
bogdanm	0:9b334a45a8ff	722	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	723	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	724
bogdanm	0:9b334a45a8ff	725	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	726	{
bogdanm	0:9b334a45a8ff	727	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	728	}
bogdanm	0:9b334a45a8ff	729	else
bogdanm	0:9b334a45a8ff	730	{
bogdanm	0:9b334a45a8ff	731	return HAL_OK;
bogdanm	0:9b334a45a8ff	732	}
bogdanm	0:9b334a45a8ff	733	}
bogdanm	0:9b334a45a8ff	734
bogdanm	0:9b334a45a8ff	735	/**
bogdanm	0:9b334a45a8ff	736	* @brief Transmit and Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	737	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	738	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	739	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	740	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	741	* @param Size: amount of data to be sent and received
bogdanm	0:9b334a45a8ff	742	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	743	* @retval HAL status
bogdanm	0:9b334a45a8ff	744	*/
bogdanm	0:9b334a45a8ff	745	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	746	{
bogdanm	0:9b334a45a8ff	747	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	748	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	749
bogdanm	0:9b334a45a8ff	750	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	751
bogdanm	0:9b334a45a8ff	752	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	753	{
bogdanm	0:9b334a45a8ff	754	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	755	}
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	758	{
bogdanm	0:9b334a45a8ff	759	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	760	}
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762
bogdanm	0:9b334a45a8ff	763	/* Process Locked */
bogdanm	0:9b334a45a8ff	764	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	765
bogdanm	0:9b334a45a8ff	766	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	767	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	768	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	769	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	770	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	771	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	772	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	773	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	774
bogdanm	0:9b334a45a8ff	775	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	776	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	777	{
bogdanm	0:9b334a45a8ff	778	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	779	}
bogdanm	0:9b334a45a8ff	780
bogdanm	0:9b334a45a8ff	781	/* Set the Rx Fido threshold */
bogdanm	0:9b334a45a8ff	782	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount > 1))
bogdanm	0:9b334a45a8ff	783	{
bogdanm	0:9b334a45a8ff	784	/* set fiforxthreshold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	785	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	786	}
bogdanm	0:9b334a45a8ff	787	else
bogdanm	0:9b334a45a8ff	788	{
bogdanm	0:9b334a45a8ff	789	/* set fiforxthreshold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	790	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	791	}
bogdanm	0:9b334a45a8ff	792
bogdanm	0:9b334a45a8ff	793	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	794	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	795	{
bogdanm	0:9b334a45a8ff	796	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	797	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	798	}
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	/* Transmit and Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	801	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	802	{
bogdanm	0:9b334a45a8ff	803	while ((hspi->TxXferCount > 0 ) \|\| (hspi->RxXferCount > 0))
bogdanm	0:9b334a45a8ff	804	{
bogdanm	0:9b334a45a8ff	805	/* Check TXE flag */
bogdanm	0:9b334a45a8ff	806	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
bogdanm	0:9b334a45a8ff	807	{
bogdanm	0:9b334a45a8ff	808	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	809	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	810	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	811
bogdanm	0:9b334a45a8ff	812	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	813	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	814	{
bogdanm	0:9b334a45a8ff	815	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	816	}
bogdanm	0:9b334a45a8ff	817	}
bogdanm	0:9b334a45a8ff	818
bogdanm	0:9b334a45a8ff	819	/* Check RXNE flag */
bogdanm	0:9b334a45a8ff	820	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
bogdanm	0:9b334a45a8ff	821	{
bogdanm	0:9b334a45a8ff	822	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	823	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	824	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	825	}
bogdanm	0:9b334a45a8ff	826	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	827	{
bogdanm	0:9b334a45a8ff	828	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	829	{
bogdanm	0:9b334a45a8ff	830	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	831	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	832	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	833	}
bogdanm	0:9b334a45a8ff	834	}
bogdanm	0:9b334a45a8ff	835	}
bogdanm	0:9b334a45a8ff	836	}
bogdanm	0:9b334a45a8ff	837	/* Transmit and Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	838	else
bogdanm	0:9b334a45a8ff	839	{
bogdanm	0:9b334a45a8ff	840	while((hspi->TxXferCount > 0) \|\| (hspi->RxXferCount > 0))
bogdanm	0:9b334a45a8ff	841	{
bogdanm	0:9b334a45a8ff	842	/* check TXE flag */
bogdanm	0:9b334a45a8ff	843	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
bogdanm	0:9b334a45a8ff	844	{
bogdanm	0:9b334a45a8ff	845	if(hspi->TxXferCount > 1)
bogdanm	0:9b334a45a8ff	846	{
bogdanm	0:9b334a45a8ff	847	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	848	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	849	hspi->TxXferCount -= 2;
bogdanm	0:9b334a45a8ff	850	}
bogdanm	0:9b334a45a8ff	851	else
bogdanm	0:9b334a45a8ff	852	{
bogdanm	0:9b334a45a8ff	853	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	854	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	855	}
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	858	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	859	{
bogdanm	0:9b334a45a8ff	860	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	861	}
bogdanm	0:9b334a45a8ff	862	}
bogdanm	0:9b334a45a8ff	863
bogdanm	0:9b334a45a8ff	864	/* Wait until RXNE flag is reset */
bogdanm	0:9b334a45a8ff	865	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
bogdanm	0:9b334a45a8ff	866	{
bogdanm	0:9b334a45a8ff	867	if(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	868	{
bogdanm	0:9b334a45a8ff	869	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	870	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	871	hspi->RxXferCount -= 2;
bogdanm	0:9b334a45a8ff	872	if(hspi->RxXferCount <= 1)
bogdanm	0:9b334a45a8ff	873	{
bogdanm	0:9b334a45a8ff	874	/* set fiforxthreshold before to switch on 8 bit data size */
bogdanm	0:9b334a45a8ff	875	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	876	}
bogdanm	0:9b334a45a8ff	877	}
bogdanm	0:9b334a45a8ff	878	else
bogdanm	0:9b334a45a8ff	879	{
bogdanm	0:9b334a45a8ff	880	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	881	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	882	}
bogdanm	0:9b334a45a8ff	883	}
bogdanm	0:9b334a45a8ff	884	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	885	{
bogdanm	0:9b334a45a8ff	886	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	887	{
bogdanm	0:9b334a45a8ff	888	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	889	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	890	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	891	}
bogdanm	0:9b334a45a8ff	892	}
bogdanm	0:9b334a45a8ff	893	}
bogdanm	0:9b334a45a8ff	894	}
bogdanm	0:9b334a45a8ff	895
bogdanm	0:9b334a45a8ff	896	/* Read CRC from DR to close CRC calculation process */
bogdanm	0:9b334a45a8ff	897	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	898	{
bogdanm	0:9b334a45a8ff	899	/* Wait until TXE flag */
bogdanm	0:9b334a45a8ff	900	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	901	{
bogdanm	0:9b334a45a8ff	902	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	903	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	904	}
bogdanm	0:9b334a45a8ff	905
bogdanm	0:9b334a45a8ff	906	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
bogdanm	0:9b334a45a8ff	907	{
bogdanm	0:9b334a45a8ff	908	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	909	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	910	}
bogdanm	0:9b334a45a8ff	911	else
bogdanm	0:9b334a45a8ff	912	{
bogdanm	0:9b334a45a8ff	913	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	914	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	915
bogdanm	0:9b334a45a8ff	916	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
bogdanm	0:9b334a45a8ff	917	{
bogdanm	0:9b334a45a8ff	918	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	919	{
bogdanm	0:9b334a45a8ff	920	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	921	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	922	}
bogdanm	0:9b334a45a8ff	923	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	924	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	925	}
bogdanm	0:9b334a45a8ff	926	}
bogdanm	0:9b334a45a8ff	927	}
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	930	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	931	{
bogdanm	0:9b334a45a8ff	932	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	933	}
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	936
bogdanm	0:9b334a45a8ff	937	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	938	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	939	{
bogdanm	0:9b334a45a8ff	940	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	941	/* Clear CRC Flag */
bogdanm	0:9b334a45a8ff	942	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	943
bogdanm	0:9b334a45a8ff	944	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	945	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	948	}
bogdanm	0:9b334a45a8ff	949
bogdanm	0:9b334a45a8ff	950	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	951	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	952
bogdanm	0:9b334a45a8ff	953	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	954	{
bogdanm	0:9b334a45a8ff	955	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	956	}
bogdanm	0:9b334a45a8ff	957	else
bogdanm	0:9b334a45a8ff	958	{
bogdanm	0:9b334a45a8ff	959	return HAL_OK;
bogdanm	0:9b334a45a8ff	960	}
bogdanm	0:9b334a45a8ff	961	}
bogdanm	0:9b334a45a8ff	962
bogdanm	0:9b334a45a8ff	963	/**
bogdanm	0:9b334a45a8ff	964	* @brief Transmit an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	965	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	966	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	967	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	968	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	969	* @retval HAL status
bogdanm	0:9b334a45a8ff	970	*/
bogdanm	0:9b334a45a8ff	971	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	972	{
bogdanm	0:9b334a45a8ff	973	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	974
bogdanm	0:9b334a45a8ff	975	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	976	{
bogdanm	0:9b334a45a8ff	977	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	978	{
bogdanm	0:9b334a45a8ff	979	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	980	}
bogdanm	0:9b334a45a8ff	981
bogdanm	0:9b334a45a8ff	982	/* Process Locked */
bogdanm	0:9b334a45a8ff	983	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	984
bogdanm	0:9b334a45a8ff	985	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	986	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	987	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	988	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	989	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	990	hspi->pRxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	991	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	992	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	993
bogdanm	0:9b334a45a8ff	994	/* Set the function for IT treatement */
bogdanm	0:9b334a45a8ff	995	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
bogdanm	0:9b334a45a8ff	996	{
bogdanm	0:9b334a45a8ff	997	hspi->RxISR = NULL;
bogdanm	0:9b334a45a8ff	998	hspi->TxISR = SPI_TxISR_16BIT;
bogdanm	0:9b334a45a8ff	999	}
bogdanm	0:9b334a45a8ff	1000	else
bogdanm	0:9b334a45a8ff	1001	{
bogdanm	0:9b334a45a8ff	1002	hspi->RxISR = NULL;
bogdanm	0:9b334a45a8ff	1003	hspi->TxISR = SPI_TxISR_8BIT;
bogdanm	0:9b334a45a8ff	1004	}
bogdanm	0:9b334a45a8ff	1005
bogdanm	0:9b334a45a8ff	1006	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1007	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1008	{
bogdanm	0:9b334a45a8ff	1009	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1010	}
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1013	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1014	{
bogdanm	0:9b334a45a8ff	1015	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1016	}
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1019	__HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
bogdanm	0:9b334a45a8ff	1020
bogdanm	0:9b334a45a8ff	1021	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1022	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1023
bogdanm	0:9b334a45a8ff	1024	/* Note : The SPI must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1025	to avoid the risk of SPI interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1026	process unlock */
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1029	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1030	{
bogdanm	0:9b334a45a8ff	1031	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1032	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1033	}
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	return HAL_OK;
bogdanm	0:9b334a45a8ff	1036	}
bogdanm	0:9b334a45a8ff	1037	else
bogdanm	0:9b334a45a8ff	1038	{
bogdanm	0:9b334a45a8ff	1039	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1040	}
bogdanm	0:9b334a45a8ff	1041	}
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	/**
bogdanm	0:9b334a45a8ff	1044	* @brief Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1045	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1046	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1047	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1048	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1049	* @retval HAL status
bogdanm	0:9b334a45a8ff	1050	*/
bogdanm	0:9b334a45a8ff	1051	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1052	{
bogdanm	0:9b334a45a8ff	1053	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1054	{
bogdanm	0:9b334a45a8ff	1055	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1056	{
bogdanm	0:9b334a45a8ff	1057	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1058	}
bogdanm	0:9b334a45a8ff	1059
bogdanm	0:9b334a45a8ff	1060	/* Process Locked */
bogdanm	0:9b334a45a8ff	1061	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	/* Configure communication */
bogdanm	0:9b334a45a8ff	1064	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1065	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1066	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1067	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1068	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1069	hspi->pTxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1070	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1071	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1072
bogdanm	0:9b334a45a8ff	1073	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	1074	{
bogdanm	0:9b334a45a8ff	1075	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1076	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1077	/* the receive process is not supported in 2Lines direction master mode */
bogdanm	0:9b334a45a8ff	1078	/* in this we call the transmitReceive process */
bogdanm	0:9b334a45a8ff	1079	return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
bogdanm	0:9b334a45a8ff	1080	}
bogdanm	0:9b334a45a8ff	1081
bogdanm	0:9b334a45a8ff	1082	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1083	{
bogdanm	0:9b334a45a8ff	1084	hspi->CRCSize = 1;
bogdanm	0:9b334a45a8ff	1085	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
bogdanm	0:9b334a45a8ff	1086	{
bogdanm	0:9b334a45a8ff	1087	hspi->CRCSize = 2;
bogdanm	0:9b334a45a8ff	1088	}
bogdanm	0:9b334a45a8ff	1089	}
bogdanm	0:9b334a45a8ff	1090	else
bogdanm	0:9b334a45a8ff	1091	{
bogdanm	0:9b334a45a8ff	1092	hspi->CRCSize = 0;
bogdanm	0:9b334a45a8ff	1093	}
bogdanm	0:9b334a45a8ff	1094
bogdanm	0:9b334a45a8ff	1095	/* check the data size to adapt Rx threshold and the set the function for IT treatment */
bogdanm	0:9b334a45a8ff	1096	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
bogdanm	0:9b334a45a8ff	1097	{
bogdanm	0:9b334a45a8ff	1098	/* set fiforxthreshold according the reception data length: 16 bit */
bogdanm	0:9b334a45a8ff	1099	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1100	hspi->RxISR = SPI_RxISR_16BIT;
bogdanm	0:9b334a45a8ff	1101	hspi->TxISR = NULL;
bogdanm	0:9b334a45a8ff	1102	}
bogdanm	0:9b334a45a8ff	1103	else
bogdanm	0:9b334a45a8ff	1104	{
bogdanm	0:9b334a45a8ff	1105	/* set fiforxthreshold according the reception data length: 8 bit */
bogdanm	0:9b334a45a8ff	1106	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1107	hspi->RxISR = SPI_RxISR_8BIT;
bogdanm	0:9b334a45a8ff	1108	hspi->TxISR = NULL;
bogdanm	0:9b334a45a8ff	1109	}
bogdanm	0:9b334a45a8ff	1110
bogdanm	0:9b334a45a8ff	1111	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1112	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1113	{
bogdanm	0:9b334a45a8ff	1114	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1115	}
bogdanm	0:9b334a45a8ff	1116
bogdanm	0:9b334a45a8ff	1117	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1118	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1119	{
bogdanm	0:9b334a45a8ff	1120	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1121	}
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1124	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1125
bogdanm	0:9b334a45a8ff	1126	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1127	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1128
bogdanm	0:9b334a45a8ff	1129	/* Note : The SPI must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1130	to avoid the risk of SPI interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1131	process unlock */
bogdanm	0:9b334a45a8ff	1132
bogdanm	0:9b334a45a8ff	1133	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1134	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1135	{
bogdanm	0:9b334a45a8ff	1136	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1137	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1138	}
bogdanm	0:9b334a45a8ff	1139
bogdanm	0:9b334a45a8ff	1140	return HAL_OK;
bogdanm	0:9b334a45a8ff	1141	}
bogdanm	0:9b334a45a8ff	1142	else
bogdanm	0:9b334a45a8ff	1143	{
bogdanm	0:9b334a45a8ff	1144	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1145	}
bogdanm	0:9b334a45a8ff	1146	}
bogdanm	0:9b334a45a8ff	1147
bogdanm	0:9b334a45a8ff	1148	/**
bogdanm	0:9b334a45a8ff	1149	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1150	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1151	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1152	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1153	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	1154	* @param Size: amount of data to be sent and received
bogdanm	0:9b334a45a8ff	1155	* @retval HAL status
bogdanm	0:9b334a45a8ff	1156	*/
bogdanm	0:9b334a45a8ff	1157	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1158	{
bogdanm	0:9b334a45a8ff	1159	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1160
bogdanm	0:9b334a45a8ff	1161	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
bogdanm	0:9b334a45a8ff	1162	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1163	{
bogdanm	0:9b334a45a8ff	1164	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1165	{
bogdanm	0:9b334a45a8ff	1166	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1167	}
bogdanm	0:9b334a45a8ff	1168
bogdanm	0:9b334a45a8ff	1169	/* Process locked */
bogdanm	0:9b334a45a8ff	1170	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1171
bogdanm	0:9b334a45a8ff	1172	hspi->CRCSize = 0;
bogdanm	0:9b334a45a8ff	1173	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1174	{
bogdanm	0:9b334a45a8ff	1175	hspi->CRCSize = 1;
bogdanm	0:9b334a45a8ff	1176	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
bogdanm	0:9b334a45a8ff	1177	{
bogdanm	0:9b334a45a8ff	1178	hspi->CRCSize = 2;
bogdanm	0:9b334a45a8ff	1179	}
bogdanm	0:9b334a45a8ff	1180	}
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1183	{
bogdanm	0:9b334a45a8ff	1184	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1185	}
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1188	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	1189	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1190	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1191	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	1192	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1193	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1194
bogdanm	0:9b334a45a8ff	1195	/* Set the function for IT treatement */
bogdanm	0:9b334a45a8ff	1196	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
bogdanm	0:9b334a45a8ff	1197	{
bogdanm	0:9b334a45a8ff	1198	hspi->RxISR = SPI_2linesRxISR_16BIT;
bogdanm	0:9b334a45a8ff	1199	hspi->TxISR = SPI_2linesTxISR_16BIT;
bogdanm	0:9b334a45a8ff	1200	}
bogdanm	0:9b334a45a8ff	1201	else
bogdanm	0:9b334a45a8ff	1202	{
bogdanm	0:9b334a45a8ff	1203	hspi->RxISR = SPI_2linesRxISR_8BIT;
bogdanm	0:9b334a45a8ff	1204	hspi->TxISR = SPI_2linesTxISR_8BIT;
bogdanm	0:9b334a45a8ff	1205	}
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1208	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1209	{
bogdanm	0:9b334a45a8ff	1210	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1211	}
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	/* check if packing mode is enabled and if there is more than 2 data to receive */
bogdanm	0:9b334a45a8ff	1214	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount >= 2))
bogdanm	0:9b334a45a8ff	1215	{
bogdanm	0:9b334a45a8ff	1216	/* set fiforxthreshold according the reception data length: 16 bit */
bogdanm	0:9b334a45a8ff	1217	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1218	}
bogdanm	0:9b334a45a8ff	1219	else
bogdanm	0:9b334a45a8ff	1220	{
bogdanm	0:9b334a45a8ff	1221	/* set fiforxthreshold according the reception data length: 8 bit */
bogdanm	0:9b334a45a8ff	1222	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1223	}
bogdanm	0:9b334a45a8ff	1224
bogdanm	0:9b334a45a8ff	1225	/* Enable TXE, RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1226	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1227
bogdanm	0:9b334a45a8ff	1228	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1229	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1230
bogdanm	0:9b334a45a8ff	1231	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1232	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1233	{
bogdanm	0:9b334a45a8ff	1234	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1235	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1236	}
bogdanm	0:9b334a45a8ff	1237
bogdanm	0:9b334a45a8ff	1238	return HAL_OK;
bogdanm	0:9b334a45a8ff	1239	}
bogdanm	0:9b334a45a8ff	1240	else
bogdanm	0:9b334a45a8ff	1241	{
bogdanm	0:9b334a45a8ff	1242	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1243	}
bogdanm	0:9b334a45a8ff	1244	}
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	/**
bogdanm	0:9b334a45a8ff	1247	* @brief Transmit an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1248	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1249	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1250	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1251	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1252	* @retval HAL status
bogdanm	0:9b334a45a8ff	1253	*/
bogdanm	0:9b334a45a8ff	1254	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1255	{
bogdanm	0:9b334a45a8ff	1256	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1257
bogdanm	0:9b334a45a8ff	1258	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1259	{
bogdanm	0:9b334a45a8ff	1260	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1261	}
bogdanm	0:9b334a45a8ff	1262
bogdanm	0:9b334a45a8ff	1263	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1264	{
bogdanm	0:9b334a45a8ff	1265	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1266	}
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	/* Process Locked */
bogdanm	0:9b334a45a8ff	1269	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1270
bogdanm	0:9b334a45a8ff	1271	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	1272	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1273	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1274	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1275	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1276	hspi->pRxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	1277	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	1278	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1281	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1282	{
bogdanm	0:9b334a45a8ff	1283	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1284	}
bogdanm	0:9b334a45a8ff	1285
bogdanm	0:9b334a45a8ff	1286	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1287	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1288	{
bogdanm	0:9b334a45a8ff	1289	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1290	}
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	/* Set the SPI TxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1293	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	/* Set the SPI TxDMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1296	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
bogdanm	0:9b334a45a8ff	1297
bogdanm	0:9b334a45a8ff	1298	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1299	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1300
bogdanm	0:9b334a45a8ff	1301	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1302	/* packing mode is enabled only if the DMA setting is HALWORD */
bogdanm	0:9b334a45a8ff	1303	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
bogdanm	0:9b334a45a8ff	1304	{
bogdanm	0:9b334a45a8ff	1305	/* Check the even/odd of the data size + crc if enabled */
bogdanm	0:9b334a45a8ff	1306	if((hspi->TxXferCount & 0x1) == 0)
bogdanm	0:9b334a45a8ff	1307	{
bogdanm	0:9b334a45a8ff	1308	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1309	hspi->TxXferCount = (hspi->TxXferCount >> 1);
bogdanm	0:9b334a45a8ff	1310	}
bogdanm	0:9b334a45a8ff	1311	else
bogdanm	0:9b334a45a8ff	1312	{
bogdanm	0:9b334a45a8ff	1313	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1314	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
bogdanm	0:9b334a45a8ff	1315	}
bogdanm	0:9b334a45a8ff	1316	}
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	/* Enable the Tx DMA channel */
bogdanm	0:9b334a45a8ff	1319	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1322	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1323	{
bogdanm	0:9b334a45a8ff	1324	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1325	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1326	}
bogdanm	0:9b334a45a8ff	1327
bogdanm	0:9b334a45a8ff	1328	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1329	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	1330
bogdanm	0:9b334a45a8ff	1331	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1332	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	return HAL_OK;
bogdanm	0:9b334a45a8ff	1335	}
bogdanm	0:9b334a45a8ff	1336
bogdanm	0:9b334a45a8ff	1337	/**
bogdanm	0:9b334a45a8ff	1338	* @brief Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1339	* @param hspi: SPI handle
bogdanm	0:9b334a45a8ff	1340	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1341	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1342	* @retval HAL status
bogdanm	0:9b334a45a8ff	1343	*/
bogdanm	0:9b334a45a8ff	1344	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1345	{
bogdanm	0:9b334a45a8ff	1346	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1347	{
bogdanm	0:9b334a45a8ff	1348	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1349	}
bogdanm	0:9b334a45a8ff	1350
bogdanm	0:9b334a45a8ff	1351	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1352	{
bogdanm	0:9b334a45a8ff	1353	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1354	}
bogdanm	0:9b334a45a8ff	1355
bogdanm	0:9b334a45a8ff	1356	/* Process Locked */
bogdanm	0:9b334a45a8ff	1357	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1358
bogdanm	0:9b334a45a8ff	1359	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1360	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1361	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1362	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1363	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1364	hspi->pTxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	1365	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1366	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1367
bogdanm	0:9b334a45a8ff	1368	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	1369	{
bogdanm	0:9b334a45a8ff	1370	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1371	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1372	/* the receive process is not supported in 2Lines direction master mode */
bogdanm	0:9b334a45a8ff	1373	/* in this case we call the transmitReceive process */
bogdanm	0:9b334a45a8ff	1374	return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
bogdanm	0:9b334a45a8ff	1375	}
bogdanm	0:9b334a45a8ff	1376
bogdanm	0:9b334a45a8ff	1377	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1378	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1379	{
bogdanm	0:9b334a45a8ff	1380	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1381	}
bogdanm	0:9b334a45a8ff	1382
bogdanm	0:9b334a45a8ff	1383	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1384	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1385	{
bogdanm	0:9b334a45a8ff	1386	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1387	}
bogdanm	0:9b334a45a8ff	1388
bogdanm	0:9b334a45a8ff	1389	/* packing mode management is enabled by the DMA settings */
bogdanm	0:9b334a45a8ff	1390	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
bogdanm	0:9b334a45a8ff	1391	{
bogdanm	0:9b334a45a8ff	1392	/* Process Locked */
bogdanm	0:9b334a45a8ff	1393	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1394	/* Restriction the DMA data received is not allowed in this mode */
bogdanm	0:9b334a45a8ff	1395	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1396	}
bogdanm	0:9b334a45a8ff	1397
bogdanm	0:9b334a45a8ff	1398	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
bogdanm	0:9b334a45a8ff	1399	if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1400	{
bogdanm	0:9b334a45a8ff	1401	/* set fiforxthreshold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	1402	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1403	}
bogdanm	0:9b334a45a8ff	1404	else
bogdanm	0:9b334a45a8ff	1405	{
bogdanm	0:9b334a45a8ff	1406	/* set fiforxthreshold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	1407	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1408	}
bogdanm	0:9b334a45a8ff	1409
bogdanm	0:9b334a45a8ff	1410	/* Set the SPI RxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1411	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1412
bogdanm	0:9b334a45a8ff	1413	/* Set the SPI Rx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1414	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1415
bogdanm	0:9b334a45a8ff	1416	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1417	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1418
bogdanm	0:9b334a45a8ff	1419	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1420	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	1421
bogdanm	0:9b334a45a8ff	1422	/* Enable the Rx DMA channel */
bogdanm	0:9b334a45a8ff	1423	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1424
bogdanm	0:9b334a45a8ff	1425	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1426	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1427
bogdanm	0:9b334a45a8ff	1428	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1429	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1430	{
bogdanm	0:9b334a45a8ff	1431	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1432	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1433	}
bogdanm	0:9b334a45a8ff	1434
bogdanm	0:9b334a45a8ff	1435	return HAL_OK;
bogdanm	0:9b334a45a8ff	1436	}
bogdanm	0:9b334a45a8ff	1437
bogdanm	0:9b334a45a8ff	1438	/**
bogdanm	0:9b334a45a8ff	1439	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1440	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1441	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1442	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1443	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	1444	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
bogdanm	0:9b334a45a8ff	1445	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1446	* @retval HAL status
bogdanm	0:9b334a45a8ff	1447	*/
bogdanm	0:9b334a45a8ff	1448	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1449	{
bogdanm	0:9b334a45a8ff	1450	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1451
bogdanm	0:9b334a45a8ff	1452	if((hspi->State == HAL_SPI_STATE_READY) \|\|
bogdanm	0:9b334a45a8ff	1453	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1454	{
bogdanm	0:9b334a45a8ff	1455	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1456	{
bogdanm	0:9b334a45a8ff	1457	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1458	}
bogdanm	0:9b334a45a8ff	1459
bogdanm	0:9b334a45a8ff	1460	/* Process locked */
bogdanm	0:9b334a45a8ff	1461	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1462
bogdanm	0:9b334a45a8ff	1463	/* check if the transmit Receive function is not called by a receive master */
bogdanm	0:9b334a45a8ff	1464	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1465	{
bogdanm	0:9b334a45a8ff	1466	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1467	}
bogdanm	0:9b334a45a8ff	1468
bogdanm	0:9b334a45a8ff	1469	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1470	hspi->pTxBuffPtr = (uint8_t *)pTxData;
bogdanm	0:9b334a45a8ff	1471	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1472	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1473	hspi->pRxBuffPtr = (uint8_t *)pRxData;
bogdanm	0:9b334a45a8ff	1474	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1475	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1476
bogdanm	0:9b334a45a8ff	1477	/* Reset CRC Calculation + increase the rxsize */
bogdanm	0:9b334a45a8ff	1478	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1479	{
bogdanm	0:9b334a45a8ff	1480	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1481	}
bogdanm	0:9b334a45a8ff	1482
bogdanm	0:9b334a45a8ff	1483	/* Reset the threshold bit */
bogdanm	0:9b334a45a8ff	1484	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1485	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
bogdanm	0:9b334a45a8ff	1486
bogdanm	0:9b334a45a8ff	1487	/* the packing mode management is enabled by the DMA settings according the spi data size */
bogdanm	0:9b334a45a8ff	1488	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1489	{
bogdanm	0:9b334a45a8ff	1490	/* set fiforxthreshold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	1491	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1492	}
bogdanm	0:9b334a45a8ff	1493	else
bogdanm	0:9b334a45a8ff	1494	{
bogdanm	0:9b334a45a8ff	1495	/* set fiforxthreshold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	1496	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1497
bogdanm	0:9b334a45a8ff	1498	if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
bogdanm	0:9b334a45a8ff	1499	{
bogdanm	0:9b334a45a8ff	1500	if((hspi->TxXferSize & 0x1) == 0x0 )
bogdanm	0:9b334a45a8ff	1501	{
bogdanm	0:9b334a45a8ff	1502	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1503	hspi->TxXferCount = hspi->TxXferCount >> 1;
bogdanm	0:9b334a45a8ff	1504	}
bogdanm	0:9b334a45a8ff	1505	else
bogdanm	0:9b334a45a8ff	1506	{
bogdanm	0:9b334a45a8ff	1507	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1508	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
bogdanm	0:9b334a45a8ff	1509	}
bogdanm	0:9b334a45a8ff	1510	}
bogdanm	0:9b334a45a8ff	1511
bogdanm	0:9b334a45a8ff	1512	if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
bogdanm	0:9b334a45a8ff	1513	{
bogdanm	0:9b334a45a8ff	1514	/* set fiforxthreshold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	1515	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1516
bogdanm	0:9b334a45a8ff	1517	/* Size must include the CRC length */
bogdanm	0:9b334a45a8ff	1518	if((hspi->RxXferCount & 0x1) == 0x0 )
bogdanm	0:9b334a45a8ff	1519	{
bogdanm	0:9b334a45a8ff	1520	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
bogdanm	0:9b334a45a8ff	1521	hspi->RxXferCount = hspi->RxXferCount >> 1;
bogdanm	0:9b334a45a8ff	1522	}
bogdanm	0:9b334a45a8ff	1523	else
bogdanm	0:9b334a45a8ff	1524	{
bogdanm	0:9b334a45a8ff	1525	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
bogdanm	0:9b334a45a8ff	1526	hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
bogdanm	0:9b334a45a8ff	1527	}
bogdanm	0:9b334a45a8ff	1528	}
bogdanm	0:9b334a45a8ff	1529	}
bogdanm	0:9b334a45a8ff	1530
bogdanm	0:9b334a45a8ff	1531	/* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
bogdanm	0:9b334a45a8ff	1532	the reception request (RXNE) */
bogdanm	0:9b334a45a8ff	1533	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1534	{
bogdanm	0:9b334a45a8ff	1535	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1536	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1537	}
bogdanm	0:9b334a45a8ff	1538	else
bogdanm	0:9b334a45a8ff	1539	{
bogdanm	0:9b334a45a8ff	1540	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1541	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1542	}
bogdanm	0:9b334a45a8ff	1543	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1544	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1545
bogdanm	0:9b334a45a8ff	1546	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1547	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	1548
bogdanm	0:9b334a45a8ff	1549	/* Enable the Rx DMA channel */
bogdanm	0:9b334a45a8ff	1550	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1551
bogdanm	0:9b334a45a8ff	1552	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
bogdanm	0:9b334a45a8ff	1553	is performed in DMA reception complete callback */
bogdanm	0:9b334a45a8ff	1554	hspi->hdmatx->XferHalfCpltCallback = NULL;
bogdanm	0:9b334a45a8ff	1555	hspi->hdmatx->XferCpltCallback = NULL;
bogdanm	0:9b334a45a8ff	1556
bogdanm	0:9b334a45a8ff	1557	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1558	{
bogdanm	0:9b334a45a8ff	1559	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1560	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1561	}
bogdanm	0:9b334a45a8ff	1562	else
bogdanm	0:9b334a45a8ff	1563	{
bogdanm	0:9b334a45a8ff	1564	hspi->hdmatx->XferErrorCallback = NULL;
bogdanm	0:9b334a45a8ff	1565	}
bogdanm	0:9b334a45a8ff	1566
bogdanm	0:9b334a45a8ff	1567	/* Enable the Tx DMA channel */
bogdanm	0:9b334a45a8ff	1568	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1569
bogdanm	0:9b334a45a8ff	1570	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1571	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1572
bogdanm	0:9b334a45a8ff	1573	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1574	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1575	{
bogdanm	0:9b334a45a8ff	1576	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1577	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1578	}
bogdanm	0:9b334a45a8ff	1579
bogdanm	0:9b334a45a8ff	1580	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1581	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	1582
bogdanm	0:9b334a45a8ff	1583	return HAL_OK;
bogdanm	0:9b334a45a8ff	1584	}
bogdanm	0:9b334a45a8ff	1585	else
bogdanm	0:9b334a45a8ff	1586	{
bogdanm	0:9b334a45a8ff	1587	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1588	}
bogdanm	0:9b334a45a8ff	1589	}
bogdanm	0:9b334a45a8ff	1590
bogdanm	0:9b334a45a8ff	1591	/**
bogdanm	0:9b334a45a8ff	1592	* @brief Pauses the DMA Transfer.
bogdanm	0:9b334a45a8ff	1593	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1594	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1595	* @retval HAL status
bogdanm	0:9b334a45a8ff	1596	*/
bogdanm	0:9b334a45a8ff	1597	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1598	{
bogdanm	0:9b334a45a8ff	1599	/* Process Locked */
bogdanm	0:9b334a45a8ff	1600	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1601
bogdanm	0:9b334a45a8ff	1602	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1603	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1604
bogdanm	0:9b334a45a8ff	1605	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1606	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1607
bogdanm	0:9b334a45a8ff	1608	return HAL_OK;
bogdanm	0:9b334a45a8ff	1609	}
bogdanm	0:9b334a45a8ff	1610
bogdanm	0:9b334a45a8ff	1611	/**
bogdanm	0:9b334a45a8ff	1612	* @brief Resumes the DMA Transfer.
bogdanm	0:9b334a45a8ff	1613	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1614	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1615	* @retval HAL status
bogdanm	0:9b334a45a8ff	1616	*/
bogdanm	0:9b334a45a8ff	1617	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1618	{
bogdanm	0:9b334a45a8ff	1619	/* Process Locked */
bogdanm	0:9b334a45a8ff	1620	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1621
bogdanm	0:9b334a45a8ff	1622	/* Enable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1623	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1624
bogdanm	0:9b334a45a8ff	1625	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1626	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1627
bogdanm	0:9b334a45a8ff	1628	return HAL_OK;
bogdanm	0:9b334a45a8ff	1629	}
bogdanm	0:9b334a45a8ff	1630
bogdanm	0:9b334a45a8ff	1631	/**
bogdanm	0:9b334a45a8ff	1632	* @brief Stops the DMA Transfer.
bogdanm	0:9b334a45a8ff	1633	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1634	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1635	* @retval HAL status
bogdanm	0:9b334a45a8ff	1636	*/
bogdanm	0:9b334a45a8ff	1637	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1638	{
bogdanm	0:9b334a45a8ff	1639	/* The Lock is not implemented on this API to allow the user application
bogdanm	0:9b334a45a8ff	1640	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
bogdanm	0:9b334a45a8ff	1641	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
bogdanm	0:9b334a45a8ff	1642	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
bogdanm	0:9b334a45a8ff	1643	*/
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	/* Abort the SPI DMA tx Stream */
bogdanm	0:9b334a45a8ff	1646	if(hspi->hdmatx != NULL)
bogdanm	0:9b334a45a8ff	1647	{
bogdanm	0:9b334a45a8ff	1648	HAL_DMA_Abort(hspi->hdmatx);
bogdanm	0:9b334a45a8ff	1649	}
bogdanm	0:9b334a45a8ff	1650	/* Abort the SPI DMA rx Stream */
bogdanm	0:9b334a45a8ff	1651	if(hspi->hdmarx != NULL)
bogdanm	0:9b334a45a8ff	1652	{
bogdanm	0:9b334a45a8ff	1653	HAL_DMA_Abort(hspi->hdmarx);
bogdanm	0:9b334a45a8ff	1654	}
bogdanm	0:9b334a45a8ff	1655
bogdanm	0:9b334a45a8ff	1656	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1657	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1658	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1659	return HAL_OK;
bogdanm	0:9b334a45a8ff	1660	}
bogdanm	0:9b334a45a8ff	1661
bogdanm	0:9b334a45a8ff	1662	/**
bogdanm	0:9b334a45a8ff	1663	* @brief This function handles SPI interrupt request.
bogdanm	0:9b334a45a8ff	1664	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1665	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1666	* @retval None
bogdanm	0:9b334a45a8ff	1667	*/
bogdanm	0:9b334a45a8ff	1668	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1669	{
bogdanm	0:9b334a45a8ff	1670	/* SPI in mode Receiver ----------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1671	if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
bogdanm	0:9b334a45a8ff	1672	(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
bogdanm	0:9b334a45a8ff	1673	{
bogdanm	0:9b334a45a8ff	1674	hspi->RxISR(hspi);
bogdanm	0:9b334a45a8ff	1675	return;
bogdanm	0:9b334a45a8ff	1676	}
bogdanm	0:9b334a45a8ff	1677
bogdanm	0:9b334a45a8ff	1678	/* SPI in mode Transmitter ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1679	if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
bogdanm	0:9b334a45a8ff	1680	{
bogdanm	0:9b334a45a8ff	1681	hspi->TxISR(hspi);
bogdanm	0:9b334a45a8ff	1682	return;
bogdanm	0:9b334a45a8ff	1683	}
bogdanm	0:9b334a45a8ff	1684
bogdanm	0:9b334a45a8ff	1685	/* SPI in ERROR Treatment ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1686	if((hspi->Instance->SR & (SPI_FLAG_MODF \| SPI_FLAG_OVR \| SPI_FLAG_FRE)) != RESET)
bogdanm	0:9b334a45a8ff	1687	{
bogdanm	0:9b334a45a8ff	1688	/* SPI Overrun error interrupt occurred -------------------------------------*/
bogdanm	0:9b334a45a8ff	1689	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
bogdanm	0:9b334a45a8ff	1690	{
bogdanm	0:9b334a45a8ff	1691	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	1692	{
bogdanm	0:9b334a45a8ff	1693	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
bogdanm	0:9b334a45a8ff	1694	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1695	}
bogdanm	0:9b334a45a8ff	1696	else
bogdanm	0:9b334a45a8ff	1697	{
bogdanm	0:9b334a45a8ff	1698	return;
bogdanm	0:9b334a45a8ff	1699	}
bogdanm	0:9b334a45a8ff	1700	}
bogdanm	0:9b334a45a8ff	1701
bogdanm	0:9b334a45a8ff	1702	/* SPI Mode Fault error interrupt occurred -------------------------------------*/
bogdanm	0:9b334a45a8ff	1703	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
bogdanm	0:9b334a45a8ff	1704	{
bogdanm	0:9b334a45a8ff	1705	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
bogdanm	0:9b334a45a8ff	1706	__HAL_SPI_CLEAR_MODFFLAG(hspi);
bogdanm	0:9b334a45a8ff	1707	}
bogdanm	0:9b334a45a8ff	1708
bogdanm	0:9b334a45a8ff	1709	/* SPI Frame error interrupt occurred ----------------------------------------*/
bogdanm	0:9b334a45a8ff	1710	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
bogdanm	0:9b334a45a8ff	1711	{
bogdanm	0:9b334a45a8ff	1712	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
bogdanm	0:9b334a45a8ff	1713	__HAL_SPI_CLEAR_FREFLAG(hspi);
bogdanm	0:9b334a45a8ff	1714	}
bogdanm	0:9b334a45a8ff	1715
bogdanm	0:9b334a45a8ff	1716	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
bogdanm	0:9b334a45a8ff	1717	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1718	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1719
bogdanm	0:9b334a45a8ff	1720	return;
bogdanm	0:9b334a45a8ff	1721	}
bogdanm	0:9b334a45a8ff	1722	}
bogdanm	0:9b334a45a8ff	1723
bogdanm	0:9b334a45a8ff	1724	/**
bogdanm	0:9b334a45a8ff	1725	* @brief Tx Transfer completed callback
bogdanm	0:9b334a45a8ff	1726	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1727	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1728	* @retval None
bogdanm	0:9b334a45a8ff	1729	*/
bogdanm	0:9b334a45a8ff	1730	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1731	{
mbed_official	83:a036322b8637	1732	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1733	UNUSED(hspi);
mbed_official	83:a036322b8637	1734
bogdanm	0:9b334a45a8ff	1735	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1736	the HAL_SPI_TxCpltCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1737	*/
bogdanm	0:9b334a45a8ff	1738	}
bogdanm	0:9b334a45a8ff	1739
bogdanm	0:9b334a45a8ff	1740	/**
bogdanm	0:9b334a45a8ff	1741	* @brief Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1742	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1743	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1744	* @retval None
bogdanm	0:9b334a45a8ff	1745	*/
bogdanm	0:9b334a45a8ff	1746	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1747	{
mbed_official	83:a036322b8637	1748	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1749	UNUSED(hspi);
mbed_official	83:a036322b8637	1750
bogdanm	0:9b334a45a8ff	1751	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1752	the HAL_SPI_RxCpltCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1753	*/
bogdanm	0:9b334a45a8ff	1754	}
bogdanm	0:9b334a45a8ff	1755
bogdanm	0:9b334a45a8ff	1756	/**
bogdanm	0:9b334a45a8ff	1757	* @brief Tx and Rx Transfer completed callback
bogdanm	0:9b334a45a8ff	1758	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1759	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1760	* @retval None
bogdanm	0:9b334a45a8ff	1761	*/
bogdanm	0:9b334a45a8ff	1762	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1763	{
mbed_official	83:a036322b8637	1764	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1765	UNUSED(hspi);
mbed_official	83:a036322b8637	1766
bogdanm	0:9b334a45a8ff	1767	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1768	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1769	*/
bogdanm	0:9b334a45a8ff	1770	}
bogdanm	0:9b334a45a8ff	1771
bogdanm	0:9b334a45a8ff	1772	/**
bogdanm	0:9b334a45a8ff	1773	* @brief Tx Half Transfer completed callback
bogdanm	0:9b334a45a8ff	1774	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1775	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1776	* @retval None
bogdanm	0:9b334a45a8ff	1777	*/
bogdanm	0:9b334a45a8ff	1778	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1779	{
mbed_official	83:a036322b8637	1780	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1781	UNUSED(hspi);
mbed_official	83:a036322b8637	1782
bogdanm	0:9b334a45a8ff	1783	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1784	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1785	*/
bogdanm	0:9b334a45a8ff	1786	}
bogdanm	0:9b334a45a8ff	1787
bogdanm	0:9b334a45a8ff	1788	/**
bogdanm	0:9b334a45a8ff	1789	* @brief Rx Half Transfer completed callback
bogdanm	0:9b334a45a8ff	1790	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1791	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1792	* @retval None
bogdanm	0:9b334a45a8ff	1793	*/
bogdanm	0:9b334a45a8ff	1794	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1795	{
mbed_official	83:a036322b8637	1796	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1797	UNUSED(hspi);
mbed_official	83:a036322b8637	1798
bogdanm	0:9b334a45a8ff	1799	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1800	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
bogdanm	0:9b334a45a8ff	1801	*/
bogdanm	0:9b334a45a8ff	1802	}
bogdanm	0:9b334a45a8ff	1803
bogdanm	0:9b334a45a8ff	1804	/**
bogdanm	0:9b334a45a8ff	1805	* @brief Tx and Rx Half Transfer callback
bogdanm	0:9b334a45a8ff	1806	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1807	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1808	* @retval None
bogdanm	0:9b334a45a8ff	1809	*/
bogdanm	0:9b334a45a8ff	1810	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1811	{
mbed_official	83:a036322b8637	1812	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1813	UNUSED(hspi);
mbed_official	83:a036322b8637	1814
bogdanm	0:9b334a45a8ff	1815	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1816	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
bogdanm	0:9b334a45a8ff	1817	*/
bogdanm	0:9b334a45a8ff	1818	}
bogdanm	0:9b334a45a8ff	1819
bogdanm	0:9b334a45a8ff	1820	/**
bogdanm	0:9b334a45a8ff	1821	* @brief SPI error callback
bogdanm	0:9b334a45a8ff	1822	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1823	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1824	* @retval None
bogdanm	0:9b334a45a8ff	1825	*/
bogdanm	0:9b334a45a8ff	1826	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1827	{
mbed_official	83:a036322b8637	1828	/* Prevent unused argument(s) compilation warning */
mbed_official	83:a036322b8637	1829	UNUSED(hspi);
mbed_official	83:a036322b8637	1830
bogdanm	0:9b334a45a8ff	1831	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1832	the HAL_SPI_ErrorCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1833	*/
bogdanm	0:9b334a45a8ff	1834	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
bogdanm	0:9b334a45a8ff	1835	and user can use HAL_SPI_GetError() API to check the latest error occurred
bogdanm	0:9b334a45a8ff	1836	*/
bogdanm	0:9b334a45a8ff	1837	}
bogdanm	0:9b334a45a8ff	1838
bogdanm	0:9b334a45a8ff	1839	/**
bogdanm	0:9b334a45a8ff	1840	* @}
bogdanm	0:9b334a45a8ff	1841	*/
bogdanm	0:9b334a45a8ff	1842
bogdanm	0:9b334a45a8ff	1843	/**
bogdanm	0:9b334a45a8ff	1844	* @}
bogdanm	0:9b334a45a8ff	1845	*/
bogdanm	0:9b334a45a8ff	1846
bogdanm	0:9b334a45a8ff	1847	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	1848	* @brief SPI control functions
bogdanm	0:9b334a45a8ff	1849	*
bogdanm	0:9b334a45a8ff	1850	@verbatim
bogdanm	0:9b334a45a8ff	1851	===============================================================================
bogdanm	0:9b334a45a8ff	1852	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1853	===============================================================================
bogdanm	0:9b334a45a8ff	1854	[..]
bogdanm	0:9b334a45a8ff	1855	This subsection provides a set of functions allowing to control the SPI.
bogdanm	0:9b334a45a8ff	1856	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
bogdanm	0:9b334a45a8ff	1857	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
bogdanm	0:9b334a45a8ff	1858	@endverbatim
bogdanm	0:9b334a45a8ff	1859	* @{
bogdanm	0:9b334a45a8ff	1860	*/
bogdanm	0:9b334a45a8ff	1861
bogdanm	0:9b334a45a8ff	1862	/**
bogdanm	0:9b334a45a8ff	1863	* @brief Return the SPI state
bogdanm	0:9b334a45a8ff	1864	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1865	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1866	* @retval SPI state
bogdanm	0:9b334a45a8ff	1867	*/
bogdanm	0:9b334a45a8ff	1868	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1869	{
bogdanm	0:9b334a45a8ff	1870	return hspi->State;
bogdanm	0:9b334a45a8ff	1871	}
bogdanm	0:9b334a45a8ff	1872
bogdanm	0:9b334a45a8ff	1873	/**
bogdanm	0:9b334a45a8ff	1874	* @brief Return the SPI error code
bogdanm	0:9b334a45a8ff	1875	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1876	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1877	* @retval SPI error code in bitmap format
bogdanm	0:9b334a45a8ff	1878	*/
bogdanm	0:9b334a45a8ff	1879	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1880	{
bogdanm	0:9b334a45a8ff	1881	return hspi->ErrorCode;
bogdanm	0:9b334a45a8ff	1882	}
bogdanm	0:9b334a45a8ff	1883
bogdanm	0:9b334a45a8ff	1884	/**
bogdanm	0:9b334a45a8ff	1885	* @}
bogdanm	0:9b334a45a8ff	1886	*/
bogdanm	0:9b334a45a8ff	1887
bogdanm	0:9b334a45a8ff	1888	/**
bogdanm	0:9b334a45a8ff	1889	* @}
bogdanm	0:9b334a45a8ff	1890	*/
bogdanm	0:9b334a45a8ff	1891
bogdanm	0:9b334a45a8ff	1892	/** @defgroup SPI_Private_Functions SPI Private Functions
bogdanm	0:9b334a45a8ff	1893	* @{
bogdanm	0:9b334a45a8ff	1894	*/
bogdanm	0:9b334a45a8ff	1895
bogdanm	0:9b334a45a8ff	1896	/**
bogdanm	0:9b334a45a8ff	1897	* @brief DMA SPI transmit process complete callback
bogdanm	0:9b334a45a8ff	1898	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1899	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1900	* @retval None
bogdanm	0:9b334a45a8ff	1901	*/
bogdanm	0:9b334a45a8ff	1902	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1903	{
bogdanm	0:9b334a45a8ff	1904	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1905
bogdanm	0:9b334a45a8ff	1906	/* DMA Normal Mode */
bogdanm	0:9b334a45a8ff	1907	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm	0:9b334a45a8ff	1908	{
bogdanm	0:9b334a45a8ff	1909	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1910	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1911
bogdanm	0:9b334a45a8ff	1912	/* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
bogdanm	0:9b334a45a8ff	1913	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1914	{
bogdanm	0:9b334a45a8ff	1915	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1916	}
bogdanm	0:9b334a45a8ff	1917
bogdanm	0:9b334a45a8ff	1918	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1919	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1920
bogdanm	0:9b334a45a8ff	1921	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1922	{
bogdanm	0:9b334a45a8ff	1923	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1924	return;
bogdanm	0:9b334a45a8ff	1925	}
bogdanm	0:9b334a45a8ff	1926	}
bogdanm	0:9b334a45a8ff	1927	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1928	}
bogdanm	0:9b334a45a8ff	1929
bogdanm	0:9b334a45a8ff	1930	/**
bogdanm	0:9b334a45a8ff	1931	* @brief DMA SPI receive process complete callback
bogdanm	0:9b334a45a8ff	1932	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1933	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1934	* @retval None
bogdanm	0:9b334a45a8ff	1935	*/
bogdanm	0:9b334a45a8ff	1936	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1937	{
bogdanm	0:9b334a45a8ff	1938	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	1939	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1940
bogdanm	0:9b334a45a8ff	1941	/* DMA Normal mode */
bogdanm	0:9b334a45a8ff	1942	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm	0:9b334a45a8ff	1943	{
bogdanm	0:9b334a45a8ff	1944	/* CRC handling */
bogdanm	0:9b334a45a8ff	1945	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1946	{
bogdanm	0:9b334a45a8ff	1947	/* Wait until TXE flag */
bogdanm	0:9b334a45a8ff	1948	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	1949	{
bogdanm	0:9b334a45a8ff	1950	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	1951	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	1952	}
bogdanm	0:9b334a45a8ff	1953	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1954	{
bogdanm	0:9b334a45a8ff	1955	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1956	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	1957	}
bogdanm	0:9b334a45a8ff	1958	else
bogdanm	0:9b334a45a8ff	1959	{
bogdanm	0:9b334a45a8ff	1960	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1961	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	1962
bogdanm	0:9b334a45a8ff	1963	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
bogdanm	0:9b334a45a8ff	1964	{
bogdanm	0:9b334a45a8ff	1965	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	1966	{
bogdanm	0:9b334a45a8ff	1967	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	1968	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	1969	}
bogdanm	0:9b334a45a8ff	1970	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1971	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	1972	}
bogdanm	0:9b334a45a8ff	1973	}
bogdanm	0:9b334a45a8ff	1974	}
bogdanm	0:9b334a45a8ff	1975
bogdanm	0:9b334a45a8ff	1976	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1977	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1978	/* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
bogdanm	0:9b334a45a8ff	1979	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1980
bogdanm	0:9b334a45a8ff	1981	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	1982	SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
bogdanm	0:9b334a45a8ff	1983
bogdanm	0:9b334a45a8ff	1984	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1985	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1986
bogdanm	0:9b334a45a8ff	1987	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	1988	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1989	{
bogdanm	0:9b334a45a8ff	1990	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	1991	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1992	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1993	}
bogdanm	0:9b334a45a8ff	1994	else
bogdanm	0:9b334a45a8ff	1995	{
bogdanm	0:9b334a45a8ff	1996	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1997	{
bogdanm	0:9b334a45a8ff	1998	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1999	}
bogdanm	0:9b334a45a8ff	2000	else
bogdanm	0:9b334a45a8ff	2001	{
bogdanm	0:9b334a45a8ff	2002	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2003	}
bogdanm	0:9b334a45a8ff	2004	}
bogdanm	0:9b334a45a8ff	2005	}
bogdanm	0:9b334a45a8ff	2006	else
bogdanm	0:9b334a45a8ff	2007	{
bogdanm	0:9b334a45a8ff	2008	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2009	}
bogdanm	0:9b334a45a8ff	2010	}
bogdanm	0:9b334a45a8ff	2011
bogdanm	0:9b334a45a8ff	2012	/**
bogdanm	0:9b334a45a8ff	2013	* @brief DMA SPI transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2014	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2015	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2016	* @retval None
bogdanm	0:9b334a45a8ff	2017	*/
bogdanm	0:9b334a45a8ff	2018	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2019	{
bogdanm	0:9b334a45a8ff	2020	__IO int16_t tmpreg;
bogdanm	0:9b334a45a8ff	2021	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2022
bogdanm	0:9b334a45a8ff	2023	/* CRC handling */
bogdanm	0:9b334a45a8ff	2024	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2025	{
bogdanm	0:9b334a45a8ff	2026	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
bogdanm	0:9b334a45a8ff	2027	{
bogdanm	0:9b334a45a8ff	2028	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	2029	{
bogdanm	0:9b334a45a8ff	2030	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	2031	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2032	}
bogdanm	0:9b334a45a8ff	2033	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2034	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2035	}
bogdanm	0:9b334a45a8ff	2036	else
bogdanm	0:9b334a45a8ff	2037	{
bogdanm	0:9b334a45a8ff	2038	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	2039	{
bogdanm	0:9b334a45a8ff	2040	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	2041	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2042	}
bogdanm	0:9b334a45a8ff	2043	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2044	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2045	}
bogdanm	0:9b334a45a8ff	2046	}
bogdanm	0:9b334a45a8ff	2047
bogdanm	0:9b334a45a8ff	2048	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	2049	SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
bogdanm	0:9b334a45a8ff	2050
bogdanm	0:9b334a45a8ff	2051	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	2052	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2053
bogdanm	0:9b334a45a8ff	2054	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	2055	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2056
bogdanm	0:9b334a45a8ff	2057	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2058	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2059	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2060
bogdanm	0:9b334a45a8ff	2061	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2062	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2063	{
bogdanm	0:9b334a45a8ff	2064	hspi->ErrorCode = HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2065	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2066	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2067	}
bogdanm	0:9b334a45a8ff	2068	else
bogdanm	0:9b334a45a8ff	2069	{
bogdanm	0:9b334a45a8ff	2070	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2071	{
bogdanm	0:9b334a45a8ff	2072	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2073	}
bogdanm	0:9b334a45a8ff	2074	else
bogdanm	0:9b334a45a8ff	2075	{
bogdanm	0:9b334a45a8ff	2076	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2077	}
bogdanm	0:9b334a45a8ff	2078	}
bogdanm	0:9b334a45a8ff	2079	}
bogdanm	0:9b334a45a8ff	2080
bogdanm	0:9b334a45a8ff	2081	/**
bogdanm	0:9b334a45a8ff	2082	* @brief DMA SPI half transmit process complete callback
bogdanm	0:9b334a45a8ff	2083	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2084	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2085	* @retval None
bogdanm	0:9b334a45a8ff	2086	*/
bogdanm	0:9b334a45a8ff	2087	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2088	{
bogdanm	0:9b334a45a8ff	2089	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2090
bogdanm	0:9b334a45a8ff	2091	HAL_SPI_TxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2092	}
bogdanm	0:9b334a45a8ff	2093
bogdanm	0:9b334a45a8ff	2094	/**
bogdanm	0:9b334a45a8ff	2095	* @brief DMA SPI half receive process complete callback
bogdanm	0:9b334a45a8ff	2096	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2097	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2098	* @retval None
bogdanm	0:9b334a45a8ff	2099	*/
bogdanm	0:9b334a45a8ff	2100	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2101	{
bogdanm	0:9b334a45a8ff	2102	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2103
bogdanm	0:9b334a45a8ff	2104	HAL_SPI_RxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2105	}
bogdanm	0:9b334a45a8ff	2106
bogdanm	0:9b334a45a8ff	2107	/**
bogdanm	0:9b334a45a8ff	2108	* @brief DMA SPI Half transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2109	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2110	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2111	* @retval None
bogdanm	0:9b334a45a8ff	2112	*/
bogdanm	0:9b334a45a8ff	2113	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2114	{
bogdanm	0:9b334a45a8ff	2115	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2116
bogdanm	0:9b334a45a8ff	2117	HAL_SPI_TxRxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2118	}
bogdanm	0:9b334a45a8ff	2119
bogdanm	0:9b334a45a8ff	2120	/**
bogdanm	0:9b334a45a8ff	2121	* @brief DMA SPI communication error callback
bogdanm	0:9b334a45a8ff	2122	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2123	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2124	* @retval None
bogdanm	0:9b334a45a8ff	2125	*/
bogdanm	0:9b334a45a8ff	2126	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2127	{
bogdanm	0:9b334a45a8ff	2128	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2129
bogdanm	0:9b334a45a8ff	2130	/* Stop the disable DMA transfer on SPI side */
bogdanm	0:9b334a45a8ff	2131	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2132
bogdanm	0:9b334a45a8ff	2133	hspi->ErrorCode\|= HAL_SPI_ERROR_DMA;
bogdanm	0:9b334a45a8ff	2134	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2135	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2136	}
bogdanm	0:9b334a45a8ff	2137
bogdanm	0:9b334a45a8ff	2138	/**
bogdanm	0:9b334a45a8ff	2139	* @brief Rx Handler for Transmit and Receive in Interrupt mode
bogdanm	0:9b334a45a8ff	2140	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2141	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2142	* @retval None
bogdanm	0:9b334a45a8ff	2143	*/
bogdanm	0:9b334a45a8ff	2144	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2145	{
bogdanm	0:9b334a45a8ff	2146	/* Receive data in packing mode */
bogdanm	0:9b334a45a8ff	2147	if(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	2148	{
bogdanm	0:9b334a45a8ff	2149	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2150	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2151	hspi->RxXferCount -= 2;
bogdanm	0:9b334a45a8ff	2152	if(hspi->RxXferCount == 1)
bogdanm	0:9b334a45a8ff	2153	{
bogdanm	0:9b334a45a8ff	2154	/* set fiforxthreshold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	2155	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	2156	}
bogdanm	0:9b334a45a8ff	2157	}
bogdanm	0:9b334a45a8ff	2158	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	2159	else
bogdanm	0:9b334a45a8ff	2160	{
bogdanm	0:9b334a45a8ff	2161	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2162	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2163	}
bogdanm	0:9b334a45a8ff	2164
bogdanm	0:9b334a45a8ff	2165	/* check end of the reception */
bogdanm	0:9b334a45a8ff	2166	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2167	{
bogdanm	0:9b334a45a8ff	2168	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2169	{
bogdanm	0:9b334a45a8ff	2170	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	2171	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
bogdanm	0:9b334a45a8ff	2172	return;
bogdanm	0:9b334a45a8ff	2173	}
bogdanm	0:9b334a45a8ff	2174
bogdanm	0:9b334a45a8ff	2175	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	2176	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	2177
bogdanm	0:9b334a45a8ff	2178	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2179	{
bogdanm	0:9b334a45a8ff	2180	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2181	}
bogdanm	0:9b334a45a8ff	2182	}
bogdanm	0:9b334a45a8ff	2183	}
bogdanm	0:9b334a45a8ff	2184
bogdanm	0:9b334a45a8ff	2185	/**
bogdanm	0:9b334a45a8ff	2186	* @brief Rx Handler for Transmit and Receive in Interrupt mode
bogdanm	0:9b334a45a8ff	2187	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2188	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2189	* @retval None
bogdanm	0:9b334a45a8ff	2190	*/
bogdanm	0:9b334a45a8ff	2191	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2192	{
bogdanm	0:9b334a45a8ff	2193	__IO uint8_t tmpreg;
bogdanm	0:9b334a45a8ff	2194
bogdanm	0:9b334a45a8ff	2195	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2196	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2197
bogdanm	0:9b334a45a8ff	2198	hspi->CRCSize--;
bogdanm	0:9b334a45a8ff	2199
bogdanm	0:9b334a45a8ff	2200	/* check end of the reception */
bogdanm	0:9b334a45a8ff	2201	if(hspi->CRCSize == 0)
bogdanm	0:9b334a45a8ff	2202	{
bogdanm	0:9b334a45a8ff	2203	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	2204	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	2205
bogdanm	0:9b334a45a8ff	2206	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2207	{
bogdanm	0:9b334a45a8ff	2208	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2209	}
bogdanm	0:9b334a45a8ff	2210	}
bogdanm	0:9b334a45a8ff	2211	}
bogdanm	0:9b334a45a8ff	2212
bogdanm	0:9b334a45a8ff	2213	/**
bogdanm	0:9b334a45a8ff	2214	* @brief Tx Handler for Transmit and Receive in Interrupt mode
bogdanm	0:9b334a45a8ff	2215	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2216	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2217	* @retval None
bogdanm	0:9b334a45a8ff	2218	*/
bogdanm	0:9b334a45a8ff	2219	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2220	{
bogdanm	0:9b334a45a8ff	2221	/* Transmit data in packing Bit mode */
bogdanm	0:9b334a45a8ff	2222	if(hspi->TxXferCount >= 2)
bogdanm	0:9b334a45a8ff	2223	{
bogdanm	0:9b334a45a8ff	2224	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	2225	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2226	hspi->TxXferCount -= 2;
bogdanm	0:9b334a45a8ff	2227	}
bogdanm	0:9b334a45a8ff	2228	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	2229	else
bogdanm	0:9b334a45a8ff	2230	{
bogdanm	0:9b334a45a8ff	2231	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	2232	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	2233	}
bogdanm	0:9b334a45a8ff	2234
bogdanm	0:9b334a45a8ff	2235	/* check the end of the transmission */
bogdanm	0:9b334a45a8ff	2236	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2237	{
bogdanm	0:9b334a45a8ff	2238	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2239	{
bogdanm	0:9b334a45a8ff	2240	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2241	}
bogdanm	0:9b334a45a8ff	2242	/* Disable TXE interrupt */
bogdanm	0:9b334a45a8ff	2243	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
bogdanm	0:9b334a45a8ff	2244
bogdanm	0:9b334a45a8ff	2245	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2246	{
bogdanm	0:9b334a45a8ff	2247	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2248	}
bogdanm	0:9b334a45a8ff	2249	}
bogdanm	0:9b334a45a8ff	2250	}
bogdanm	0:9b334a45a8ff	2251
bogdanm	0:9b334a45a8ff	2252	/**
bogdanm	0:9b334a45a8ff	2253	* @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
bogdanm	0:9b334a45a8ff	2254	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2255	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2256	* @retval None
bogdanm	0:9b334a45a8ff	2257	*/
bogdanm	0:9b334a45a8ff	2258	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2259	{
bogdanm	0:9b334a45a8ff	2260	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2261	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2262	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2263	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2264
bogdanm	0:9b334a45a8ff	2265	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2266	{
bogdanm	0:9b334a45a8ff	2267	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2268	{
bogdanm	0:9b334a45a8ff	2269	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
bogdanm	0:9b334a45a8ff	2270	return;
bogdanm	0:9b334a45a8ff	2271	}
bogdanm	0:9b334a45a8ff	2272
bogdanm	0:9b334a45a8ff	2273	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	2274	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	2275
bogdanm	0:9b334a45a8ff	2276	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2277	{
bogdanm	0:9b334a45a8ff	2278	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2279	}
bogdanm	0:9b334a45a8ff	2280	}
bogdanm	0:9b334a45a8ff	2281	}
bogdanm	0:9b334a45a8ff	2282
bogdanm	0:9b334a45a8ff	2283	/**
bogdanm	0:9b334a45a8ff	2284	* @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
bogdanm	0:9b334a45a8ff	2285	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2286	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2287	* @retval None
bogdanm	0:9b334a45a8ff	2288	*/
bogdanm	0:9b334a45a8ff	2289	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2290	{
bogdanm	0:9b334a45a8ff	2291	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2292	__IO uint16_t tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2293	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2294
bogdanm	0:9b334a45a8ff	2295	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	2296	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	2297
bogdanm	0:9b334a45a8ff	2298	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2299	}
bogdanm	0:9b334a45a8ff	2300
bogdanm	0:9b334a45a8ff	2301	/**
bogdanm	0:9b334a45a8ff	2302	* @brief Tx Handler for Transmit and Receive in Interrupt mode
bogdanm	0:9b334a45a8ff	2303	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2304	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2305	* @retval None
bogdanm	0:9b334a45a8ff	2306	*/
bogdanm	0:9b334a45a8ff	2307	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2308	{
bogdanm	0:9b334a45a8ff	2309	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2310	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	2311	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2312	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	2313
bogdanm	0:9b334a45a8ff	2314	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2315	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2316	{
bogdanm	0:9b334a45a8ff	2317	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2318	{
bogdanm	0:9b334a45a8ff	2319	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2320	}
bogdanm	0:9b334a45a8ff	2321	/* Disable TXE interrupt */
bogdanm	0:9b334a45a8ff	2322	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
bogdanm	0:9b334a45a8ff	2323
bogdanm	0:9b334a45a8ff	2324	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2325	{
bogdanm	0:9b334a45a8ff	2326	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2327	}
bogdanm	0:9b334a45a8ff	2328	}
bogdanm	0:9b334a45a8ff	2329	}
bogdanm	0:9b334a45a8ff	2330
bogdanm	0:9b334a45a8ff	2331	/**
bogdanm	0:9b334a45a8ff	2332	* @brief Manage the CRC receive in Interrupt context
bogdanm	0:9b334a45a8ff	2333	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2334	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2335	* @retval None
bogdanm	0:9b334a45a8ff	2336	*/
bogdanm	0:9b334a45a8ff	2337	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2338	{
bogdanm	0:9b334a45a8ff	2339	__IO uint8_t tmpreg;
bogdanm	0:9b334a45a8ff	2340	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2341	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2342
bogdanm	0:9b334a45a8ff	2343	hspi->CRCSize--;
bogdanm	0:9b334a45a8ff	2344
bogdanm	0:9b334a45a8ff	2345	if(hspi->CRCSize == 0)
bogdanm	0:9b334a45a8ff	2346	{
bogdanm	0:9b334a45a8ff	2347	SPI_CloseRx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2348	}
bogdanm	0:9b334a45a8ff	2349	}
bogdanm	0:9b334a45a8ff	2350
bogdanm	0:9b334a45a8ff	2351	/**
bogdanm	0:9b334a45a8ff	2352	* @brief Manage the receive in Interrupt context
bogdanm	0:9b334a45a8ff	2353	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2354	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2355	* @retval None
bogdanm	0:9b334a45a8ff	2356	*/
bogdanm	0:9b334a45a8ff	2357	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2358	{
bogdanm	0:9b334a45a8ff	2359	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2360	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2361
bogdanm	0:9b334a45a8ff	2362	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2363	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	2364	{
bogdanm	0:9b334a45a8ff	2365	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2366	}
bogdanm	0:9b334a45a8ff	2367
bogdanm	0:9b334a45a8ff	2368	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2369	{
bogdanm	0:9b334a45a8ff	2370	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2371	{
bogdanm	0:9b334a45a8ff	2372	hspi->RxISR = SPI_RxISR_8BITCRC;
bogdanm	0:9b334a45a8ff	2373	return;
bogdanm	0:9b334a45a8ff	2374	}
bogdanm	0:9b334a45a8ff	2375	SPI_CloseRx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2376	}
bogdanm	0:9b334a45a8ff	2377	}
bogdanm	0:9b334a45a8ff	2378
bogdanm	0:9b334a45a8ff	2379	/**
bogdanm	0:9b334a45a8ff	2380	* @brief Manage the CRC 16bit receive in Interrupt context
bogdanm	0:9b334a45a8ff	2381	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2382	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2383	* @retval None
bogdanm	0:9b334a45a8ff	2384	*/
bogdanm	0:9b334a45a8ff	2385	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2386	{
bogdanm	0:9b334a45a8ff	2387	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	2388
bogdanm	0:9b334a45a8ff	2389	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2390	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2391
bogdanm	0:9b334a45a8ff	2392	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	2393	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2394
bogdanm	0:9b334a45a8ff	2395	SPI_CloseRx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2396	}
bogdanm	0:9b334a45a8ff	2397
bogdanm	0:9b334a45a8ff	2398	/**
bogdanm	0:9b334a45a8ff	2399	* @brief Manage the 16Bit receive in Interrupt context
bogdanm	0:9b334a45a8ff	2400	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2401	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2402	* @retval None
bogdanm	0:9b334a45a8ff	2403	*/
bogdanm	0:9b334a45a8ff	2404	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2405	{
bogdanm	0:9b334a45a8ff	2406	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2407	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2408	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2409
bogdanm	0:9b334a45a8ff	2410	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2411	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	2412	{
bogdanm	0:9b334a45a8ff	2413	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2414	}
bogdanm	0:9b334a45a8ff	2415
bogdanm	0:9b334a45a8ff	2416	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2417	{
bogdanm	0:9b334a45a8ff	2418	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2419	{
bogdanm	0:9b334a45a8ff	2420	hspi->RxISR = SPI_RxISR_16BITCRC;
bogdanm	0:9b334a45a8ff	2421	return;
bogdanm	0:9b334a45a8ff	2422	}
bogdanm	0:9b334a45a8ff	2423	SPI_CloseRx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2424	}
bogdanm	0:9b334a45a8ff	2425	}
bogdanm	0:9b334a45a8ff	2426
bogdanm	0:9b334a45a8ff	2427	/**
bogdanm	0:9b334a45a8ff	2428	* @brief Handle the data 8Bit transmit in Interrupt mode
bogdanm	0:9b334a45a8ff	2429	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2430	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2431	* @retval None
bogdanm	0:9b334a45a8ff	2432	*/
bogdanm	0:9b334a45a8ff	2433	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2434	{
bogdanm	0:9b334a45a8ff	2435	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	2436	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	2437
bogdanm	0:9b334a45a8ff	2438	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2439	{
bogdanm	0:9b334a45a8ff	2440	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2441	{
bogdanm	0:9b334a45a8ff	2442	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2443	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2444	}
bogdanm	0:9b334a45a8ff	2445	SPI_CloseTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2446	}
bogdanm	0:9b334a45a8ff	2447	}
bogdanm	0:9b334a45a8ff	2448
bogdanm	0:9b334a45a8ff	2449	/**
bogdanm	0:9b334a45a8ff	2450	* @brief Handle the data 16Bit transmit in Interrupt mode
bogdanm	0:9b334a45a8ff	2451	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2452	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2453	* @retval None
bogdanm	0:9b334a45a8ff	2454	*/
bogdanm	0:9b334a45a8ff	2455	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2456	{
bogdanm	0:9b334a45a8ff	2457	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2458	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	2459	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2460	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	2461
bogdanm	0:9b334a45a8ff	2462	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2463	{
bogdanm	0:9b334a45a8ff	2464	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2465	{
bogdanm	0:9b334a45a8ff	2466	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2467	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2468	}
bogdanm	0:9b334a45a8ff	2469	SPI_CloseTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2470	}
bogdanm	0:9b334a45a8ff	2471	}
bogdanm	0:9b334a45a8ff	2472
bogdanm	0:9b334a45a8ff	2473	/**
bogdanm	0:9b334a45a8ff	2474	* @brief This function handles SPI Communication Timeout.
bogdanm	0:9b334a45a8ff	2475	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2476	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2477	* @param Flag : SPI flag to check
bogdanm	0:9b334a45a8ff	2478	* @param State : flag state to check
bogdanm	0:9b334a45a8ff	2479	* @param Timeout : Timeout duration
bogdanm	0:9b334a45a8ff	2480	* @retval HAL status
bogdanm	0:9b334a45a8ff	2481	*/
bogdanm	0:9b334a45a8ff	2482	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2483	{
bogdanm	0:9b334a45a8ff	2484	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2485
bogdanm	0:9b334a45a8ff	2486	while((hspi->Instance->SR & Flag) != State)
bogdanm	0:9b334a45a8ff	2487	{
bogdanm	0:9b334a45a8ff	2488	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2489	{
bogdanm	0:9b334a45a8ff	2490	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) >= Timeout))
bogdanm	0:9b334a45a8ff	2491	{
bogdanm	0:9b334a45a8ff	2492	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2493	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2494	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2495
bogdanm	0:9b334a45a8ff	2496	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2497	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2498
bogdanm	0:9b334a45a8ff	2499	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2500	{
bogdanm	0:9b334a45a8ff	2501	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2502	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2503	}
bogdanm	0:9b334a45a8ff	2504
bogdanm	0:9b334a45a8ff	2505	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2506	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2507	{
bogdanm	0:9b334a45a8ff	2508	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2509	}
bogdanm	0:9b334a45a8ff	2510
bogdanm	0:9b334a45a8ff	2511	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2512
bogdanm	0:9b334a45a8ff	2513	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2514	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2515
bogdanm	0:9b334a45a8ff	2516	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2517	}
bogdanm	0:9b334a45a8ff	2518	}
bogdanm	0:9b334a45a8ff	2519	}
bogdanm	0:9b334a45a8ff	2520
bogdanm	0:9b334a45a8ff	2521	return HAL_OK;
bogdanm	0:9b334a45a8ff	2522	}
bogdanm	0:9b334a45a8ff	2523
bogdanm	0:9b334a45a8ff	2524	/**
bogdanm	0:9b334a45a8ff	2525	* @brief This function handles SPI Communication Timeout.
bogdanm	0:9b334a45a8ff	2526	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2527	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2528	* @param Fifo : Fifo to check
bogdanm	0:9b334a45a8ff	2529	* @param State : Fifo state to check
bogdanm	0:9b334a45a8ff	2530	* @param Timeout : Timeout duration
bogdanm	0:9b334a45a8ff	2531	* @retval HAL status
bogdanm	0:9b334a45a8ff	2532	*/
bogdanm	0:9b334a45a8ff	2533	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2534	{
bogdanm	0:9b334a45a8ff	2535	__IO uint8_t tmpreg;
bogdanm	0:9b334a45a8ff	2536	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2537
bogdanm	0:9b334a45a8ff	2538	while((hspi->Instance->SR & Fifo) != State)
bogdanm	0:9b334a45a8ff	2539	{
bogdanm	0:9b334a45a8ff	2540	if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
bogdanm	0:9b334a45a8ff	2541	{
bogdanm	0:9b334a45a8ff	2542	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2543	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2544	}
bogdanm	0:9b334a45a8ff	2545
bogdanm	0:9b334a45a8ff	2546	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2547	{
bogdanm	0:9b334a45a8ff	2548	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) >= Timeout))
bogdanm	0:9b334a45a8ff	2549	{
bogdanm	0:9b334a45a8ff	2550	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2551	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2552	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2553
bogdanm	0:9b334a45a8ff	2554	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2555	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2556
bogdanm	0:9b334a45a8ff	2557	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2558	{
bogdanm	0:9b334a45a8ff	2559	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2560	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2561	}
bogdanm	0:9b334a45a8ff	2562
bogdanm	0:9b334a45a8ff	2563	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2564	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2565	{
bogdanm	0:9b334a45a8ff	2566	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2567	}
bogdanm	0:9b334a45a8ff	2568
bogdanm	0:9b334a45a8ff	2569	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2570
bogdanm	0:9b334a45a8ff	2571	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2572	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2573
bogdanm	0:9b334a45a8ff	2574	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2575	}
bogdanm	0:9b334a45a8ff	2576	}
bogdanm	0:9b334a45a8ff	2577	}
bogdanm	0:9b334a45a8ff	2578
bogdanm	0:9b334a45a8ff	2579	return HAL_OK;
bogdanm	0:9b334a45a8ff	2580	}
bogdanm	0:9b334a45a8ff	2581
bogdanm	0:9b334a45a8ff	2582	/**
bogdanm	0:9b334a45a8ff	2583	* @brief This function handles the check of the RX transaction complete.
bogdanm	0:9b334a45a8ff	2584	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2585	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2586	* @param Timeout : Timeout duration
bogdanm	0:9b334a45a8ff	2587	* @retval None
bogdanm	0:9b334a45a8ff	2588	*/
bogdanm	0:9b334a45a8ff	2589	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2590	{
bogdanm	0:9b334a45a8ff	2591	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2592	{
bogdanm	0:9b334a45a8ff	2593	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2594	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2595	}
bogdanm	0:9b334a45a8ff	2596	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2597	{
bogdanm	0:9b334a45a8ff	2598	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2599	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2600	}
bogdanm	0:9b334a45a8ff	2601	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2602	{
bogdanm	0:9b334a45a8ff	2603	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2604	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2605	}
bogdanm	0:9b334a45a8ff	2606
bogdanm	0:9b334a45a8ff	2607	return HAL_OK;
bogdanm	0:9b334a45a8ff	2608	}
bogdanm	0:9b334a45a8ff	2609
bogdanm	0:9b334a45a8ff	2610	/**
bogdanm	0:9b334a45a8ff	2611	* @brief This function handles the check of the RXTX or TX transaction complete.
bogdanm	0:9b334a45a8ff	2612	* @param hspi: SPI handle
bogdanm	0:9b334a45a8ff	2613	* @param Timeout : Timeout duration
bogdanm	0:9b334a45a8ff	2614	*/
bogdanm	0:9b334a45a8ff	2615	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2616	{
bogdanm	0:9b334a45a8ff	2617	/* Procedure to check the transaction complete */
bogdanm	0:9b334a45a8ff	2618	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2619	{
bogdanm	0:9b334a45a8ff	2620	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2621	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2622	}
bogdanm	0:9b334a45a8ff	2623	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2624	{
bogdanm	0:9b334a45a8ff	2625	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2626	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2627	}
bogdanm	0:9b334a45a8ff	2628	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2629	{
bogdanm	0:9b334a45a8ff	2630	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2631	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2632	}
bogdanm	0:9b334a45a8ff	2633	return HAL_OK;
bogdanm	0:9b334a45a8ff	2634	}
bogdanm	0:9b334a45a8ff	2635
bogdanm	0:9b334a45a8ff	2636	/**
bogdanm	0:9b334a45a8ff	2637	* @brief This function handles the close of the RXTX transaction.
bogdanm	0:9b334a45a8ff	2638	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2639	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2640	* @retval None
bogdanm	0:9b334a45a8ff	2641	*/
bogdanm	0:9b334a45a8ff	2642	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2643	{
bogdanm	0:9b334a45a8ff	2644	/* Disable ERR interrupt */
bogdanm	0:9b334a45a8ff	2645	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
bogdanm	0:9b334a45a8ff	2646
bogdanm	0:9b334a45a8ff	2647	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2648	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2649	{
bogdanm	0:9b334a45a8ff	2650	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2651	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2652	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2653	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2654	}
bogdanm	0:9b334a45a8ff	2655	else
bogdanm	0:9b334a45a8ff	2656	{
bogdanm	0:9b334a45a8ff	2657	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2658	{
bogdanm	0:9b334a45a8ff	2659	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	2660	{
bogdanm	0:9b334a45a8ff	2661	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2662	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2663	}
bogdanm	0:9b334a45a8ff	2664	else
bogdanm	0:9b334a45a8ff	2665	{
bogdanm	0:9b334a45a8ff	2666	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2667	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2668	}
bogdanm	0:9b334a45a8ff	2669	}
bogdanm	0:9b334a45a8ff	2670	else
bogdanm	0:9b334a45a8ff	2671	{
bogdanm	0:9b334a45a8ff	2672	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2673	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2674	}
bogdanm	0:9b334a45a8ff	2675	}
bogdanm	0:9b334a45a8ff	2676	}
bogdanm	0:9b334a45a8ff	2677
bogdanm	0:9b334a45a8ff	2678	/**
bogdanm	0:9b334a45a8ff	2679	* @brief This function handles the close of the RX transaction.
bogdanm	0:9b334a45a8ff	2680	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2681	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2682	* @retval None
bogdanm	0:9b334a45a8ff	2683	*/
bogdanm	0:9b334a45a8ff	2684	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2685	{
bogdanm	0:9b334a45a8ff	2686	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	2687	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2688
bogdanm	0:9b334a45a8ff	2689	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	2690	SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
bogdanm	0:9b334a45a8ff	2691
bogdanm	0:9b334a45a8ff	2692	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2693
bogdanm	0:9b334a45a8ff	2694	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2695	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2696	{
bogdanm	0:9b334a45a8ff	2697	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2698	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2699	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2700	}
bogdanm	0:9b334a45a8ff	2701	else
bogdanm	0:9b334a45a8ff	2702	{
bogdanm	0:9b334a45a8ff	2703	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2704	{
bogdanm	0:9b334a45a8ff	2705	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2706	}
bogdanm	0:9b334a45a8ff	2707	else
bogdanm	0:9b334a45a8ff	2708	{
bogdanm	0:9b334a45a8ff	2709	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2710	}
bogdanm	0:9b334a45a8ff	2711	}
bogdanm	0:9b334a45a8ff	2712	}
bogdanm	0:9b334a45a8ff	2713
bogdanm	0:9b334a45a8ff	2714	/**
bogdanm	0:9b334a45a8ff	2715	* @brief This function handles the close of the TX transaction.
bogdanm	0:9b334a45a8ff	2716	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2717	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2718	* @retval None
bogdanm	0:9b334a45a8ff	2719	*/
bogdanm	0:9b334a45a8ff	2720	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2721	{
bogdanm	0:9b334a45a8ff	2722	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	2723	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2724
bogdanm	0:9b334a45a8ff	2725	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	2726	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	2727	{
bogdanm	0:9b334a45a8ff	2728	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2729	}
bogdanm	0:9b334a45a8ff	2730
bogdanm	0:9b334a45a8ff	2731	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2732	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2733	{
bogdanm	0:9b334a45a8ff	2734	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2735	}
bogdanm	0:9b334a45a8ff	2736	else
bogdanm	0:9b334a45a8ff	2737	{
bogdanm	0:9b334a45a8ff	2738	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2739	}
bogdanm	0:9b334a45a8ff	2740	}
bogdanm	0:9b334a45a8ff	2741
bogdanm	0:9b334a45a8ff	2742	/**
bogdanm	0:9b334a45a8ff	2743	* @}
bogdanm	0:9b334a45a8ff	2744	*/
bogdanm	0:9b334a45a8ff	2745
bogdanm	0:9b334a45a8ff	2746	#endif /* HAL_SPI_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2747	/**
bogdanm	0:9b334a45a8ff	2748	* @}
bogdanm	0:9b334a45a8ff	2749	*/
bogdanm	0:9b334a45a8ff	2750
bogdanm	0:9b334a45a8ff	2751	/**
bogdanm	0:9b334a45a8ff	2752	* @}
bogdanm	0:9b334a45a8ff	2753	*/
bogdanm	0:9b334a45a8ff	2754
bogdanm	0:9b334a45a8ff	2755	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c@83:a036322b8637, 2016-03-07 (annotated)

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