en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
34:bb6061527455
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f3xx_hal_rcc.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.1.0
bogdanm 0:9b334a45a8ff 6 * @date 12-Sept-2014
bogdanm 0:9b334a45a8ff 7 * @brief Header file of RCC HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32F3xx_HAL_RCC_H
bogdanm 0:9b334a45a8ff 40 #define __STM32F3xx_HAL_RCC_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32f3xx_hal_def.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @addtogroup RCC
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Exported types ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /** @defgroup RCC_Exported_Types RCC Exported Types
bogdanm 0:9b334a45a8ff 60 * @{
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /**
bogdanm 0:9b334a45a8ff 64 * @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm 0:9b334a45a8ff 65 */
bogdanm 0:9b334a45a8ff 66 typedef struct
bogdanm 0:9b334a45a8ff 67 {
bogdanm 0:9b334a45a8ff 68 uint32_t ClockType; /*!< The clock to be configured.
bogdanm 0:9b334a45a8ff 69 This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm 0:9b334a45a8ff 72 This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm 0:9b334a45a8ff 75 This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 0:9b334a45a8ff 78 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 0:9b334a45a8ff 81 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 }RCC_ClkInitTypeDef;
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /**
bogdanm 0:9b334a45a8ff 86 * @}
bogdanm 0:9b334a45a8ff 87 */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 90 /** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm 0:9b334a45a8ff 91 * @{
bogdanm 0:9b334a45a8ff 92 */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
bogdanm 0:9b334a45a8ff 95 * @brief RCC registers bit address in the alias region
bogdanm 0:9b334a45a8ff 96 * @{
bogdanm 0:9b334a45a8ff 97 */
bogdanm 0:9b334a45a8ff 98 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm 0:9b334a45a8ff 99 /* --- CR Register ---*/
bogdanm 0:9b334a45a8ff 100 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
bogdanm 0:9b334a45a8ff 101 /* Alias word address of HSION bit */
bogdanm 0:9b334a45a8ff 102 #define HSION_BitNumber 0
bogdanm 0:9b334a45a8ff 103 #define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
bogdanm 0:9b334a45a8ff 104 /* Alias word address of HSEON bit */
bogdanm 0:9b334a45a8ff 105 #define HSEON_BitNumber 16
bogdanm 0:9b334a45a8ff 106 #define CR_HSEON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSEON_BitNumber * 4))
bogdanm 0:9b334a45a8ff 107 /* Alias word address of CSSON bit */
bogdanm 0:9b334a45a8ff 108 #define CSSON_BitNumber 19
bogdanm 0:9b334a45a8ff 109 #define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
bogdanm 0:9b334a45a8ff 110 /* Alias word address of PLLON bit */
bogdanm 0:9b334a45a8ff 111 #define PLLON_BitNumber 24
bogdanm 0:9b334a45a8ff 112 #define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /* --- CFGR Register ---*/
bogdanm 0:9b334a45a8ff 115 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
bogdanm 0:9b334a45a8ff 116 /* Alias word address of PLLSRC bit */
bogdanm 0:9b334a45a8ff 117 #define PLLSRC_BitNumber 16
bogdanm 0:9b334a45a8ff 118 #define CFGR_PLLSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (PLLSRC_BitNumber * 4))
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 /* --- CIR Register ---*/
bogdanm 0:9b334a45a8ff 121 #define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 /* --- BDCR Register ---*/
bogdanm 0:9b334a45a8ff 124 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
bogdanm 0:9b334a45a8ff 125 /* Alias word address of LSEON bit */
bogdanm 0:9b334a45a8ff 126 #define LSEON_BitNumber 0
bogdanm 0:9b334a45a8ff 127 #define BDCR_LSEON_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (LSEON_BitNumber * 4))
bogdanm 0:9b334a45a8ff 128 /* Alias word address of RTCEN bit */
bogdanm 0:9b334a45a8ff 129 #define RTCEN_BitNumber 15
bogdanm 0:9b334a45a8ff 130 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
bogdanm 0:9b334a45a8ff 131 /* Alias word address of BDRST bit */
bogdanm 0:9b334a45a8ff 132 #define BDRST_BitNumber 16
bogdanm 0:9b334a45a8ff 133 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /* --- CSR Register ---*/
bogdanm 0:9b334a45a8ff 136 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
bogdanm 0:9b334a45a8ff 137 /* Alias word address of LSION bit */
bogdanm 0:9b334a45a8ff 138 #define LSION_BitNumber 0
bogdanm 0:9b334a45a8ff 139 #define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
bogdanm 0:9b334a45a8ff 140 /* Alias word address of RMVF bit */
bogdanm 0:9b334a45a8ff 141 #define RMVF_BitNumber 24
bogdanm 0:9b334a45a8ff 142 #define CSR_RMVF_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RMVF_BitNumber * 4))
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 /* CR register byte 2 (Bits[23:16]) base address */
bogdanm 0:9b334a45a8ff 145 #define CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /* CIR register byte 1 (Bits[15:8]) base address */
bogdanm 0:9b334a45a8ff 148 #define CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 /* CIR register byte 2 (Bits[23:16]) base address */
bogdanm 0:9b334a45a8ff 151 #define CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 /* CSR register byte 1 (Bits[15:8]) base address */
bogdanm 0:9b334a45a8ff 154 #define CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /* BDCR register byte 0 (Bits[7:0] base address */
bogdanm 0:9b334a45a8ff 157 #define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 /**
bogdanm 0:9b334a45a8ff 160 * @}
bogdanm 0:9b334a45a8ff 161 */
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 /** @defgroup RCC_Timeout RCC Timeout
bogdanm 0:9b334a45a8ff 164 * @{
bogdanm 0:9b334a45a8ff 165 */
bogdanm 0:9b334a45a8ff 166 /* LSE state change timeout */
bogdanm 0:9b334a45a8ff 167 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 /* Disable Backup domain write protection state change timeout */
bogdanm 0:9b334a45a8ff 170 #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm 0:9b334a45a8ff 171 /**
bogdanm 0:9b334a45a8ff 172 * @}
bogdanm 0:9b334a45a8ff 173 */
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 /** @defgroup RCC_Oscillator_Type RCC Oscillator Type
bogdanm 0:9b334a45a8ff 176 * @{
bogdanm 0:9b334a45a8ff 177 */
bogdanm 0:9b334a45a8ff 178 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 179 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 180 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 181 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 182 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
bogdanm 0:9b334a45a8ff 185 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
bogdanm 0:9b334a45a8ff 186 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
bogdanm 0:9b334a45a8ff 187 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
bogdanm 0:9b334a45a8ff 188 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
bogdanm 0:9b334a45a8ff 189 /**
bogdanm 0:9b334a45a8ff 190 * @}
bogdanm 0:9b334a45a8ff 191 */
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 /** @defgroup RCC_HSE_Config RCC HSE Config
bogdanm 0:9b334a45a8ff 194 * @{
bogdanm 0:9b334a45a8ff 195 */
bogdanm 0:9b334a45a8ff 196 #define RCC_HSE_OFF ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 197 #define RCC_HSE_ON ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 198 #define RCC_HSE_BYPASS ((uint32_t)0x00000005)
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
bogdanm 0:9b334a45a8ff 201 ((HSE) == RCC_HSE_BYPASS))
bogdanm 0:9b334a45a8ff 202 /**
bogdanm 0:9b334a45a8ff 203 * @}
bogdanm 0:9b334a45a8ff 204 */
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /** @defgroup RCC_LSE_Config RCC_LSE_Config
bogdanm 0:9b334a45a8ff 207 * @{
bogdanm 0:9b334a45a8ff 208 */
bogdanm 0:9b334a45a8ff 209 #define RCC_LSE_OFF ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 210 #define RCC_LSE_ON ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 211 #define RCC_LSE_BYPASS ((uint32_t)0x00000005)
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
bogdanm 0:9b334a45a8ff 214 ((LSE) == RCC_LSE_BYPASS))
bogdanm 0:9b334a45a8ff 215 /**
bogdanm 0:9b334a45a8ff 216 * @}
bogdanm 0:9b334a45a8ff 217 */
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 /** @defgroup RCC_HSI_Config RCC HSI Config
bogdanm 0:9b334a45a8ff 220 * @{
bogdanm 0:9b334a45a8ff 221 */
bogdanm 0:9b334a45a8ff 222 #define RCC_HSI_OFF ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 223 #define RCC_HSI_ON ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
bogdanm 0:9b334a45a8ff 230 /**
bogdanm 0:9b334a45a8ff 231 * @}
bogdanm 0:9b334a45a8ff 232 */
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 /** @defgroup RCC_LSI_Config RCC LSI Config
bogdanm 0:9b334a45a8ff 235 * @{
bogdanm 0:9b334a45a8ff 236 */
bogdanm 0:9b334a45a8ff 237 #define RCC_LSI_OFF ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 238 #define RCC_LSI_ON ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
bogdanm 0:9b334a45a8ff 241 /**
bogdanm 0:9b334a45a8ff 242 * @}
bogdanm 0:9b334a45a8ff 243 */
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 /** @defgroup RCC_PLL_Config RCC PLL Config
bogdanm 0:9b334a45a8ff 246 * @{
bogdanm 0:9b334a45a8ff 247 */
bogdanm 0:9b334a45a8ff 248 #define RCC_PLL_NONE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 249 #define RCC_PLL_OFF ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 250 #define RCC_PLL_ON ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
bogdanm 0:9b334a45a8ff 253 /**
bogdanm 0:9b334a45a8ff 254 * @}
bogdanm 0:9b334a45a8ff 255 */
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
bogdanm 0:9b334a45a8ff 258 * @{
bogdanm 0:9b334a45a8ff 259 */
bogdanm 0:9b334a45a8ff 260 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
bogdanm 0:9b334a45a8ff 261 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
bogdanm 0:9b334a45a8ff 262 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
bogdanm 0:9b334a45a8ff 263 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
bogdanm 0:9b334a45a8ff 264 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
bogdanm 0:9b334a45a8ff 265 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
bogdanm 0:9b334a45a8ff 266 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
bogdanm 0:9b334a45a8ff 267 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
bogdanm 0:9b334a45a8ff 268 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
bogdanm 0:9b334a45a8ff 269 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
bogdanm 0:9b334a45a8ff 270 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
bogdanm 0:9b334a45a8ff 271 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
bogdanm 0:9b334a45a8ff 272 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
bogdanm 0:9b334a45a8ff 273 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
bogdanm 0:9b334a45a8ff 274 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \
bogdanm 0:9b334a45a8ff 277 ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \
bogdanm 0:9b334a45a8ff 278 ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \
bogdanm 0:9b334a45a8ff 279 ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \
bogdanm 0:9b334a45a8ff 280 ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \
bogdanm 0:9b334a45a8ff 281 ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \
bogdanm 0:9b334a45a8ff 282 ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \
bogdanm 0:9b334a45a8ff 283 ((MUL) == RCC_PLL_MUL16))
bogdanm 0:9b334a45a8ff 284 /**
bogdanm 0:9b334a45a8ff 285 * @}
bogdanm 0:9b334a45a8ff 286 */
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
bogdanm 0:9b334a45a8ff 289 * @{
bogdanm 0:9b334a45a8ff 290 */
bogdanm 0:9b334a45a8ff 291 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 292 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 293 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 294 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
bogdanm 0:9b334a45a8ff 297 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
bogdanm 0:9b334a45a8ff 298 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
bogdanm 0:9b334a45a8ff 299 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
bogdanm 0:9b334a45a8ff 300 /**
bogdanm 0:9b334a45a8ff 301 * @}
bogdanm 0:9b334a45a8ff 302 */
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
bogdanm 0:9b334a45a8ff 305 * @{
bogdanm 0:9b334a45a8ff 306 */
bogdanm 0:9b334a45a8ff 307 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm 0:9b334a45a8ff 308 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm 0:9b334a45a8ff 309 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
bogdanm 0:9b334a45a8ff 312 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
bogdanm 0:9b334a45a8ff 313 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm 0:9b334a45a8ff 314 /**
bogdanm 0:9b334a45a8ff 315 * @}
bogdanm 0:9b334a45a8ff 316 */
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 /** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
bogdanm 0:9b334a45a8ff 319 * @{
bogdanm 0:9b334a45a8ff 320 */
bogdanm 0:9b334a45a8ff 321 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
bogdanm 0:9b334a45a8ff 322 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
bogdanm 0:9b334a45a8ff 323 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
bogdanm 0:9b334a45a8ff 326 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
bogdanm 0:9b334a45a8ff 327 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)))
bogdanm 0:9b334a45a8ff 328 /**
bogdanm 0:9b334a45a8ff 329 * @}
bogdanm 0:9b334a45a8ff 330 */
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
bogdanm 0:9b334a45a8ff 333 * @{
bogdanm 0:9b334a45a8ff 334 */
bogdanm 0:9b334a45a8ff 335 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm 0:9b334a45a8ff 336 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm 0:9b334a45a8ff 337 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm 0:9b334a45a8ff 338 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm 0:9b334a45a8ff 339 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm 0:9b334a45a8ff 340 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm 0:9b334a45a8ff 341 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm 0:9b334a45a8ff 342 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm 0:9b334a45a8ff 343 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 #define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \
bogdanm 0:9b334a45a8ff 346 ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \
bogdanm 0:9b334a45a8ff 347 ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \
bogdanm 0:9b334a45a8ff 348 ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \
bogdanm 0:9b334a45a8ff 349 ((DIV) == RCC_SYSCLK_DIV512))
bogdanm 0:9b334a45a8ff 350 /**
bogdanm 0:9b334a45a8ff 351 * @}
bogdanm 0:9b334a45a8ff 352 */
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
bogdanm 0:9b334a45a8ff 355 * @{
bogdanm 0:9b334a45a8ff 356 */
bogdanm 0:9b334a45a8ff 357 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
bogdanm 0:9b334a45a8ff 358 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
bogdanm 0:9b334a45a8ff 359 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
bogdanm 0:9b334a45a8ff 360 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
bogdanm 0:9b334a45a8ff 361 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 #define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \
bogdanm 0:9b334a45a8ff 364 ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \
bogdanm 0:9b334a45a8ff 365 ((DIV) == RCC_HCLK_DIV16))
bogdanm 0:9b334a45a8ff 366 /**
bogdanm 0:9b334a45a8ff 367 * @}
bogdanm 0:9b334a45a8ff 368 */
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
bogdanm 0:9b334a45a8ff 371 * @{
bogdanm 0:9b334a45a8ff 372 */
bogdanm 0:9b334a45a8ff 373 #define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
bogdanm 0:9b334a45a8ff 374 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
bogdanm 0:9b334a45a8ff 375 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
bogdanm 0:9b334a45a8ff 376 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \
bogdanm 0:9b334a45a8ff 379 ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
bogdanm 0:9b334a45a8ff 380 ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
bogdanm 0:9b334a45a8ff 381 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
bogdanm 0:9b334a45a8ff 382 /**
bogdanm 0:9b334a45a8ff 383 * @}
bogdanm 0:9b334a45a8ff 384 */
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 /** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
bogdanm 0:9b334a45a8ff 387 * @{
bogdanm 0:9b334a45a8ff 388 */
bogdanm 0:9b334a45a8ff 389 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
bogdanm 0:9b334a45a8ff 390 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
bogdanm 0:9b334a45a8ff 391 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
bogdanm 0:9b334a45a8ff 392 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
bogdanm 0:9b334a45a8ff 395 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
bogdanm 0:9b334a45a8ff 396 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
bogdanm 0:9b334a45a8ff 397 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
bogdanm 0:9b334a45a8ff 398 /**
bogdanm 0:9b334a45a8ff 399 * @}
bogdanm 0:9b334a45a8ff 400 */
bogdanm 0:9b334a45a8ff 401
bogdanm 0:9b334a45a8ff 402 /** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
bogdanm 0:9b334a45a8ff 403 * @{
bogdanm 0:9b334a45a8ff 404 */
bogdanm 0:9b334a45a8ff 405 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
bogdanm 0:9b334a45a8ff 406 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
bogdanm 0:9b334a45a8ff 407 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
bogdanm 0:9b334a45a8ff 408 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
bogdanm 0:9b334a45a8ff 411 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
bogdanm 0:9b334a45a8ff 412 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
bogdanm 0:9b334a45a8ff 413 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
bogdanm 0:9b334a45a8ff 414 /**
bogdanm 0:9b334a45a8ff 415 * @}
bogdanm 0:9b334a45a8ff 416 */
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
bogdanm 0:9b334a45a8ff 419 * @{
bogdanm 0:9b334a45a8ff 420 */
bogdanm 0:9b334a45a8ff 421 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
bogdanm 0:9b334a45a8ff 422 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
bogdanm 0:9b334a45a8ff 425 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
bogdanm 0:9b334a45a8ff 426 /**
bogdanm 0:9b334a45a8ff 427 * @}
bogdanm 0:9b334a45a8ff 428 */
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 /** @defgroup RCC_MCOx_Index RCC MCOx Index
bogdanm 0:9b334a45a8ff 431 * @{
bogdanm 0:9b334a45a8ff 432 */
bogdanm 0:9b334a45a8ff 433 #define RCC_MCO ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 #define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
bogdanm 0:9b334a45a8ff 436 /**
bogdanm 0:9b334a45a8ff 437 * @}
bogdanm 0:9b334a45a8ff 438 */
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 /** @defgroup RCC_Interrupt RCC Interrupt
bogdanm 0:9b334a45a8ff 441 * @{
bogdanm 0:9b334a45a8ff 442 */
bogdanm 0:9b334a45a8ff 443 #define RCC_IT_LSIRDY ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 444 #define RCC_IT_LSERDY ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 445 #define RCC_IT_HSIRDY ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 446 #define RCC_IT_HSERDY ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 447 #define RCC_IT_PLLRDY ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 448 #define RCC_IT_CSS ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 449 /**
bogdanm 0:9b334a45a8ff 450 * @}
bogdanm 0:9b334a45a8ff 451 */
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /** @defgroup RCC_Flag RCC Flag
bogdanm 0:9b334a45a8ff 454 * Elements values convention: 0XXYYYYYb
bogdanm 0:9b334a45a8ff 455 * - YYYYY : Flag position in the register
bogdanm 0:9b334a45a8ff 456 * - XX : Register index
bogdanm 0:9b334a45a8ff 457 * - 01: CR register
bogdanm 0:9b334a45a8ff 458 * - 10: BDCR register
bogdanm 0:9b334a45a8ff 459 * - 11: CSR register
bogdanm 0:9b334a45a8ff 460 * @{
bogdanm 0:9b334a45a8ff 461 */
bogdanm 0:9b334a45a8ff 462 #define CR_REG_INDEX 1U
bogdanm 0:9b334a45a8ff 463 #define BDCR_REG_INDEX 2U
bogdanm 0:9b334a45a8ff 464 #define CSR_REG_INDEX 3U
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /* Flags in the CR register */
bogdanm 0:9b334a45a8ff 467 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_HSIRDY))))
bogdanm 0:9b334a45a8ff 468 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_HSERDY))))
bogdanm 0:9b334a45a8ff 469 #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_PLLRDY))))
bogdanm 0:9b334a45a8ff 470
bogdanm 0:9b334a45a8ff 471 /* Flags in the BDCR register */
bogdanm 0:9b334a45a8ff 472 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_BDCR_LSERDY))))
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 /* Flags in the CSR register */
bogdanm 0:9b334a45a8ff 475 #define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_LSIRDY))))
bogdanm 0:9b334a45a8ff 476 #define RCC_FLAG_RMV ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_RMVF))))
bogdanm 0:9b334a45a8ff 477 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_OBLRSTF))))
bogdanm 0:9b334a45a8ff 478 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_PINRSTF))))
bogdanm 0:9b334a45a8ff 479 #define RCC_FLAG_PORRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_PORRSTF))))
bogdanm 0:9b334a45a8ff 480 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_SFTRSTF))))
bogdanm 0:9b334a45a8ff 481 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_IWDGRSTF))))
bogdanm 0:9b334a45a8ff 482 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_WWDGRSTF))))
bogdanm 0:9b334a45a8ff 483 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_LPWRRSTF))))
bogdanm 0:9b334a45a8ff 484 /**
bogdanm 0:9b334a45a8ff 485 * @}
bogdanm 0:9b334a45a8ff 486 */
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 /**
bogdanm 0:9b334a45a8ff 489 * @}
bogdanm 0:9b334a45a8ff 490 */
bogdanm 0:9b334a45a8ff 491 /* Exported macro ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 492
bogdanm 0:9b334a45a8ff 493 /** @defgroup RCC_Exported_Macros RCC Exported Macros
bogdanm 0:9b334a45a8ff 494 * @{
bogdanm 0:9b334a45a8ff 495 */
bogdanm 0:9b334a45a8ff 496
bogdanm 0:9b334a45a8ff 497 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
bogdanm 0:9b334a45a8ff 498 * @brief Enable or disable the AHB peripheral clock.
bogdanm 0:9b334a45a8ff 499 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 500 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 501 * using it.
bogdanm 0:9b334a45a8ff 502 * @{
bogdanm 0:9b334a45a8ff 503 */
bogdanm 0:9b334a45a8ff 504 #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
bogdanm 0:9b334a45a8ff 505 #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
bogdanm 0:9b334a45a8ff 506 #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
bogdanm 0:9b334a45a8ff 507 #define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
bogdanm 0:9b334a45a8ff 508 #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
bogdanm 0:9b334a45a8ff 509 #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
bogdanm 0:9b334a45a8ff 510 #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
bogdanm 0:9b334a45a8ff 511 #define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN))
bogdanm 0:9b334a45a8ff 512 #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
bogdanm 0:9b334a45a8ff 513 #define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
bogdanm 0:9b334a45a8ff 514
bogdanm 0:9b334a45a8ff 515 #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
bogdanm 0:9b334a45a8ff 516 #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
bogdanm 0:9b334a45a8ff 517 #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
bogdanm 0:9b334a45a8ff 518 #define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
bogdanm 0:9b334a45a8ff 519 #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
bogdanm 0:9b334a45a8ff 520 #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
bogdanm 0:9b334a45a8ff 521 #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
bogdanm 0:9b334a45a8ff 522 #define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
bogdanm 0:9b334a45a8ff 523 #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
bogdanm 0:9b334a45a8ff 524 #define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
bogdanm 0:9b334a45a8ff 525 /**
bogdanm 0:9b334a45a8ff 526 * @}
bogdanm 0:9b334a45a8ff 527 */
bogdanm 0:9b334a45a8ff 528
bogdanm 0:9b334a45a8ff 529 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
bogdanm 0:9b334a45a8ff 530 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 0:9b334a45a8ff 531 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 532 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 533 * using it.
bogdanm 0:9b334a45a8ff 534 * @{
bogdanm 0:9b334a45a8ff 535 */
bogdanm 0:9b334a45a8ff 536 #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
bogdanm 0:9b334a45a8ff 537 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
bogdanm 0:9b334a45a8ff 538 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
bogdanm 0:9b334a45a8ff 539 #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
bogdanm 0:9b334a45a8ff 540 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
bogdanm 0:9b334a45a8ff 541 #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
bogdanm 0:9b334a45a8ff 542 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
bogdanm 0:9b334a45a8ff 543 #define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC1EN))
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm 0:9b334a45a8ff 546 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm 0:9b334a45a8ff 547 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm 0:9b334a45a8ff 548 #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm 0:9b334a45a8ff 549 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm 0:9b334a45a8ff 550 #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
bogdanm 0:9b334a45a8ff 551 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm 0:9b334a45a8ff 552 #define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
bogdanm 0:9b334a45a8ff 553 /**
bogdanm 0:9b334a45a8ff 554 * @}
bogdanm 0:9b334a45a8ff 555 */
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
bogdanm 0:9b334a45a8ff 558 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 0:9b334a45a8ff 559 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 560 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 561 * using it.
bogdanm 0:9b334a45a8ff 562 * @{
bogdanm 0:9b334a45a8ff 563 */
bogdanm 0:9b334a45a8ff 564 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
bogdanm 0:9b334a45a8ff 565 #define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
bogdanm 0:9b334a45a8ff 566 #define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN))
bogdanm 0:9b334a45a8ff 567 #define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN))
bogdanm 0:9b334a45a8ff 568 #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
bogdanm 0:9b334a45a8ff 569
bogdanm 0:9b334a45a8ff 570 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
bogdanm 0:9b334a45a8ff 571 #define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
bogdanm 0:9b334a45a8ff 572 #define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
bogdanm 0:9b334a45a8ff 573 #define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
bogdanm 0:9b334a45a8ff 574 #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
bogdanm 0:9b334a45a8ff 575 /**
bogdanm 0:9b334a45a8ff 576 * @}
bogdanm 0:9b334a45a8ff 577 */
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
bogdanm 0:9b334a45a8ff 580 * @brief Force or release AHB peripheral reset.
bogdanm 0:9b334a45a8ff 581 * @{
bogdanm 0:9b334a45a8ff 582 */
bogdanm 0:9b334a45a8ff 583 #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 584 #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
bogdanm 0:9b334a45a8ff 585 #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
bogdanm 0:9b334a45a8ff 586 #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
bogdanm 0:9b334a45a8ff 587 #define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
bogdanm 0:9b334a45a8ff 588 #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
bogdanm 0:9b334a45a8ff 589 #define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
bogdanm 0:9b334a45a8ff 592 #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
bogdanm 0:9b334a45a8ff 593 #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
bogdanm 0:9b334a45a8ff 594 #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
bogdanm 0:9b334a45a8ff 595 #define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
bogdanm 0:9b334a45a8ff 596 #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
bogdanm 0:9b334a45a8ff 597 #define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
bogdanm 0:9b334a45a8ff 598 /**
bogdanm 0:9b334a45a8ff 599 * @}
bogdanm 0:9b334a45a8ff 600 */
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
bogdanm 0:9b334a45a8ff 603 * @brief Force or release APB1 peripheral reset.
bogdanm 0:9b334a45a8ff 604 * @{
bogdanm 0:9b334a45a8ff 605 */
bogdanm 0:9b334a45a8ff 606 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 607 #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
bogdanm 0:9b334a45a8ff 608 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
bogdanm 0:9b334a45a8ff 609 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
bogdanm 0:9b334a45a8ff 610 #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
bogdanm 0:9b334a45a8ff 611 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
bogdanm 0:9b334a45a8ff 612 #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
bogdanm 0:9b334a45a8ff 613 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
bogdanm 0:9b334a45a8ff 614 #define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm 0:9b334a45a8ff 617 #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm 0:9b334a45a8ff 618 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm 0:9b334a45a8ff 619 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
bogdanm 0:9b334a45a8ff 620 #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm 0:9b334a45a8ff 621 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm 0:9b334a45a8ff 622 #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
bogdanm 0:9b334a45a8ff 623 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm 0:9b334a45a8ff 624 #define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
bogdanm 0:9b334a45a8ff 625 /**
bogdanm 0:9b334a45a8ff 626 * @}
bogdanm 0:9b334a45a8ff 627 */
bogdanm 0:9b334a45a8ff 628
bogdanm 0:9b334a45a8ff 629 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
bogdanm 0:9b334a45a8ff 630 * @brief Force or release APB2 peripheral reset.
bogdanm 0:9b334a45a8ff 631 * @{
bogdanm 0:9b334a45a8ff 632 */
bogdanm 0:9b334a45a8ff 633 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 634 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
bogdanm 0:9b334a45a8ff 635 #define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
bogdanm 0:9b334a45a8ff 636 #define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
bogdanm 0:9b334a45a8ff 637 #define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
bogdanm 0:9b334a45a8ff 638 #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm 0:9b334a45a8ff 641 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
bogdanm 0:9b334a45a8ff 642 #define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
bogdanm 0:9b334a45a8ff 643 #define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
bogdanm 0:9b334a45a8ff 644 #define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
bogdanm 0:9b334a45a8ff 645 #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm 0:9b334a45a8ff 646 /**
bogdanm 0:9b334a45a8ff 647 * @}
bogdanm 0:9b334a45a8ff 648 */
bogdanm 0:9b334a45a8ff 649
bogdanm 0:9b334a45a8ff 650 /** @defgroup RCC_HSI_Configuration RCC HSI Configuration
bogdanm 0:9b334a45a8ff 651 * @{
bogdanm 0:9b334a45a8ff 652 */
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm 0:9b334a45a8ff 655 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 656 * It is used (enabled by hardware) as system clock source after startup
bogdanm 0:9b334a45a8ff 657 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
bogdanm 0:9b334a45a8ff 658 * of the HSE used directly or indirectly as system clock (if the Clock
bogdanm 0:9b334a45a8ff 659 * Security System CSS is enabled).
bogdanm 0:9b334a45a8ff 660 * @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm 0:9b334a45a8ff 661 * you have to select another source of the system clock then stop the HSI.
bogdanm 0:9b334a45a8ff 662 * @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm 0:9b334a45a8ff 663 * flag to be set indicating that HSI clock is stable and can be used as
bogdanm 0:9b334a45a8ff 664 * system clock source.
bogdanm 0:9b334a45a8ff 665 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm 0:9b334a45a8ff 666 * clock cycles.
bogdanm 0:9b334a45a8ff 667 */
bogdanm 0:9b334a45a8ff 668 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *)CR_HSION_BB = ENABLE)
bogdanm 0:9b334a45a8ff 669 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *)CR_HSION_BB = DISABLE)
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm 0:9b334a45a8ff 673 * @note The calibration is used to compensate for the variations in voltage
bogdanm 0:9b334a45a8ff 674 * and temperature that influence the frequency of the internal HSI RC.
bogdanm 0:9b334a45a8ff 675 * @param __HSICalibrationValue__: specifies the calibration trimming value.
bogdanm 0:9b334a45a8ff 676 * This parameter must be a number between 0 and 0x1F.
bogdanm 0:9b334a45a8ff 677 */
bogdanm 0:9b334a45a8ff 678 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
bogdanm 0:9b334a45a8ff 679 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM))
bogdanm 0:9b334a45a8ff 680 /**
bogdanm 0:9b334a45a8ff 681 * @}
bogdanm 0:9b334a45a8ff 682 */
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684 /** @defgroup RCC_LSI_Configuration RCC LSI Configuration
bogdanm 0:9b334a45a8ff 685 * @{
bogdanm 0:9b334a45a8ff 686 */
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 /** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm 0:9b334a45a8ff 689 * @note After enabling the LSI, the application software should wait on
bogdanm 0:9b334a45a8ff 690 * LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm 0:9b334a45a8ff 691 * be used to clock the IWDG and/or the RTC.
bogdanm 0:9b334a45a8ff 692 * @note LSI can not be disabled if the IWDG is running.
bogdanm 0:9b334a45a8ff 693 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm 0:9b334a45a8ff 694 * clock cycles.
bogdanm 0:9b334a45a8ff 695 */
bogdanm 0:9b334a45a8ff 696 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *)CSR_LSION_BB = ENABLE)
bogdanm 0:9b334a45a8ff 697 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *)CSR_LSION_BB = DISABLE)
bogdanm 0:9b334a45a8ff 698 /**
bogdanm 0:9b334a45a8ff 699 * @}
bogdanm 0:9b334a45a8ff 700 */
bogdanm 0:9b334a45a8ff 701
bogdanm 0:9b334a45a8ff 702 /** @defgroup RCC_HSE_Configuration RCC HSE Configuration
bogdanm 0:9b334a45a8ff 703 * @{
bogdanm 0:9b334a45a8ff 704 */
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 /**
bogdanm 0:9b334a45a8ff 707 * @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm 0:9b334a45a8ff 708 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm 0:9b334a45a8ff 709 * software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm 0:9b334a45a8ff 710 * is stable and can be used to clock the PLL and/or system clock.
bogdanm 0:9b334a45a8ff 711 * @note HSE state can not be changed if it is used directly or through the
bogdanm 0:9b334a45a8ff 712 * PLL as system clock. In this case, you have to select another source
bogdanm 0:9b334a45a8ff 713 * of the system clock then change the HSE state (ex. disable it).
bogdanm 0:9b334a45a8ff 714 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 715 * @note This function reset the CSSON bit, so if the Clock security system(CSS)
bogdanm 0:9b334a45a8ff 716 * was previously enabled you have to enable it again after calling this
bogdanm 0:9b334a45a8ff 717 * function.
bogdanm 0:9b334a45a8ff 718 * @param __STATE__: specifies the new state of the HSE.
bogdanm 0:9b334a45a8ff 719 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 720 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm 0:9b334a45a8ff 721 * 6 HSE oscillator clock cycles.
bogdanm 0:9b334a45a8ff 722 * @arg RCC_HSE_ON: turn ON the HSE oscillator
bogdanm 0:9b334a45a8ff 723 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
bogdanm 0:9b334a45a8ff 724 */
bogdanm 0:9b334a45a8ff 725 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)CR_BYTE2_ADDRESS = (__STATE__))
bogdanm 0:9b334a45a8ff 726 /**
bogdanm 0:9b334a45a8ff 727 * @}
bogdanm 0:9b334a45a8ff 728 */
bogdanm 0:9b334a45a8ff 729
bogdanm 0:9b334a45a8ff 730 /** @defgroup RCC_LSE_Configuration RCC LSE Configuration
bogdanm 0:9b334a45a8ff 731 * @{
bogdanm 0:9b334a45a8ff 732 */
bogdanm 0:9b334a45a8ff 733 /**
bogdanm 0:9b334a45a8ff 734 * @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm 0:9b334a45a8ff 735 * @note As the LSE is in the Backup domain and write access is denied to
bogdanm 0:9b334a45a8ff 736 * this domain after reset, you have to enable write access using
bogdanm 0:9b334a45a8ff 737 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm 0:9b334a45a8ff 738 * (to be done once after reset).
bogdanm 0:9b334a45a8ff 739 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm 0:9b334a45a8ff 740 * software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm 0:9b334a45a8ff 741 * is stable and can be used to clock the RTC.
bogdanm 0:9b334a45a8ff 742 * @param __STATE__: specifies the new state of the LSE.
bogdanm 0:9b334a45a8ff 743 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 744 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm 0:9b334a45a8ff 745 * 6 LSE oscillator clock cycles.
bogdanm 0:9b334a45a8ff 746 * @arg RCC_LSE_ON: turn ON the LSE oscillator
bogdanm 0:9b334a45a8ff 747 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
bogdanm 0:9b334a45a8ff 748 */
bogdanm 0:9b334a45a8ff 749 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
bogdanm 0:9b334a45a8ff 750 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
bogdanm 0:9b334a45a8ff 751 /**
bogdanm 0:9b334a45a8ff 752 * @}
bogdanm 0:9b334a45a8ff 753 */
bogdanm 0:9b334a45a8ff 754
bogdanm 0:9b334a45a8ff 755 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
bogdanm 0:9b334a45a8ff 756 * @{
bogdanm 0:9b334a45a8ff 757 */
bogdanm 0:9b334a45a8ff 758 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
bogdanm 0:9b334a45a8ff 759 * @param __I2C1CLKSource__: specifies the I2C1 clock source.
bogdanm 0:9b334a45a8ff 760 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 761 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm 0:9b334a45a8ff 762 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm 0:9b334a45a8ff 763 */
bogdanm 0:9b334a45a8ff 764 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
bogdanm 0:9b334a45a8ff 765 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
bogdanm 0:9b334a45a8ff 766
bogdanm 0:9b334a45a8ff 767 /** @brief Macro to get the I2C1 clock source.
bogdanm 0:9b334a45a8ff 768 * @retval The clock source can be one of the following values:
bogdanm 0:9b334a45a8ff 769 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm 0:9b334a45a8ff 770 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm 0:9b334a45a8ff 771 */
bogdanm 0:9b334a45a8ff 772 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
bogdanm 0:9b334a45a8ff 773 /**
bogdanm 0:9b334a45a8ff 774 * @}
bogdanm 0:9b334a45a8ff 775 */
bogdanm 0:9b334a45a8ff 776
bogdanm 0:9b334a45a8ff 777 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
bogdanm 0:9b334a45a8ff 778 * @{
bogdanm 0:9b334a45a8ff 779 */
bogdanm 0:9b334a45a8ff 780
bogdanm 0:9b334a45a8ff 781 /** @brief Macro to configure the USART1 clock (USART1CLK).
bogdanm 0:9b334a45a8ff 782 * @param __USART1CLKSource__: specifies the USART1 clock source.
bogdanm 0:9b334a45a8ff 783 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 784 * @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock
bogdanm 0:9b334a45a8ff 785 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm 0:9b334a45a8ff 786 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm 0:9b334a45a8ff 787 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm 0:9b334a45a8ff 788 */
bogdanm 0:9b334a45a8ff 789 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
bogdanm 0:9b334a45a8ff 790 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
bogdanm 0:9b334a45a8ff 791
bogdanm 0:9b334a45a8ff 792 /** @brief Macro to get the USART1 clock source.
bogdanm 0:9b334a45a8ff 793 * @retval The clock source can be one of the following values:
bogdanm 0:9b334a45a8ff 794 * @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock
bogdanm 0:9b334a45a8ff 795 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm 0:9b334a45a8ff 796 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm 0:9b334a45a8ff 797 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm 0:9b334a45a8ff 798 */
bogdanm 0:9b334a45a8ff 799 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
bogdanm 0:9b334a45a8ff 800
bogdanm 0:9b334a45a8ff 801 /** @brief Macro to configure the USART2 clock (USART2CLK).
bogdanm 0:9b334a45a8ff 802 * @param __USART2CLKSource__: specifies the USART2 clock source.
bogdanm 0:9b334a45a8ff 803 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 804 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm 0:9b334a45a8ff 805 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm 0:9b334a45a8ff 806 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm 0:9b334a45a8ff 807 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm 0:9b334a45a8ff 808 */
bogdanm 0:9b334a45a8ff 809 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
bogdanm 0:9b334a45a8ff 810 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
bogdanm 0:9b334a45a8ff 811
bogdanm 0:9b334a45a8ff 812 /** @brief Macro to get the USART2 clock source.
bogdanm 0:9b334a45a8ff 813 * @retval The clock source can be one of the following values:
bogdanm 0:9b334a45a8ff 814 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm 0:9b334a45a8ff 815 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm 0:9b334a45a8ff 816 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm 0:9b334a45a8ff 817 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm 0:9b334a45a8ff 818 */
bogdanm 0:9b334a45a8ff 819 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
bogdanm 0:9b334a45a8ff 820
bogdanm 0:9b334a45a8ff 821 /** @brief Macro to configure the USART3 clock (USART3CLK).
bogdanm 0:9b334a45a8ff 822 * @param __USART3CLKSource__: specifies the USART3 clock source.
bogdanm 0:9b334a45a8ff 823 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 824 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm 0:9b334a45a8ff 825 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm 0:9b334a45a8ff 826 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm 0:9b334a45a8ff 827 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm 0:9b334a45a8ff 828 */
bogdanm 0:9b334a45a8ff 829 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
bogdanm 0:9b334a45a8ff 830 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 /** @brief Macro to get the USART3 clock source.
bogdanm 0:9b334a45a8ff 833 * @retval The clock source can be one of the following values:
bogdanm 0:9b334a45a8ff 834 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm 0:9b334a45a8ff 835 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm 0:9b334a45a8ff 836 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm 0:9b334a45a8ff 837 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm 0:9b334a45a8ff 838 */
bogdanm 0:9b334a45a8ff 839 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
bogdanm 0:9b334a45a8ff 840 /**
bogdanm 0:9b334a45a8ff 841 * @}
bogdanm 0:9b334a45a8ff 842 */
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
bogdanm 0:9b334a45a8ff 845 * @{
bogdanm 0:9b334a45a8ff 846 */
bogdanm 0:9b334a45a8ff 847 /** @brief Macros to enable or disable the the RTC clock.
bogdanm 0:9b334a45a8ff 848 * @note These macros must be used only after the RTC clock source was selected.
bogdanm 0:9b334a45a8ff 849 */
bogdanm 0:9b334a45a8ff 850 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *)BDCR_RTCEN_BB = ENABLE)
bogdanm 0:9b334a45a8ff 851 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *)BDCR_RTCEN_BB = DISABLE)
bogdanm 0:9b334a45a8ff 852
bogdanm 0:9b334a45a8ff 853 /** @brief Macro to configure the RTC clock (RTCCLK).
bogdanm 0:9b334a45a8ff 854 * @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm 0:9b334a45a8ff 855 * access is denied to this domain after reset, you have to enable write
bogdanm 0:9b334a45a8ff 856 * access using the Power Backup Access macro before to configure
bogdanm 0:9b334a45a8ff 857 * the RTC clock source (to be done once after reset).
bogdanm 0:9b334a45a8ff 858 * @note Once the RTC clock is configured it can't be changed unless the
bogdanm 0:9b334a45a8ff 859 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
bogdanm 0:9b334a45a8ff 860 * a Power On Reset (POR).
bogdanm 0:9b334a45a8ff 861 * @param __RTCCLKSource__: specifies the RTC clock source.
bogdanm 0:9b334a45a8ff 862 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 863 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
bogdanm 0:9b334a45a8ff 864 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm 0:9b334a45a8ff 865 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm 0:9b334a45a8ff 866 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
bogdanm 0:9b334a45a8ff 867 *
bogdanm 0:9b334a45a8ff 868 * @note If the LSE is used as RTC clock source, the RTC continues to
bogdanm 0:9b334a45a8ff 869 * work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm 0:9b334a45a8ff 870 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
bogdanm 0:9b334a45a8ff 871 * the RTC cannot be used in STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 872 * @note The system must always be configured so as to get a PCLK frequency greater than or
bogdanm 0:9b334a45a8ff 873 * equal to the RTCCLK frequency for a proper operation of the RTC.
bogdanm 0:9b334a45a8ff 874 */
bogdanm 0:9b334a45a8ff 875 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
bogdanm 0:9b334a45a8ff 876 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
bogdanm 0:9b334a45a8ff 877
bogdanm 0:9b334a45a8ff 878 /** @brief Macro to get the RTC clock source.
bogdanm 0:9b334a45a8ff 879 * @retval The clock source can be one of the following values:
bogdanm 0:9b334a45a8ff 880 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
bogdanm 0:9b334a45a8ff 881 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm 0:9b334a45a8ff 882 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm 0:9b334a45a8ff 883 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
bogdanm 0:9b334a45a8ff 884 */
bogdanm 0:9b334a45a8ff 885 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
bogdanm 0:9b334a45a8ff 886 /**
bogdanm 0:9b334a45a8ff 887 * @}
bogdanm 0:9b334a45a8ff 888 */
bogdanm 0:9b334a45a8ff 889
bogdanm 0:9b334a45a8ff 890 /** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
bogdanm 0:9b334a45a8ff 891 * @{
bogdanm 0:9b334a45a8ff 892 */
bogdanm 0:9b334a45a8ff 893
bogdanm 0:9b334a45a8ff 894 /** @brief Macro to force or release the Backup domain reset.
bogdanm 0:9b334a45a8ff 895 * @note These macros reset the RTC peripheral (including the backup registers)
bogdanm 0:9b334a45a8ff 896 * and the RTC clock source selection in RCC_CSR register.
bogdanm 0:9b334a45a8ff 897 * @note The BKPSRAM is not affected by this reset.
bogdanm 0:9b334a45a8ff 898 */
bogdanm 0:9b334a45a8ff 899 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *)BDCR_BDRST_BB = ENABLE)
bogdanm 0:9b334a45a8ff 900 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *)BDCR_BDRST_BB = DISABLE)
bogdanm 0:9b334a45a8ff 901 /**
bogdanm 0:9b334a45a8ff 902 * @}
bogdanm 0:9b334a45a8ff 903 */
bogdanm 0:9b334a45a8ff 904
bogdanm 0:9b334a45a8ff 905 /** @defgroup RCC_PLL_Configuration RCC PLL Configuration
bogdanm 0:9b334a45a8ff 906 * @{
bogdanm 0:9b334a45a8ff 907 */
bogdanm 0:9b334a45a8ff 908
bogdanm 0:9b334a45a8ff 909 /** @brief Macro to enable or disable the PLL.
bogdanm 0:9b334a45a8ff 910 * @note After enabling the PLL, the application software should wait on
bogdanm 0:9b334a45a8ff 911 * PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm 0:9b334a45a8ff 912 * be used as system clock source.
bogdanm 0:9b334a45a8ff 913 * @note The PLL can not be disabled if it is used as system clock source
bogdanm 0:9b334a45a8ff 914 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 915 */
bogdanm 0:9b334a45a8ff 916 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *)CR_PLLON_BB = ENABLE)
bogdanm 0:9b334a45a8ff 917 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *)CR_PLLON_BB = DISABLE)
bogdanm 0:9b334a45a8ff 918 /**
bogdanm 0:9b334a45a8ff 919 * @}
bogdanm 0:9b334a45a8ff 920 */
bogdanm 0:9b334a45a8ff 921
bogdanm 0:9b334a45a8ff 922 /** @defgroup RCC_Get_Clock_source RCC Get Clock source
bogdanm 0:9b334a45a8ff 923 * @{
bogdanm 0:9b334a45a8ff 924 */
bogdanm 0:9b334a45a8ff 925
bogdanm 0:9b334a45a8ff 926 /** @brief Macro to get the clock source used as system clock.
bogdanm 0:9b334a45a8ff 927 * @retval The clock source used as system clock.
bogdanm 0:9b334a45a8ff 928 * The returned value can be one of the following value:
bogdanm 0:9b334a45a8ff 929 * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
bogdanm 0:9b334a45a8ff 930 * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
bogdanm 0:9b334a45a8ff 931 * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
bogdanm 0:9b334a45a8ff 932 */
bogdanm 0:9b334a45a8ff 933 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
bogdanm 0:9b334a45a8ff 934
bogdanm 0:9b334a45a8ff 935 /** @brief Macro to get the oscillator used as PLL clock source.
bogdanm 0:9b334a45a8ff 936 * @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm 0:9b334a45a8ff 937 * of the following:
bogdanm 0:9b334a45a8ff 938 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm 0:9b334a45a8ff 939 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm 0:9b334a45a8ff 940 */
bogdanm 0:9b334a45a8ff 941 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
bogdanm 0:9b334a45a8ff 942 /**
bogdanm 0:9b334a45a8ff 943 * @}
bogdanm 0:9b334a45a8ff 944 */
bogdanm 0:9b334a45a8ff 945
bogdanm 0:9b334a45a8ff 946 /** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
bogdanm 0:9b334a45a8ff 947 * @brief macros to manage the specified RCC Flags and interrupts.
bogdanm 0:9b334a45a8ff 948 * @{
bogdanm 0:9b334a45a8ff 949 */
bogdanm 0:9b334a45a8ff 950
bogdanm 0:9b334a45a8ff 951 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
bogdanm 0:9b334a45a8ff 952 * the selected interrupts.).
bogdanm 0:9b334a45a8ff 953 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm 0:9b334a45a8ff 954 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 955 * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
bogdanm 0:9b334a45a8ff 956 * @arg RCC_IT_LSERDY: LSE ready interrupt enable
bogdanm 0:9b334a45a8ff 957 * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
bogdanm 0:9b334a45a8ff 958 * @arg RCC_IT_HSERDY: HSE ready interrupt enable
bogdanm 0:9b334a45a8ff 959 * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
bogdanm 0:9b334a45a8ff 960 */
bogdanm 0:9b334a45a8ff 961 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 962
bogdanm 0:9b334a45a8ff 963 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
bogdanm 0:9b334a45a8ff 964 * the selected interrupts.).
bogdanm 0:9b334a45a8ff 965 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm 0:9b334a45a8ff 966 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 967 * @arg RCC_IT_LSIRDYIE: LSI ready interrupt enable
bogdanm 0:9b334a45a8ff 968 * @arg RCC_IT_LSERDYIE: LSE ready interrupt enable
bogdanm 0:9b334a45a8ff 969 * @arg RCC_IT_HSIRDYIE: HSI ready interrupt enable
bogdanm 0:9b334a45a8ff 970 * @arg RCC_IT_HSERDYIE: HSE ready interrupt enable
bogdanm 0:9b334a45a8ff 971 * @arg RCC_IT_PLLRDYIE: PLL ready interrupt enable
bogdanm 0:9b334a45a8ff 972 */
bogdanm 0:9b334a45a8ff 973 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
bogdanm 0:9b334a45a8ff 974
bogdanm 0:9b334a45a8ff 975 /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
bogdanm 0:9b334a45a8ff 976 * bits to clear the selected interrupt pending bits.
bogdanm 0:9b334a45a8ff 977 * @param __IT__: specifies the interrupt pending bit to clear.
bogdanm 0:9b334a45a8ff 978 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 979 * @arg RCC_IT_LSIRDYC: LSI ready interrupt clear
bogdanm 0:9b334a45a8ff 980 * @arg RCC_IT_LSERDYC: LSE ready interrupt clear
bogdanm 0:9b334a45a8ff 981 * @arg RCC_IT_HSIRDYC: HSI ready interrupt clear
bogdanm 0:9b334a45a8ff 982 * @arg RCC_IT_HSERDYC: HSE ready interrupt clear
bogdanm 0:9b334a45a8ff 983 * @arg RCC_IT_PLLRDYC: PLL ready interrupt clear
bogdanm 0:9b334a45a8ff 984 * @arg RCC_IT_CSSC: Clock Security System interrupt clear
bogdanm 0:9b334a45a8ff 985 */
bogdanm 0:9b334a45a8ff 986 #define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)CIR_BYTE2_ADDRESS = (__IT__))
bogdanm 0:9b334a45a8ff 987
bogdanm 0:9b334a45a8ff 988 /** @brief Check the RCC's interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 989 * @param __IT__: specifies the RCC interrupt source to check.
bogdanm 0:9b334a45a8ff 990 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 991 * @arg RCC_IT_LSIRDYF: LSI ready interrupt flag
bogdanm 0:9b334a45a8ff 992 * @arg RCC_IT_LSERDYF: LSE ready interrupt flag
bogdanm 0:9b334a45a8ff 993 * @arg RCC_IT_HSIRDYF: HSI ready interrupt flag
bogdanm 0:9b334a45a8ff 994 * @arg RCC_IT_HSERDYF: HSE ready interrupt flag
bogdanm 0:9b334a45a8ff 995 * @arg RCC_IT_PLLRDYF: PLL ready interrupt flag
bogdanm 0:9b334a45a8ff 996 * @arg RCC_IT_CSSF: Clock Security System interrupt flag
bogdanm 0:9b334a45a8ff 997 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 0:9b334a45a8ff 998 */
bogdanm 0:9b334a45a8ff 999 #define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
bogdanm 0:9b334a45a8ff 1000
bogdanm 0:9b334a45a8ff 1001 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
bogdanm 0:9b334a45a8ff 1002 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
bogdanm 0:9b334a45a8ff 1003 */
bogdanm 0:9b334a45a8ff 1004 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)CSR_RMVF_BB = ENABLE)
bogdanm 0:9b334a45a8ff 1005
bogdanm 0:9b334a45a8ff 1006 /** @brief Check RCC flag is set or not.
bogdanm 0:9b334a45a8ff 1007 * @param __FLAG__: specifies the flag to check.
bogdanm 0:9b334a45a8ff 1008 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1009 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
bogdanm 0:9b334a45a8ff 1010 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
bogdanm 0:9b334a45a8ff 1011 * @arg RCC_FLAG_PLLRDY: PLL clock ready
bogdanm 0:9b334a45a8ff 1012 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
bogdanm 0:9b334a45a8ff 1013 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
bogdanm 0:9b334a45a8ff 1014 * @arg RCC_FLAG_OBLRST: Option Byte Load reset
bogdanm 0:9b334a45a8ff 1015 * @arg RCC_FLAG_PINRST: Pin reset
bogdanm 0:9b334a45a8ff 1016 * @arg RCC_FLAG_PORRST: POR/PDR reset
bogdanm 0:9b334a45a8ff 1017 * @arg RCC_FLAG_SFTRST: Software reset
bogdanm 0:9b334a45a8ff 1018 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
bogdanm 0:9b334a45a8ff 1019 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
bogdanm 0:9b334a45a8ff 1020 * @arg RCC_FLAG_LPWRRST: Low Power reset
bogdanm 0:9b334a45a8ff 1021 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 0:9b334a45a8ff 1022 */
bogdanm 0:9b334a45a8ff 1023 #define RCC_FLAG_MASK ((uint32_t)0x0000001F)
bogdanm 0:9b334a45a8ff 1024 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
bogdanm 0:9b334a45a8ff 1025 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
bogdanm 0:9b334a45a8ff 1026 RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
bogdanm 0:9b334a45a8ff 1027
bogdanm 0:9b334a45a8ff 1028
bogdanm 0:9b334a45a8ff 1029 /**
bogdanm 0:9b334a45a8ff 1030 * @}
bogdanm 0:9b334a45a8ff 1031 */
bogdanm 0:9b334a45a8ff 1032
bogdanm 0:9b334a45a8ff 1033 /**
bogdanm 0:9b334a45a8ff 1034 * @}
bogdanm 0:9b334a45a8ff 1035 */
bogdanm 0:9b334a45a8ff 1036
bogdanm 0:9b334a45a8ff 1037 /* Include RCC HAL Extended module */
bogdanm 0:9b334a45a8ff 1038 #include "stm32f3xx_hal_rcc_ex.h"
bogdanm 0:9b334a45a8ff 1039
bogdanm 0:9b334a45a8ff 1040 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1041
bogdanm 0:9b334a45a8ff 1042 /** @addtogroup RCC_Exported_Functions
bogdanm 0:9b334a45a8ff 1043 * @{
bogdanm 0:9b334a45a8ff 1044 */
bogdanm 0:9b334a45a8ff 1045
bogdanm 0:9b334a45a8ff 1046 /** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 1047 * @{
bogdanm 0:9b334a45a8ff 1048 */
bogdanm 0:9b334a45a8ff 1049
bogdanm 0:9b334a45a8ff 1050 /* Initialization and de-initialization functions ***************************/
bogdanm 0:9b334a45a8ff 1051 void HAL_RCC_DeInit(void);
bogdanm 0:9b334a45a8ff 1052 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 0:9b334a45a8ff 1053 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm 0:9b334a45a8ff 1054
bogdanm 0:9b334a45a8ff 1055 /**
bogdanm 0:9b334a45a8ff 1056 * @}
bogdanm 0:9b334a45a8ff 1057 */
bogdanm 0:9b334a45a8ff 1058
bogdanm 0:9b334a45a8ff 1059 /** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions
bogdanm 0:9b334a45a8ff 1060 * @{
bogdanm 0:9b334a45a8ff 1061 */
bogdanm 0:9b334a45a8ff 1062
bogdanm 0:9b334a45a8ff 1063 /* Peripheral Control functions *********************************************/
bogdanm 0:9b334a45a8ff 1064 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm 0:9b334a45a8ff 1065 void HAL_RCC_EnableCSS(void);
bogdanm 0:9b334a45a8ff 1066 void HAL_RCC_DisableCSS(void);
bogdanm 0:9b334a45a8ff 1067 uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm 0:9b334a45a8ff 1068 uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm 0:9b334a45a8ff 1069 uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm 0:9b334a45a8ff 1070 uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm 0:9b334a45a8ff 1071 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 0:9b334a45a8ff 1072 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
bogdanm 0:9b334a45a8ff 1073
bogdanm 0:9b334a45a8ff 1074 /* CSS NMI IRQ handler */
bogdanm 0:9b334a45a8ff 1075 void HAL_RCC_NMI_IRQHandler(void);
bogdanm 0:9b334a45a8ff 1076
bogdanm 0:9b334a45a8ff 1077 /* User Callbacks in non blocking mode (IT mode) */
bogdanm 0:9b334a45a8ff 1078 void HAL_RCC_CCSCallback(void);
bogdanm 0:9b334a45a8ff 1079
bogdanm 0:9b334a45a8ff 1080 /**
bogdanm 0:9b334a45a8ff 1081 * @}
bogdanm 0:9b334a45a8ff 1082 */
bogdanm 0:9b334a45a8ff 1083
bogdanm 0:9b334a45a8ff 1084 /**
bogdanm 0:9b334a45a8ff 1085 * @}
bogdanm 0:9b334a45a8ff 1086 */
bogdanm 0:9b334a45a8ff 1087
bogdanm 0:9b334a45a8ff 1088 /**
bogdanm 0:9b334a45a8ff 1089 * @}
bogdanm 0:9b334a45a8ff 1090 */
bogdanm 0:9b334a45a8ff 1091
bogdanm 0:9b334a45a8ff 1092 /**
bogdanm 0:9b334a45a8ff 1093 * @}
bogdanm 0:9b334a45a8ff 1094 */
bogdanm 0:9b334a45a8ff 1095
bogdanm 0:9b334a45a8ff 1096 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 1097 }
bogdanm 0:9b334a45a8ff 1098 #endif
bogdanm 0:9b334a45a8ff 1099
bogdanm 0:9b334a45a8ff 1100 #endif /* __STM32F3xx_HAL_RCC_H */
bogdanm 0:9b334a45a8ff 1101
bogdanm 0:9b334a45a8ff 1102 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/