en 129
fix LPC812 PWM
Fork of
mbed-dev
by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_fsmc.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 124:6a4a5b7d7324
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f1xx_ll_fsmc.h |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.0.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 15-December-2014 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Header file of FSMC HAL module. |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * @attention |
| bogdanm | 0:9b334a45a8ff | 10 | * |
| bogdanm | 0:9b334a45a8ff | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 12 | * |
| bogdanm | 0:9b334a45a8ff | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 14 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 16 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 18 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 19 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 21 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 22 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 23 | * |
| bogdanm | 0:9b334a45a8ff | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 34 | * |
| bogdanm | 0:9b334a45a8ff | 35 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 36 | */ |
| bogdanm | 0:9b334a45a8ff | 37 | |
| bogdanm | 0:9b334a45a8ff | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 39 | #ifndef __STM32F1xx_LL_FSMC_H |
| bogdanm | 0:9b334a45a8ff | 40 | #define __STM32F1xx_LL_FSMC_H |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 43 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 44 | #endif |
| bogdanm | 0:9b334a45a8ff | 45 | |
| bogdanm | 0:9b334a45a8ff | 46 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 47 | #include "stm32f1xx_hal_def.h" |
| bogdanm | 0:9b334a45a8ff | 48 | |
| bogdanm | 0:9b334a45a8ff | 49 | /** @addtogroup STM32F1xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 50 | * @{ |
| bogdanm | 0:9b334a45a8ff | 51 | */ |
| bogdanm | 0:9b334a45a8ff | 52 | |
| bogdanm | 0:9b334a45a8ff | 53 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE) |
| bogdanm | 0:9b334a45a8ff | 54 | |
| bogdanm | 0:9b334a45a8ff | 55 | /** @addtogroup FSMC_LL |
| bogdanm | 0:9b334a45a8ff | 56 | * @{ |
| bogdanm | 0:9b334a45a8ff | 57 | */ |
| bogdanm | 0:9b334a45a8ff | 58 | |
| bogdanm | 0:9b334a45a8ff | 59 | /** @addtogroup FSMC_LL_Private_Macros |
| bogdanm | 0:9b334a45a8ff | 60 | * @{ |
| bogdanm | 0:9b334a45a8ff | 61 | */ |
| bogdanm | 0:9b334a45a8ff | 62 | |
| bogdanm | 0:9b334a45a8ff | 63 | #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ |
| bogdanm | 0:9b334a45a8ff | 64 | ((__BANK__) == FSMC_NORSRAM_BANK2) || \ |
| bogdanm | 0:9b334a45a8ff | 65 | ((__BANK__) == FSMC_NORSRAM_BANK3) || \ |
| bogdanm | 0:9b334a45a8ff | 66 | ((__BANK__) == FSMC_NORSRAM_BANK4)) |
| bogdanm | 0:9b334a45a8ff | 67 | |
| bogdanm | 0:9b334a45a8ff | 68 | #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 69 | ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 70 | |
| bogdanm | 0:9b334a45a8ff | 71 | #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ |
| bogdanm | 0:9b334a45a8ff | 72 | ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ |
| bogdanm | 0:9b334a45a8ff | 73 | ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) |
| bogdanm | 0:9b334a45a8ff | 74 | |
| bogdanm | 0:9b334a45a8ff | 75 | #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| bogdanm | 0:9b334a45a8ff | 76 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| bogdanm | 0:9b334a45a8ff | 77 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| bogdanm | 0:9b334a45a8ff | 78 | |
| bogdanm | 0:9b334a45a8ff | 79 | #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ |
| bogdanm | 0:9b334a45a8ff | 80 | ((__MODE__) == FSMC_ACCESS_MODE_B) || \ |
| bogdanm | 0:9b334a45a8ff | 81 | ((__MODE__) == FSMC_ACCESS_MODE_C) || \ |
| bogdanm | 0:9b334a45a8ff | 82 | ((__MODE__) == FSMC_ACCESS_MODE_D)) |
| bogdanm | 0:9b334a45a8ff | 83 | |
| bogdanm | 0:9b334a45a8ff | 84 | #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \ |
| bogdanm | 0:9b334a45a8ff | 85 | ((BANK) == FSMC_NAND_BANK3)) |
| bogdanm | 0:9b334a45a8ff | 86 | |
| bogdanm | 0:9b334a45a8ff | 87 | #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 88 | ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 89 | |
| bogdanm | 0:9b334a45a8ff | 90 | #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ |
| bogdanm | 0:9b334a45a8ff | 91 | ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) |
| bogdanm | 0:9b334a45a8ff | 92 | |
| bogdanm | 0:9b334a45a8ff | 93 | #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 94 | ((STATE) == FSMC_NAND_ECC_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 95 | |
| bogdanm | 0:9b334a45a8ff | 96 | #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
| bogdanm | 0:9b334a45a8ff | 97 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
| bogdanm | 0:9b334a45a8ff | 98 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
| bogdanm | 0:9b334a45a8ff | 99 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
| bogdanm | 0:9b334a45a8ff | 100 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
| bogdanm | 0:9b334a45a8ff | 101 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
| bogdanm | 0:9b334a45a8ff | 102 | /** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 103 | * @{ |
| bogdanm | 0:9b334a45a8ff | 104 | */ |
| bogdanm | 0:9b334a45a8ff | 105 | #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255) |
| bogdanm | 0:9b334a45a8ff | 106 | /** |
| bogdanm | 0:9b334a45a8ff | 107 | * @} |
| bogdanm | 0:9b334a45a8ff | 108 | */ |
| bogdanm | 0:9b334a45a8ff | 109 | |
| bogdanm | 0:9b334a45a8ff | 110 | /** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 111 | * @{ |
| bogdanm | 0:9b334a45a8ff | 112 | */ |
| bogdanm | 0:9b334a45a8ff | 113 | #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255) |
| bogdanm | 0:9b334a45a8ff | 114 | /** |
| bogdanm | 0:9b334a45a8ff | 115 | * @} |
| bogdanm | 0:9b334a45a8ff | 116 | */ |
| bogdanm | 0:9b334a45a8ff | 117 | |
| bogdanm | 0:9b334a45a8ff | 118 | /** @defgroup FSMC_Setup_Time FSMC_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 119 | * @{ |
| bogdanm | 0:9b334a45a8ff | 120 | */ |
| bogdanm | 0:9b334a45a8ff | 121 | #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255) |
| bogdanm | 0:9b334a45a8ff | 122 | /** |
| bogdanm | 0:9b334a45a8ff | 123 | * @} |
| bogdanm | 0:9b334a45a8ff | 124 | */ |
| bogdanm | 0:9b334a45a8ff | 125 | |
| bogdanm | 0:9b334a45a8ff | 126 | /** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 127 | * @{ |
| bogdanm | 0:9b334a45a8ff | 128 | */ |
| bogdanm | 0:9b334a45a8ff | 129 | #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255) |
| bogdanm | 0:9b334a45a8ff | 130 | /** |
| bogdanm | 0:9b334a45a8ff | 131 | * @} |
| bogdanm | 0:9b334a45a8ff | 132 | */ |
| bogdanm | 0:9b334a45a8ff | 133 | |
| bogdanm | 0:9b334a45a8ff | 134 | /** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 135 | * @{ |
| bogdanm | 0:9b334a45a8ff | 136 | */ |
| bogdanm | 0:9b334a45a8ff | 137 | #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255) |
| bogdanm | 0:9b334a45a8ff | 138 | /** |
| bogdanm | 0:9b334a45a8ff | 139 | * @} |
| bogdanm | 0:9b334a45a8ff | 140 | */ |
| bogdanm | 0:9b334a45a8ff | 141 | |
| bogdanm | 0:9b334a45a8ff | 142 | /** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time |
| bogdanm | 0:9b334a45a8ff | 143 | * @{ |
| bogdanm | 0:9b334a45a8ff | 144 | */ |
| bogdanm | 0:9b334a45a8ff | 145 | #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255) |
| bogdanm | 0:9b334a45a8ff | 146 | /** |
| bogdanm | 0:9b334a45a8ff | 147 | * @} |
| bogdanm | 0:9b334a45a8ff | 148 | */ |
| bogdanm | 0:9b334a45a8ff | 149 | |
| bogdanm | 0:9b334a45a8ff | 150 | /** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance |
| bogdanm | 0:9b334a45a8ff | 151 | * @{ |
| bogdanm | 0:9b334a45a8ff | 152 | */ |
| bogdanm | 0:9b334a45a8ff | 153 | |
| bogdanm | 0:9b334a45a8ff | 154 | #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) |
| bogdanm | 0:9b334a45a8ff | 155 | |
| bogdanm | 0:9b334a45a8ff | 156 | /** |
| bogdanm | 0:9b334a45a8ff | 157 | * @} |
| bogdanm | 0:9b334a45a8ff | 158 | */ |
| bogdanm | 0:9b334a45a8ff | 159 | |
| bogdanm | 0:9b334a45a8ff | 160 | /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance |
| bogdanm | 0:9b334a45a8ff | 161 | * @{ |
| bogdanm | 0:9b334a45a8ff | 162 | */ |
| bogdanm | 0:9b334a45a8ff | 163 | |
| bogdanm | 0:9b334a45a8ff | 164 | #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) |
| bogdanm | 0:9b334a45a8ff | 165 | |
| bogdanm | 0:9b334a45a8ff | 166 | /** |
| bogdanm | 0:9b334a45a8ff | 167 | * @} |
| bogdanm | 0:9b334a45a8ff | 168 | */ |
| bogdanm | 0:9b334a45a8ff | 169 | |
| bogdanm | 0:9b334a45a8ff | 170 | /** @defgroup FSMC_NAND_Device_Instance FSMC_NAND_Device_Instance |
| bogdanm | 0:9b334a45a8ff | 171 | * @{ |
| bogdanm | 0:9b334a45a8ff | 172 | */ |
| bogdanm | 0:9b334a45a8ff | 173 | #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE) |
| bogdanm | 0:9b334a45a8ff | 174 | /** |
| bogdanm | 0:9b334a45a8ff | 175 | * @} |
| bogdanm | 0:9b334a45a8ff | 176 | */ |
| bogdanm | 0:9b334a45a8ff | 177 | |
| bogdanm | 0:9b334a45a8ff | 178 | /** @defgroup FSMC_PCCARD_Device_Instance FSMC_PCCARD_Device_Instance |
| bogdanm | 0:9b334a45a8ff | 179 | * @{ |
| bogdanm | 0:9b334a45a8ff | 180 | */ |
| bogdanm | 0:9b334a45a8ff | 181 | #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE) |
| bogdanm | 0:9b334a45a8ff | 182 | |
| bogdanm | 0:9b334a45a8ff | 183 | /** |
| bogdanm | 0:9b334a45a8ff | 184 | * @} |
| bogdanm | 0:9b334a45a8ff | 185 | */ |
| bogdanm | 0:9b334a45a8ff | 186 | |
| bogdanm | 0:9b334a45a8ff | 187 | #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 188 | ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 189 | |
| bogdanm | 0:9b334a45a8ff | 190 | #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| bogdanm | 0:9b334a45a8ff | 191 | ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| bogdanm | 0:9b334a45a8ff | 192 | |
| bogdanm | 0:9b334a45a8ff | 193 | #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 194 | ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 195 | |
| bogdanm | 0:9b334a45a8ff | 196 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ |
| bogdanm | 0:9b334a45a8ff | 197 | ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) |
| bogdanm | 0:9b334a45a8ff | 198 | |
| bogdanm | 0:9b334a45a8ff | 199 | #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 200 | ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 201 | |
| bogdanm | 0:9b334a45a8ff | 202 | #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 203 | ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 204 | |
| bogdanm | 0:9b334a45a8ff | 205 | #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 206 | ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 207 | |
| bogdanm | 0:9b334a45a8ff | 208 | #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 209 | ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 210 | |
| bogdanm | 0:9b334a45a8ff | 211 | #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16)) |
| bogdanm | 0:9b334a45a8ff | 212 | |
| bogdanm | 0:9b334a45a8ff | 213 | /** @defgroup FSMC_Data_Latency FSMC Data Latency |
| bogdanm | 0:9b334a45a8ff | 214 | * @{ |
| bogdanm | 0:9b334a45a8ff | 215 | */ |
| bogdanm | 0:9b334a45a8ff | 216 | |
| bogdanm | 0:9b334a45a8ff | 217 | #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) |
| bogdanm | 0:9b334a45a8ff | 218 | /** |
| bogdanm | 0:9b334a45a8ff | 219 | * @} |
| bogdanm | 0:9b334a45a8ff | 220 | */ |
| bogdanm | 0:9b334a45a8ff | 221 | |
| bogdanm | 0:9b334a45a8ff | 222 | #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ |
| bogdanm | 0:9b334a45a8ff | 223 | ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) |
| bogdanm | 0:9b334a45a8ff | 224 | /** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time |
| bogdanm | 0:9b334a45a8ff | 225 | * @{ |
| bogdanm | 0:9b334a45a8ff | 226 | */ |
| bogdanm | 0:9b334a45a8ff | 227 | |
| bogdanm | 0:9b334a45a8ff | 228 | #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) |
| bogdanm | 0:9b334a45a8ff | 229 | /** |
| bogdanm | 0:9b334a45a8ff | 230 | * @} |
| bogdanm | 0:9b334a45a8ff | 231 | */ |
| bogdanm | 0:9b334a45a8ff | 232 | |
| bogdanm | 0:9b334a45a8ff | 233 | /** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time |
| bogdanm | 0:9b334a45a8ff | 234 | * @{ |
| bogdanm | 0:9b334a45a8ff | 235 | */ |
| bogdanm | 0:9b334a45a8ff | 236 | |
| bogdanm | 0:9b334a45a8ff | 237 | #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) |
| bogdanm | 0:9b334a45a8ff | 238 | /** |
| bogdanm | 0:9b334a45a8ff | 239 | * @} |
| bogdanm | 0:9b334a45a8ff | 240 | */ |
| bogdanm | 0:9b334a45a8ff | 241 | |
| bogdanm | 0:9b334a45a8ff | 242 | /** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time |
| bogdanm | 0:9b334a45a8ff | 243 | * @{ |
| bogdanm | 0:9b334a45a8ff | 244 | */ |
| bogdanm | 0:9b334a45a8ff | 245 | |
| bogdanm | 0:9b334a45a8ff | 246 | #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) |
| bogdanm | 0:9b334a45a8ff | 247 | /** |
| bogdanm | 0:9b334a45a8ff | 248 | * @} |
| bogdanm | 0:9b334a45a8ff | 249 | */ |
| bogdanm | 0:9b334a45a8ff | 250 | |
| bogdanm | 0:9b334a45a8ff | 251 | /** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration |
| bogdanm | 0:9b334a45a8ff | 252 | * @{ |
| bogdanm | 0:9b334a45a8ff | 253 | */ |
| bogdanm | 0:9b334a45a8ff | 254 | |
| bogdanm | 0:9b334a45a8ff | 255 | #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) |
| bogdanm | 0:9b334a45a8ff | 256 | /** |
| bogdanm | 0:9b334a45a8ff | 257 | * @} |
| bogdanm | 0:9b334a45a8ff | 258 | */ |
| bogdanm | 0:9b334a45a8ff | 259 | |
| bogdanm | 0:9b334a45a8ff | 260 | /** |
| bogdanm | 0:9b334a45a8ff | 261 | * @} |
| bogdanm | 0:9b334a45a8ff | 262 | */ |
| bogdanm | 0:9b334a45a8ff | 263 | |
| bogdanm | 0:9b334a45a8ff | 264 | /* Exported typedef ----------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 265 | |
| bogdanm | 0:9b334a45a8ff | 266 | /** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types |
| bogdanm | 0:9b334a45a8ff | 267 | * @{ |
| bogdanm | 0:9b334a45a8ff | 268 | */ |
| bogdanm | 0:9b334a45a8ff | 269 | |
| bogdanm | 0:9b334a45a8ff | 270 | #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef |
| bogdanm | 0:9b334a45a8ff | 271 | #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef |
| bogdanm | 0:9b334a45a8ff | 272 | #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef |
| bogdanm | 0:9b334a45a8ff | 273 | #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef |
| bogdanm | 0:9b334a45a8ff | 274 | |
| bogdanm | 0:9b334a45a8ff | 275 | #define FSMC_NORSRAM_DEVICE FSMC_Bank1 |
| bogdanm | 0:9b334a45a8ff | 276 | #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E |
| bogdanm | 0:9b334a45a8ff | 277 | #define FSMC_NAND_DEVICE FSMC_Bank2_3 |
| bogdanm | 0:9b334a45a8ff | 278 | #define FSMC_PCCARD_DEVICE FSMC_Bank4 |
| bogdanm | 0:9b334a45a8ff | 279 | |
| bogdanm | 0:9b334a45a8ff | 280 | /** |
| bogdanm | 0:9b334a45a8ff | 281 | * @brief FSMC_NORSRAM Configuration Structure definition |
| bogdanm | 0:9b334a45a8ff | 282 | */ |
| bogdanm | 0:9b334a45a8ff | 283 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 284 | { |
| bogdanm | 0:9b334a45a8ff | 285 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| bogdanm | 0:9b334a45a8ff | 286 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
| bogdanm | 0:9b334a45a8ff | 287 | |
| bogdanm | 0:9b334a45a8ff | 288 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
| bogdanm | 0:9b334a45a8ff | 289 | multiplexed on the data bus or not. |
| bogdanm | 0:9b334a45a8ff | 290 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
| bogdanm | 0:9b334a45a8ff | 291 | |
| bogdanm | 0:9b334a45a8ff | 292 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
| bogdanm | 0:9b334a45a8ff | 293 | the corresponding memory device. |
| bogdanm | 0:9b334a45a8ff | 294 | This parameter can be a value of @ref FSMC_Memory_Type */ |
| bogdanm | 0:9b334a45a8ff | 295 | |
| bogdanm | 0:9b334a45a8ff | 296 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| bogdanm | 0:9b334a45a8ff | 297 | This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ |
| bogdanm | 0:9b334a45a8ff | 298 | |
| bogdanm | 0:9b334a45a8ff | 299 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
| bogdanm | 0:9b334a45a8ff | 300 | valid only with synchronous burst Flash memories. |
| bogdanm | 0:9b334a45a8ff | 301 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
| bogdanm | 0:9b334a45a8ff | 302 | |
| bogdanm | 0:9b334a45a8ff | 303 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
| bogdanm | 0:9b334a45a8ff | 304 | the Flash memory in burst mode. |
| bogdanm | 0:9b334a45a8ff | 305 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
| bogdanm | 0:9b334a45a8ff | 306 | |
| bogdanm | 0:9b334a45a8ff | 307 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
| bogdanm | 0:9b334a45a8ff | 308 | memory, valid only when accessing Flash memories in burst mode. |
| bogdanm | 0:9b334a45a8ff | 309 | This parameter can be a value of @ref FSMC_Wrap_Mode */ |
| bogdanm | 0:9b334a45a8ff | 310 | |
| bogdanm | 0:9b334a45a8ff | 311 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
| bogdanm | 0:9b334a45a8ff | 312 | clock cycle before the wait state or during the wait state, |
| bogdanm | 0:9b334a45a8ff | 313 | valid only when accessing memories in burst mode. |
| bogdanm | 0:9b334a45a8ff | 314 | This parameter can be a value of @ref FSMC_Wait_Timing */ |
| bogdanm | 0:9b334a45a8ff | 315 | |
| bogdanm | 0:9b334a45a8ff | 316 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. |
| bogdanm | 0:9b334a45a8ff | 317 | This parameter can be a value of @ref FSMC_Write_Operation */ |
| bogdanm | 0:9b334a45a8ff | 318 | |
| bogdanm | 0:9b334a45a8ff | 319 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
| bogdanm | 0:9b334a45a8ff | 320 | signal, valid for Flash memory access in burst mode. |
| bogdanm | 0:9b334a45a8ff | 321 | This parameter can be a value of @ref FSMC_Wait_Signal */ |
| bogdanm | 0:9b334a45a8ff | 322 | |
| bogdanm | 0:9b334a45a8ff | 323 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
| bogdanm | 0:9b334a45a8ff | 324 | This parameter can be a value of @ref FSMC_Extended_Mode */ |
| bogdanm | 0:9b334a45a8ff | 325 | |
| bogdanm | 0:9b334a45a8ff | 326 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
| bogdanm | 0:9b334a45a8ff | 327 | valid only with asynchronous Flash memories. |
| bogdanm | 0:9b334a45a8ff | 328 | This parameter can be a value of @ref FSMC_AsynchronousWait */ |
| bogdanm | 0:9b334a45a8ff | 329 | |
| bogdanm | 0:9b334a45a8ff | 330 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
| bogdanm | 0:9b334a45a8ff | 331 | This parameter can be a value of @ref FSMC_Write_Burst */ |
| bogdanm | 0:9b334a45a8ff | 332 | |
| bogdanm | 0:9b334a45a8ff | 333 | }FSMC_NORSRAM_InitTypeDef; |
| bogdanm | 0:9b334a45a8ff | 334 | |
| bogdanm | 0:9b334a45a8ff | 335 | |
| bogdanm | 0:9b334a45a8ff | 336 | /** |
| bogdanm | 0:9b334a45a8ff | 337 | * @brief FSMC_NORSRAM Timing parameters structure definition |
| bogdanm | 0:9b334a45a8ff | 338 | */ |
| bogdanm | 0:9b334a45a8ff | 339 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 340 | { |
| bogdanm | 0:9b334a45a8ff | 341 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| bogdanm | 0:9b334a45a8ff | 342 | the duration of the address setup time. |
| bogdanm | 0:9b334a45a8ff | 343 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| bogdanm | 0:9b334a45a8ff | 344 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| bogdanm | 0:9b334a45a8ff | 345 | |
| bogdanm | 0:9b334a45a8ff | 346 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
| bogdanm | 0:9b334a45a8ff | 347 | the duration of the address hold time. |
| bogdanm | 0:9b334a45a8ff | 348 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| bogdanm | 0:9b334a45a8ff | 349 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| bogdanm | 0:9b334a45a8ff | 350 | |
| bogdanm | 0:9b334a45a8ff | 351 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
| bogdanm | 0:9b334a45a8ff | 352 | the duration of the data setup time. |
| bogdanm | 0:9b334a45a8ff | 353 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| bogdanm | 0:9b334a45a8ff | 354 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| bogdanm | 0:9b334a45a8ff | 355 | NOR Flash memories. */ |
| bogdanm | 0:9b334a45a8ff | 356 | |
| bogdanm | 0:9b334a45a8ff | 357 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
| bogdanm | 0:9b334a45a8ff | 358 | the duration of the bus turnaround. |
| bogdanm | 0:9b334a45a8ff | 359 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| bogdanm | 0:9b334a45a8ff | 360 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| bogdanm | 0:9b334a45a8ff | 361 | |
| bogdanm | 0:9b334a45a8ff | 362 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
| bogdanm | 0:9b334a45a8ff | 363 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
| bogdanm | 0:9b334a45a8ff | 364 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| bogdanm | 0:9b334a45a8ff | 365 | accesses. */ |
| bogdanm | 0:9b334a45a8ff | 366 | |
| bogdanm | 0:9b334a45a8ff | 367 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
| bogdanm | 0:9b334a45a8ff | 368 | to the memory before getting the first data. |
| bogdanm | 0:9b334a45a8ff | 369 | The parameter value depends on the memory type as shown below: |
| bogdanm | 0:9b334a45a8ff | 370 | - It must be set to 0 in case of a CRAM |
| bogdanm | 0:9b334a45a8ff | 371 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| bogdanm | 0:9b334a45a8ff | 372 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
| bogdanm | 0:9b334a45a8ff | 373 | with synchronous burst mode enable */ |
| bogdanm | 0:9b334a45a8ff | 374 | |
| bogdanm | 0:9b334a45a8ff | 375 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
| bogdanm | 0:9b334a45a8ff | 376 | This parameter can be a value of @ref FSMC_Access_Mode */ |
| bogdanm | 0:9b334a45a8ff | 377 | |
| bogdanm | 0:9b334a45a8ff | 378 | }FSMC_NORSRAM_TimingTypeDef; |
| bogdanm | 0:9b334a45a8ff | 379 | |
| bogdanm | 0:9b334a45a8ff | 380 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) |
| bogdanm | 0:9b334a45a8ff | 381 | /** |
| bogdanm | 0:9b334a45a8ff | 382 | * @brief FSMC_NAND Configuration Structure definition |
| bogdanm | 0:9b334a45a8ff | 383 | */ |
| bogdanm | 0:9b334a45a8ff | 384 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 385 | { |
| bogdanm | 0:9b334a45a8ff | 386 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
| bogdanm | 0:9b334a45a8ff | 387 | This parameter can be a value of @ref FSMC_NAND_Bank */ |
| bogdanm | 0:9b334a45a8ff | 388 | |
| bogdanm | 0:9b334a45a8ff | 389 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
| bogdanm | 0:9b334a45a8ff | 390 | This parameter can be any value of @ref FSMC_Wait_feature */ |
| bogdanm | 0:9b334a45a8ff | 391 | |
| bogdanm | 0:9b334a45a8ff | 392 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| bogdanm | 0:9b334a45a8ff | 393 | This parameter can be any value of @ref FSMC_NAND_Data_Width */ |
| bogdanm | 0:9b334a45a8ff | 394 | |
| bogdanm | 0:9b334a45a8ff | 395 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
| bogdanm | 0:9b334a45a8ff | 396 | This parameter can be any value of @ref FSMC_ECC */ |
| bogdanm | 0:9b334a45a8ff | 397 | |
| bogdanm | 0:9b334a45a8ff | 398 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
| bogdanm | 0:9b334a45a8ff | 399 | This parameter can be any value of @ref FSMC_ECC_Page_Size */ |
| bogdanm | 0:9b334a45a8ff | 400 | |
| bogdanm | 0:9b334a45a8ff | 401 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| bogdanm | 0:9b334a45a8ff | 402 | delay between CLE low and RE low. |
| bogdanm | 0:9b334a45a8ff | 403 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 404 | |
| bogdanm | 0:9b334a45a8ff | 405 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| bogdanm | 0:9b334a45a8ff | 406 | delay between ALE low and RE low. |
| bogdanm | 0:9b334a45a8ff | 407 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 408 | |
| bogdanm | 0:9b334a45a8ff | 409 | }FSMC_NAND_InitTypeDef; |
| bogdanm | 0:9b334a45a8ff | 410 | |
| bogdanm | 0:9b334a45a8ff | 411 | /** |
| bogdanm | 0:9b334a45a8ff | 412 | * @brief FSMC_NAND_PCCARD Timing parameters structure definition |
| bogdanm | 0:9b334a45a8ff | 413 | */ |
| bogdanm | 0:9b334a45a8ff | 414 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 415 | { |
| bogdanm | 0:9b334a45a8ff | 416 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
| bogdanm | 0:9b334a45a8ff | 417 | the command assertion for NAND-Flash read or write access |
| bogdanm | 0:9b334a45a8ff | 418 | to common/Attribute or I/O memory space (depending on |
| bogdanm | 0:9b334a45a8ff | 419 | the memory space timing to be configured). |
| bogdanm | 0:9b334a45a8ff | 420 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 421 | |
| bogdanm | 0:9b334a45a8ff | 422 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
| bogdanm | 0:9b334a45a8ff | 423 | command for NAND-Flash read or write access to |
| bogdanm | 0:9b334a45a8ff | 424 | common/Attribute or I/O memory space (depending on the |
| bogdanm | 0:9b334a45a8ff | 425 | memory space timing to be configured). |
| bogdanm | 0:9b334a45a8ff | 426 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 427 | |
| bogdanm | 0:9b334a45a8ff | 428 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
| bogdanm | 0:9b334a45a8ff | 429 | (and data for write access) after the command de-assertion |
| bogdanm | 0:9b334a45a8ff | 430 | for NAND-Flash read or write access to common/Attribute |
| bogdanm | 0:9b334a45a8ff | 431 | or I/O memory space (depending on the memory space timing |
| bogdanm | 0:9b334a45a8ff | 432 | to be configured). |
| bogdanm | 0:9b334a45a8ff | 433 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 434 | |
| bogdanm | 0:9b334a45a8ff | 435 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
| bogdanm | 0:9b334a45a8ff | 436 | data bus is kept in HiZ after the start of a NAND-Flash |
| bogdanm | 0:9b334a45a8ff | 437 | write access to common/Attribute or I/O memory space (depending |
| bogdanm | 0:9b334a45a8ff | 438 | on the memory space timing to be configured). |
| bogdanm | 0:9b334a45a8ff | 439 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 440 | |
| bogdanm | 0:9b334a45a8ff | 441 | }FSMC_NAND_PCC_TimingTypeDef; |
| bogdanm | 0:9b334a45a8ff | 442 | |
| bogdanm | 0:9b334a45a8ff | 443 | /** |
| bogdanm | 0:9b334a45a8ff | 444 | * @brief FSMC_NAND Configuration Structure definition |
| bogdanm | 0:9b334a45a8ff | 445 | */ |
| bogdanm | 0:9b334a45a8ff | 446 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 447 | { |
| bogdanm | 0:9b334a45a8ff | 448 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. |
| bogdanm | 0:9b334a45a8ff | 449 | This parameter can be any value of @ref FSMC_Wait_feature */ |
| bogdanm | 0:9b334a45a8ff | 450 | |
| bogdanm | 0:9b334a45a8ff | 451 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| bogdanm | 0:9b334a45a8ff | 452 | delay between CLE low and RE low. |
| bogdanm | 0:9b334a45a8ff | 453 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 454 | |
| bogdanm | 0:9b334a45a8ff | 455 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| bogdanm | 0:9b334a45a8ff | 456 | delay between ALE low and RE low. |
| bogdanm | 0:9b334a45a8ff | 457 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| bogdanm | 0:9b334a45a8ff | 458 | |
| bogdanm | 0:9b334a45a8ff | 459 | }FSMC_PCCARD_InitTypeDef; |
| bogdanm | 0:9b334a45a8ff | 460 | |
| bogdanm | 0:9b334a45a8ff | 461 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
| bogdanm | 0:9b334a45a8ff | 462 | /** |
| bogdanm | 0:9b334a45a8ff | 463 | * @} |
| bogdanm | 0:9b334a45a8ff | 464 | */ |
| bogdanm | 0:9b334a45a8ff | 465 | |
| bogdanm | 0:9b334a45a8ff | 466 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 467 | |
| bogdanm | 0:9b334a45a8ff | 468 | /** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants |
| bogdanm | 0:9b334a45a8ff | 469 | * @{ |
| bogdanm | 0:9b334a45a8ff | 470 | */ |
| bogdanm | 0:9b334a45a8ff | 471 | |
| bogdanm | 0:9b334a45a8ff | 472 | /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants |
| bogdanm | 0:9b334a45a8ff | 473 | * @{ |
| bogdanm | 0:9b334a45a8ff | 474 | */ |
| bogdanm | 0:9b334a45a8ff | 475 | |
| bogdanm | 0:9b334a45a8ff | 476 | /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank |
| bogdanm | 0:9b334a45a8ff | 477 | * @{ |
| bogdanm | 0:9b334a45a8ff | 478 | */ |
| bogdanm | 0:9b334a45a8ff | 479 | #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 480 | #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002) |
| bogdanm | 0:9b334a45a8ff | 481 | #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004) |
| bogdanm | 0:9b334a45a8ff | 482 | #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006) |
| bogdanm | 0:9b334a45a8ff | 483 | |
| bogdanm | 0:9b334a45a8ff | 484 | /** |
| bogdanm | 0:9b334a45a8ff | 485 | * @} |
| bogdanm | 0:9b334a45a8ff | 486 | */ |
| bogdanm | 0:9b334a45a8ff | 487 | |
| bogdanm | 0:9b334a45a8ff | 488 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing |
| bogdanm | 0:9b334a45a8ff | 489 | * @{ |
| bogdanm | 0:9b334a45a8ff | 490 | */ |
| bogdanm | 0:9b334a45a8ff | 491 | |
| bogdanm | 0:9b334a45a8ff | 492 | #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 493 | #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN) |
| bogdanm | 0:9b334a45a8ff | 494 | |
| bogdanm | 0:9b334a45a8ff | 495 | /** |
| bogdanm | 0:9b334a45a8ff | 496 | * @} |
| bogdanm | 0:9b334a45a8ff | 497 | */ |
| bogdanm | 0:9b334a45a8ff | 498 | |
| bogdanm | 0:9b334a45a8ff | 499 | /** @defgroup FSMC_Memory_Type FSMC Memory Type |
| bogdanm | 0:9b334a45a8ff | 500 | * @{ |
| bogdanm | 0:9b334a45a8ff | 501 | */ |
| bogdanm | 0:9b334a45a8ff | 502 | |
| bogdanm | 0:9b334a45a8ff | 503 | #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 504 | #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0) |
| bogdanm | 0:9b334a45a8ff | 505 | #define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1) |
| bogdanm | 0:9b334a45a8ff | 506 | |
| bogdanm | 0:9b334a45a8ff | 507 | |
| bogdanm | 0:9b334a45a8ff | 508 | /** |
| bogdanm | 0:9b334a45a8ff | 509 | * @} |
| bogdanm | 0:9b334a45a8ff | 510 | */ |
| bogdanm | 0:9b334a45a8ff | 511 | |
| bogdanm | 0:9b334a45a8ff | 512 | /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width |
| bogdanm | 0:9b334a45a8ff | 513 | * @{ |
| bogdanm | 0:9b334a45a8ff | 514 | */ |
| bogdanm | 0:9b334a45a8ff | 515 | |
| bogdanm | 0:9b334a45a8ff | 516 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 517 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0) |
| bogdanm | 0:9b334a45a8ff | 518 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1) |
| bogdanm | 0:9b334a45a8ff | 519 | |
| bogdanm | 0:9b334a45a8ff | 520 | /** |
| bogdanm | 0:9b334a45a8ff | 521 | * @} |
| bogdanm | 0:9b334a45a8ff | 522 | */ |
| bogdanm | 0:9b334a45a8ff | 523 | |
| bogdanm | 0:9b334a45a8ff | 524 | /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access |
| bogdanm | 0:9b334a45a8ff | 525 | * @{ |
| bogdanm | 0:9b334a45a8ff | 526 | */ |
| bogdanm | 0:9b334a45a8ff | 527 | |
| bogdanm | 0:9b334a45a8ff | 528 | #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN) |
| bogdanm | 0:9b334a45a8ff | 529 | #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 530 | /** |
| bogdanm | 0:9b334a45a8ff | 531 | * @} |
| bogdanm | 0:9b334a45a8ff | 532 | */ |
| bogdanm | 0:9b334a45a8ff | 533 | |
| bogdanm | 0:9b334a45a8ff | 534 | /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode |
| bogdanm | 0:9b334a45a8ff | 535 | * @{ |
| bogdanm | 0:9b334a45a8ff | 536 | */ |
| bogdanm | 0:9b334a45a8ff | 537 | |
| bogdanm | 0:9b334a45a8ff | 538 | #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 539 | #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN) |
| bogdanm | 0:9b334a45a8ff | 540 | |
| bogdanm | 0:9b334a45a8ff | 541 | /** |
| bogdanm | 0:9b334a45a8ff | 542 | * @} |
| bogdanm | 0:9b334a45a8ff | 543 | */ |
| bogdanm | 0:9b334a45a8ff | 544 | |
| bogdanm | 0:9b334a45a8ff | 545 | |
| bogdanm | 0:9b334a45a8ff | 546 | /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity |
| bogdanm | 0:9b334a45a8ff | 547 | * @{ |
| bogdanm | 0:9b334a45a8ff | 548 | */ |
| bogdanm | 0:9b334a45a8ff | 549 | |
| bogdanm | 0:9b334a45a8ff | 550 | #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 551 | #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL) |
| bogdanm | 0:9b334a45a8ff | 552 | |
| bogdanm | 0:9b334a45a8ff | 553 | /** |
| bogdanm | 0:9b334a45a8ff | 554 | * @} |
| bogdanm | 0:9b334a45a8ff | 555 | */ |
| bogdanm | 0:9b334a45a8ff | 556 | |
| bogdanm | 0:9b334a45a8ff | 557 | /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode |
| bogdanm | 0:9b334a45a8ff | 558 | * @{ |
| bogdanm | 0:9b334a45a8ff | 559 | */ |
| bogdanm | 0:9b334a45a8ff | 560 | |
| bogdanm | 0:9b334a45a8ff | 561 | #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 562 | #define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD) |
| bogdanm | 0:9b334a45a8ff | 563 | |
| bogdanm | 0:9b334a45a8ff | 564 | /** |
| bogdanm | 0:9b334a45a8ff | 565 | * @} |
| bogdanm | 0:9b334a45a8ff | 566 | */ |
| bogdanm | 0:9b334a45a8ff | 567 | |
| bogdanm | 0:9b334a45a8ff | 568 | /** @defgroup FSMC_Wait_Timing FSMC Wait Timing |
| bogdanm | 0:9b334a45a8ff | 569 | * @{ |
| bogdanm | 0:9b334a45a8ff | 570 | */ |
| bogdanm | 0:9b334a45a8ff | 571 | |
| bogdanm | 0:9b334a45a8ff | 572 | #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 573 | #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG) |
| bogdanm | 0:9b334a45a8ff | 574 | |
| bogdanm | 0:9b334a45a8ff | 575 | /** |
| bogdanm | 0:9b334a45a8ff | 576 | * @} |
| bogdanm | 0:9b334a45a8ff | 577 | */ |
| bogdanm | 0:9b334a45a8ff | 578 | |
| bogdanm | 0:9b334a45a8ff | 579 | /** @defgroup FSMC_Write_Operation FSMC Write Operation |
| bogdanm | 0:9b334a45a8ff | 580 | * @{ |
| bogdanm | 0:9b334a45a8ff | 581 | */ |
| bogdanm | 0:9b334a45a8ff | 582 | |
| bogdanm | 0:9b334a45a8ff | 583 | #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 584 | #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN) |
| bogdanm | 0:9b334a45a8ff | 585 | |
| bogdanm | 0:9b334a45a8ff | 586 | /** |
| bogdanm | 0:9b334a45a8ff | 587 | * @} |
| bogdanm | 0:9b334a45a8ff | 588 | */ |
| bogdanm | 0:9b334a45a8ff | 589 | |
| bogdanm | 0:9b334a45a8ff | 590 | /** @defgroup FSMC_Wait_Signal FSMC Wait Signal |
| bogdanm | 0:9b334a45a8ff | 591 | * @{ |
| bogdanm | 0:9b334a45a8ff | 592 | */ |
| bogdanm | 0:9b334a45a8ff | 593 | |
| bogdanm | 0:9b334a45a8ff | 594 | #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 595 | #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN) |
| bogdanm | 0:9b334a45a8ff | 596 | |
| bogdanm | 0:9b334a45a8ff | 597 | /** |
| bogdanm | 0:9b334a45a8ff | 598 | * @} |
| bogdanm | 0:9b334a45a8ff | 599 | */ |
| bogdanm | 0:9b334a45a8ff | 600 | |
| bogdanm | 0:9b334a45a8ff | 601 | /** @defgroup FSMC_Extended_Mode FSMC Extended Mode |
| bogdanm | 0:9b334a45a8ff | 602 | * @{ |
| bogdanm | 0:9b334a45a8ff | 603 | */ |
| bogdanm | 0:9b334a45a8ff | 604 | |
| bogdanm | 0:9b334a45a8ff | 605 | #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 606 | #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD) |
| bogdanm | 0:9b334a45a8ff | 607 | |
| bogdanm | 0:9b334a45a8ff | 608 | /** |
| bogdanm | 0:9b334a45a8ff | 609 | * @} |
| bogdanm | 0:9b334a45a8ff | 610 | */ |
| bogdanm | 0:9b334a45a8ff | 611 | |
| bogdanm | 0:9b334a45a8ff | 612 | /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait |
| bogdanm | 0:9b334a45a8ff | 613 | * @{ |
| bogdanm | 0:9b334a45a8ff | 614 | */ |
| bogdanm | 0:9b334a45a8ff | 615 | |
| bogdanm | 0:9b334a45a8ff | 616 | #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 617 | #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT) |
| bogdanm | 0:9b334a45a8ff | 618 | |
| bogdanm | 0:9b334a45a8ff | 619 | /** |
| bogdanm | 0:9b334a45a8ff | 620 | * @} |
| bogdanm | 0:9b334a45a8ff | 621 | */ |
| bogdanm | 0:9b334a45a8ff | 622 | |
| bogdanm | 0:9b334a45a8ff | 623 | /** @defgroup FSMC_Write_Burst FSMC Write Burst |
| bogdanm | 0:9b334a45a8ff | 624 | * @{ |
| bogdanm | 0:9b334a45a8ff | 625 | */ |
| bogdanm | 0:9b334a45a8ff | 626 | |
| bogdanm | 0:9b334a45a8ff | 627 | #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 628 | #define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW) |
| bogdanm | 0:9b334a45a8ff | 629 | |
| bogdanm | 0:9b334a45a8ff | 630 | /** |
| bogdanm | 0:9b334a45a8ff | 631 | * @} |
| bogdanm | 0:9b334a45a8ff | 632 | */ |
| bogdanm | 0:9b334a45a8ff | 633 | |
| bogdanm | 0:9b334a45a8ff | 634 | /** @defgroup FSMC_Access_Mode FSMC Access Mode |
| bogdanm | 0:9b334a45a8ff | 635 | * @{ |
| bogdanm | 0:9b334a45a8ff | 636 | */ |
| bogdanm | 0:9b334a45a8ff | 637 | |
| bogdanm | 0:9b334a45a8ff | 638 | #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 639 | #define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0) |
| bogdanm | 0:9b334a45a8ff | 640 | #define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1) |
| bogdanm | 0:9b334a45a8ff | 641 | #define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1)) |
| bogdanm | 0:9b334a45a8ff | 642 | |
| bogdanm | 0:9b334a45a8ff | 643 | /** |
| bogdanm | 0:9b334a45a8ff | 644 | * @} |
| bogdanm | 0:9b334a45a8ff | 645 | */ |
| bogdanm | 0:9b334a45a8ff | 646 | |
| bogdanm | 0:9b334a45a8ff | 647 | |
| bogdanm | 0:9b334a45a8ff | 648 | /** |
| bogdanm | 0:9b334a45a8ff | 649 | * @} |
| bogdanm | 0:9b334a45a8ff | 650 | */ |
| bogdanm | 0:9b334a45a8ff | 651 | |
| bogdanm | 0:9b334a45a8ff | 652 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) |
| bogdanm | 0:9b334a45a8ff | 653 | /** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller |
| bogdanm | 0:9b334a45a8ff | 654 | * @{ |
| bogdanm | 0:9b334a45a8ff | 655 | */ |
| bogdanm | 0:9b334a45a8ff | 656 | |
| bogdanm | 0:9b334a45a8ff | 657 | /** @defgroup FSMC_NAND_Bank FSMC_NAND_Bank |
| bogdanm | 0:9b334a45a8ff | 658 | * @{ |
| bogdanm | 0:9b334a45a8ff | 659 | */ |
| bogdanm | 0:9b334a45a8ff | 660 | #define FSMC_NAND_BANK2 ((uint32_t)0x00000010) |
| bogdanm | 0:9b334a45a8ff | 661 | #define FSMC_NAND_BANK3 ((uint32_t)0x00000100) |
| bogdanm | 0:9b334a45a8ff | 662 | |
| bogdanm | 0:9b334a45a8ff | 663 | /** |
| bogdanm | 0:9b334a45a8ff | 664 | * @} |
| bogdanm | 0:9b334a45a8ff | 665 | */ |
| bogdanm | 0:9b334a45a8ff | 666 | |
| bogdanm | 0:9b334a45a8ff | 667 | /** @defgroup FSMC_Wait_feature FSMC_Wait_feature |
| bogdanm | 0:9b334a45a8ff | 668 | * @{ |
| bogdanm | 0:9b334a45a8ff | 669 | */ |
| bogdanm | 0:9b334a45a8ff | 670 | #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 671 | #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) |
| bogdanm | 0:9b334a45a8ff | 672 | |
| bogdanm | 0:9b334a45a8ff | 673 | /** |
| bogdanm | 0:9b334a45a8ff | 674 | * @} |
| bogdanm | 0:9b334a45a8ff | 675 | */ |
| bogdanm | 0:9b334a45a8ff | 676 | |
| bogdanm | 0:9b334a45a8ff | 677 | /** @defgroup FSMC_PCR_Memory_Type FSMC_PCR_Memory_Type |
| bogdanm | 0:9b334a45a8ff | 678 | * @{ |
| bogdanm | 0:9b334a45a8ff | 679 | */ |
| bogdanm | 0:9b334a45a8ff | 680 | #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 681 | #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FSMC_PCRx_PTYP) |
| bogdanm | 0:9b334a45a8ff | 682 | /** |
| bogdanm | 0:9b334a45a8ff | 683 | * @} |
| bogdanm | 0:9b334a45a8ff | 684 | */ |
| bogdanm | 0:9b334a45a8ff | 685 | |
| bogdanm | 0:9b334a45a8ff | 686 | /** @defgroup FSMC_NAND_Data_Width FSMC_NAND_Data_Width |
| bogdanm | 0:9b334a45a8ff | 687 | * @{ |
| bogdanm | 0:9b334a45a8ff | 688 | */ |
| bogdanm | 0:9b334a45a8ff | 689 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 690 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_PCRx_PWID_0) |
| bogdanm | 0:9b334a45a8ff | 691 | |
| bogdanm | 0:9b334a45a8ff | 692 | /** |
| bogdanm | 0:9b334a45a8ff | 693 | * @} |
| bogdanm | 0:9b334a45a8ff | 694 | */ |
| bogdanm | 0:9b334a45a8ff | 695 | |
| bogdanm | 0:9b334a45a8ff | 696 | /** @defgroup FSMC_ECC FSMC_ECC |
| bogdanm | 0:9b334a45a8ff | 697 | * @{ |
| bogdanm | 0:9b334a45a8ff | 698 | */ |
| bogdanm | 0:9b334a45a8ff | 699 | #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 700 | #define FSMC_NAND_ECC_ENABLE ((uint32_t)FSMC_PCRx_ECCEN) |
| bogdanm | 0:9b334a45a8ff | 701 | |
| bogdanm | 0:9b334a45a8ff | 702 | /** |
| bogdanm | 0:9b334a45a8ff | 703 | * @} |
| bogdanm | 0:9b334a45a8ff | 704 | */ |
| bogdanm | 0:9b334a45a8ff | 705 | |
| bogdanm | 0:9b334a45a8ff | 706 | /** @defgroup FSMC_ECC_Page_Size FSMC_ECC_Page_Size |
| bogdanm | 0:9b334a45a8ff | 707 | * @{ |
| bogdanm | 0:9b334a45a8ff | 708 | */ |
| bogdanm | 0:9b334a45a8ff | 709 | #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 710 | #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FSMC_PCRx_ECCPS_0) |
| bogdanm | 0:9b334a45a8ff | 711 | #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FSMC_PCRx_ECCPS_1) |
| bogdanm | 0:9b334a45a8ff | 712 | #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_1) |
| bogdanm | 0:9b334a45a8ff | 713 | #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FSMC_PCRx_ECCPS_2) |
| bogdanm | 0:9b334a45a8ff | 714 | #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_2) |
| bogdanm | 0:9b334a45a8ff | 715 | |
| bogdanm | 0:9b334a45a8ff | 716 | /** |
| bogdanm | 0:9b334a45a8ff | 717 | * @} |
| bogdanm | 0:9b334a45a8ff | 718 | */ |
| bogdanm | 0:9b334a45a8ff | 719 | |
| bogdanm | 0:9b334a45a8ff | 720 | /** @defgroup FSMC_Interrupt_definition FSMC_Interrupt_definition |
| bogdanm | 0:9b334a45a8ff | 721 | * @brief FSMC Interrupt definition |
| bogdanm | 0:9b334a45a8ff | 722 | * @{ |
| bogdanm | 0:9b334a45a8ff | 723 | */ |
| bogdanm | 0:9b334a45a8ff | 724 | #define FSMC_IT_RISING_EDGE ((uint32_t)FSMC_SRx_IREN) |
| bogdanm | 0:9b334a45a8ff | 725 | #define FSMC_IT_LEVEL ((uint32_t)FSMC_SRx_ILEN) |
| bogdanm | 0:9b334a45a8ff | 726 | #define FSMC_IT_FALLING_EDGE ((uint32_t)FSMC_SRx_IFEN) |
| bogdanm | 0:9b334a45a8ff | 727 | |
| bogdanm | 0:9b334a45a8ff | 728 | /** |
| bogdanm | 0:9b334a45a8ff | 729 | * @} |
| bogdanm | 0:9b334a45a8ff | 730 | */ |
| bogdanm | 0:9b334a45a8ff | 731 | |
| bogdanm | 0:9b334a45a8ff | 732 | /** @defgroup FSMC_Flag_definition FSMC_Flag_definition |
| bogdanm | 0:9b334a45a8ff | 733 | * @brief FSMC Flag definition |
| bogdanm | 0:9b334a45a8ff | 734 | * @{ |
| bogdanm | 0:9b334a45a8ff | 735 | */ |
| bogdanm | 0:9b334a45a8ff | 736 | #define FSMC_FLAG_RISING_EDGE ((uint32_t)FSMC_SRx_IRS) |
| bogdanm | 0:9b334a45a8ff | 737 | #define FSMC_FLAG_LEVEL ((uint32_t)FSMC_SRx_ILS) |
| bogdanm | 0:9b334a45a8ff | 738 | #define FSMC_FLAG_FALLING_EDGE ((uint32_t)FSMC_SRx_IFS) |
| bogdanm | 0:9b334a45a8ff | 739 | #define FSMC_FLAG_FEMPT ((uint32_t)FSMC_SRx_FEMPT) |
| bogdanm | 0:9b334a45a8ff | 740 | |
| bogdanm | 0:9b334a45a8ff | 741 | /** |
| bogdanm | 0:9b334a45a8ff | 742 | * @} |
| bogdanm | 0:9b334a45a8ff | 743 | */ |
| bogdanm | 0:9b334a45a8ff | 744 | |
| bogdanm | 0:9b334a45a8ff | 745 | /** |
| bogdanm | 0:9b334a45a8ff | 746 | * @} |
| bogdanm | 0:9b334a45a8ff | 747 | */ |
| bogdanm | 0:9b334a45a8ff | 748 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
| bogdanm | 0:9b334a45a8ff | 749 | |
| bogdanm | 0:9b334a45a8ff | 750 | /** |
| bogdanm | 0:9b334a45a8ff | 751 | * @} |
| bogdanm | 0:9b334a45a8ff | 752 | */ |
| bogdanm | 0:9b334a45a8ff | 753 | |
| bogdanm | 0:9b334a45a8ff | 754 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 755 | |
| bogdanm | 0:9b334a45a8ff | 756 | /** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros |
| bogdanm | 0:9b334a45a8ff | 757 | * @{ |
| bogdanm | 0:9b334a45a8ff | 758 | */ |
| bogdanm | 0:9b334a45a8ff | 759 | |
| bogdanm | 0:9b334a45a8ff | 760 | /** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros |
| bogdanm | 0:9b334a45a8ff | 761 | * @brief macros to handle NOR device enable/disable and read/write operations |
| bogdanm | 0:9b334a45a8ff | 762 | * @{ |
| bogdanm | 0:9b334a45a8ff | 763 | */ |
| bogdanm | 0:9b334a45a8ff | 764 | |
| bogdanm | 0:9b334a45a8ff | 765 | /** |
| bogdanm | 0:9b334a45a8ff | 766 | * @brief Enable the NORSRAM device access. |
| bogdanm | 0:9b334a45a8ff | 767 | * @param __INSTANCE__: FSMC_NORSRAM Instance |
| bogdanm | 0:9b334a45a8ff | 768 | * @param __BANK__: FSMC_NORSRAM Bank |
| bogdanm | 0:9b334a45a8ff | 769 | * @retval none |
| bogdanm | 0:9b334a45a8ff | 770 | */ |
| bogdanm | 0:9b334a45a8ff | 771 | #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN) |
| bogdanm | 0:9b334a45a8ff | 772 | |
| bogdanm | 0:9b334a45a8ff | 773 | /** |
| bogdanm | 0:9b334a45a8ff | 774 | * @brief Disable the NORSRAM device access. |
| bogdanm | 0:9b334a45a8ff | 775 | * @param __INSTANCE__: FSMC_NORSRAM Instance |
| bogdanm | 0:9b334a45a8ff | 776 | * @param __BANK__: FSMC_NORSRAM Bank |
| bogdanm | 0:9b334a45a8ff | 777 | * @retval none |
| bogdanm | 0:9b334a45a8ff | 778 | */ |
| bogdanm | 0:9b334a45a8ff | 779 | #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN) |
| bogdanm | 0:9b334a45a8ff | 780 | |
| bogdanm | 0:9b334a45a8ff | 781 | /** |
| bogdanm | 0:9b334a45a8ff | 782 | * @} |
| bogdanm | 0:9b334a45a8ff | 783 | */ |
| bogdanm | 0:9b334a45a8ff | 784 | |
| bogdanm | 0:9b334a45a8ff | 785 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) |
| bogdanm | 0:9b334a45a8ff | 786 | /** @defgroup FSMC_NAND_Macros FSMC_NAND_Macros |
| bogdanm | 0:9b334a45a8ff | 787 | * @brief macros to handle NAND device enable/disable |
| bogdanm | 0:9b334a45a8ff | 788 | * @{ |
| bogdanm | 0:9b334a45a8ff | 789 | */ |
| bogdanm | 0:9b334a45a8ff | 790 | |
| bogdanm | 0:9b334a45a8ff | 791 | /** |
| bogdanm | 0:9b334a45a8ff | 792 | * @brief Enable the NAND device access. |
| bogdanm | 0:9b334a45a8ff | 793 | * @param __INSTANCE__: FSMC_NAND Instance |
| bogdanm | 0:9b334a45a8ff | 794 | * @param __BANK__: FSMC_NAND Bank |
| bogdanm | 0:9b334a45a8ff | 795 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 796 | */ |
| bogdanm | 0:9b334a45a8ff | 797 | #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \ |
| bogdanm | 0:9b334a45a8ff | 798 | SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) |
| bogdanm | 0:9b334a45a8ff | 799 | |
| bogdanm | 0:9b334a45a8ff | 800 | /** |
| bogdanm | 0:9b334a45a8ff | 801 | * @brief Disable the NAND device access. |
| bogdanm | 0:9b334a45a8ff | 802 | * @param __INSTANCE__: FSMC_NAND Instance |
| bogdanm | 0:9b334a45a8ff | 803 | * @param __BANK__: FSMC_NAND Bank |
| bogdanm | 0:9b334a45a8ff | 804 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 805 | */ |
| bogdanm | 0:9b334a45a8ff | 806 | #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \ |
| bogdanm | 0:9b334a45a8ff | 807 | CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) |
| bogdanm | 0:9b334a45a8ff | 808 | /** |
| bogdanm | 0:9b334a45a8ff | 809 | * @} |
| bogdanm | 0:9b334a45a8ff | 810 | */ |
| bogdanm | 0:9b334a45a8ff | 811 | |
| bogdanm | 0:9b334a45a8ff | 812 | /** @defgroup FSMC_PCCARD_Macros FSMC_PCCARD_Macros |
| bogdanm | 0:9b334a45a8ff | 813 | * @brief macros to handle SRAM read/write operations |
| bogdanm | 0:9b334a45a8ff | 814 | * @{ |
| bogdanm | 0:9b334a45a8ff | 815 | */ |
| bogdanm | 0:9b334a45a8ff | 816 | |
| bogdanm | 0:9b334a45a8ff | 817 | /** |
| bogdanm | 0:9b334a45a8ff | 818 | * @brief Enable the PCCARD device access. |
| bogdanm | 0:9b334a45a8ff | 819 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| bogdanm | 0:9b334a45a8ff | 820 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 821 | */ |
| bogdanm | 0:9b334a45a8ff | 822 | #define __FSMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN) |
| bogdanm | 0:9b334a45a8ff | 823 | |
| bogdanm | 0:9b334a45a8ff | 824 | /** |
| bogdanm | 0:9b334a45a8ff | 825 | * @brief Disable the PCCARD device access. |
| bogdanm | 0:9b334a45a8ff | 826 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| bogdanm | 0:9b334a45a8ff | 827 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 828 | */ |
| bogdanm | 0:9b334a45a8ff | 829 | #define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN) |
| bogdanm | 0:9b334a45a8ff | 830 | /** |
| bogdanm | 0:9b334a45a8ff | 831 | * @} |
| bogdanm | 0:9b334a45a8ff | 832 | */ |
| bogdanm | 0:9b334a45a8ff | 833 | |
| bogdanm | 0:9b334a45a8ff | 834 | /** @defgroup FSMC_Interrupt FSMC_Interrupt |
| bogdanm | 0:9b334a45a8ff | 835 | * @brief macros to handle FSMC interrupts |
| bogdanm | 0:9b334a45a8ff | 836 | * @{ |
| bogdanm | 0:9b334a45a8ff | 837 | */ |
| bogdanm | 0:9b334a45a8ff | 838 | |
| bogdanm | 0:9b334a45a8ff | 839 | /** |
| bogdanm | 0:9b334a45a8ff | 840 | * @brief Enable the NAND device interrupt. |
| bogdanm | 0:9b334a45a8ff | 841 | * @param __INSTANCE__: FSMC_NAND Instance |
| bogdanm | 0:9b334a45a8ff | 842 | * @param __BANK__: FSMC_NAND Bank |
| bogdanm | 0:9b334a45a8ff | 843 | * @param __INTERRUPT__: FSMC_NAND interrupt |
| bogdanm | 0:9b334a45a8ff | 844 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 845 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| bogdanm | 0:9b334a45a8ff | 846 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| bogdanm | 0:9b334a45a8ff | 847 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| bogdanm | 0:9b334a45a8ff | 848 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 849 | */ |
| bogdanm | 0:9b334a45a8ff | 850 | #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \ |
| bogdanm | 0:9b334a45a8ff | 851 | SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__))) |
| bogdanm | 0:9b334a45a8ff | 852 | |
| bogdanm | 0:9b334a45a8ff | 853 | /** |
| bogdanm | 0:9b334a45a8ff | 854 | * @brief Disable the NAND device interrupt. |
| bogdanm | 0:9b334a45a8ff | 855 | * @param __INSTANCE__: FSMC_NAND Instance |
| bogdanm | 0:9b334a45a8ff | 856 | * @param __BANK__: FSMC_NAND Bank |
| bogdanm | 0:9b334a45a8ff | 857 | * @param __INTERRUPT__: FSMC_NAND interrupt |
| bogdanm | 0:9b334a45a8ff | 858 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 859 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| bogdanm | 0:9b334a45a8ff | 860 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| bogdanm | 0:9b334a45a8ff | 861 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| bogdanm | 0:9b334a45a8ff | 862 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 863 | */ |
| bogdanm | 0:9b334a45a8ff | 864 | #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \ |
| bogdanm | 0:9b334a45a8ff | 865 | CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__))) |
| bogdanm | 0:9b334a45a8ff | 866 | |
| bogdanm | 0:9b334a45a8ff | 867 | /** |
| bogdanm | 0:9b334a45a8ff | 868 | * @brief Get flag status of the NAND device. |
| bogdanm | 0:9b334a45a8ff | 869 | * @param __INSTANCE__: FSMC_NAND Instance |
| bogdanm | 0:9b334a45a8ff | 870 | * @param __BANK__: FSMC_NAND Bank |
| bogdanm | 0:9b334a45a8ff | 871 | * @param __FLAG__: FSMC_NAND flag |
| bogdanm | 0:9b334a45a8ff | 872 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 873 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| bogdanm | 0:9b334a45a8ff | 874 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| bogdanm | 0:9b334a45a8ff | 875 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| bogdanm | 0:9b334a45a8ff | 876 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| bogdanm | 0:9b334a45a8ff | 877 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 0:9b334a45a8ff | 878 | */ |
| bogdanm | 0:9b334a45a8ff | 879 | #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ |
| bogdanm | 0:9b334a45a8ff | 880 | (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) |
| bogdanm | 0:9b334a45a8ff | 881 | /** |
| bogdanm | 0:9b334a45a8ff | 882 | * @brief Clear flag status of the NAND device. |
| bogdanm | 0:9b334a45a8ff | 883 | * @param __INSTANCE__: FSMC_NAND Instance |
| bogdanm | 0:9b334a45a8ff | 884 | * @param __BANK__: FSMC_NAND Bank |
| bogdanm | 0:9b334a45a8ff | 885 | * @param __FLAG__: FSMC_NAND flag |
| bogdanm | 0:9b334a45a8ff | 886 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 887 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| bogdanm | 0:9b334a45a8ff | 888 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| bogdanm | 0:9b334a45a8ff | 889 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| bogdanm | 0:9b334a45a8ff | 890 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| bogdanm | 0:9b334a45a8ff | 891 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 892 | */ |
| bogdanm | 0:9b334a45a8ff | 893 | #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \ |
| bogdanm | 0:9b334a45a8ff | 894 | CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__))) |
| bogdanm | 0:9b334a45a8ff | 895 | /** |
| bogdanm | 0:9b334a45a8ff | 896 | * @brief Enable the PCCARD device interrupt. |
| bogdanm | 0:9b334a45a8ff | 897 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| bogdanm | 0:9b334a45a8ff | 898 | * @param __INTERRUPT__: FSMC_PCCARD interrupt |
| bogdanm | 0:9b334a45a8ff | 899 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 900 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| bogdanm | 0:9b334a45a8ff | 901 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| bogdanm | 0:9b334a45a8ff | 902 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| bogdanm | 0:9b334a45a8ff | 903 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 904 | */ |
| bogdanm | 0:9b334a45a8ff | 905 | #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 906 | |
| bogdanm | 0:9b334a45a8ff | 907 | /** |
| bogdanm | 0:9b334a45a8ff | 908 | * @brief Disable the PCCARD device interrupt. |
| bogdanm | 0:9b334a45a8ff | 909 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| bogdanm | 0:9b334a45a8ff | 910 | * @param __INTERRUPT__: FSMC_PCCARD interrupt |
| bogdanm | 0:9b334a45a8ff | 911 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 912 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| bogdanm | 0:9b334a45a8ff | 913 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| bogdanm | 0:9b334a45a8ff | 914 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| bogdanm | 0:9b334a45a8ff | 915 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 916 | */ |
| bogdanm | 0:9b334a45a8ff | 917 | #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__)) |
| bogdanm | 0:9b334a45a8ff | 918 | |
| bogdanm | 0:9b334a45a8ff | 919 | /** |
| bogdanm | 0:9b334a45a8ff | 920 | * @brief Get flag status of the PCCARD device. |
| bogdanm | 0:9b334a45a8ff | 921 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| bogdanm | 0:9b334a45a8ff | 922 | * @param __FLAG__: FSMC_PCCARD flag |
| bogdanm | 0:9b334a45a8ff | 923 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 924 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| bogdanm | 0:9b334a45a8ff | 925 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| bogdanm | 0:9b334a45a8ff | 926 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| bogdanm | 0:9b334a45a8ff | 927 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| bogdanm | 0:9b334a45a8ff | 928 | * @retval The state of FLAG (SET or RESET). |
| bogdanm | 0:9b334a45a8ff | 929 | */ |
| bogdanm | 0:9b334a45a8ff | 930 | #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 931 | |
| bogdanm | 0:9b334a45a8ff | 932 | /** |
| bogdanm | 0:9b334a45a8ff | 933 | * @brief Clear flag status of the PCCARD device. |
| bogdanm | 0:9b334a45a8ff | 934 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| bogdanm | 0:9b334a45a8ff | 935 | * @param __FLAG__: FSMC_PCCARD flag |
| bogdanm | 0:9b334a45a8ff | 936 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 937 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| bogdanm | 0:9b334a45a8ff | 938 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| bogdanm | 0:9b334a45a8ff | 939 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| bogdanm | 0:9b334a45a8ff | 940 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| bogdanm | 0:9b334a45a8ff | 941 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 942 | */ |
| bogdanm | 0:9b334a45a8ff | 943 | #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__)) |
| bogdanm | 0:9b334a45a8ff | 944 | |
| bogdanm | 0:9b334a45a8ff | 945 | /** |
| bogdanm | 0:9b334a45a8ff | 946 | * @} |
| bogdanm | 0:9b334a45a8ff | 947 | */ |
| bogdanm | 0:9b334a45a8ff | 948 | |
| bogdanm | 0:9b334a45a8ff | 949 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
| bogdanm | 0:9b334a45a8ff | 950 | |
| bogdanm | 0:9b334a45a8ff | 951 | /** |
| bogdanm | 0:9b334a45a8ff | 952 | * @} |
| bogdanm | 0:9b334a45a8ff | 953 | */ |
| bogdanm | 0:9b334a45a8ff | 954 | |
| bogdanm | 0:9b334a45a8ff | 955 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 956 | |
| bogdanm | 0:9b334a45a8ff | 957 | /** @addtogroup FSMC_LL_Exported_Functions |
| bogdanm | 0:9b334a45a8ff | 958 | * @{ |
| bogdanm | 0:9b334a45a8ff | 959 | */ |
| bogdanm | 0:9b334a45a8ff | 960 | |
| bogdanm | 0:9b334a45a8ff | 961 | /** @addtogroup FSMC_NORSRAM |
| bogdanm | 0:9b334a45a8ff | 962 | * @{ |
| bogdanm | 0:9b334a45a8ff | 963 | */ |
| bogdanm | 0:9b334a45a8ff | 964 | |
| bogdanm | 0:9b334a45a8ff | 965 | /** @addtogroup FSMC_NORSRAM_Group1 |
| bogdanm | 0:9b334a45a8ff | 966 | * @{ |
| bogdanm | 0:9b334a45a8ff | 967 | */ |
| bogdanm | 0:9b334a45a8ff | 968 | |
| bogdanm | 0:9b334a45a8ff | 969 | /* FSMC_NORSRAM Controller functions ******************************************/ |
| bogdanm | 0:9b334a45a8ff | 970 | /* Initialization/de-initialization functions */ |
| bogdanm | 0:9b334a45a8ff | 971 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); |
| bogdanm | 0:9b334a45a8ff | 972 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 973 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
| bogdanm | 0:9b334a45a8ff | 974 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 975 | |
| bogdanm | 0:9b334a45a8ff | 976 | /** |
| bogdanm | 0:9b334a45a8ff | 977 | * @} |
| bogdanm | 0:9b334a45a8ff | 978 | */ |
| bogdanm | 0:9b334a45a8ff | 979 | |
| bogdanm | 0:9b334a45a8ff | 980 | /** @addtogroup FSMC_NORSRAM_Group2 |
| bogdanm | 0:9b334a45a8ff | 981 | * @{ |
| bogdanm | 0:9b334a45a8ff | 982 | */ |
| bogdanm | 0:9b334a45a8ff | 983 | |
| bogdanm | 0:9b334a45a8ff | 984 | /* FSMC_NORSRAM Control functions */ |
| bogdanm | 0:9b334a45a8ff | 985 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 986 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 987 | |
| bogdanm | 0:9b334a45a8ff | 988 | /** |
| bogdanm | 0:9b334a45a8ff | 989 | * @} |
| bogdanm | 0:9b334a45a8ff | 990 | */ |
| bogdanm | 0:9b334a45a8ff | 991 | |
| bogdanm | 0:9b334a45a8ff | 992 | /** |
| bogdanm | 0:9b334a45a8ff | 993 | * @} |
| bogdanm | 0:9b334a45a8ff | 994 | */ |
| bogdanm | 0:9b334a45a8ff | 995 | |
| bogdanm | 0:9b334a45a8ff | 996 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) |
| bogdanm | 0:9b334a45a8ff | 997 | /** @addtogroup FSMC_NAND |
| bogdanm | 0:9b334a45a8ff | 998 | * @{ |
| bogdanm | 0:9b334a45a8ff | 999 | */ |
| bogdanm | 0:9b334a45a8ff | 1000 | |
| bogdanm | 0:9b334a45a8ff | 1001 | /* FSMC_NAND Controller functions **********************************************/ |
| bogdanm | 0:9b334a45a8ff | 1002 | /* Initialization/de-initialization functions */ |
| bogdanm | 0:9b334a45a8ff | 1003 | /** @addtogroup FSMC_NAND_Exported_Functions_Group1 |
| bogdanm | 0:9b334a45a8ff | 1004 | * @{ |
| bogdanm | 0:9b334a45a8ff | 1005 | */ |
| bogdanm | 0:9b334a45a8ff | 1006 | |
| bogdanm | 0:9b334a45a8ff | 1007 | HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); |
| bogdanm | 0:9b334a45a8ff | 1008 | HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 1009 | HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 1010 | HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 1011 | |
| bogdanm | 0:9b334a45a8ff | 1012 | /** |
| bogdanm | 0:9b334a45a8ff | 1013 | * @} |
| bogdanm | 0:9b334a45a8ff | 1014 | */ |
| bogdanm | 0:9b334a45a8ff | 1015 | |
| bogdanm | 0:9b334a45a8ff | 1016 | /* FSMC_NAND Control functions */ |
| bogdanm | 0:9b334a45a8ff | 1017 | /** @addtogroup FSMC_NAND_Exported_Functions_Group2 |
| bogdanm | 0:9b334a45a8ff | 1018 | * @{ |
| bogdanm | 0:9b334a45a8ff | 1019 | */ |
| bogdanm | 0:9b334a45a8ff | 1020 | |
| bogdanm | 0:9b334a45a8ff | 1021 | HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 1022 | HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| bogdanm | 0:9b334a45a8ff | 1023 | HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); |
| bogdanm | 0:9b334a45a8ff | 1024 | |
| bogdanm | 0:9b334a45a8ff | 1025 | /** |
| bogdanm | 0:9b334a45a8ff | 1026 | * @} |
| bogdanm | 0:9b334a45a8ff | 1027 | */ |
| bogdanm | 0:9b334a45a8ff | 1028 | |
| bogdanm | 0:9b334a45a8ff | 1029 | /** |
| bogdanm | 0:9b334a45a8ff | 1030 | * @} |
| bogdanm | 0:9b334a45a8ff | 1031 | */ |
| bogdanm | 0:9b334a45a8ff | 1032 | |
| bogdanm | 0:9b334a45a8ff | 1033 | /** @addtogroup FSMC_PCCARD |
| bogdanm | 0:9b334a45a8ff | 1034 | * @{ |
| bogdanm | 0:9b334a45a8ff | 1035 | */ |
| bogdanm | 0:9b334a45a8ff | 1036 | |
| bogdanm | 0:9b334a45a8ff | 1037 | /* FSMC_PCCARD Controller functions ********************************************/ |
| bogdanm | 0:9b334a45a8ff | 1038 | /* Initialization/de-initialization functions */ |
| bogdanm | 0:9b334a45a8ff | 1039 | /** @addtogroup FSMC_PCCARD_Exported_Functions_Group1 |
| bogdanm | 0:9b334a45a8ff | 1040 | * @{ |
| bogdanm | 0:9b334a45a8ff | 1041 | */ |
| bogdanm | 0:9b334a45a8ff | 1042 | |
| bogdanm | 0:9b334a45a8ff | 1043 | HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); |
| bogdanm | 0:9b334a45a8ff | 1044 | HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| bogdanm | 0:9b334a45a8ff | 1045 | HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| bogdanm | 0:9b334a45a8ff | 1046 | HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| bogdanm | 0:9b334a45a8ff | 1047 | HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); |
| bogdanm | 0:9b334a45a8ff | 1048 | |
| bogdanm | 0:9b334a45a8ff | 1049 | /** |
| bogdanm | 0:9b334a45a8ff | 1050 | * @} |
| bogdanm | 0:9b334a45a8ff | 1051 | */ |
| bogdanm | 0:9b334a45a8ff | 1052 | |
| bogdanm | 0:9b334a45a8ff | 1053 | /** |
| bogdanm | 0:9b334a45a8ff | 1054 | * @} |
| bogdanm | 0:9b334a45a8ff | 1055 | */ |
| bogdanm | 0:9b334a45a8ff | 1056 | |
| bogdanm | 0:9b334a45a8ff | 1057 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
| bogdanm | 0:9b334a45a8ff | 1058 | |
| bogdanm | 0:9b334a45a8ff | 1059 | /** |
| bogdanm | 0:9b334a45a8ff | 1060 | * @} |
| bogdanm | 0:9b334a45a8ff | 1061 | */ |
| bogdanm | 0:9b334a45a8ff | 1062 | |
| bogdanm | 0:9b334a45a8ff | 1063 | /** |
| bogdanm | 0:9b334a45a8ff | 1064 | * @} |
| bogdanm | 0:9b334a45a8ff | 1065 | */ |
| bogdanm | 0:9b334a45a8ff | 1066 | |
| bogdanm | 0:9b334a45a8ff | 1067 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ |
| bogdanm | 0:9b334a45a8ff | 1068 | |
| bogdanm | 0:9b334a45a8ff | 1069 | /** |
| bogdanm | 0:9b334a45a8ff | 1070 | * @} |
| bogdanm | 0:9b334a45a8ff | 1071 | */ |
| bogdanm | 0:9b334a45a8ff | 1072 | |
| bogdanm | 0:9b334a45a8ff | 1073 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 1074 | } |
| bogdanm | 0:9b334a45a8ff | 1075 | #endif |
| bogdanm | 0:9b334a45a8ff | 1076 | |
| bogdanm | 0:9b334a45a8ff | 1077 | #endif /* __STM32F1xx_LL_FSMC_H */ |
| bogdanm | 0:9b334a45a8ff | 1078 | |
| bogdanm | 0:9b334a45a8ff | 1079 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| bogdanm | 0:9b334a45a8ff | 1080 |