mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 124:6a4a5b7d7324

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f1xx_hal_rcc.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 15-December-2014
bogdanm	0:9b334a45a8ff	7	* @brief Header file of RCC HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F1xx_HAL_RCC_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F1xx_HAL_RCC_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32f1xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32F1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup RCC
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/** @addtogroup RCC_Private_Constants
bogdanm	0:9b334a45a8ff	58	* @{
bogdanm	0:9b334a45a8ff	59	*/
bogdanm	0:9b334a45a8ff	60
bogdanm	0:9b334a45a8ff	61	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
bogdanm	0:9b334a45a8ff	62	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
bogdanm	0:9b334a45a8ff	63	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
bogdanm	0:9b334a45a8ff	64	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
bogdanm	0:9b334a45a8ff	65	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	66	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	67	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm	0:9b334a45a8ff	68	#define LSI_VALUE ((uint32_t)40000) /* 40kHz */
bogdanm	0:9b334a45a8ff	69
bogdanm	0:9b334a45a8ff	70	/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
bogdanm	0:9b334a45a8ff	71	* @brief RCC registers bit address in the alias region
bogdanm	0:9b334a45a8ff	72	* @{
bogdanm	0:9b334a45a8ff	73	*/
bogdanm	0:9b334a45a8ff	74	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm	0:9b334a45a8ff	75	#define RCC_CR_OFFSET 0x00
bogdanm	0:9b334a45a8ff	76	#define RCC_CFGR_OFFSET 0x04
bogdanm	0:9b334a45a8ff	77	#define RCC_CIR_OFFSET 0x08
bogdanm	0:9b334a45a8ff	78	#define RCC_BDCR_OFFSET 0x20
bogdanm	0:9b334a45a8ff	79	#define RCC_CSR_OFFSET 0x24
bogdanm	0:9b334a45a8ff	80	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
bogdanm	0:9b334a45a8ff	81	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
bogdanm	0:9b334a45a8ff	82	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
bogdanm	0:9b334a45a8ff	83	#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
bogdanm	0:9b334a45a8ff	84	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	/* --- CR Register ---*/
bogdanm	0:9b334a45a8ff	87	/* Alias word address of HSION bit */
bogdanm	0:9b334a45a8ff	88	#define HSION_BITNUMBER POSITION_VAL(RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	89	#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4)))
bogdanm	0:9b334a45a8ff	90	/* Alias word address of HSEON bit */
bogdanm	0:9b334a45a8ff	91	#define HSEON_BITNUMBER POSITION_VAL(RCC_CR_HSEON)
bogdanm	0:9b334a45a8ff	92	#define CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4)))
bogdanm	0:9b334a45a8ff	93	/* Alias word address of CSSON bit */
bogdanm	0:9b334a45a8ff	94	#define CSSON_BITNUMBER POSITION_VAL(RCC_CR_CSSON)
bogdanm	0:9b334a45a8ff	95	#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4)))
bogdanm	0:9b334a45a8ff	96	/* Alias word address of PLLON bit */
bogdanm	0:9b334a45a8ff	97	#define PLLON_BITNUMBER POSITION_VAL(RCC_CR_PLLON)
bogdanm	0:9b334a45a8ff	98	#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4)))
bogdanm	0:9b334a45a8ff	99
bogdanm	0:9b334a45a8ff	100	/* --- CSR Register ---*/
bogdanm	0:9b334a45a8ff	101	/* Alias word address of LSION bit */
bogdanm	0:9b334a45a8ff	102	#define LSION_BITNUMBER POSITION_VAL(RCC_CSR_LSION)
bogdanm	0:9b334a45a8ff	103	#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4)))
bogdanm	0:9b334a45a8ff	104
bogdanm	0:9b334a45a8ff	105	/* --- BDCR Register ---*/
bogdanm	0:9b334a45a8ff	106	/* Alias word address of LSEON bit */
bogdanm	0:9b334a45a8ff	107	#define LSEON_BITNUMBER POSITION_VAL(RCC_BDCR_LSEON)
bogdanm	0:9b334a45a8ff	108	#define BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4)))
bogdanm	0:9b334a45a8ff	109
bogdanm	0:9b334a45a8ff	110	/* Alias word address of LSEON bit */
bogdanm	0:9b334a45a8ff	111	#define LSEBYP_BITNUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
bogdanm	0:9b334a45a8ff	112	#define BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4)))
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	/* Alias word address of RTCEN bit */
bogdanm	0:9b334a45a8ff	115	#define RTCEN_BITNUMBER POSITION_VAL(RCC_BDCR_RTCEN)
bogdanm	0:9b334a45a8ff	116	#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4)))
bogdanm	0:9b334a45a8ff	117
bogdanm	0:9b334a45a8ff	118	/* Alias word address of BDRST bit */
bogdanm	0:9b334a45a8ff	119	#define BDRST_BITNUMBER POSITION_VAL(RCC_BDCR_BDRST)
bogdanm	0:9b334a45a8ff	120	#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (BDRST_BITNUMBER * 4)))
bogdanm	0:9b334a45a8ff	121
bogdanm	0:9b334a45a8ff	122	/* CR register byte 2 (Bits[23:16]) base address */
bogdanm	0:9b334a45a8ff	123	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
bogdanm	0:9b334a45a8ff	124
bogdanm	0:9b334a45a8ff	125	/* CIR register byte 1 (Bits[15:8]) base address */
bogdanm	0:9b334a45a8ff	126	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	/* CIR register byte 2 (Bits[23:16]) base address */
bogdanm	0:9b334a45a8ff	129	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	/* Defines used for Flags */
bogdanm	0:9b334a45a8ff	132	#define CR_REG_INDEX ((uint8_t)1)
bogdanm	0:9b334a45a8ff	133	#define BDCR_REG_INDEX ((uint8_t)2)
bogdanm	0:9b334a45a8ff	134	#define CSR_REG_INDEX ((uint8_t)3)
bogdanm	0:9b334a45a8ff	135
bogdanm	0:9b334a45a8ff	136	#define RCC_FLAG_MASK ((uint8_t)0x1F)
bogdanm	0:9b334a45a8ff	137
bogdanm	0:9b334a45a8ff	138	/**
bogdanm	0:9b334a45a8ff	139	* @}
bogdanm	0:9b334a45a8ff	140	*/
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/** @addtogroup RCC_Private_Macros
bogdanm	0:9b334a45a8ff	143	* @{
bogdanm	0:9b334a45a8ff	144	*/
bogdanm	0:9b334a45a8ff	145
bogdanm	0:9b334a45a8ff	146	/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
bogdanm	0:9b334a45a8ff	147	* @{
bogdanm	0:9b334a45a8ff	148	*/
bogdanm	0:9b334a45a8ff	149	#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
bogdanm	0:9b334a45a8ff	150	#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
bogdanm	0:9b334a45a8ff	151	#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
bogdanm	0:9b334a45a8ff	152	#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
bogdanm	0:9b334a45a8ff	153	/**
bogdanm	0:9b334a45a8ff	154	* @}
bogdanm	0:9b334a45a8ff	155	*/
bogdanm	0:9b334a45a8ff	156
bogdanm	0:9b334a45a8ff	157	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
bogdanm	0:9b334a45a8ff	160
bogdanm	0:9b334a45a8ff	161	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
bogdanm	0:9b334a45a8ff	162
bogdanm	0:9b334a45a8ff	163	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
bogdanm	0:9b334a45a8ff	164	((__HSE__) == RCC_HSE_BYPASS))
bogdanm	0:9b334a45a8ff	165
bogdanm	0:9b334a45a8ff	166	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
bogdanm	0:9b334a45a8ff	167	((__LSE__) == RCC_LSE_BYPASS))
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	170	((__SOURCE__) == RCC_PLLSOURCE_HSE))
bogdanm	0:9b334a45a8ff	171
bogdanm	0:9b334a45a8ff	172	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	173	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	174	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	175	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	176	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
bogdanm	0:9b334a45a8ff	177
bogdanm	0:9b334a45a8ff	178	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
bogdanm	0:9b334a45a8ff	179
bogdanm	0:9b334a45a8ff	180	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
bogdanm	0:9b334a45a8ff	181	((__PLL__) == RCC_PLL_ON))
bogdanm	0:9b334a45a8ff	182
bogdanm	0:9b334a45a8ff	183	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	184	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	185	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm	0:9b334a45a8ff	186
bogdanm	0:9b334a45a8ff	187	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	188	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	189	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
bogdanm	0:9b334a45a8ff	190	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
bogdanm	0:9b334a45a8ff	191	((__HCLK__) == RCC_SYSCLK_DIV512))
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	194	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	195	((__PCLK__) == RCC_HCLK_DIV16))
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
bogdanm	0:9b334a45a8ff	198
bogdanm	0:9b334a45a8ff	199	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	/**
bogdanm	0:9b334a45a8ff	202	* @}
bogdanm	0:9b334a45a8ff	203	*/
bogdanm	0:9b334a45a8ff	204
bogdanm	0:9b334a45a8ff	205	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	206
bogdanm	0:9b334a45a8ff	207	/** @defgroup RCC_Exported_Types RCC Exported Types
bogdanm	0:9b334a45a8ff	208	* @{
bogdanm	0:9b334a45a8ff	209	*/
bogdanm	0:9b334a45a8ff	210
bogdanm	0:9b334a45a8ff	211	/**
bogdanm	0:9b334a45a8ff	212	* @brief RCC PLL configuration structure definition
bogdanm	0:9b334a45a8ff	213	*/
bogdanm	0:9b334a45a8ff	214	typedef struct
bogdanm	0:9b334a45a8ff	215	{
bogdanm	0:9b334a45a8ff	216	uint32_t PLLState; /*!< The new state of the PLL.
bogdanm	0:9b334a45a8ff	217	This parameter can be a value of @ref __HAL_RCC_PLL_CONFIG */
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
bogdanm	0:9b334a45a8ff	220	This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm	0:9b334a45a8ff	221
bogdanm	0:9b334a45a8ff	222	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
bogdanm	0:9b334a45a8ff	223	This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
bogdanm	0:9b334a45a8ff	224	} RCC_PLLInitTypeDef;
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	/**
bogdanm	0:9b334a45a8ff	227	* @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm	0:9b334a45a8ff	228	*/
bogdanm	0:9b334a45a8ff	229	typedef struct
bogdanm	0:9b334a45a8ff	230	{
bogdanm	0:9b334a45a8ff	231	uint32_t ClockType; /*!< The clock to be configured.
bogdanm	0:9b334a45a8ff	232	This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm	0:9b334a45a8ff	233
bogdanm	0:9b334a45a8ff	234	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm	0:9b334a45a8ff	235	This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm	0:9b334a45a8ff	236
bogdanm	0:9b334a45a8ff	237	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm	0:9b334a45a8ff	238	This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm	0:9b334a45a8ff	239
bogdanm	0:9b334a45a8ff	240	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	0:9b334a45a8ff	241	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	0:9b334a45a8ff	244	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	} RCC_ClkInitTypeDef;
bogdanm	0:9b334a45a8ff	247
bogdanm	0:9b334a45a8ff	248	/**
bogdanm	0:9b334a45a8ff	249	* @}
bogdanm	0:9b334a45a8ff	250	*/
bogdanm	0:9b334a45a8ff	251
bogdanm	0:9b334a45a8ff	252	/**
bogdanm	0:9b334a45a8ff	253	* @}
bogdanm	0:9b334a45a8ff	254	*/
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	257	/** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm	0:9b334a45a8ff	258	* @{
bogdanm	0:9b334a45a8ff	259	*/
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
bogdanm	0:9b334a45a8ff	262	* @{
bogdanm	0:9b334a45a8ff	263	*/
bogdanm	0:9b334a45a8ff	264
bogdanm	0:9b334a45a8ff	265	#define RCC_PLLSOURCE_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
bogdanm	0:9b334a45a8ff	266	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /!< HSE clock selected as PLL entry clock source /
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	/**
bogdanm	0:9b334a45a8ff	269	* @}
bogdanm	0:9b334a45a8ff	270	*/
bogdanm	0:9b334a45a8ff	271
bogdanm	0:9b334a45a8ff	272	/** @defgroup RCC_Oscillator_Type Oscillator Type
bogdanm	0:9b334a45a8ff	273	* @{
bogdanm	0:9b334a45a8ff	274	*/
bogdanm	0:9b334a45a8ff	275	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	276	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	277	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	278	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	279	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	/**
bogdanm	0:9b334a45a8ff	282	* @}
bogdanm	0:9b334a45a8ff	283	*/
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	/** @defgroup __HAL_RCC_HSE_CONFIG HSE Config
bogdanm	0:9b334a45a8ff	286	* @{
bogdanm	0:9b334a45a8ff	287	*/
bogdanm	0:9b334a45a8ff	288	#define RCC_HSE_OFF ((uint32_t)0x00000000) /!< HSE clock deactivation /
bogdanm	0:9b334a45a8ff	289	#define RCC_HSE_ON ((uint32_t)0x00000001) /!< HSE clock activation /
bogdanm	0:9b334a45a8ff	290	#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for HSE clock /
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/**
bogdanm	0:9b334a45a8ff	293	* @}
bogdanm	0:9b334a45a8ff	294	*/
bogdanm	0:9b334a45a8ff	295
bogdanm	0:9b334a45a8ff	296	/** @defgroup __HAL_RCC_LSE_CONFIG LSE Config
bogdanm	0:9b334a45a8ff	297	* @{
bogdanm	0:9b334a45a8ff	298	*/
bogdanm	0:9b334a45a8ff	299	#define RCC_LSE_OFF ((uint32_t)0x00000000) /!< LSE clock deactivation /
bogdanm	0:9b334a45a8ff	300	#define RCC_LSE_ON ((uint32_t)0x00000001) /!< LSE clock activation /
bogdanm	0:9b334a45a8ff	301	#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /!< External clock source for LSE clock /
bogdanm	0:9b334a45a8ff	302
bogdanm	0:9b334a45a8ff	303	/**
bogdanm	0:9b334a45a8ff	304	* @}
bogdanm	0:9b334a45a8ff	305	*/
bogdanm	0:9b334a45a8ff	306
bogdanm	0:9b334a45a8ff	307	/** @defgroup RCC_HSI_Config HSI Config
bogdanm	0:9b334a45a8ff	308	* @{
bogdanm	0:9b334a45a8ff	309	*/
bogdanm	0:9b334a45a8ff	310	#define RCC_HSI_OFF ((uint32_t)0x00000000) /!< HSI clock deactivation /
bogdanm	0:9b334a45a8ff	311	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	/**
bogdanm	0:9b334a45a8ff	316	* @}
bogdanm	0:9b334a45a8ff	317	*/
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319	/** @defgroup RCC_LSI_Config LSI Config
bogdanm	0:9b334a45a8ff	320	* @{
bogdanm	0:9b334a45a8ff	321	*/
bogdanm	0:9b334a45a8ff	322	#define RCC_LSI_OFF ((uint32_t)0x00000000) /!< LSI clock deactivation /
bogdanm	0:9b334a45a8ff	323	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
bogdanm	0:9b334a45a8ff	324
bogdanm	0:9b334a45a8ff	325	/**
bogdanm	0:9b334a45a8ff	326	* @}
bogdanm	0:9b334a45a8ff	327	*/
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	/** @defgroup __HAL_RCC_PLL_CONFIG PLL Config
bogdanm	0:9b334a45a8ff	330	* @{
bogdanm	0:9b334a45a8ff	331	*/
bogdanm	0:9b334a45a8ff	332	#define RCC_PLL_NONE ((uint32_t)0x00000000) /!< PLL is not configured /
bogdanm	0:9b334a45a8ff	333	#define RCC_PLL_OFF ((uint32_t)0x00000001) /!< PLL deactivation /
bogdanm	0:9b334a45a8ff	334	#define RCC_PLL_ON ((uint32_t)0x00000002) /!< PLL activation /
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	/**
bogdanm	0:9b334a45a8ff	337	* @}
bogdanm	0:9b334a45a8ff	338	*/
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	/** @defgroup RCC_System_Clock_Type System Clock Type
bogdanm	0:9b334a45a8ff	341	* @{
bogdanm	0:9b334a45a8ff	342	*/
bogdanm	0:9b334a45a8ff	343	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
bogdanm	0:9b334a45a8ff	344	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
bogdanm	0:9b334a45a8ff	345	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
bogdanm	0:9b334a45a8ff	346	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
bogdanm	0:9b334a45a8ff	347
bogdanm	0:9b334a45a8ff	348	/**
bogdanm	0:9b334a45a8ff	349	* @}
bogdanm	0:9b334a45a8ff	350	*/
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/** @defgroup RCC_System_Clock_Source System Clock Source
bogdanm	0:9b334a45a8ff	353	* @{
bogdanm	0:9b334a45a8ff	354	*/
bogdanm	0:9b334a45a8ff	355	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
bogdanm	0:9b334a45a8ff	356	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
bogdanm	0:9b334a45a8ff	357	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	/**
bogdanm	0:9b334a45a8ff	360	* @}
bogdanm	0:9b334a45a8ff	361	*/
bogdanm	0:9b334a45a8ff	362
bogdanm	0:9b334a45a8ff	363	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
bogdanm	0:9b334a45a8ff	364	* @{
bogdanm	0:9b334a45a8ff	365	*/
bogdanm	0:9b334a45a8ff	366	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
bogdanm	0:9b334a45a8ff	367	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
bogdanm	0:9b334a45a8ff	368	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
bogdanm	0:9b334a45a8ff	369
bogdanm	0:9b334a45a8ff	370	/**
bogdanm	0:9b334a45a8ff	371	* @}
bogdanm	0:9b334a45a8ff	372	*/
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
bogdanm	0:9b334a45a8ff	375	* @{
bogdanm	0:9b334a45a8ff	376	*/
bogdanm	0:9b334a45a8ff	377	#define RCC_SYSCLK_DIV1 (RCC_CFGR_HPRE_DIV1) /!< SYSCLK not divided /
bogdanm	0:9b334a45a8ff	378	#define RCC_SYSCLK_DIV2 (RCC_CFGR_HPRE_DIV2) /!< SYSCLK divided by 2 /
bogdanm	0:9b334a45a8ff	379	#define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_DIV4) /!< SYSCLK divided by 4 /
bogdanm	0:9b334a45a8ff	380	#define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_DIV8) /!< SYSCLK divided by 8 /
bogdanm	0:9b334a45a8ff	381	#define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_DIV16) /!< SYSCLK divided by 16 /
bogdanm	0:9b334a45a8ff	382	#define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_DIV64) /!< SYSCLK divided by 64 /
bogdanm	0:9b334a45a8ff	383	#define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_DIV128) /!< SYSCLK divided by 128 /
bogdanm	0:9b334a45a8ff	384	#define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_DIV256) /!< SYSCLK divided by 256 /
bogdanm	0:9b334a45a8ff	385	#define RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_DIV512) /!< SYSCLK divided by 512 /
bogdanm	0:9b334a45a8ff	386
bogdanm	0:9b334a45a8ff	387	/**
bogdanm	0:9b334a45a8ff	388	* @}
bogdanm	0:9b334a45a8ff	389	*/
bogdanm	0:9b334a45a8ff	390
bogdanm	0:9b334a45a8ff	391	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
bogdanm	0:9b334a45a8ff	392	* @{
bogdanm	0:9b334a45a8ff	393	*/
bogdanm	0:9b334a45a8ff	394	#define RCC_HCLK_DIV1 (RCC_CFGR_PPRE1_DIV1) /!< HCLK not divided /
bogdanm	0:9b334a45a8ff	395	#define RCC_HCLK_DIV2 (RCC_CFGR_PPRE1_DIV2) /!< HCLK divided by 2 /
bogdanm	0:9b334a45a8ff	396	#define RCC_HCLK_DIV4 (RCC_CFGR_PPRE1_DIV4) /!< HCLK divided by 4 /
bogdanm	0:9b334a45a8ff	397	#define RCC_HCLK_DIV8 (RCC_CFGR_PPRE1_DIV8) /!< HCLK divided by 8 /
bogdanm	0:9b334a45a8ff	398	#define RCC_HCLK_DIV16 (RCC_CFGR_PPRE1_DIV16) /!< HCLK divided by 16 /
bogdanm	0:9b334a45a8ff	399
bogdanm	0:9b334a45a8ff	400	/**
bogdanm	0:9b334a45a8ff	401	* @}
bogdanm	0:9b334a45a8ff	402	*/
bogdanm	0:9b334a45a8ff	403
bogdanm	0:9b334a45a8ff	404	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
bogdanm	0:9b334a45a8ff	405	* @{
bogdanm	0:9b334a45a8ff	406	*/
bogdanm	0:9b334a45a8ff	407	#define RCC_RTCCLKSOURCE_LSE (RCC_BDCR_RTCSEL_LSE) /!< LSE oscillator clock used as RTC clock /
bogdanm	0:9b334a45a8ff	408	#define RCC_RTCCLKSOURCE_LSI (RCC_BDCR_RTCSEL_LSI) /!< LSI oscillator clock used as RTC clock /
bogdanm	0:9b334a45a8ff	409	#define RCC_RTCCLKSOURCE_HSE_DIV128 (RCC_BDCR_RTCSEL_HSE) /!< HSE oscillator clock divided by 128 used as RTC clock /
bogdanm	0:9b334a45a8ff	410	/**
bogdanm	0:9b334a45a8ff	411	* @}
bogdanm	0:9b334a45a8ff	412	*/
bogdanm	0:9b334a45a8ff	413
bogdanm	0:9b334a45a8ff	414	/** @defgroup RCC_MCO_Index MCO Index
bogdanm	0:9b334a45a8ff	415	* @{
bogdanm	0:9b334a45a8ff	416	*/
bogdanm	0:9b334a45a8ff	417	#define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	418	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
bogdanm	0:9b334a45a8ff	419
bogdanm	0:9b334a45a8ff	420	/**
bogdanm	0:9b334a45a8ff	421	* @}
bogdanm	0:9b334a45a8ff	422	*/
bogdanm	0:9b334a45a8ff	423
bogdanm	0:9b334a45a8ff	424	/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
bogdanm	0:9b334a45a8ff	425	* @{
bogdanm	0:9b334a45a8ff	426	*/
bogdanm	0:9b334a45a8ff	427	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	428
bogdanm	0:9b334a45a8ff	429	/**
bogdanm	0:9b334a45a8ff	430	* @}
bogdanm	0:9b334a45a8ff	431	*/
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/** @defgroup RCC_Interrupt Interrupts
bogdanm	0:9b334a45a8ff	434	* @{
bogdanm	0:9b334a45a8ff	435	*/
bogdanm	0:9b334a45a8ff	436	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	437	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	438	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	439	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	440	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	441	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
bogdanm	0:9b334a45a8ff	442	/**
bogdanm	0:9b334a45a8ff	443	* @}
bogdanm	0:9b334a45a8ff	444	*/
bogdanm	0:9b334a45a8ff	445
bogdanm	0:9b334a45a8ff	446	/** @defgroup RCC_Flag Flags
bogdanm	0:9b334a45a8ff	447	* Elements values convention: 0XXYYYYYb
bogdanm	0:9b334a45a8ff	448	* - YYYYY : Flag position in the register
bogdanm	0:9b334a45a8ff	449	* - XX : Register index
bogdanm	0:9b334a45a8ff	450	* - 01: CR register
bogdanm	0:9b334a45a8ff	451	* - 10: BDCR register
bogdanm	0:9b334a45a8ff	452	* - 11: CSR register
bogdanm	0:9b334a45a8ff	453	* @{
bogdanm	0:9b334a45a8ff	454	*/
bogdanm	0:9b334a45a8ff	455	/* Flags in the CR register */
bogdanm	0:9b334a45a8ff	456	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< Internal High Speed clock ready flag /
bogdanm	0:9b334a45a8ff	457	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSERDY))) /!< External High Speed clock ready flag /
bogdanm	0:9b334a45a8ff	458	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL clock ready flag /
bogdanm	0:9b334a45a8ff	459
bogdanm	0:9b334a45a8ff	460	/* Flags in the BDCR register */
bogdanm	0:9b334a45a8ff	461	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< External Low Speed oscillator Ready /
bogdanm	0:9b334a45a8ff	462
bogdanm	0:9b334a45a8ff	463	/* Flags in the CSR register */
bogdanm	0:9b334a45a8ff	464	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< Internal Low Speed oscillator Ready /
bogdanm	0:9b334a45a8ff	465	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_RMVF))) /!< Remove reset flag /
bogdanm	0:9b334a45a8ff	466	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
bogdanm	0:9b334a45a8ff	467	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PORRSTF))) /!< POR/PDR reset flag /
bogdanm	0:9b334a45a8ff	468	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
bogdanm	0:9b334a45a8ff	469	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
bogdanm	0:9b334a45a8ff	470	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
bogdanm	0:9b334a45a8ff	471	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
bogdanm	0:9b334a45a8ff	472
bogdanm	0:9b334a45a8ff	473	/**
bogdanm	0:9b334a45a8ff	474	* @}
bogdanm	0:9b334a45a8ff	475	*/
bogdanm	0:9b334a45a8ff	476
bogdanm	0:9b334a45a8ff	477	/**
bogdanm	0:9b334a45a8ff	478	* @}
bogdanm	0:9b334a45a8ff	479	*/
bogdanm	0:9b334a45a8ff	480
bogdanm	0:9b334a45a8ff	481	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	482
bogdanm	0:9b334a45a8ff	483	/** @defgroup RCC_Exported_Macros RCC Exported Macros
bogdanm	0:9b334a45a8ff	484	* @{
bogdanm	0:9b334a45a8ff	485	*/
bogdanm	0:9b334a45a8ff	486
bogdanm	0:9b334a45a8ff	487	/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
bogdanm	0:9b334a45a8ff	488	* @brief Enable or disable the AHB1 peripheral clock.
bogdanm	0:9b334a45a8ff	489	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	490	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	491	* using it.
bogdanm	0:9b334a45a8ff	492	* @{
bogdanm	0:9b334a45a8ff	493	*/
bogdanm	0:9b334a45a8ff	494	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	495	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	496	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
bogdanm	0:9b334a45a8ff	497	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	498	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
bogdanm	0:9b334a45a8ff	499	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	500	} while(0)
bogdanm	0:9b334a45a8ff	501
bogdanm	0:9b334a45a8ff	502	#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	503	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	504	SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
bogdanm	0:9b334a45a8ff	505	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	506	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
bogdanm	0:9b334a45a8ff	507	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	508	} while(0)
bogdanm	0:9b334a45a8ff	509
bogdanm	0:9b334a45a8ff	510	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	511	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	512	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
bogdanm	0:9b334a45a8ff	513	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	514	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
bogdanm	0:9b334a45a8ff	515	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	516	} while(0)
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	519	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	520	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
bogdanm	0:9b334a45a8ff	521	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	522	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
bogdanm	0:9b334a45a8ff	523	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	524	} while(0)
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
bogdanm	0:9b334a45a8ff	527	#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
bogdanm	0:9b334a45a8ff	528	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
bogdanm	0:9b334a45a8ff	529	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
bogdanm	0:9b334a45a8ff	530
bogdanm	0:9b334a45a8ff	531	/**
bogdanm	0:9b334a45a8ff	532	* @}
bogdanm	0:9b334a45a8ff	533	*/
bogdanm	0:9b334a45a8ff	534
bogdanm	0:9b334a45a8ff	535	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	536	* @brief Get the enable or disable status of the AHB peripheral clock.
bogdanm	0:9b334a45a8ff	537	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	538	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	539	* using it.
bogdanm	0:9b334a45a8ff	540	* @{
bogdanm	0:9b334a45a8ff	541	*/
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
bogdanm	0:9b334a45a8ff	544	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
bogdanm	0:9b334a45a8ff	545	#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
bogdanm	0:9b334a45a8ff	546	#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
bogdanm	0:9b334a45a8ff	547	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
bogdanm	0:9b334a45a8ff	548	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
bogdanm	0:9b334a45a8ff	549	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
bogdanm	0:9b334a45a8ff	550	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
bogdanm	0:9b334a45a8ff	551
bogdanm	0:9b334a45a8ff	552	/**
bogdanm	0:9b334a45a8ff	553	* @}
bogdanm	0:9b334a45a8ff	554	*/
bogdanm	0:9b334a45a8ff	555
bogdanm	0:9b334a45a8ff	556	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
bogdanm	0:9b334a45a8ff	557	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	0:9b334a45a8ff	558	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	559	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	560	* using it.
bogdanm	0:9b334a45a8ff	561	* @{
bogdanm	0:9b334a45a8ff	562	*/
bogdanm	0:9b334a45a8ff	563	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	564	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	565	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
bogdanm	0:9b334a45a8ff	566	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	567	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
bogdanm	0:9b334a45a8ff	568	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	569	} while(0)
bogdanm	0:9b334a45a8ff	570
bogdanm	0:9b334a45a8ff	571	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	572	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	573	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
bogdanm	0:9b334a45a8ff	574	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	575	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
bogdanm	0:9b334a45a8ff	576	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	577	} while(0)
bogdanm	0:9b334a45a8ff	578
bogdanm	0:9b334a45a8ff	579	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	580	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	581	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
bogdanm	0:9b334a45a8ff	582	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	583	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
bogdanm	0:9b334a45a8ff	584	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	585	} while(0)
bogdanm	0:9b334a45a8ff	586
bogdanm	0:9b334a45a8ff	587	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	588	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	589	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
bogdanm	0:9b334a45a8ff	590	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	591	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
bogdanm	0:9b334a45a8ff	592	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	593	} while(0)
bogdanm	0:9b334a45a8ff	594
bogdanm	0:9b334a45a8ff	595	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	596	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	597	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
bogdanm	0:9b334a45a8ff	598	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	599	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
bogdanm	0:9b334a45a8ff	600	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	601	} while(0)
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	#define __HAL_RCC_BKP_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	604	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	605	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
bogdanm	0:9b334a45a8ff	606	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	607	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
bogdanm	0:9b334a45a8ff	608	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	609	} while(0)
bogdanm	0:9b334a45a8ff	610
bogdanm	0:9b334a45a8ff	611	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	612	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	613	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
bogdanm	0:9b334a45a8ff	614	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	615	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
bogdanm	0:9b334a45a8ff	616	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	617	} while(0)
bogdanm	0:9b334a45a8ff	618
bogdanm	0:9b334a45a8ff	619	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm	0:9b334a45a8ff	620	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm	0:9b334a45a8ff	621	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm	0:9b334a45a8ff	622	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm	0:9b334a45a8ff	623	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625	#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
bogdanm	0:9b334a45a8ff	626	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm	0:9b334a45a8ff	627
bogdanm	0:9b334a45a8ff	628	/**
bogdanm	0:9b334a45a8ff	629	* @}
bogdanm	0:9b334a45a8ff	630	*/
bogdanm	0:9b334a45a8ff	631
bogdanm	0:9b334a45a8ff	632	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	633	* @brief Get the enable or disable status of the APB1 peripheral clock.
bogdanm	0:9b334a45a8ff	634	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	635	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	636	* using it.
bogdanm	0:9b334a45a8ff	637	* @{
bogdanm	0:9b334a45a8ff	638	*/
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
bogdanm	0:9b334a45a8ff	641	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
bogdanm	0:9b334a45a8ff	642	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
bogdanm	0:9b334a45a8ff	643	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
bogdanm	0:9b334a45a8ff	644	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
bogdanm	0:9b334a45a8ff	645	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
bogdanm	0:9b334a45a8ff	646	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
bogdanm	0:9b334a45a8ff	647	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
bogdanm	0:9b334a45a8ff	648	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
bogdanm	0:9b334a45a8ff	649	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
bogdanm	0:9b334a45a8ff	650	#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
bogdanm	0:9b334a45a8ff	651	#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
bogdanm	0:9b334a45a8ff	652	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
bogdanm	0:9b334a45a8ff	653	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
bogdanm	0:9b334a45a8ff	654
bogdanm	0:9b334a45a8ff	655	/**
bogdanm	0:9b334a45a8ff	656	* @}
bogdanm	0:9b334a45a8ff	657	*/
bogdanm	0:9b334a45a8ff	658
bogdanm	0:9b334a45a8ff	659	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
bogdanm	0:9b334a45a8ff	660	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	0:9b334a45a8ff	661	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	662	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	663	* using it.
bogdanm	0:9b334a45a8ff	664	* @{
bogdanm	0:9b334a45a8ff	665	*/
bogdanm	0:9b334a45a8ff	666	#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	667	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	668	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
bogdanm	0:9b334a45a8ff	669	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	670	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
bogdanm	0:9b334a45a8ff	671	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	672	} while(0)
bogdanm	0:9b334a45a8ff	673
bogdanm	0:9b334a45a8ff	674	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	675	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	676	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
bogdanm	0:9b334a45a8ff	677	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	678	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
bogdanm	0:9b334a45a8ff	679	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	680	} while(0)
bogdanm	0:9b334a45a8ff	681
bogdanm	0:9b334a45a8ff	682	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	683	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	684	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
bogdanm	0:9b334a45a8ff	685	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	686	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
bogdanm	0:9b334a45a8ff	687	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	688	} while(0)
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	691	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	692	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
bogdanm	0:9b334a45a8ff	693	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	694	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
bogdanm	0:9b334a45a8ff	695	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	696	} while(0)
bogdanm	0:9b334a45a8ff	697
bogdanm	0:9b334a45a8ff	698	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	699	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	700	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
bogdanm	0:9b334a45a8ff	701	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	702	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
bogdanm	0:9b334a45a8ff	703	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	704	} while(0)
bogdanm	0:9b334a45a8ff	705
bogdanm	0:9b334a45a8ff	706	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	707	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	708	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
bogdanm	0:9b334a45a8ff	709	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	710	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
bogdanm	0:9b334a45a8ff	711	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	712	} while(0)
bogdanm	0:9b334a45a8ff	713
bogdanm	0:9b334a45a8ff	714	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	715	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	716	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
bogdanm	0:9b334a45a8ff	717	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	718	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
bogdanm	0:9b334a45a8ff	719	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	720	} while(0)
bogdanm	0:9b334a45a8ff	721
bogdanm	0:9b334a45a8ff	722	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	723	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	724	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
bogdanm	0:9b334a45a8ff	725	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	726	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
bogdanm	0:9b334a45a8ff	727	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	728	} while(0)
bogdanm	0:9b334a45a8ff	729
bogdanm	0:9b334a45a8ff	730	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	731	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	732	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
bogdanm	0:9b334a45a8ff	733	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	734	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
bogdanm	0:9b334a45a8ff	735	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	736	} while(0)
bogdanm	0:9b334a45a8ff	737
bogdanm	0:9b334a45a8ff	738	#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
bogdanm	0:9b334a45a8ff	739	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
bogdanm	0:9b334a45a8ff	740	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
bogdanm	0:9b334a45a8ff	741	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
bogdanm	0:9b334a45a8ff	742	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
bogdanm	0:9b334a45a8ff	743	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
bogdanm	0:9b334a45a8ff	744
bogdanm	0:9b334a45a8ff	745	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
bogdanm	0:9b334a45a8ff	746	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm	0:9b334a45a8ff	747	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
bogdanm	0:9b334a45a8ff	748
bogdanm	0:9b334a45a8ff	749	/**
bogdanm	0:9b334a45a8ff	750	* @}
bogdanm	0:9b334a45a8ff	751	*/
bogdanm	0:9b334a45a8ff	752
bogdanm	0:9b334a45a8ff	753	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	754	* @brief Get the enable or disable status of the APB2 peripheral clock.
bogdanm	0:9b334a45a8ff	755	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	756	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	757	* using it.
bogdanm	0:9b334a45a8ff	758	* @{
bogdanm	0:9b334a45a8ff	759	*/
bogdanm	0:9b334a45a8ff	760
bogdanm	0:9b334a45a8ff	761	#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
bogdanm	0:9b334a45a8ff	762	#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
bogdanm	0:9b334a45a8ff	763	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
bogdanm	0:9b334a45a8ff	764	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
bogdanm	0:9b334a45a8ff	765	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
bogdanm	0:9b334a45a8ff	766	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
bogdanm	0:9b334a45a8ff	767	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
bogdanm	0:9b334a45a8ff	768	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
bogdanm	0:9b334a45a8ff	769	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
bogdanm	0:9b334a45a8ff	770	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
bogdanm	0:9b334a45a8ff	771	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
bogdanm	0:9b334a45a8ff	772	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
bogdanm	0:9b334a45a8ff	773	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
bogdanm	0:9b334a45a8ff	774	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
bogdanm	0:9b334a45a8ff	775	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
bogdanm	0:9b334a45a8ff	776	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
bogdanm	0:9b334a45a8ff	777	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
bogdanm	0:9b334a45a8ff	778	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
bogdanm	0:9b334a45a8ff	779
bogdanm	0:9b334a45a8ff	780	/**
bogdanm	0:9b334a45a8ff	781	* @}
bogdanm	0:9b334a45a8ff	782	*/
bogdanm	0:9b334a45a8ff	783
bogdanm	0:9b334a45a8ff	784	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
bogdanm	0:9b334a45a8ff	785	* @brief Force or release APB1 peripheral reset.
bogdanm	0:9b334a45a8ff	786	* @{
bogdanm	0:9b334a45a8ff	787	*/
bogdanm	0:9b334a45a8ff	788	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	789	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	790	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
bogdanm	0:9b334a45a8ff	791	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
bogdanm	0:9b334a45a8ff	792	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	793	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	794
bogdanm	0:9b334a45a8ff	795	#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_BKPRST))
bogdanm	0:9b334a45a8ff	796	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
bogdanm	0:9b334a45a8ff	797
bogdanm	0:9b334a45a8ff	798	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm	0:9b334a45a8ff	799	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	800	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm	0:9b334a45a8ff	801	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
bogdanm	0:9b334a45a8ff	802	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	803	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	804
bogdanm	0:9b334a45a8ff	805	#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
bogdanm	0:9b334a45a8ff	806	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm	0:9b334a45a8ff	807
bogdanm	0:9b334a45a8ff	808	/**
bogdanm	0:9b334a45a8ff	809	* @}
bogdanm	0:9b334a45a8ff	810	*/
bogdanm	0:9b334a45a8ff	811
bogdanm	0:9b334a45a8ff	812	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
bogdanm	0:9b334a45a8ff	813	* @brief Force or release APB2 peripheral reset.
bogdanm	0:9b334a45a8ff	814	* @{
bogdanm	0:9b334a45a8ff	815	*/
bogdanm	0:9b334a45a8ff	816	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm	0:9b334a45a8ff	817	#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_AFIORST))
bogdanm	0:9b334a45a8ff	818	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPARST))
bogdanm	0:9b334a45a8ff	819	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPBRST))
bogdanm	0:9b334a45a8ff	820	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPCRST))
bogdanm	0:9b334a45a8ff	821	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPDRST))
bogdanm	0:9b334a45a8ff	822	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
bogdanm	0:9b334a45a8ff	825	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
bogdanm	0:9b334a45a8ff	826	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
bogdanm	0:9b334a45a8ff	827
bogdanm	0:9b334a45a8ff	828	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm	0:9b334a45a8ff	829	#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
bogdanm	0:9b334a45a8ff	830	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
bogdanm	0:9b334a45a8ff	831	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
bogdanm	0:9b334a45a8ff	832	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
bogdanm	0:9b334a45a8ff	833	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
bogdanm	0:9b334a45a8ff	834	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
bogdanm	0:9b334a45a8ff	835
bogdanm	0:9b334a45a8ff	836	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
bogdanm	0:9b334a45a8ff	837	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm	0:9b334a45a8ff	838	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	/**
bogdanm	0:9b334a45a8ff	841	* @}
bogdanm	0:9b334a45a8ff	842	*/
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/** @defgroup RCC_HSI_Configuration HSI Configuration
bogdanm	0:9b334a45a8ff	845	* @{
bogdanm	0:9b334a45a8ff	846	*/
bogdanm	0:9b334a45a8ff	847
bogdanm	0:9b334a45a8ff	848	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm	0:9b334a45a8ff	849	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	850	* @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm	0:9b334a45a8ff	851	* you have to select another source of the system clock then stop the HSI.
bogdanm	0:9b334a45a8ff	852	* @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm	0:9b334a45a8ff	853	* flag to be set indicating that HSI clock is stable and can be used as
bogdanm	0:9b334a45a8ff	854	* system clock source.
bogdanm	0:9b334a45a8ff	855	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm	0:9b334a45a8ff	856	* clock cycles.
bogdanm	0:9b334a45a8ff	857	*/
bogdanm	0:9b334a45a8ff	858	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
bogdanm	0:9b334a45a8ff	859	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
bogdanm	0:9b334a45a8ff	860
bogdanm	0:9b334a45a8ff	861	/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm	0:9b334a45a8ff	862	* @note The calibration is used to compensate for the variations in voltage
bogdanm	0:9b334a45a8ff	863	* and temperature that influence the frequency of the internal HSI RC.
bogdanm	0:9b334a45a8ff	864	* @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
bogdanm	0:9b334a45a8ff	865	* (default is RCC_HSICALIBRATION_DEFAULT).
bogdanm	0:9b334a45a8ff	866	* This parameter must be a number between 0 and 0x1F.
bogdanm	0:9b334a45a8ff	867	*/
bogdanm	0:9b334a45a8ff	868	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
bogdanm	0:9b334a45a8ff	869	(MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
bogdanm	0:9b334a45a8ff	870
bogdanm	0:9b334a45a8ff	871	/**
bogdanm	0:9b334a45a8ff	872	* @}
bogdanm	0:9b334a45a8ff	873	*/
bogdanm	0:9b334a45a8ff	874
bogdanm	0:9b334a45a8ff	875	/** @defgroup RCC_LSI_Configuration LSI Configuration
bogdanm	0:9b334a45a8ff	876	* @{
bogdanm	0:9b334a45a8ff	877	*/
bogdanm	0:9b334a45a8ff	878
bogdanm	0:9b334a45a8ff	879	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm	0:9b334a45a8ff	880	* @note After enabling the LSI, the application software should wait on
bogdanm	0:9b334a45a8ff	881	* LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm	0:9b334a45a8ff	882	* be used to clock the IWDG and/or the RTC.
bogdanm	0:9b334a45a8ff	883	* @note LSI can not be disabled if the IWDG is running.
bogdanm	0:9b334a45a8ff	884	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm	0:9b334a45a8ff	885	* clock cycles.
bogdanm	0:9b334a45a8ff	886	*/
bogdanm	0:9b334a45a8ff	887	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
bogdanm	0:9b334a45a8ff	888	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/**
bogdanm	0:9b334a45a8ff	891	* @}
bogdanm	0:9b334a45a8ff	892	*/
bogdanm	0:9b334a45a8ff	893
bogdanm	0:9b334a45a8ff	894	/** @defgroup RCC_HSE_Configuration HSE Configuration
bogdanm	0:9b334a45a8ff	895	* @{
bogdanm	0:9b334a45a8ff	896	*/
bogdanm	0:9b334a45a8ff	897
bogdanm	0:9b334a45a8ff	898	/**
bogdanm	0:9b334a45a8ff	899	* @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm	0:9b334a45a8ff	900	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm	0:9b334a45a8ff	901	* software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm	0:9b334a45a8ff	902	* is stable and can be used to clock the PLL and/or system clock.
bogdanm	0:9b334a45a8ff	903	* @note HSE state can not be changed if it is used directly or through the
bogdanm	0:9b334a45a8ff	904	* PLL as system clock. In this case, you have to select another source
bogdanm	0:9b334a45a8ff	905	* of the system clock then change the HSE state (ex. disable it).
bogdanm	0:9b334a45a8ff	906	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	907	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
bogdanm	0:9b334a45a8ff	908	* was previously enabled you have to enable it again after calling this
bogdanm	0:9b334a45a8ff	909	* function.
bogdanm	0:9b334a45a8ff	910	* @param __STATE__: specifies the new state of the HSE.
bogdanm	0:9b334a45a8ff	911	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	912	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm	0:9b334a45a8ff	913	* 6 HSE oscillator clock cycles.
bogdanm	0:9b334a45a8ff	914	* @arg RCC_HSE_ON: turn ON the HSE oscillator
bogdanm	0:9b334a45a8ff	915	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
bogdanm	0:9b334a45a8ff	916	*/
bogdanm	0:9b334a45a8ff	917	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
bogdanm	0:9b334a45a8ff	918	do { \
bogdanm	0:9b334a45a8ff	919	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	920	if((__STATE__) == RCC_HSE_ON) \
bogdanm	0:9b334a45a8ff	921	{ \
bogdanm	0:9b334a45a8ff	922	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	923	SET_BIT(RCC->CR, RCC_CR_HSEON); \
bogdanm	0:9b334a45a8ff	924	} \
bogdanm	0:9b334a45a8ff	925	else if((__STATE__) == RCC_HSE_BYPASS) \
bogdanm	0:9b334a45a8ff	926	{ \
bogdanm	0:9b334a45a8ff	927	((__IO uint8_t ) RCC_CR_BYTE2_ADDRESS = (__STATE__)); \
bogdanm	0:9b334a45a8ff	928	} \
bogdanm	0:9b334a45a8ff	929	else \
bogdanm	0:9b334a45a8ff	930	{ \
bogdanm	0:9b334a45a8ff	931	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
bogdanm	0:9b334a45a8ff	932	} \
bogdanm	0:9b334a45a8ff	933	} while(0)
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	/**
bogdanm	0:9b334a45a8ff	936	* @}
bogdanm	0:9b334a45a8ff	937	*/
bogdanm	0:9b334a45a8ff	938
bogdanm	0:9b334a45a8ff	939	/** @defgroup RCC_LSE_Configuration LSE Configuration
bogdanm	0:9b334a45a8ff	940	* @{
bogdanm	0:9b334a45a8ff	941	*/
bogdanm	0:9b334a45a8ff	942
bogdanm	0:9b334a45a8ff	943	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE).
bogdanm	0:9b334a45a8ff	944	*/
bogdanm	0:9b334a45a8ff	945	#define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \
bogdanm	0:9b334a45a8ff	946	do{ \
bogdanm	0:9b334a45a8ff	947	if ((__LSE_STATE__) == RCC_LSE_OFF) \
bogdanm	0:9b334a45a8ff	948	{ \
bogdanm	0:9b334a45a8ff	949	(__IO uint32_t ) BDCR_LSEON_BB = DISABLE; \
bogdanm	0:9b334a45a8ff	950	(__IO uint32_t ) BDCR_LSEBYP_BB = DISABLE; \
bogdanm	0:9b334a45a8ff	951	} \
bogdanm	0:9b334a45a8ff	952	else if ((__LSE_STATE__) == RCC_LSE_ON) \
bogdanm	0:9b334a45a8ff	953	{ \
bogdanm	0:9b334a45a8ff	954	(__IO uint32_t ) BDCR_LSEBYP_BB = DISABLE; \
bogdanm	0:9b334a45a8ff	955	(__IO uint32_t ) BDCR_LSEON_BB = ENABLE; \
bogdanm	0:9b334a45a8ff	956	} \
bogdanm	0:9b334a45a8ff	957	else \
bogdanm	0:9b334a45a8ff	958	{ \
bogdanm	0:9b334a45a8ff	959	(__IO uint32_t ) BDCR_LSEON_BB = DISABLE; \
bogdanm	0:9b334a45a8ff	960	(__IO uint32_t ) BDCR_LSEBYP_BB = ENABLE; \
bogdanm	0:9b334a45a8ff	961	} \
bogdanm	0:9b334a45a8ff	962	}while(0)
bogdanm	0:9b334a45a8ff	963
bogdanm	0:9b334a45a8ff	964
bogdanm	0:9b334a45a8ff	965	/**
bogdanm	0:9b334a45a8ff	966	* @}
bogdanm	0:9b334a45a8ff	967	*/
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	/** @defgroup RCC_PLL_Configuration PLL Configuration
bogdanm	0:9b334a45a8ff	970	* @{
bogdanm	0:9b334a45a8ff	971	*/
bogdanm	0:9b334a45a8ff	972
bogdanm	0:9b334a45a8ff	973	/** @brief Macros to enable the main PLL.
bogdanm	0:9b334a45a8ff	974	* @note After enabling the main PLL, the application software should wait on
bogdanm	0:9b334a45a8ff	975	* PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm	0:9b334a45a8ff	976	* be used as system clock source.
bogdanm	0:9b334a45a8ff	977	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	978	*/
bogdanm	0:9b334a45a8ff	979	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
bogdanm	0:9b334a45a8ff	980
bogdanm	0:9b334a45a8ff	981	/** @brief Macros to disable the main PLL.
bogdanm	0:9b334a45a8ff	982	* @note The main PLL can not be disabled if it is used as system clock source
bogdanm	0:9b334a45a8ff	983	*/
bogdanm	0:9b334a45a8ff	984	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
bogdanm	0:9b334a45a8ff	985
bogdanm	0:9b334a45a8ff	986	/** @brief macros to configure the main PLL clock source and multiplication factors.
bogdanm	0:9b334a45a8ff	987	* @note This function must be used only when the main PLL is disabled.
bogdanm	0:9b334a45a8ff	988	*
bogdanm	0:9b334a45a8ff	989	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
bogdanm	0:9b334a45a8ff	990	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	991	* @arg RCC_PLLSOURCE_HSI_DIV2: HSI oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	992	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	0:9b334a45a8ff	993	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
bogdanm	0:9b334a45a8ff	994	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	995	* @arg RCC_PLL_MUL2: PLLVCO = PLL clock entry x 2 (*)
bogdanm	0:9b334a45a8ff	996	* @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3 (*)
bogdanm	0:9b334a45a8ff	997	* @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4
bogdanm	0:9b334a45a8ff	998	* @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6
bogdanm	0:9b334a45a8ff	999	* @arg RCC_PLL_MUL6_5: PLLVCO = PLL clock entry x 6.5 (**)
bogdanm	0:9b334a45a8ff	1000	* @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8
bogdanm	0:9b334a45a8ff	1001	* @arg RCC_PLL_MUL9: PLLVCO = PLL clock entry x 9
bogdanm	0:9b334a45a8ff	1002	* @arg RCC_PLL_MUL10: PLLVCO = PLL clock entry x 10 (*)
bogdanm	0:9b334a45a8ff	1003	* @arg RCC_PLL_MUL11: PLLVCO = PLL clock entry x 11 (*)
bogdanm	0:9b334a45a8ff	1004	* @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12 (*)
bogdanm	0:9b334a45a8ff	1005	* @arg RCC_PLL_MUL13: PLLVCO = PLL clock entry x 13 (*)
bogdanm	0:9b334a45a8ff	1006	* @arg RCC_PLL_MUL14: PLLVCO = PLL clock entry x 14 (*)
bogdanm	0:9b334a45a8ff	1007	* @arg RCC_PLL_MUL15: PLLVCO = PLL clock entry x 15 (*)
bogdanm	0:9b334a45a8ff	1008	* @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16 (*)
bogdanm	0:9b334a45a8ff	1009	* @note (*) These values are not available in STM32F105xx & STM32F107xx devices.
bogdanm	0:9b334a45a8ff	1010	* @note (**) This value is available in STM32F105xx & STM32F107xx devices only.
bogdanm	0:9b334a45a8ff	1011	*
bogdanm	0:9b334a45a8ff	1012	*/
bogdanm	0:9b334a45a8ff	1013	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
bogdanm	0:9b334a45a8ff	1014	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) \| (__PLLMUL__) ))
bogdanm	0:9b334a45a8ff	1015	/**
bogdanm	0:9b334a45a8ff	1016	* @}
bogdanm	0:9b334a45a8ff	1017	*/
bogdanm	0:9b334a45a8ff	1018
bogdanm	0:9b334a45a8ff	1019	/** @defgroup RCC_Get_Clock_source Get Clock source
bogdanm	0:9b334a45a8ff	1020	* @{
bogdanm	0:9b334a45a8ff	1021	*/
bogdanm	0:9b334a45a8ff	1022
bogdanm	0:9b334a45a8ff	1023	/** @brief Macro to get the clock source used as system clock.
bogdanm	0:9b334a45a8ff	1024	* @retval The clock source used as system clock. The returned value can be one
bogdanm	0:9b334a45a8ff	1025	* of the following:
bogdanm	0:9b334a45a8ff	1026	* @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
bogdanm	0:9b334a45a8ff	1027	* @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
bogdanm	0:9b334a45a8ff	1028	* @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
bogdanm	0:9b334a45a8ff	1029	*/
bogdanm	0:9b334a45a8ff	1030	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
bogdanm	0:9b334a45a8ff	1031
bogdanm	0:9b334a45a8ff	1032	/** @brief Get oscillator clock selected as PLL input clock
bogdanm	0:9b334a45a8ff	1033	* @retval The clock source used for PLL entry. The returned value can be one
bogdanm	0:9b334a45a8ff	1034	* of the following:
bogdanm	0:9b334a45a8ff	1035	* @arg RCC_PLLSOURCE_HSI_DIV2: HSI oscillator clock selected as PLL input clock
bogdanm	0:9b334a45a8ff	1036	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
bogdanm	0:9b334a45a8ff	1037	*/
bogdanm	0:9b334a45a8ff	1038	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
bogdanm	0:9b334a45a8ff	1039
bogdanm	0:9b334a45a8ff	1040	/**
bogdanm	0:9b334a45a8ff	1041	* @}
bogdanm	0:9b334a45a8ff	1042	*/
bogdanm	0:9b334a45a8ff	1043	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
bogdanm	0:9b334a45a8ff	1044	* @{
bogdanm	0:9b334a45a8ff	1045	*/
bogdanm	0:9b334a45a8ff	1046
bogdanm	0:9b334a45a8ff	1047	/** @brief Macro to configures the RTC clock (RTCCLK).
bogdanm	0:9b334a45a8ff	1048	* @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm	0:9b334a45a8ff	1049	* access is denied to this domain after reset, you have to enable write
bogdanm	0:9b334a45a8ff	1050	* access using the Power Backup Access macro before to configure
bogdanm	0:9b334a45a8ff	1051	* the RTC clock source (to be done once after reset).
bogdanm	0:9b334a45a8ff	1052	* @note Once the RTC clock is configured it can't be changed unless the
bogdanm	0:9b334a45a8ff	1053	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
bogdanm	0:9b334a45a8ff	1054	* a Power On Reset (POR).
bogdanm	0:9b334a45a8ff	1055	*
bogdanm	0:9b334a45a8ff	1056	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
bogdanm	0:9b334a45a8ff	1057	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1058	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm	0:9b334a45a8ff	1059	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm	0:9b334a45a8ff	1060	* @arg RCC_RTCCLKSOURCE_HSE_DIV128: HSE divided by 128 selected as RTC clock
bogdanm	0:9b334a45a8ff	1061	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm	0:9b334a45a8ff	1062	* work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm	0:9b334a45a8ff	1063	* However, when the HSE clock is used as RTC clock source, the RTC
bogdanm	0:9b334a45a8ff	1064	* cannot be used in STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1065	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm	0:9b334a45a8ff	1066	* RTC clock source).
bogdanm	0:9b334a45a8ff	1067	*/
bogdanm	0:9b334a45a8ff	1068	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	1069
bogdanm	0:9b334a45a8ff	1070
bogdanm	0:9b334a45a8ff	1071	/** @brief macros to get the RTC clock source.
bogdanm	0:9b334a45a8ff	1072	*/
bogdanm	0:9b334a45a8ff	1073	#define __HAL_RCC_GET_RTC_SOURCE() READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)
bogdanm	0:9b334a45a8ff	1074
bogdanm	0:9b334a45a8ff	1075	/** @brief Macros to enable the the RTC clock.
bogdanm	0:9b334a45a8ff	1076	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	0:9b334a45a8ff	1077	*/
bogdanm	0:9b334a45a8ff	1078	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
bogdanm	0:9b334a45a8ff	1079
bogdanm	0:9b334a45a8ff	1080	/** @brief Macros to disable the the RTC clock.
bogdanm	0:9b334a45a8ff	1081	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	0:9b334a45a8ff	1082	*/
bogdanm	0:9b334a45a8ff	1083	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
bogdanm	0:9b334a45a8ff	1084
bogdanm	0:9b334a45a8ff	1085	/** @brief Macros to force the Backup domain reset.
bogdanm	0:9b334a45a8ff	1086	* @note This function resets the entire Backup domain.
bogdanm	0:9b334a45a8ff	1087	*/
bogdanm	0:9b334a45a8ff	1088	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
bogdanm	0:9b334a45a8ff	1089
bogdanm	0:9b334a45a8ff	1090	/** @brief Macros to release the Backup domain reset.
bogdanm	0:9b334a45a8ff	1091	*/
bogdanm	0:9b334a45a8ff	1092	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
bogdanm	0:9b334a45a8ff	1093
bogdanm	0:9b334a45a8ff	1094
bogdanm	0:9b334a45a8ff	1095	/**
bogdanm	0:9b334a45a8ff	1096	* @}
bogdanm	0:9b334a45a8ff	1097	*/
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
bogdanm	0:9b334a45a8ff	1100	* @brief macros to manage the specified RCC Flags and interrupts.
bogdanm	0:9b334a45a8ff	1101	* @{
bogdanm	0:9b334a45a8ff	1102	*/
bogdanm	0:9b334a45a8ff	1103
bogdanm	0:9b334a45a8ff	1104	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
bogdanm	0:9b334a45a8ff	1105	* the selected interrupts.).
bogdanm	0:9b334a45a8ff	1106	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm	0:9b334a45a8ff	1107	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1108	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	1109	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	1110	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	1111	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	1112	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
bogdanm	0:9b334a45a8ff	1113	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
bogdanm	0:9b334a45a8ff	1114	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
bogdanm	0:9b334a45a8ff	1115	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
bogdanm	0:9b334a45a8ff	1116	*/
bogdanm	0:9b334a45a8ff	1117	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1118
bogdanm	0:9b334a45a8ff	1119	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
bogdanm	0:9b334a45a8ff	1120	* the selected interrupts).
bogdanm	0:9b334a45a8ff	1121	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm	0:9b334a45a8ff	1122	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1123	* @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm	0:9b334a45a8ff	1124	* @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm	0:9b334a45a8ff	1125	* @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm	0:9b334a45a8ff	1126	* @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm	0:9b334a45a8ff	1127	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
bogdanm	0:9b334a45a8ff	1128	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
bogdanm	0:9b334a45a8ff	1129	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
bogdanm	0:9b334a45a8ff	1130	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
bogdanm	0:9b334a45a8ff	1131	*/
bogdanm	0:9b334a45a8ff	1132	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1133
bogdanm	0:9b334a45a8ff	1134	/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
bogdanm	0:9b334a45a8ff	1135	* bits to clear the selected interrupt pending bits.
bogdanm	0:9b334a45a8ff	1136	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	1137	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1138	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm	0:9b334a45a8ff	1139	* @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm	0:9b334a45a8ff	1140	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm	0:9b334a45a8ff	1141	* @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm	0:9b334a45a8ff	1142	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm	0:9b334a45a8ff	1143	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
bogdanm	0:9b334a45a8ff	1144	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
bogdanm	0:9b334a45a8ff	1145	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
bogdanm	0:9b334a45a8ff	1146	* @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm	0:9b334a45a8ff	1147	*/
bogdanm	0:9b334a45a8ff	1148	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1149
bogdanm	0:9b334a45a8ff	1150	/** @brief Check the RCC's interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	1151	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm	0:9b334a45a8ff	1152	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1153	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm	0:9b334a45a8ff	1154	* @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm	0:9b334a45a8ff	1155	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm	0:9b334a45a8ff	1156	* @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm	0:9b334a45a8ff	1157	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm	0:9b334a45a8ff	1158	* @arg RCC_IT_PLL2RDY: Main PLL2 ready interrupt.(*)
bogdanm	0:9b334a45a8ff	1159	* @arg RCC_IT_PLLI2S2RDY: Main PLLI2S ready interrupt.(*)
bogdanm	0:9b334a45a8ff	1160	* @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm	0:9b334a45a8ff	1161	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
bogdanm	0:9b334a45a8ff	1162	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1163	*/
bogdanm	0:9b334a45a8ff	1164	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1165
bogdanm	0:9b334a45a8ff	1166	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
bogdanm	0:9b334a45a8ff	1167	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
bogdanm	0:9b334a45a8ff	1168	*/
bogdanm	0:9b334a45a8ff	1169	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
bogdanm	0:9b334a45a8ff	1170
bogdanm	0:9b334a45a8ff	1171	/** @brief Check RCC flag is set or not.
bogdanm	0:9b334a45a8ff	1172	* @param __FLAG__: specifies the flag to check.
bogdanm	0:9b334a45a8ff	1173	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1174	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
bogdanm	0:9b334a45a8ff	1175	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
bogdanm	0:9b334a45a8ff	1176	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
bogdanm	0:9b334a45a8ff	1177	* @arg RCC_FLAG_PLL2RDY: Main PLL2 clock ready.(*)
bogdanm	0:9b334a45a8ff	1178	* @arg RCC_FLAG_PLLI2SRDY: Main PLLI2S clock ready.(*)
bogdanm	0:9b334a45a8ff	1179	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
bogdanm	0:9b334a45a8ff	1180	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
bogdanm	0:9b334a45a8ff	1181	* @arg RCC_FLAG_PINRST: Pin reset.
bogdanm	0:9b334a45a8ff	1182	* @arg RCC_FLAG_PORRST: POR/PDR reset.
bogdanm	0:9b334a45a8ff	1183	* @arg RCC_FLAG_SFTRST: Software reset.
bogdanm	0:9b334a45a8ff	1184	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
bogdanm	0:9b334a45a8ff	1185	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
bogdanm	0:9b334a45a8ff	1186	* @arg RCC_FLAG_LPWRRST: Low Power reset.
bogdanm	0:9b334a45a8ff	1187	* @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
bogdanm	0:9b334a45a8ff	1188	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1189	*/
bogdanm	0:9b334a45a8ff	1190	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
bogdanm	0:9b334a45a8ff	1191	/**
bogdanm	0:9b334a45a8ff	1192	* @}
bogdanm	0:9b334a45a8ff	1193	*/
bogdanm	0:9b334a45a8ff	1194
bogdanm	0:9b334a45a8ff	1195	/**
bogdanm	0:9b334a45a8ff	1196	* @}
bogdanm	0:9b334a45a8ff	1197	*/
bogdanm	0:9b334a45a8ff	1198
bogdanm	0:9b334a45a8ff	1199	/* Include RCC HAL Extension module */
bogdanm	0:9b334a45a8ff	1200	#include "stm32f1xx_hal_rcc_ex.h"
bogdanm	0:9b334a45a8ff	1201
bogdanm	0:9b334a45a8ff	1202	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1203	/** @addtogroup RCC_Exported_Functions
bogdanm	0:9b334a45a8ff	1204	* @{
bogdanm	0:9b334a45a8ff	1205	*/
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	/** @addtogroup RCC_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	1208	* @{
bogdanm	0:9b334a45a8ff	1209	*/
bogdanm	0:9b334a45a8ff	1210
bogdanm	0:9b334a45a8ff	1211	/* Initialization and de-initialization functions ******************************/
bogdanm	0:9b334a45a8ff	1212	void HAL_RCC_DeInit(void);
bogdanm	0:9b334a45a8ff	1213	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	0:9b334a45a8ff	1214	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm	0:9b334a45a8ff	1215
bogdanm	0:9b334a45a8ff	1216	/**
bogdanm	0:9b334a45a8ff	1217	* @}
bogdanm	0:9b334a45a8ff	1218	*/
bogdanm	0:9b334a45a8ff	1219
bogdanm	0:9b334a45a8ff	1220	/** @addtogroup RCC_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	1221	* @{
bogdanm	0:9b334a45a8ff	1222	*/
bogdanm	0:9b334a45a8ff	1223
bogdanm	0:9b334a45a8ff	1224	/* Peripheral Control functions ************************************************/
bogdanm	0:9b334a45a8ff	1225	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm	0:9b334a45a8ff	1226	void HAL_RCC_EnableCSS(void);
bogdanm	0:9b334a45a8ff	1227	void HAL_RCC_DisableCSS(void);
bogdanm	0:9b334a45a8ff	1228	uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm	0:9b334a45a8ff	1229	uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm	0:9b334a45a8ff	1230	uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm	0:9b334a45a8ff	1231	uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm	0:9b334a45a8ff	1232	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	0:9b334a45a8ff	1233	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
bogdanm	0:9b334a45a8ff	1234
bogdanm	0:9b334a45a8ff	1235	/* CSS NMI IRQ handler */
bogdanm	0:9b334a45a8ff	1236	void HAL_RCC_NMI_IRQHandler(void);
bogdanm	0:9b334a45a8ff	1237
bogdanm	0:9b334a45a8ff	1238	/* User Callbacks in non blocking mode (IT mode) */
bogdanm	0:9b334a45a8ff	1239	void HAL_RCC_CSSCallback(void);
bogdanm	0:9b334a45a8ff	1240
bogdanm	0:9b334a45a8ff	1241	/**
bogdanm	0:9b334a45a8ff	1242	* @}
bogdanm	0:9b334a45a8ff	1243	*/
bogdanm	0:9b334a45a8ff	1244
bogdanm	0:9b334a45a8ff	1245	/**
bogdanm	0:9b334a45a8ff	1246	* @}
bogdanm	0:9b334a45a8ff	1247	*/
bogdanm	0:9b334a45a8ff	1248
bogdanm	0:9b334a45a8ff	1249	/**
bogdanm	0:9b334a45a8ff	1250	* @}
bogdanm	0:9b334a45a8ff	1251	*/
bogdanm	0:9b334a45a8ff	1252
bogdanm	0:9b334a45a8ff	1253	/**
bogdanm	0:9b334a45a8ff	1254	* @}
bogdanm	0:9b334a45a8ff	1255	*/
bogdanm	0:9b334a45a8ff	1256
bogdanm	0:9b334a45a8ff	1257	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1258	}
bogdanm	0:9b334a45a8ff	1259	#endif
bogdanm	0:9b334a45a8ff	1260
bogdanm	0:9b334a45a8ff	1261	#endif /* __STM32F1xx_HAL_RCC_H */
bogdanm	0:9b334a45a8ff	1262
bogdanm	0:9b334a45a8ff	1263	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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