mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212_features.h@121:7f86b4238bec, 2016-05-03 (annotated)

Committer:: mbed_official
Date:: Tue May 03 00:15:16 2016 +0100
Revision:: 121:7f86b4238bec

Synchronized with git revision 9cef243de23875778f461bbe9a8c1bc47e65212b



Full URL: https://github.com/mbedmicro/mbed/commit/9cef243de23875778f461bbe9a8c1bc47e65212b/



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User	Revision	Line number	New contents of line
mbed_official	121:7f86b4238bec	1	/*
mbed_official	121:7f86b4238bec	2	** ###################################################################
mbed_official	121:7f86b4238bec	3	** Version: rev. 2.14, 2015-06-08
mbed_official	121:7f86b4238bec	4	** Build: b151216
mbed_official	121:7f86b4238bec	5	**
mbed_official	121:7f86b4238bec	6	** Abstract:
mbed_official	121:7f86b4238bec	7	** Chip specific module features.
mbed_official	121:7f86b4238bec	8	**
mbed_official	121:7f86b4238bec	9	** Copyright (c) 2015 Freescale Semiconductor, Inc.
mbed_official	121:7f86b4238bec	10	** All rights reserved.
mbed_official	121:7f86b4238bec	11	**
mbed_official	121:7f86b4238bec	12	** Redistribution and use in source and binary forms, with or without modification,
mbed_official	121:7f86b4238bec	13	** are permitted provided that the following conditions are met:
mbed_official	121:7f86b4238bec	14	**
mbed_official	121:7f86b4238bec	15	** o Redistributions of source code must retain the above copyright notice, this list
mbed_official	121:7f86b4238bec	16	** of conditions and the following disclaimer.
mbed_official	121:7f86b4238bec	17	**
mbed_official	121:7f86b4238bec	18	** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official	121:7f86b4238bec	19	** list of conditions and the following disclaimer in the documentation and/or
mbed_official	121:7f86b4238bec	20	** other materials provided with the distribution.
mbed_official	121:7f86b4238bec	21	**
mbed_official	121:7f86b4238bec	22	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official	121:7f86b4238bec	23	** contributors may be used to endorse or promote products derived from this
mbed_official	121:7f86b4238bec	24	** software without specific prior written permission.
mbed_official	121:7f86b4238bec	25	**
mbed_official	121:7f86b4238bec	26	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official	121:7f86b4238bec	27	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official	121:7f86b4238bec	28	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	121:7f86b4238bec	29	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official	121:7f86b4238bec	30	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official	121:7f86b4238bec	31	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official	121:7f86b4238bec	32	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official	121:7f86b4238bec	33	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official	121:7f86b4238bec	34	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official	121:7f86b4238bec	35	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	121:7f86b4238bec	36	**
mbed_official	121:7f86b4238bec	37	** http: www.freescale.com
mbed_official	121:7f86b4238bec	38	** mail: support@freescale.com
mbed_official	121:7f86b4238bec	39	**
mbed_official	121:7f86b4238bec	40	** Revisions:
mbed_official	121:7f86b4238bec	41	** - rev. 1.0 (2013-07-23)
mbed_official	121:7f86b4238bec	42	** Initial version.
mbed_official	121:7f86b4238bec	43	** - rev. 1.1 (2013-09-17)
mbed_official	121:7f86b4238bec	44	** RM rev. 0.4 update.
mbed_official	121:7f86b4238bec	45	** - rev. 2.0 (2013-10-29)
mbed_official	121:7f86b4238bec	46	** Register accessor macros added to the memory map.
mbed_official	121:7f86b4238bec	47	** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official	121:7f86b4238bec	48	** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official	121:7f86b4238bec	49	** System initialization updated.
mbed_official	121:7f86b4238bec	50	** - rev. 2.1 (2013-10-30)
mbed_official	121:7f86b4238bec	51	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official	121:7f86b4238bec	52	** - rev. 2.2 (2013-12-20)
mbed_official	121:7f86b4238bec	53	** Update according to reference manual rev. 0.6,
mbed_official	121:7f86b4238bec	54	** - rev. 2.3 (2014-01-13)
mbed_official	121:7f86b4238bec	55	** Update according to reference manual rev. 0.61,
mbed_official	121:7f86b4238bec	56	** - rev. 2.4 (2014-01-30)
mbed_official	121:7f86b4238bec	57	** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
mbed_official	121:7f86b4238bec	58	** - rev. 2.5 (2014-02-10)
mbed_official	121:7f86b4238bec	59	** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official	121:7f86b4238bec	60	** - rev. 2.6 (2014-05-06)
mbed_official	121:7f86b4238bec	61	** Update according to reference manual rev. 1.0,
mbed_official	121:7f86b4238bec	62	** Update of system and startup files.
mbed_official	121:7f86b4238bec	63	** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official	121:7f86b4238bec	64	** - rev. 2.7 (2014-08-28)
mbed_official	121:7f86b4238bec	65	** Update of system files - default clock configuration changed.
mbed_official	121:7f86b4238bec	66	** Update of startup files - possibility to override DefaultISR added.
mbed_official	121:7f86b4238bec	67	** - rev. 2.8 (2014-10-14)
mbed_official	121:7f86b4238bec	68	** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
mbed_official	121:7f86b4238bec	69	** - rev. 2.9 (2015-01-21)
mbed_official	121:7f86b4238bec	70	** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
mbed_official	121:7f86b4238bec	71	** - rev. 2.10 (2015-02-19)
mbed_official	121:7f86b4238bec	72	** Renamed interrupt vector LLW to LLWU.
mbed_official	121:7f86b4238bec	73	** - rev. 2.11 (2015-05-19)
mbed_official	121:7f86b4238bec	74	** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
mbed_official	121:7f86b4238bec	75	** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
mbed_official	121:7f86b4238bec	76	** Added features for PDB and PORT.
mbed_official	121:7f86b4238bec	77	** - rev. 2.12 (2015-05-25)
mbed_official	121:7f86b4238bec	78	** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
mbed_official	121:7f86b4238bec	79	** - rev. 2.13 (2015-05-27)
mbed_official	121:7f86b4238bec	80	** Several USB features added.
mbed_official	121:7f86b4238bec	81	** - rev. 2.14 (2015-06-08)
mbed_official	121:7f86b4238bec	82	** FTM features BUS_CLOCK and FAST_CLOCK removed.
mbed_official	121:7f86b4238bec	83	**
mbed_official	121:7f86b4238bec	84	** ###################################################################
mbed_official	121:7f86b4238bec	85	*/
mbed_official	121:7f86b4238bec	86
mbed_official	121:7f86b4238bec	87	#ifndef _MK22F51212_FEATURES_H_
mbed_official	121:7f86b4238bec	88	#define _MK22F51212_FEATURES_H_
mbed_official	121:7f86b4238bec	89
mbed_official	121:7f86b4238bec	90	/* SOC module features */
mbed_official	121:7f86b4238bec	91
mbed_official	121:7f86b4238bec	92	/* @brief ACMP availability on the SoC. */
mbed_official	121:7f86b4238bec	93	#define FSL_FEATURE_SOC_ACMP_COUNT (0)
mbed_official	121:7f86b4238bec	94	/* @brief ADC16 availability on the SoC. */
mbed_official	121:7f86b4238bec	95	#define FSL_FEATURE_SOC_ADC16_COUNT (2)
mbed_official	121:7f86b4238bec	96	/* @brief ADC12 availability on the SoC. */
mbed_official	121:7f86b4238bec	97	#define FSL_FEATURE_SOC_ADC12_COUNT (0)
mbed_official	121:7f86b4238bec	98	/* @brief AFE availability on the SoC. */
mbed_official	121:7f86b4238bec	99	#define FSL_FEATURE_SOC_AFE_COUNT (0)
mbed_official	121:7f86b4238bec	100	/* @brief AIPS availability on the SoC. */
mbed_official	121:7f86b4238bec	101	#define FSL_FEATURE_SOC_AIPS_COUNT (0)
mbed_official	121:7f86b4238bec	102	/* @brief AOI availability on the SoC. */
mbed_official	121:7f86b4238bec	103	#define FSL_FEATURE_SOC_AOI_COUNT (0)
mbed_official	121:7f86b4238bec	104	/* @brief AXBS availability on the SoC. */
mbed_official	121:7f86b4238bec	105	#define FSL_FEATURE_SOC_AXBS_COUNT (0)
mbed_official	121:7f86b4238bec	106	/* @brief ASMC availability on the SoC. */
mbed_official	121:7f86b4238bec	107	#define FSL_FEATURE_SOC_ASMC_COUNT (0)
mbed_official	121:7f86b4238bec	108	/* @brief CADC availability on the SoC. */
mbed_official	121:7f86b4238bec	109	#define FSL_FEATURE_SOC_CADC_COUNT (0)
mbed_official	121:7f86b4238bec	110	/* @brief FLEXCAN availability on the SoC. */
mbed_official	121:7f86b4238bec	111	#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
mbed_official	121:7f86b4238bec	112	/* @brief MMCAU availability on the SoC. */
mbed_official	121:7f86b4238bec	113	#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
mbed_official	121:7f86b4238bec	114	/* @brief CMP availability on the SoC. */
mbed_official	121:7f86b4238bec	115	#define FSL_FEATURE_SOC_CMP_COUNT (2)
mbed_official	121:7f86b4238bec	116	/* @brief CMT availability on the SoC. */
mbed_official	121:7f86b4238bec	117	#define FSL_FEATURE_SOC_CMT_COUNT (0)
mbed_official	121:7f86b4238bec	118	/* @brief CNC availability on the SoC. */
mbed_official	121:7f86b4238bec	119	#define FSL_FEATURE_SOC_CNC_COUNT (0)
mbed_official	121:7f86b4238bec	120	/* @brief CRC availability on the SoC. */
mbed_official	121:7f86b4238bec	121	#define FSL_FEATURE_SOC_CRC_COUNT (1)
mbed_official	121:7f86b4238bec	122	/* @brief DAC availability on the SoC. */
mbed_official	121:7f86b4238bec	123	#define FSL_FEATURE_SOC_DAC_COUNT (2)
mbed_official	121:7f86b4238bec	124	/* @brief DAC32 availability on the SoC. */
mbed_official	121:7f86b4238bec	125	#define FSL_FEATURE_SOC_DAC32_COUNT (0)
mbed_official	121:7f86b4238bec	126	/* @brief DCDC availability on the SoC. */
mbed_official	121:7f86b4238bec	127	#define FSL_FEATURE_SOC_DCDC_COUNT (0)
mbed_official	121:7f86b4238bec	128	/* @brief DDR availability on the SoC. */
mbed_official	121:7f86b4238bec	129	#define FSL_FEATURE_SOC_DDR_COUNT (0)
mbed_official	121:7f86b4238bec	130	/* @brief DMA availability on the SoC. */
mbed_official	121:7f86b4238bec	131	#define FSL_FEATURE_SOC_DMA_COUNT (0)
mbed_official	121:7f86b4238bec	132	/* @brief EDMA availability on the SoC. */
mbed_official	121:7f86b4238bec	133	#define FSL_FEATURE_SOC_EDMA_COUNT (1)
mbed_official	121:7f86b4238bec	134	/* @brief DMAMUX availability on the SoC. */
mbed_official	121:7f86b4238bec	135	#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
mbed_official	121:7f86b4238bec	136	/* @brief DRY availability on the SoC. */
mbed_official	121:7f86b4238bec	137	#define FSL_FEATURE_SOC_DRY_COUNT (0)
mbed_official	121:7f86b4238bec	138	/* @brief DSPI availability on the SoC. */
mbed_official	121:7f86b4238bec	139	#define FSL_FEATURE_SOC_DSPI_COUNT (2)
mbed_official	121:7f86b4238bec	140	/* @brief EMVSIM availability on the SoC. */
mbed_official	121:7f86b4238bec	141	#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
mbed_official	121:7f86b4238bec	142	/* @brief ENC availability on the SoC. */
mbed_official	121:7f86b4238bec	143	#define FSL_FEATURE_SOC_ENC_COUNT (0)
mbed_official	121:7f86b4238bec	144	/* @brief ENET availability on the SoC. */
mbed_official	121:7f86b4238bec	145	#define FSL_FEATURE_SOC_ENET_COUNT (0)
mbed_official	121:7f86b4238bec	146	/* @brief EWM availability on the SoC. */
mbed_official	121:7f86b4238bec	147	#define FSL_FEATURE_SOC_EWM_COUNT (1)
mbed_official	121:7f86b4238bec	148	/* @brief FB availability on the SoC. */
mbed_official	121:7f86b4238bec	149	#define FSL_FEATURE_SOC_FB_COUNT (1)
mbed_official	121:7f86b4238bec	150	/* @brief FGPIO availability on the SoC. */
mbed_official	121:7f86b4238bec	151	#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
mbed_official	121:7f86b4238bec	152	/* @brief FLEXIO availability on the SoC. */
mbed_official	121:7f86b4238bec	153	#define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
mbed_official	121:7f86b4238bec	154	/* @brief FMC availability on the SoC. */
mbed_official	121:7f86b4238bec	155	#define FSL_FEATURE_SOC_FMC_COUNT (1)
mbed_official	121:7f86b4238bec	156	/* @brief FSKDT availability on the SoC. */
mbed_official	121:7f86b4238bec	157	#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
mbed_official	121:7f86b4238bec	158	/* @brief FTFA availability on the SoC. */
mbed_official	121:7f86b4238bec	159	#define FSL_FEATURE_SOC_FTFA_COUNT (1)
mbed_official	121:7f86b4238bec	160	/* @brief FTFE availability on the SoC. */
mbed_official	121:7f86b4238bec	161	#define FSL_FEATURE_SOC_FTFE_COUNT (0)
mbed_official	121:7f86b4238bec	162	/* @brief FTFL availability on the SoC. */
mbed_official	121:7f86b4238bec	163	#define FSL_FEATURE_SOC_FTFL_COUNT (0)
mbed_official	121:7f86b4238bec	164	/* @brief FTM availability on the SoC. */
mbed_official	121:7f86b4238bec	165	#define FSL_FEATURE_SOC_FTM_COUNT (4)
mbed_official	121:7f86b4238bec	166	/* @brief FTMRA availability on the SoC. */
mbed_official	121:7f86b4238bec	167	#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
mbed_official	121:7f86b4238bec	168	/* @brief FTMRE availability on the SoC. */
mbed_official	121:7f86b4238bec	169	#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
mbed_official	121:7f86b4238bec	170	/* @brief FTMRH availability on the SoC. */
mbed_official	121:7f86b4238bec	171	#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
mbed_official	121:7f86b4238bec	172	/* @brief GPIO availability on the SoC. */
mbed_official	121:7f86b4238bec	173	#define FSL_FEATURE_SOC_GPIO_COUNT (5)
mbed_official	121:7f86b4238bec	174	/* @brief HSADC availability on the SoC. */
mbed_official	121:7f86b4238bec	175	#define FSL_FEATURE_SOC_HSADC_COUNT (0)
mbed_official	121:7f86b4238bec	176	/* @brief I2C availability on the SoC. */
mbed_official	121:7f86b4238bec	177	#define FSL_FEATURE_SOC_I2C_COUNT (2)
mbed_official	121:7f86b4238bec	178	/* @brief I2S availability on the SoC. */
mbed_official	121:7f86b4238bec	179	#define FSL_FEATURE_SOC_I2S_COUNT (1)
mbed_official	121:7f86b4238bec	180	/* @brief ICS availability on the SoC. */
mbed_official	121:7f86b4238bec	181	#define FSL_FEATURE_SOC_ICS_COUNT (0)
mbed_official	121:7f86b4238bec	182	/* @brief INTMUX availability on the SoC. */
mbed_official	121:7f86b4238bec	183	#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
mbed_official	121:7f86b4238bec	184	/* @brief IRQ availability on the SoC. */
mbed_official	121:7f86b4238bec	185	#define FSL_FEATURE_SOC_IRQ_COUNT (0)
mbed_official	121:7f86b4238bec	186	/* @brief KBI availability on the SoC. */
mbed_official	121:7f86b4238bec	187	#define FSL_FEATURE_SOC_KBI_COUNT (0)
mbed_official	121:7f86b4238bec	188	/* @brief SLCD availability on the SoC. */
mbed_official	121:7f86b4238bec	189	#define FSL_FEATURE_SOC_SLCD_COUNT (0)
mbed_official	121:7f86b4238bec	190	/* @brief LCDC availability on the SoC. */
mbed_official	121:7f86b4238bec	191	#define FSL_FEATURE_SOC_LCDC_COUNT (0)
mbed_official	121:7f86b4238bec	192	/* @brief LDO availability on the SoC. */
mbed_official	121:7f86b4238bec	193	#define FSL_FEATURE_SOC_LDO_COUNT (0)
mbed_official	121:7f86b4238bec	194	/* @brief LLWU availability on the SoC. */
mbed_official	121:7f86b4238bec	195	#define FSL_FEATURE_SOC_LLWU_COUNT (1)
mbed_official	121:7f86b4238bec	196	/* @brief LMEM availability on the SoC. */
mbed_official	121:7f86b4238bec	197	#define FSL_FEATURE_SOC_LMEM_COUNT (0)
mbed_official	121:7f86b4238bec	198	/* @brief LPI2C availability on the SoC. */
mbed_official	121:7f86b4238bec	199	#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
mbed_official	121:7f86b4238bec	200	/* @brief LPIT availability on the SoC. */
mbed_official	121:7f86b4238bec	201	#define FSL_FEATURE_SOC_LPIT_COUNT (0)
mbed_official	121:7f86b4238bec	202	/* @brief LPSCI availability on the SoC. */
mbed_official	121:7f86b4238bec	203	#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
mbed_official	121:7f86b4238bec	204	/* @brief LPSPI availability on the SoC. */
mbed_official	121:7f86b4238bec	205	#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
mbed_official	121:7f86b4238bec	206	/* @brief LPTMR availability on the SoC. */
mbed_official	121:7f86b4238bec	207	#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
mbed_official	121:7f86b4238bec	208	/* @brief LPTPM availability on the SoC. */
mbed_official	121:7f86b4238bec	209	#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
mbed_official	121:7f86b4238bec	210	/* @brief LPUART availability on the SoC. */
mbed_official	121:7f86b4238bec	211	#define FSL_FEATURE_SOC_LPUART_COUNT (1)
mbed_official	121:7f86b4238bec	212	/* @brief LTC availability on the SoC. */
mbed_official	121:7f86b4238bec	213	#define FSL_FEATURE_SOC_LTC_COUNT (0)
mbed_official	121:7f86b4238bec	214	/* @brief MC availability on the SoC. */
mbed_official	121:7f86b4238bec	215	#define FSL_FEATURE_SOC_MC_COUNT (0)
mbed_official	121:7f86b4238bec	216	/* @brief MCG availability on the SoC. */
mbed_official	121:7f86b4238bec	217	#define FSL_FEATURE_SOC_MCG_COUNT (1)
mbed_official	121:7f86b4238bec	218	/* @brief MCGLITE availability on the SoC. */
mbed_official	121:7f86b4238bec	219	#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
mbed_official	121:7f86b4238bec	220	/* @brief MCM availability on the SoC. */
mbed_official	121:7f86b4238bec	221	#define FSL_FEATURE_SOC_MCM_COUNT (1)
mbed_official	121:7f86b4238bec	222	/* @brief MMAU availability on the SoC. */
mbed_official	121:7f86b4238bec	223	#define FSL_FEATURE_SOC_MMAU_COUNT (0)
mbed_official	121:7f86b4238bec	224	/* @brief MMDVSQ availability on the SoC. */
mbed_official	121:7f86b4238bec	225	#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
mbed_official	121:7f86b4238bec	226	/* @brief MPU availability on the SoC. */
mbed_official	121:7f86b4238bec	227	#define FSL_FEATURE_SOC_MPU_COUNT (0)
mbed_official	121:7f86b4238bec	228	/* @brief MSCAN availability on the SoC. */
mbed_official	121:7f86b4238bec	229	#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
mbed_official	121:7f86b4238bec	230	/* @brief MSCM availability on the SoC. */
mbed_official	121:7f86b4238bec	231	#define FSL_FEATURE_SOC_MSCM_COUNT (0)
mbed_official	121:7f86b4238bec	232	/* @brief MTB availability on the SoC. */
mbed_official	121:7f86b4238bec	233	#define FSL_FEATURE_SOC_MTB_COUNT (0)
mbed_official	121:7f86b4238bec	234	/* @brief MTBDWT availability on the SoC. */
mbed_official	121:7f86b4238bec	235	#define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
mbed_official	121:7f86b4238bec	236	/* @brief MU availability on the SoC. */
mbed_official	121:7f86b4238bec	237	#define FSL_FEATURE_SOC_MU_COUNT (0)
mbed_official	121:7f86b4238bec	238	/* @brief NFC availability on the SoC. */
mbed_official	121:7f86b4238bec	239	#define FSL_FEATURE_SOC_NFC_COUNT (0)
mbed_official	121:7f86b4238bec	240	/* @brief OPAMP availability on the SoC. */
mbed_official	121:7f86b4238bec	241	#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
mbed_official	121:7f86b4238bec	242	/* @brief OSC availability on the SoC. */
mbed_official	121:7f86b4238bec	243	#define FSL_FEATURE_SOC_OSC_COUNT (1)
mbed_official	121:7f86b4238bec	244	/* @brief OSC32 availability on the SoC. */
mbed_official	121:7f86b4238bec	245	#define FSL_FEATURE_SOC_OSC32_COUNT (0)
mbed_official	121:7f86b4238bec	246	/* @brief OTFAD availability on the SoC. */
mbed_official	121:7f86b4238bec	247	#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
mbed_official	121:7f86b4238bec	248	/* @brief PDB availability on the SoC. */
mbed_official	121:7f86b4238bec	249	#define FSL_FEATURE_SOC_PDB_COUNT (1)
mbed_official	121:7f86b4238bec	250	/* @brief PCC availability on the SoC. */
mbed_official	121:7f86b4238bec	251	#define FSL_FEATURE_SOC_PCC_COUNT (0)
mbed_official	121:7f86b4238bec	252	/* @brief PGA availability on the SoC. */
mbed_official	121:7f86b4238bec	253	#define FSL_FEATURE_SOC_PGA_COUNT (0)
mbed_official	121:7f86b4238bec	254	/* @brief PIT availability on the SoC. */
mbed_official	121:7f86b4238bec	255	#define FSL_FEATURE_SOC_PIT_COUNT (1)
mbed_official	121:7f86b4238bec	256	/* @brief PMC availability on the SoC. */
mbed_official	121:7f86b4238bec	257	#define FSL_FEATURE_SOC_PMC_COUNT (1)
mbed_official	121:7f86b4238bec	258	/* @brief PORT availability on the SoC. */
mbed_official	121:7f86b4238bec	259	#define FSL_FEATURE_SOC_PORT_COUNT (5)
mbed_official	121:7f86b4238bec	260	/* @brief PWM availability on the SoC. */
mbed_official	121:7f86b4238bec	261	#define FSL_FEATURE_SOC_PWM_COUNT (0)
mbed_official	121:7f86b4238bec	262	/* @brief PWT availability on the SoC. */
mbed_official	121:7f86b4238bec	263	#define FSL_FEATURE_SOC_PWT_COUNT (0)
mbed_official	121:7f86b4238bec	264	/* @brief QuadSPI availability on the SoC. */
mbed_official	121:7f86b4238bec	265	#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
mbed_official	121:7f86b4238bec	266	/* @brief RCM availability on the SoC. */
mbed_official	121:7f86b4238bec	267	#define FSL_FEATURE_SOC_RCM_COUNT (1)
mbed_official	121:7f86b4238bec	268	/* @brief RFSYS availability on the SoC. */
mbed_official	121:7f86b4238bec	269	#define FSL_FEATURE_SOC_RFSYS_COUNT (1)
mbed_official	121:7f86b4238bec	270	/* @brief RFVBAT availability on the SoC. */
mbed_official	121:7f86b4238bec	271	#define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
mbed_official	121:7f86b4238bec	272	/* @brief RNG availability on the SoC. */
mbed_official	121:7f86b4238bec	273	#define FSL_FEATURE_SOC_RNG_COUNT (1)
mbed_official	121:7f86b4238bec	274	/* @brief RNGB availability on the SoC. */
mbed_official	121:7f86b4238bec	275	#define FSL_FEATURE_SOC_RNGB_COUNT (0)
mbed_official	121:7f86b4238bec	276	/* @brief ROM availability on the SoC. */
mbed_official	121:7f86b4238bec	277	#define FSL_FEATURE_SOC_ROM_COUNT (0)
mbed_official	121:7f86b4238bec	278	/* @brief RSIM availability on the SoC. */
mbed_official	121:7f86b4238bec	279	#define FSL_FEATURE_SOC_RSIM_COUNT (0)
mbed_official	121:7f86b4238bec	280	/* @brief RTC availability on the SoC. */
mbed_official	121:7f86b4238bec	281	#define FSL_FEATURE_SOC_RTC_COUNT (1)
mbed_official	121:7f86b4238bec	282	/* @brief SCG availability on the SoC. */
mbed_official	121:7f86b4238bec	283	#define FSL_FEATURE_SOC_SCG_COUNT (0)
mbed_official	121:7f86b4238bec	284	/* @brief SCI availability on the SoC. */
mbed_official	121:7f86b4238bec	285	#define FSL_FEATURE_SOC_SCI_COUNT (0)
mbed_official	121:7f86b4238bec	286	/* @brief SDHC availability on the SoC. */
mbed_official	121:7f86b4238bec	287	#define FSL_FEATURE_SOC_SDHC_COUNT (0)
mbed_official	121:7f86b4238bec	288	/* @brief SDRAM availability on the SoC. */
mbed_official	121:7f86b4238bec	289	#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
mbed_official	121:7f86b4238bec	290	/* @brief SEMA42 availability on the SoC. */
mbed_official	121:7f86b4238bec	291	#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
mbed_official	121:7f86b4238bec	292	/* @brief SIM availability on the SoC. */
mbed_official	121:7f86b4238bec	293	#define FSL_FEATURE_SOC_SIM_COUNT (1)
mbed_official	121:7f86b4238bec	294	/* @brief SMC availability on the SoC. */
mbed_official	121:7f86b4238bec	295	#define FSL_FEATURE_SOC_SMC_COUNT (1)
mbed_official	121:7f86b4238bec	296	/* @brief SPI availability on the SoC. */
mbed_official	121:7f86b4238bec	297	#define FSL_FEATURE_SOC_SPI_COUNT (0)
mbed_official	121:7f86b4238bec	298	/* @brief TMR availability on the SoC. */
mbed_official	121:7f86b4238bec	299	#define FSL_FEATURE_SOC_TMR_COUNT (0)
mbed_official	121:7f86b4238bec	300	/* @brief TPM availability on the SoC. */
mbed_official	121:7f86b4238bec	301	#define FSL_FEATURE_SOC_TPM_COUNT (0)
mbed_official	121:7f86b4238bec	302	/* @brief TRGMUX availability on the SoC. */
mbed_official	121:7f86b4238bec	303	#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
mbed_official	121:7f86b4238bec	304	/* @brief TRIAMP availability on the SoC. */
mbed_official	121:7f86b4238bec	305	#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
mbed_official	121:7f86b4238bec	306	/* @brief TRNG availability on the SoC. */
mbed_official	121:7f86b4238bec	307	#define FSL_FEATURE_SOC_TRNG_COUNT (0)
mbed_official	121:7f86b4238bec	308	/* @brief TSI availability on the SoC. */
mbed_official	121:7f86b4238bec	309	#define FSL_FEATURE_SOC_TSI_COUNT (0)
mbed_official	121:7f86b4238bec	310	/* @brief TSTMR availability on the SoC. */
mbed_official	121:7f86b4238bec	311	#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
mbed_official	121:7f86b4238bec	312	/* @brief UART availability on the SoC. */
mbed_official	121:7f86b4238bec	313	#define FSL_FEATURE_SOC_UART_COUNT (3)
mbed_official	121:7f86b4238bec	314	/* @brief USB availability on the SoC. */
mbed_official	121:7f86b4238bec	315	#define FSL_FEATURE_SOC_USB_COUNT (1)
mbed_official	121:7f86b4238bec	316	/* @brief USBDCD availability on the SoC. */
mbed_official	121:7f86b4238bec	317	#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
mbed_official	121:7f86b4238bec	318	/* @brief USBHSDCD availability on the SoC. */
mbed_official	121:7f86b4238bec	319	#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
mbed_official	121:7f86b4238bec	320	/* @brief USBPHY availability on the SoC. */
mbed_official	121:7f86b4238bec	321	#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
mbed_official	121:7f86b4238bec	322	/* @brief VREF availability on the SoC. */
mbed_official	121:7f86b4238bec	323	#define FSL_FEATURE_SOC_VREF_COUNT (1)
mbed_official	121:7f86b4238bec	324	/* @brief WDOG availability on the SoC. */
mbed_official	121:7f86b4238bec	325	#define FSL_FEATURE_SOC_WDOG_COUNT (1)
mbed_official	121:7f86b4238bec	326	/* @brief XBAR availability on the SoC. */
mbed_official	121:7f86b4238bec	327	#define FSL_FEATURE_SOC_XBAR_COUNT (0)
mbed_official	121:7f86b4238bec	328	/* @brief XBARA availability on the SoC. */
mbed_official	121:7f86b4238bec	329	#define FSL_FEATURE_SOC_XBARA_COUNT (0)
mbed_official	121:7f86b4238bec	330	/* @brief XBARB availability on the SoC. */
mbed_official	121:7f86b4238bec	331	#define FSL_FEATURE_SOC_XBARB_COUNT (0)
mbed_official	121:7f86b4238bec	332	/* @brief XCVR availability on the SoC. */
mbed_official	121:7f86b4238bec	333	#define FSL_FEATURE_SOC_XCVR_COUNT (0)
mbed_official	121:7f86b4238bec	334	/* @brief XRDC availability on the SoC. */
mbed_official	121:7f86b4238bec	335	#define FSL_FEATURE_SOC_XRDC_COUNT (0)
mbed_official	121:7f86b4238bec	336	/* @brief ZLL availability on the SoC. */
mbed_official	121:7f86b4238bec	337	#define FSL_FEATURE_SOC_ZLL_COUNT (0)
mbed_official	121:7f86b4238bec	338
mbed_official	121:7f86b4238bec	339	/* ADC16 module features */
mbed_official	121:7f86b4238bec	340
mbed_official	121:7f86b4238bec	341	/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
mbed_official	121:7f86b4238bec	342	#define FSL_FEATURE_ADC16_HAS_PGA (0)
mbed_official	121:7f86b4238bec	343	/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
mbed_official	121:7f86b4238bec	344	#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
mbed_official	121:7f86b4238bec	345	/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
mbed_official	121:7f86b4238bec	346	#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
mbed_official	121:7f86b4238bec	347	/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
mbed_official	121:7f86b4238bec	348	#define FSL_FEATURE_ADC16_HAS_DMA (1)
mbed_official	121:7f86b4238bec	349	/* @brief Has differential mode (bitfield SC1x[DIFF]). */
mbed_official	121:7f86b4238bec	350	#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
mbed_official	121:7f86b4238bec	351	/* @brief Has FIFO (bit SC4[AFDEP]). */
mbed_official	121:7f86b4238bec	352	#define FSL_FEATURE_ADC16_HAS_FIFO (0)
mbed_official	121:7f86b4238bec	353	/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
mbed_official	121:7f86b4238bec	354	#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
mbed_official	121:7f86b4238bec	355	/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
mbed_official	121:7f86b4238bec	356	#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
mbed_official	121:7f86b4238bec	357	/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
mbed_official	121:7f86b4238bec	358	#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
mbed_official	121:7f86b4238bec	359	/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
mbed_official	121:7f86b4238bec	360	#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
mbed_official	121:7f86b4238bec	361	/* @brief Has HW averaging (bit SC3[AVGE]). */
mbed_official	121:7f86b4238bec	362	#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
mbed_official	121:7f86b4238bec	363	/* @brief Has offset correction (register OFS). */
mbed_official	121:7f86b4238bec	364	#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
mbed_official	121:7f86b4238bec	365	/* @brief Maximum ADC resolution. */
mbed_official	121:7f86b4238bec	366	#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
mbed_official	121:7f86b4238bec	367	/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
mbed_official	121:7f86b4238bec	368	#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
mbed_official	121:7f86b4238bec	369
mbed_official	121:7f86b4238bec	370	/* CMP module features */
mbed_official	121:7f86b4238bec	371
mbed_official	121:7f86b4238bec	372	/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
mbed_official	121:7f86b4238bec	373	#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
mbed_official	121:7f86b4238bec	374	/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
mbed_official	121:7f86b4238bec	375	#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
mbed_official	121:7f86b4238bec	376	/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
mbed_official	121:7f86b4238bec	377	#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
mbed_official	121:7f86b4238bec	378	/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
mbed_official	121:7f86b4238bec	379	#define FSL_FEATURE_CMP_HAS_DMA (1)
mbed_official	121:7f86b4238bec	380	/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
mbed_official	121:7f86b4238bec	381	#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
mbed_official	121:7f86b4238bec	382	/* @brief Has DAC Test function in CMP (register DACTEST). */
mbed_official	121:7f86b4238bec	383	#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
mbed_official	121:7f86b4238bec	384
mbed_official	121:7f86b4238bec	385	/* CRC module features */
mbed_official	121:7f86b4238bec	386
mbed_official	121:7f86b4238bec	387	/* @brief Has data register with name CRC */
mbed_official	121:7f86b4238bec	388	#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
mbed_official	121:7f86b4238bec	389
mbed_official	121:7f86b4238bec	390	/* DAC module features */
mbed_official	121:7f86b4238bec	391
mbed_official	121:7f86b4238bec	392	/* @brief Define the size of hardware buffer */
mbed_official	121:7f86b4238bec	393	#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
mbed_official	121:7f86b4238bec	394	/* @brief Define whether the buffer supports watermark event detection or not. */
mbed_official	121:7f86b4238bec	395	#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
mbed_official	121:7f86b4238bec	396	/* @brief Define whether the buffer supports watermark selection detection or not. */
mbed_official	121:7f86b4238bec	397	#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
mbed_official	121:7f86b4238bec	398	/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
mbed_official	121:7f86b4238bec	399	#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
mbed_official	121:7f86b4238bec	400	/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
mbed_official	121:7f86b4238bec	401	#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
mbed_official	121:7f86b4238bec	402	/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
mbed_official	121:7f86b4238bec	403	#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
mbed_official	121:7f86b4238bec	404	/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
mbed_official	121:7f86b4238bec	405	#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
mbed_official	121:7f86b4238bec	406	/* @brief Define whether FIFO buffer mode is available or not. */
mbed_official	121:7f86b4238bec	407	#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1)
mbed_official	121:7f86b4238bec	408	/* @brief Define whether swing buffer mode is available or not.. */
mbed_official	121:7f86b4238bec	409	#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
mbed_official	121:7f86b4238bec	410
mbed_official	121:7f86b4238bec	411	/* EDMA module features */
mbed_official	121:7f86b4238bec	412
mbed_official	121:7f86b4238bec	413	/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
mbed_official	121:7f86b4238bec	414	#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
mbed_official	121:7f86b4238bec	415	/* @brief Total number of DMA channels on all modules. */
mbed_official	121:7f86b4238bec	416	#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 16)
mbed_official	121:7f86b4238bec	417	/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
mbed_official	121:7f86b4238bec	418	#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
mbed_official	121:7f86b4238bec	419	/* @brief Has DMA_Error interrupt vector. */
mbed_official	121:7f86b4238bec	420	#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
mbed_official	121:7f86b4238bec	421	/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
mbed_official	121:7f86b4238bec	422	#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16)
mbed_official	121:7f86b4238bec	423
mbed_official	121:7f86b4238bec	424	/* DMAMUX module features */
mbed_official	121:7f86b4238bec	425
mbed_official	121:7f86b4238bec	426	/* @brief Number of DMA channels (related to number of register CHCFGn). */
mbed_official	121:7f86b4238bec	427	#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
mbed_official	121:7f86b4238bec	428	/* @brief Total number of DMA channels on all modules. */
mbed_official	121:7f86b4238bec	429	#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16)
mbed_official	121:7f86b4238bec	430	/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
mbed_official	121:7f86b4238bec	431	#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
mbed_official	121:7f86b4238bec	432
mbed_official	121:7f86b4238bec	433	/* EWM module features */
mbed_official	121:7f86b4238bec	434
mbed_official	121:7f86b4238bec	435	/* @brief Has clock select (register CLKCTRL). */
mbed_official	121:7f86b4238bec	436	#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0)
mbed_official	121:7f86b4238bec	437	/* @brief Has clock prescaler (register CLKPRESCALER). */
mbed_official	121:7f86b4238bec	438	#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
mbed_official	121:7f86b4238bec	439
mbed_official	121:7f86b4238bec	440	/* FLEXBUS module features */
mbed_official	121:7f86b4238bec	441
mbed_official	121:7f86b4238bec	442	/* No feature definitions */
mbed_official	121:7f86b4238bec	443
mbed_official	121:7f86b4238bec	444	/* FLASH module features */
mbed_official	121:7f86b4238bec	445
mbed_official	121:7f86b4238bec	446	/* @brief Is of type FTFA. */
mbed_official	121:7f86b4238bec	447	#define FSL_FEATURE_FLASH_IS_FTFA (1)
mbed_official	121:7f86b4238bec	448	/* @brief Is of type FTFE. */
mbed_official	121:7f86b4238bec	449	#define FSL_FEATURE_FLASH_IS_FTFE (0)
mbed_official	121:7f86b4238bec	450	/* @brief Is of type FTFL. */
mbed_official	121:7f86b4238bec	451	#define FSL_FEATURE_FLASH_IS_FTFL (0)
mbed_official	121:7f86b4238bec	452	/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
mbed_official	121:7f86b4238bec	453	#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
mbed_official	121:7f86b4238bec	454	/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
mbed_official	121:7f86b4238bec	455	#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
mbed_official	121:7f86b4238bec	456	/* @brief Has EEPROM region protection (register FEPROT). */
mbed_official	121:7f86b4238bec	457	#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
mbed_official	121:7f86b4238bec	458	/* @brief Has data flash region protection (register FDPROT). */
mbed_official	121:7f86b4238bec	459	#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
mbed_official	121:7f86b4238bec	460	/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
mbed_official	121:7f86b4238bec	461	#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
mbed_official	121:7f86b4238bec	462	/* @brief Has flash cache control in FMC module. */
mbed_official	121:7f86b4238bec	463	#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
mbed_official	121:7f86b4238bec	464	/* @brief Has flash cache control in MCM module. */
mbed_official	121:7f86b4238bec	465	#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
mbed_official	121:7f86b4238bec	466	/* @brief P-Flash start address. */
mbed_official	121:7f86b4238bec	467	#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
mbed_official	121:7f86b4238bec	468	/* @brief P-Flash block count. */
mbed_official	121:7f86b4238bec	469	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
mbed_official	121:7f86b4238bec	470	/* @brief P-Flash block size. */
mbed_official	121:7f86b4238bec	471	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144)
mbed_official	121:7f86b4238bec	472	/* @brief P-Flash sector size. */
mbed_official	121:7f86b4238bec	473	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
mbed_official	121:7f86b4238bec	474	/* @brief P-Flash write unit size. */
mbed_official	121:7f86b4238bec	475	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
mbed_official	121:7f86b4238bec	476	/* @brief P-Flash data path width. */
mbed_official	121:7f86b4238bec	477	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
mbed_official	121:7f86b4238bec	478	/* @brief P-Flash block swap feature. */
mbed_official	121:7f86b4238bec	479	#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
mbed_official	121:7f86b4238bec	480	/* @brief Has FlexNVM memory. */
mbed_official	121:7f86b4238bec	481	#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
mbed_official	121:7f86b4238bec	482	/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
mbed_official	121:7f86b4238bec	483	#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
mbed_official	121:7f86b4238bec	484	/* @brief FlexNVM block count. */
mbed_official	121:7f86b4238bec	485	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
mbed_official	121:7f86b4238bec	486	/* @brief FlexNVM block size. */
mbed_official	121:7f86b4238bec	487	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
mbed_official	121:7f86b4238bec	488	/* @brief FlexNVM sector size. */
mbed_official	121:7f86b4238bec	489	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
mbed_official	121:7f86b4238bec	490	/* @brief FlexNVM write unit size. */
mbed_official	121:7f86b4238bec	491	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
mbed_official	121:7f86b4238bec	492	/* @brief FlexNVM data path width. */
mbed_official	121:7f86b4238bec	493	#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
mbed_official	121:7f86b4238bec	494	/* @brief Has FlexRAM memory. */
mbed_official	121:7f86b4238bec	495	#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
mbed_official	121:7f86b4238bec	496	/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
mbed_official	121:7f86b4238bec	497	#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
mbed_official	121:7f86b4238bec	498	/* @brief FlexRAM size. */
mbed_official	121:7f86b4238bec	499	#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
mbed_official	121:7f86b4238bec	500	/* @brief Has 0x00 Read 1s Block command. */
mbed_official	121:7f86b4238bec	501	#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
mbed_official	121:7f86b4238bec	502	/* @brief Has 0x01 Read 1s Section command. */
mbed_official	121:7f86b4238bec	503	#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
mbed_official	121:7f86b4238bec	504	/* @brief Has 0x02 Program Check command. */
mbed_official	121:7f86b4238bec	505	#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
mbed_official	121:7f86b4238bec	506	/* @brief Has 0x03 Read Resource command. */
mbed_official	121:7f86b4238bec	507	#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
mbed_official	121:7f86b4238bec	508	/* @brief Has 0x06 Program Longword command. */
mbed_official	121:7f86b4238bec	509	#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
mbed_official	121:7f86b4238bec	510	/* @brief Has 0x07 Program Phrase command. */
mbed_official	121:7f86b4238bec	511	#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
mbed_official	121:7f86b4238bec	512	/* @brief Has 0x08 Erase Flash Block command. */
mbed_official	121:7f86b4238bec	513	#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
mbed_official	121:7f86b4238bec	514	/* @brief Has 0x09 Erase Flash Sector command. */
mbed_official	121:7f86b4238bec	515	#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
mbed_official	121:7f86b4238bec	516	/* @brief Has 0x0B Program Section command. */
mbed_official	121:7f86b4238bec	517	#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
mbed_official	121:7f86b4238bec	518	/* @brief Has 0x40 Read 1s All Blocks command. */
mbed_official	121:7f86b4238bec	519	#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
mbed_official	121:7f86b4238bec	520	/* @brief Has 0x41 Read Once command. */
mbed_official	121:7f86b4238bec	521	#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
mbed_official	121:7f86b4238bec	522	/* @brief Has 0x43 Program Once command. */
mbed_official	121:7f86b4238bec	523	#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
mbed_official	121:7f86b4238bec	524	/* @brief Has 0x44 Erase All Blocks command. */
mbed_official	121:7f86b4238bec	525	#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
mbed_official	121:7f86b4238bec	526	/* @brief Has 0x45 Verify Backdoor Access Key command. */
mbed_official	121:7f86b4238bec	527	#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
mbed_official	121:7f86b4238bec	528	/* @brief Has 0x46 Swap Control command. */
mbed_official	121:7f86b4238bec	529	#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
mbed_official	121:7f86b4238bec	530	/* @brief Has 0x49 Erase All Blocks Unsecure command. */
mbed_official	121:7f86b4238bec	531	#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
mbed_official	121:7f86b4238bec	532	/* @brief Has 0x80 Program Partition command. */
mbed_official	121:7f86b4238bec	533	#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
mbed_official	121:7f86b4238bec	534	/* @brief Has 0x81 Set FlexRAM Function command. */
mbed_official	121:7f86b4238bec	535	#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
mbed_official	121:7f86b4238bec	536	/* @brief P-Flash Erase/Read 1st all block command address alignment. */
mbed_official	121:7f86b4238bec	537	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
mbed_official	121:7f86b4238bec	538	/* @brief P-Flash Erase sector command address alignment. */
mbed_official	121:7f86b4238bec	539	#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
mbed_official	121:7f86b4238bec	540	/* @brief P-Flash Rrogram/Verify section command address alignment. */
mbed_official	121:7f86b4238bec	541	#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
mbed_official	121:7f86b4238bec	542	/* @brief P-Flash Read resource command address alignment. */
mbed_official	121:7f86b4238bec	543	#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
mbed_official	121:7f86b4238bec	544	/* @brief P-Flash Program check command address alignment. */
mbed_official	121:7f86b4238bec	545	#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
mbed_official	121:7f86b4238bec	546	/* @brief P-Flash Program check command address alignment. */
mbed_official	121:7f86b4238bec	547	#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
mbed_official	121:7f86b4238bec	548	/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
mbed_official	121:7f86b4238bec	549	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
mbed_official	121:7f86b4238bec	550	/* @brief FlexNVM Erase sector command address alignment. */
mbed_official	121:7f86b4238bec	551	#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
mbed_official	121:7f86b4238bec	552	/* @brief FlexNVM Rrogram/Verify section command address alignment. */
mbed_official	121:7f86b4238bec	553	#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
mbed_official	121:7f86b4238bec	554	/* @brief FlexNVM Read resource command address alignment. */
mbed_official	121:7f86b4238bec	555	#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
mbed_official	121:7f86b4238bec	556	/* @brief FlexNVM Program check command address alignment. */
mbed_official	121:7f86b4238bec	557	#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
mbed_official	121:7f86b4238bec	558	/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	559	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	560	/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	561	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	562	/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	563	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	564	/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	565	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	566	/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	567	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	568	/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	569	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	570	/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	571	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	572	/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	573	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	574	/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	575	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	576	/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	577	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	578	/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	579	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	580	/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	581	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	582	/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	583	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	584	/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	585	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	586	/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	587	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	588	/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
mbed_official	121:7f86b4238bec	589	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
mbed_official	121:7f86b4238bec	590	/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	591	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
mbed_official	121:7f86b4238bec	592	/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	593	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
mbed_official	121:7f86b4238bec	594	/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	595	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
mbed_official	121:7f86b4238bec	596	/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	597	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
mbed_official	121:7f86b4238bec	598	/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	599	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
mbed_official	121:7f86b4238bec	600	/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	601	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
mbed_official	121:7f86b4238bec	602	/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	603	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
mbed_official	121:7f86b4238bec	604	/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	605	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
mbed_official	121:7f86b4238bec	606	/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	607	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
mbed_official	121:7f86b4238bec	608	/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	609	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
mbed_official	121:7f86b4238bec	610	/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	611	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
mbed_official	121:7f86b4238bec	612	/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	613	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
mbed_official	121:7f86b4238bec	614	/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	615	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
mbed_official	121:7f86b4238bec	616	/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	617	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
mbed_official	121:7f86b4238bec	618	/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	619	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
mbed_official	121:7f86b4238bec	620	/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
mbed_official	121:7f86b4238bec	621	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
mbed_official	121:7f86b4238bec	622
mbed_official	121:7f86b4238bec	623	/* FTM module features */
mbed_official	121:7f86b4238bec	624
mbed_official	121:7f86b4238bec	625	/* @brief Number of channels. */
mbed_official	121:7f86b4238bec	626	#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
mbed_official	121:7f86b4238bec	627	((x) == FTM0 ? (8) : \
mbed_official	121:7f86b4238bec	628	((x) == FTM1 ? (2) : \
mbed_official	121:7f86b4238bec	629	((x) == FTM2 ? (2) : \
mbed_official	121:7f86b4238bec	630	((x) == FTM3 ? (8) : (-1)))))
mbed_official	121:7f86b4238bec	631	/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
mbed_official	121:7f86b4238bec	632	#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
mbed_official	121:7f86b4238bec	633	/* @brief Enable pwm output for the module. */
mbed_official	121:7f86b4238bec	634	#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0)
mbed_official	121:7f86b4238bec	635	/* @brief Has half-cycle reload for the module. */
mbed_official	121:7f86b4238bec	636	#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0)
mbed_official	121:7f86b4238bec	637	/* @brief Has reload interrupt. */
mbed_official	121:7f86b4238bec	638	#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0)
mbed_official	121:7f86b4238bec	639	/* @brief Has reload initialization trigger. */
mbed_official	121:7f86b4238bec	640	#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
mbed_official	121:7f86b4238bec	641
mbed_official	121:7f86b4238bec	642	/* I2C module features */
mbed_official	121:7f86b4238bec	643
mbed_official	121:7f86b4238bec	644	/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
mbed_official	121:7f86b4238bec	645	#define FSL_FEATURE_I2C_HAS_SMBUS (1)
mbed_official	121:7f86b4238bec	646	/* @brief Maximum supported baud rate in kilobit per second. */
mbed_official	121:7f86b4238bec	647	#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
mbed_official	121:7f86b4238bec	648	/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
mbed_official	121:7f86b4238bec	649	#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
mbed_official	121:7f86b4238bec	650	/* @brief Has DMA support (register bit C1[DMAEN]). */
mbed_official	121:7f86b4238bec	651	#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
mbed_official	121:7f86b4238bec	652	/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
mbed_official	121:7f86b4238bec	653	#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
mbed_official	121:7f86b4238bec	654	/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
mbed_official	121:7f86b4238bec	655	#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
mbed_official	121:7f86b4238bec	656	/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
mbed_official	121:7f86b4238bec	657	#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
mbed_official	121:7f86b4238bec	658	/* @brief Maximum width of the glitch filter in number of bus clocks. */
mbed_official	121:7f86b4238bec	659	#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
mbed_official	121:7f86b4238bec	660	/* @brief Has control of the drive capability of the I2C pins. */
mbed_official	121:7f86b4238bec	661	#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
mbed_official	121:7f86b4238bec	662	/* @brief Has double buffering support (register S2). */
mbed_official	121:7f86b4238bec	663	#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
mbed_official	121:7f86b4238bec	664
mbed_official	121:7f86b4238bec	665	/* SAI module features */
mbed_official	121:7f86b4238bec	666
mbed_official	121:7f86b4238bec	667	/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
mbed_official	121:7f86b4238bec	668	#define FSL_FEATURE_SAI_FIFO_COUNT (8)
mbed_official	121:7f86b4238bec	669	/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
mbed_official	121:7f86b4238bec	670	#define FSL_FEATURE_SAI_CHANNEL_COUNT (1)
mbed_official	121:7f86b4238bec	671	/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
mbed_official	121:7f86b4238bec	672	#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (16)
mbed_official	121:7f86b4238bec	673	/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
mbed_official	121:7f86b4238bec	674	#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
mbed_official	121:7f86b4238bec	675	/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
mbed_official	121:7f86b4238bec	676	#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
mbed_official	121:7f86b4238bec	677	/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
mbed_official	121:7f86b4238bec	678	#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
mbed_official	121:7f86b4238bec	679	/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
mbed_official	121:7f86b4238bec	680	#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
mbed_official	121:7f86b4238bec	681	/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
mbed_official	121:7f86b4238bec	682	#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
mbed_official	121:7f86b4238bec	683	/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
mbed_official	121:7f86b4238bec	684	#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
mbed_official	121:7f86b4238bec	685	/* @brief Ihe interrupt source number */
mbed_official	121:7f86b4238bec	686	#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
mbed_official	121:7f86b4238bec	687	/* @brief Has register of MCR. */
mbed_official	121:7f86b4238bec	688	#define FSL_FEATURE_SAI_HAS_MCR (1)
mbed_official	121:7f86b4238bec	689	/* @brief Has register of MDR */
mbed_official	121:7f86b4238bec	690	#define FSL_FEATURE_SAI_HAS_MDR (1)
mbed_official	121:7f86b4238bec	691
mbed_official	121:7f86b4238bec	692	/* LLWU module features */
mbed_official	121:7f86b4238bec	693
mbed_official	121:7f86b4238bec	694	#if defined(CPU_MK22FN512CAP12) \|\| defined(CPU_MK22FN512VDC12) \|\| defined(CPU_MK22FN512VLL12)
mbed_official	121:7f86b4238bec	695	/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
mbed_official	121:7f86b4238bec	696	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
mbed_official	121:7f86b4238bec	697	/* @brief Has pins 8-15 connected to LLWU device. */
mbed_official	121:7f86b4238bec	698	#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
mbed_official	121:7f86b4238bec	699	/* @brief Maximum number of internal modules connected to LLWU device. */
mbed_official	121:7f86b4238bec	700	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
mbed_official	121:7f86b4238bec	701	/* @brief Number of digital filters. */
mbed_official	121:7f86b4238bec	702	#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
mbed_official	121:7f86b4238bec	703	/* @brief Has MF5 register. */
mbed_official	121:7f86b4238bec	704	#define FSL_FEATURE_LLWU_HAS_MF (0)
mbed_official	121:7f86b4238bec	705	/* @brief Has PF register. */
mbed_official	121:7f86b4238bec	706	#define FSL_FEATURE_LLWU_HAS_PF (0)
mbed_official	121:7f86b4238bec	707	/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
mbed_official	121:7f86b4238bec	708	#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
mbed_official	121:7f86b4238bec	709	/* @brief Has external pin 0 connected to LLWU device. */
mbed_official	121:7f86b4238bec	710	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
mbed_official	121:7f86b4238bec	711	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	712	#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
mbed_official	121:7f86b4238bec	713	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	714	#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
mbed_official	121:7f86b4238bec	715	/* @brief Has external pin 1 connected to LLWU device. */
mbed_official	121:7f86b4238bec	716	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
mbed_official	121:7f86b4238bec	717	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	718	#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
mbed_official	121:7f86b4238bec	719	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	720	#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
mbed_official	121:7f86b4238bec	721	/* @brief Has external pin 2 connected to LLWU device. */
mbed_official	121:7f86b4238bec	722	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
mbed_official	121:7f86b4238bec	723	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	724	#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
mbed_official	121:7f86b4238bec	725	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	726	#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
mbed_official	121:7f86b4238bec	727	/* @brief Has external pin 3 connected to LLWU device. */
mbed_official	121:7f86b4238bec	728	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
mbed_official	121:7f86b4238bec	729	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	730	#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
mbed_official	121:7f86b4238bec	731	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	732	#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
mbed_official	121:7f86b4238bec	733	/* @brief Has external pin 4 connected to LLWU device. */
mbed_official	121:7f86b4238bec	734	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
mbed_official	121:7f86b4238bec	735	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	736	#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
mbed_official	121:7f86b4238bec	737	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	738	#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
mbed_official	121:7f86b4238bec	739	/* @brief Has external pin 5 connected to LLWU device. */
mbed_official	121:7f86b4238bec	740	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
mbed_official	121:7f86b4238bec	741	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	742	#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
mbed_official	121:7f86b4238bec	743	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	744	#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	745	/* @brief Has external pin 6 connected to LLWU device. */
mbed_official	121:7f86b4238bec	746	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
mbed_official	121:7f86b4238bec	747	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	748	#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
mbed_official	121:7f86b4238bec	749	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	750	#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
mbed_official	121:7f86b4238bec	751	/* @brief Has external pin 7 connected to LLWU device. */
mbed_official	121:7f86b4238bec	752	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
mbed_official	121:7f86b4238bec	753	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	754	#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
mbed_official	121:7f86b4238bec	755	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	756	#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
mbed_official	121:7f86b4238bec	757	/* @brief Has external pin 8 connected to LLWU device. */
mbed_official	121:7f86b4238bec	758	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
mbed_official	121:7f86b4238bec	759	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	760	#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
mbed_official	121:7f86b4238bec	761	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	762	#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
mbed_official	121:7f86b4238bec	763	/* @brief Has external pin 9 connected to LLWU device. */
mbed_official	121:7f86b4238bec	764	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
mbed_official	121:7f86b4238bec	765	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	766	#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
mbed_official	121:7f86b4238bec	767	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	768	#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
mbed_official	121:7f86b4238bec	769	/* @brief Has external pin 10 connected to LLWU device. */
mbed_official	121:7f86b4238bec	770	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
mbed_official	121:7f86b4238bec	771	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	772	#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
mbed_official	121:7f86b4238bec	773	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	774	#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
mbed_official	121:7f86b4238bec	775	/* @brief Has external pin 11 connected to LLWU device. */
mbed_official	121:7f86b4238bec	776	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
mbed_official	121:7f86b4238bec	777	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	778	#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
mbed_official	121:7f86b4238bec	779	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	780	#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
mbed_official	121:7f86b4238bec	781	/* @brief Has external pin 12 connected to LLWU device. */
mbed_official	121:7f86b4238bec	782	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
mbed_official	121:7f86b4238bec	783	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	784	#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
mbed_official	121:7f86b4238bec	785	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	786	#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	787	/* @brief Has external pin 13 connected to LLWU device. */
mbed_official	121:7f86b4238bec	788	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
mbed_official	121:7f86b4238bec	789	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	790	#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
mbed_official	121:7f86b4238bec	791	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	792	#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
mbed_official	121:7f86b4238bec	793	/* @brief Has external pin 14 connected to LLWU device. */
mbed_official	121:7f86b4238bec	794	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
mbed_official	121:7f86b4238bec	795	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	796	#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
mbed_official	121:7f86b4238bec	797	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	798	#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
mbed_official	121:7f86b4238bec	799	/* @brief Has external pin 15 connected to LLWU device. */
mbed_official	121:7f86b4238bec	800	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
mbed_official	121:7f86b4238bec	801	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	802	#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
mbed_official	121:7f86b4238bec	803	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	804	#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
mbed_official	121:7f86b4238bec	805	/* @brief Has external pin 16 connected to LLWU device. */
mbed_official	121:7f86b4238bec	806	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
mbed_official	121:7f86b4238bec	807	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	808	#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	809	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	810	#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	811	/* @brief Has external pin 17 connected to LLWU device. */
mbed_official	121:7f86b4238bec	812	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
mbed_official	121:7f86b4238bec	813	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	814	#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	815	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	816	#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	817	/* @brief Has external pin 18 connected to LLWU device. */
mbed_official	121:7f86b4238bec	818	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
mbed_official	121:7f86b4238bec	819	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	820	#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	821	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	822	#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	823	/* @brief Has external pin 19 connected to LLWU device. */
mbed_official	121:7f86b4238bec	824	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
mbed_official	121:7f86b4238bec	825	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	826	#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	827	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	828	#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	829	/* @brief Has external pin 20 connected to LLWU device. */
mbed_official	121:7f86b4238bec	830	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
mbed_official	121:7f86b4238bec	831	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	832	#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	833	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	834	#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	835	/* @brief Has external pin 21 connected to LLWU device. */
mbed_official	121:7f86b4238bec	836	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
mbed_official	121:7f86b4238bec	837	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	838	#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	839	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	840	#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	841	/* @brief Has external pin 22 connected to LLWU device. */
mbed_official	121:7f86b4238bec	842	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
mbed_official	121:7f86b4238bec	843	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	844	#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	845	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	846	#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	847	/* @brief Has external pin 23 connected to LLWU device. */
mbed_official	121:7f86b4238bec	848	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
mbed_official	121:7f86b4238bec	849	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	850	#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	851	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	852	#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	853	/* @brief Has external pin 24 connected to LLWU device. */
mbed_official	121:7f86b4238bec	854	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
mbed_official	121:7f86b4238bec	855	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	856	#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	857	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	858	#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	859	/* @brief Has external pin 25 connected to LLWU device. */
mbed_official	121:7f86b4238bec	860	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
mbed_official	121:7f86b4238bec	861	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	862	#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	863	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	864	#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	865	/* @brief Has external pin 26 connected to LLWU device. */
mbed_official	121:7f86b4238bec	866	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
mbed_official	121:7f86b4238bec	867	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	868	#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	869	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	870	#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	871	/* @brief Has external pin 27 connected to LLWU device. */
mbed_official	121:7f86b4238bec	872	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
mbed_official	121:7f86b4238bec	873	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	874	#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	875	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	876	#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	877	/* @brief Has external pin 28 connected to LLWU device. */
mbed_official	121:7f86b4238bec	878	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
mbed_official	121:7f86b4238bec	879	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	880	#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	881	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	882	#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	883	/* @brief Has external pin 29 connected to LLWU device. */
mbed_official	121:7f86b4238bec	884	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
mbed_official	121:7f86b4238bec	885	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	886	#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	887	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	888	#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	889	/* @brief Has external pin 30 connected to LLWU device. */
mbed_official	121:7f86b4238bec	890	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
mbed_official	121:7f86b4238bec	891	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	892	#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	893	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	894	#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	895	/* @brief Has external pin 31 connected to LLWU device. */
mbed_official	121:7f86b4238bec	896	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
mbed_official	121:7f86b4238bec	897	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	898	#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	899	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	900	#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	901	/* @brief Has internal module 0 connected to LLWU device. */
mbed_official	121:7f86b4238bec	902	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
mbed_official	121:7f86b4238bec	903	/* @brief Has internal module 1 connected to LLWU device. */
mbed_official	121:7f86b4238bec	904	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
mbed_official	121:7f86b4238bec	905	/* @brief Has internal module 2 connected to LLWU device. */
mbed_official	121:7f86b4238bec	906	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
mbed_official	121:7f86b4238bec	907	/* @brief Has internal module 3 connected to LLWU device. */
mbed_official	121:7f86b4238bec	908	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
mbed_official	121:7f86b4238bec	909	/* @brief Has internal module 4 connected to LLWU device. */
mbed_official	121:7f86b4238bec	910	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
mbed_official	121:7f86b4238bec	911	/* @brief Has internal module 5 connected to LLWU device. */
mbed_official	121:7f86b4238bec	912	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
mbed_official	121:7f86b4238bec	913	/* @brief Has internal module 6 connected to LLWU device. */
mbed_official	121:7f86b4238bec	914	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
mbed_official	121:7f86b4238bec	915	/* @brief Has internal module 7 connected to LLWU device. */
mbed_official	121:7f86b4238bec	916	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
mbed_official	121:7f86b4238bec	917	/* @brief Has Version ID Register (LLWU_VERID). */
mbed_official	121:7f86b4238bec	918	#define FSL_FEATURE_LLWU_HAS_VERID (0)
mbed_official	121:7f86b4238bec	919	/* @brief Has Parameter Register (LLWU_PARAM). */
mbed_official	121:7f86b4238bec	920	#define FSL_FEATURE_LLWU_HAS_PARAM (0)
mbed_official	121:7f86b4238bec	921	/* @brief Width of registers of the LLWU. */
mbed_official	121:7f86b4238bec	922	#define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
mbed_official	121:7f86b4238bec	923	/* @brief Has DMA Enable register (LLWU_DE). */
mbed_official	121:7f86b4238bec	924	#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
mbed_official	121:7f86b4238bec	925	#elif defined(CPU_MK22FN512VLH12) \|\| defined(CPU_MK22FN512VMP12)
mbed_official	121:7f86b4238bec	926	/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
mbed_official	121:7f86b4238bec	927	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
mbed_official	121:7f86b4238bec	928	/* @brief Has pins 8-15 connected to LLWU device. */
mbed_official	121:7f86b4238bec	929	#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
mbed_official	121:7f86b4238bec	930	/* @brief Maximum number of internal modules connected to LLWU device. */
mbed_official	121:7f86b4238bec	931	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
mbed_official	121:7f86b4238bec	932	/* @brief Number of digital filters. */
mbed_official	121:7f86b4238bec	933	#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
mbed_official	121:7f86b4238bec	934	/* @brief Has MF5 register. */
mbed_official	121:7f86b4238bec	935	#define FSL_FEATURE_LLWU_HAS_MF (0)
mbed_official	121:7f86b4238bec	936	/* @brief Has PF register. */
mbed_official	121:7f86b4238bec	937	#define FSL_FEATURE_LLWU_HAS_PF (0)
mbed_official	121:7f86b4238bec	938	/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
mbed_official	121:7f86b4238bec	939	#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
mbed_official	121:7f86b4238bec	940	/* @brief Has external pin 0 connected to LLWU device. */
mbed_official	121:7f86b4238bec	941	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
mbed_official	121:7f86b4238bec	942	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	943	#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
mbed_official	121:7f86b4238bec	944	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	945	#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
mbed_official	121:7f86b4238bec	946	/* @brief Has external pin 1 connected to LLWU device. */
mbed_official	121:7f86b4238bec	947	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0)
mbed_official	121:7f86b4238bec	948	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	949	#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	950	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	951	#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	952	/* @brief Has external pin 2 connected to LLWU device. */
mbed_official	121:7f86b4238bec	953	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0)
mbed_official	121:7f86b4238bec	954	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	955	#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	956	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	957	#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	958	/* @brief Has external pin 3 connected to LLWU device. */
mbed_official	121:7f86b4238bec	959	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
mbed_official	121:7f86b4238bec	960	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	961	#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
mbed_official	121:7f86b4238bec	962	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	963	#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
mbed_official	121:7f86b4238bec	964	/* @brief Has external pin 4 connected to LLWU device. */
mbed_official	121:7f86b4238bec	965	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
mbed_official	121:7f86b4238bec	966	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	967	#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
mbed_official	121:7f86b4238bec	968	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	969	#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
mbed_official	121:7f86b4238bec	970	/* @brief Has external pin 5 connected to LLWU device. */
mbed_official	121:7f86b4238bec	971	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
mbed_official	121:7f86b4238bec	972	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	973	#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
mbed_official	121:7f86b4238bec	974	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	975	#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	976	/* @brief Has external pin 6 connected to LLWU device. */
mbed_official	121:7f86b4238bec	977	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
mbed_official	121:7f86b4238bec	978	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	979	#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
mbed_official	121:7f86b4238bec	980	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	981	#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
mbed_official	121:7f86b4238bec	982	/* @brief Has external pin 7 connected to LLWU device. */
mbed_official	121:7f86b4238bec	983	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
mbed_official	121:7f86b4238bec	984	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	985	#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
mbed_official	121:7f86b4238bec	986	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	987	#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
mbed_official	121:7f86b4238bec	988	/* @brief Has external pin 8 connected to LLWU device. */
mbed_official	121:7f86b4238bec	989	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
mbed_official	121:7f86b4238bec	990	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	991	#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
mbed_official	121:7f86b4238bec	992	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	993	#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
mbed_official	121:7f86b4238bec	994	/* @brief Has external pin 9 connected to LLWU device. */
mbed_official	121:7f86b4238bec	995	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
mbed_official	121:7f86b4238bec	996	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	997	#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
mbed_official	121:7f86b4238bec	998	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	999	#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
mbed_official	121:7f86b4238bec	1000	/* @brief Has external pin 10 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1001	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
mbed_official	121:7f86b4238bec	1002	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1003	#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
mbed_official	121:7f86b4238bec	1004	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1005	#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
mbed_official	121:7f86b4238bec	1006	/* @brief Has external pin 11 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1007	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
mbed_official	121:7f86b4238bec	1008	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1009	#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
mbed_official	121:7f86b4238bec	1010	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1011	#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
mbed_official	121:7f86b4238bec	1012	/* @brief Has external pin 12 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1013	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
mbed_official	121:7f86b4238bec	1014	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1015	#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
mbed_official	121:7f86b4238bec	1016	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1017	#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1018	/* @brief Has external pin 13 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1019	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
mbed_official	121:7f86b4238bec	1020	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1021	#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
mbed_official	121:7f86b4238bec	1022	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1023	#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
mbed_official	121:7f86b4238bec	1024	/* @brief Has external pin 14 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1025	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
mbed_official	121:7f86b4238bec	1026	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1027	#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
mbed_official	121:7f86b4238bec	1028	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1029	#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
mbed_official	121:7f86b4238bec	1030	/* @brief Has external pin 15 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1031	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
mbed_official	121:7f86b4238bec	1032	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1033	#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
mbed_official	121:7f86b4238bec	1034	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1035	#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
mbed_official	121:7f86b4238bec	1036	/* @brief Has external pin 16 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1037	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
mbed_official	121:7f86b4238bec	1038	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1039	#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1040	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1041	#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1042	/* @brief Has external pin 17 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1043	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
mbed_official	121:7f86b4238bec	1044	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1045	#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1046	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1047	#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1048	/* @brief Has external pin 18 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1049	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
mbed_official	121:7f86b4238bec	1050	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1051	#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1052	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1053	#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1054	/* @brief Has external pin 19 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1055	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
mbed_official	121:7f86b4238bec	1056	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1057	#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1058	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1059	#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1060	/* @brief Has external pin 20 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1061	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
mbed_official	121:7f86b4238bec	1062	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1063	#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1064	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1065	#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1066	/* @brief Has external pin 21 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1067	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
mbed_official	121:7f86b4238bec	1068	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1069	#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1070	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1071	#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1072	/* @brief Has external pin 22 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1073	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
mbed_official	121:7f86b4238bec	1074	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1075	#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1076	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1077	#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1078	/* @brief Has external pin 23 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1079	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
mbed_official	121:7f86b4238bec	1080	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1081	#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1082	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1083	#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1084	/* @brief Has external pin 24 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1085	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
mbed_official	121:7f86b4238bec	1086	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1087	#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1088	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1089	#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1090	/* @brief Has external pin 25 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1091	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
mbed_official	121:7f86b4238bec	1092	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1093	#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1094	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1095	#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1096	/* @brief Has external pin 26 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1097	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
mbed_official	121:7f86b4238bec	1098	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1099	#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1100	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1101	#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1102	/* @brief Has external pin 27 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1103	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
mbed_official	121:7f86b4238bec	1104	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1105	#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1106	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1107	#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1108	/* @brief Has external pin 28 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1109	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
mbed_official	121:7f86b4238bec	1110	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1111	#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1112	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1113	#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1114	/* @brief Has external pin 29 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1115	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
mbed_official	121:7f86b4238bec	1116	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1117	#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1118	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1119	#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1120	/* @brief Has external pin 30 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1121	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
mbed_official	121:7f86b4238bec	1122	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1123	#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1124	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1125	#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1126	/* @brief Has external pin 31 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1127	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
mbed_official	121:7f86b4238bec	1128	/* @brief Index of port of external pin. */
mbed_official	121:7f86b4238bec	1129	#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
mbed_official	121:7f86b4238bec	1130	/* @brief Number of external pin port on specified port. */
mbed_official	121:7f86b4238bec	1131	#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
mbed_official	121:7f86b4238bec	1132	/* @brief Has internal module 0 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1133	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
mbed_official	121:7f86b4238bec	1134	/* @brief Has internal module 1 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1135	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
mbed_official	121:7f86b4238bec	1136	/* @brief Has internal module 2 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1137	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
mbed_official	121:7f86b4238bec	1138	/* @brief Has internal module 3 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1139	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
mbed_official	121:7f86b4238bec	1140	/* @brief Has internal module 4 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1141	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
mbed_official	121:7f86b4238bec	1142	/* @brief Has internal module 5 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1143	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
mbed_official	121:7f86b4238bec	1144	/* @brief Has internal module 6 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1145	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
mbed_official	121:7f86b4238bec	1146	/* @brief Has internal module 7 connected to LLWU device. */
mbed_official	121:7f86b4238bec	1147	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
mbed_official	121:7f86b4238bec	1148	/* @brief Has Version ID Register (LLWU_VERID). */
mbed_official	121:7f86b4238bec	1149	#define FSL_FEATURE_LLWU_HAS_VERID (0)
mbed_official	121:7f86b4238bec	1150	/* @brief Has Parameter Register (LLWU_PARAM). */
mbed_official	121:7f86b4238bec	1151	#define FSL_FEATURE_LLWU_HAS_PARAM (0)
mbed_official	121:7f86b4238bec	1152	/* @brief Width of registers of the LLWU. */
mbed_official	121:7f86b4238bec	1153	#define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
mbed_official	121:7f86b4238bec	1154	/* @brief Has DMA Enable register (LLWU_DE). */
mbed_official	121:7f86b4238bec	1155	#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
mbed_official	121:7f86b4238bec	1156	#endif /* defined(CPU_MK22FN512CAP12) \|\| defined(CPU_MK22FN512VDC12) \|\| defined(CPU_MK22FN512VLL12) */
mbed_official	121:7f86b4238bec	1157
mbed_official	121:7f86b4238bec	1158	/* LPTMR module features */
mbed_official	121:7f86b4238bec	1159
mbed_official	121:7f86b4238bec	1160	/* @brief Has shared interrupt handler with another LPTMR module. */
mbed_official	121:7f86b4238bec	1161	#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
mbed_official	121:7f86b4238bec	1162
mbed_official	121:7f86b4238bec	1163	/* LPUART module features */
mbed_official	121:7f86b4238bec	1164
mbed_official	121:7f86b4238bec	1165	/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official	121:7f86b4238bec	1166	#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
mbed_official	121:7f86b4238bec	1167	/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official	121:7f86b4238bec	1168	#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
mbed_official	121:7f86b4238bec	1169	/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official	121:7f86b4238bec	1170	#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
mbed_official	121:7f86b4238bec	1171	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official	121:7f86b4238bec	1172	#define FSL_FEATURE_LPUART_HAS_FIFO (0)
mbed_official	121:7f86b4238bec	1173	/* @brief Has 32-bit register MODIR */
mbed_official	121:7f86b4238bec	1174	#define FSL_FEATURE_LPUART_HAS_MODIR (1)
mbed_official	121:7f86b4238bec	1175	/* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official	121:7f86b4238bec	1176	#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
mbed_official	121:7f86b4238bec	1177	/* @brief Infrared (modulation) is supported. */
mbed_official	121:7f86b4238bec	1178	#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
mbed_official	121:7f86b4238bec	1179	/* @brief 2 bits long stop bit is available. */
mbed_official	121:7f86b4238bec	1180	#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
mbed_official	121:7f86b4238bec	1181	/* @brief Maximal data width without parity bit. */
mbed_official	121:7f86b4238bec	1182	#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
mbed_official	121:7f86b4238bec	1183	/* @brief Baud rate fine adjustment is available. */
mbed_official	121:7f86b4238bec	1184	#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
mbed_official	121:7f86b4238bec	1185	/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official	121:7f86b4238bec	1186	#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
mbed_official	121:7f86b4238bec	1187	/* @brief Baud rate oversampling is available. */
mbed_official	121:7f86b4238bec	1188	#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
mbed_official	121:7f86b4238bec	1189	/* @brief Baud rate oversampling is available. */
mbed_official	121:7f86b4238bec	1190	#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
mbed_official	121:7f86b4238bec	1191	/* @brief Peripheral type. */
mbed_official	121:7f86b4238bec	1192	#define FSL_FEATURE_LPUART_IS_SCI (1)
mbed_official	121:7f86b4238bec	1193	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official	121:7f86b4238bec	1194	#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0)
mbed_official	121:7f86b4238bec	1195	/* @brief Maximal data width without parity bit. */
mbed_official	121:7f86b4238bec	1196	#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
mbed_official	121:7f86b4238bec	1197	/* @brief Maximal data width with parity bit. */
mbed_official	121:7f86b4238bec	1198	#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
mbed_official	121:7f86b4238bec	1199	/* @brief Supports two match addresses to filter incoming frames. */
mbed_official	121:7f86b4238bec	1200	#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
mbed_official	121:7f86b4238bec	1201	/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official	121:7f86b4238bec	1202	#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
mbed_official	121:7f86b4238bec	1203	/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official	121:7f86b4238bec	1204	#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
mbed_official	121:7f86b4238bec	1205	/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official	121:7f86b4238bec	1206	#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
mbed_official	121:7f86b4238bec	1207	/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official	121:7f86b4238bec	1208	#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
mbed_official	121:7f86b4238bec	1209	/* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official	121:7f86b4238bec	1210	#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
mbed_official	121:7f86b4238bec	1211	/* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official	121:7f86b4238bec	1212	#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
mbed_official	121:7f86b4238bec	1213	/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official	121:7f86b4238bec	1214	#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
mbed_official	121:7f86b4238bec	1215	/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
mbed_official	121:7f86b4238bec	1216	#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (0)
mbed_official	121:7f86b4238bec	1217	/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
mbed_official	121:7f86b4238bec	1218	#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
mbed_official	121:7f86b4238bec	1219	/* @brief Has separate DMA RX and TX requests. */
mbed_official	121:7f86b4238bec	1220	#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
mbed_official	121:7f86b4238bec	1221	/* @brief Has LPAURT_PARAM. */
mbed_official	121:7f86b4238bec	1222	#define FSL_FEATURE_LPUART_HAS_PARAM (0)
mbed_official	121:7f86b4238bec	1223	/* @brief Has LPUART_VERID. */
mbed_official	121:7f86b4238bec	1224	#define FSL_FEATURE_LPUART_HAS_VERID (0)
mbed_official	121:7f86b4238bec	1225	/* @brief Has LPUART_GLOBAL. */
mbed_official	121:7f86b4238bec	1226	#define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
mbed_official	121:7f86b4238bec	1227	/* @brief Has LPUART_PINCFG. */
mbed_official	121:7f86b4238bec	1228	#define FSL_FEATURE_LPUART_HAS_PINCFG (0)
mbed_official	121:7f86b4238bec	1229
mbed_official	121:7f86b4238bec	1230	/* MCG module features */
mbed_official	121:7f86b4238bec	1231
mbed_official	121:7f86b4238bec	1232	/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
mbed_official	121:7f86b4238bec	1233	#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
mbed_official	121:7f86b4238bec	1234	/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
mbed_official	121:7f86b4238bec	1235	#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
mbed_official	121:7f86b4238bec	1236	/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
mbed_official	121:7f86b4238bec	1237	#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
mbed_official	121:7f86b4238bec	1238	/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
mbed_official	121:7f86b4238bec	1239	#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
mbed_official	121:7f86b4238bec	1240	/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
mbed_official	121:7f86b4238bec	1241	#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
mbed_official	121:7f86b4238bec	1242	/* @brief The PLL clock is divided by 2 before VCO divider. */
mbed_official	121:7f86b4238bec	1243	#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
mbed_official	121:7f86b4238bec	1244	/* @brief FRDIV supports 1280. */
mbed_official	121:7f86b4238bec	1245	#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
mbed_official	121:7f86b4238bec	1246	/* @brief FRDIV supports 1536. */
mbed_official	121:7f86b4238bec	1247	#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
mbed_official	121:7f86b4238bec	1248	/* @brief MCGFFCLK divider. */
mbed_official	121:7f86b4238bec	1249	#define FSL_FEATURE_MCG_FFCLK_DIV (1)
mbed_official	121:7f86b4238bec	1250	/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
mbed_official	121:7f86b4238bec	1251	#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
mbed_official	121:7f86b4238bec	1252	/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
mbed_official	121:7f86b4238bec	1253	#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
mbed_official	121:7f86b4238bec	1254	/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
mbed_official	121:7f86b4238bec	1255	#define FSL_FEATURE_MCG_HAS_PLL1 (0)
mbed_official	121:7f86b4238bec	1256	/* @brief Has 48MHz internal oscillator. */
mbed_official	121:7f86b4238bec	1257	#define FSL_FEATURE_MCG_HAS_IRC_48M (1)
mbed_official	121:7f86b4238bec	1258	/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
mbed_official	121:7f86b4238bec	1259	#define FSL_FEATURE_MCG_HAS_OSC1 (0)
mbed_official	121:7f86b4238bec	1260	/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
mbed_official	121:7f86b4238bec	1261	#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
mbed_official	121:7f86b4238bec	1262	/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
mbed_official	121:7f86b4238bec	1263	#define FSL_FEATURE_MCG_HAS_LOLRE (1)
mbed_official	121:7f86b4238bec	1264	/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
mbed_official	121:7f86b4238bec	1265	#define FSL_FEATURE_MCG_USE_OSCSEL (1)
mbed_official	121:7f86b4238bec	1266	/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
mbed_official	121:7f86b4238bec	1267	#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
mbed_official	121:7f86b4238bec	1268	/* @brief TBD */
mbed_official	121:7f86b4238bec	1269	#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
mbed_official	121:7f86b4238bec	1270	/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
mbed_official	121:7f86b4238bec	1271	#define FSL_FEATURE_MCG_HAS_PLL (1)
mbed_official	121:7f86b4238bec	1272	/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
mbed_official	121:7f86b4238bec	1273	#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
mbed_official	121:7f86b4238bec	1274	/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
mbed_official	121:7f86b4238bec	1275	#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
mbed_official	121:7f86b4238bec	1276	/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
mbed_official	121:7f86b4238bec	1277	#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
mbed_official	121:7f86b4238bec	1278	/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
mbed_official	121:7f86b4238bec	1279	#define FSL_FEATURE_MCG_HAS_FLL (1)
mbed_official	121:7f86b4238bec	1280	/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
mbed_official	121:7f86b4238bec	1281	#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
mbed_official	121:7f86b4238bec	1282	/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
mbed_official	121:7f86b4238bec	1283	#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
mbed_official	121:7f86b4238bec	1284	/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
mbed_official	121:7f86b4238bec	1285	#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
mbed_official	121:7f86b4238bec	1286	/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
mbed_official	121:7f86b4238bec	1287	#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
mbed_official	121:7f86b4238bec	1288	/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
mbed_official	121:7f86b4238bec	1289	#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
mbed_official	121:7f86b4238bec	1290	/* @brief Has external clock monitor (register bit C6[CME]). */
mbed_official	121:7f86b4238bec	1291	#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
mbed_official	121:7f86b4238bec	1292	/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
mbed_official	121:7f86b4238bec	1293	#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
mbed_official	121:7f86b4238bec	1294	/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
mbed_official	121:7f86b4238bec	1295	#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
mbed_official	121:7f86b4238bec	1296	/* @brief Has PEI mode or PBI mode. */
mbed_official	121:7f86b4238bec	1297	#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
mbed_official	121:7f86b4238bec	1298	/* @brief Reset clock mode is BLPI. */
mbed_official	121:7f86b4238bec	1299	#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
mbed_official	121:7f86b4238bec	1300
mbed_official	121:7f86b4238bec	1301	/* interrupt module features */
mbed_official	121:7f86b4238bec	1302
mbed_official	121:7f86b4238bec	1303	/* @brief Lowest interrupt request number. */
mbed_official	121:7f86b4238bec	1304	#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
mbed_official	121:7f86b4238bec	1305	/* @brief Highest interrupt request number. */
mbed_official	121:7f86b4238bec	1306	#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
mbed_official	121:7f86b4238bec	1307
mbed_official	121:7f86b4238bec	1308	/* OSC module features */
mbed_official	121:7f86b4238bec	1309
mbed_official	121:7f86b4238bec	1310	/* @brief Has OSC1 external oscillator. */
mbed_official	121:7f86b4238bec	1311	#define FSL_FEATURE_OSC_HAS_OSC1 (0)
mbed_official	121:7f86b4238bec	1312	/* @brief Has OSC0 external oscillator. */
mbed_official	121:7f86b4238bec	1313	#define FSL_FEATURE_OSC_HAS_OSC0 (0)
mbed_official	121:7f86b4238bec	1314	/* @brief Has OSC external oscillator (without index). */
mbed_official	121:7f86b4238bec	1315	#define FSL_FEATURE_OSC_HAS_OSC (1)
mbed_official	121:7f86b4238bec	1316	/* @brief Number of OSC external oscillators. */
mbed_official	121:7f86b4238bec	1317	#define FSL_FEATURE_OSC_OSC_COUNT (1)
mbed_official	121:7f86b4238bec	1318	/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
mbed_official	121:7f86b4238bec	1319	#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1)
mbed_official	121:7f86b4238bec	1320
mbed_official	121:7f86b4238bec	1321	/* PDB module features */
mbed_official	121:7f86b4238bec	1322
mbed_official	121:7f86b4238bec	1323	/* @brief Define the count of supporting ADC pre-trigger for each channel. */
mbed_official	121:7f86b4238bec	1324	#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2)
mbed_official	121:7f86b4238bec	1325	/* @brief Has DAC support. */
mbed_official	121:7f86b4238bec	1326	#define FSL_FEATURE_PDB_HAS_DAC (1)
mbed_official	121:7f86b4238bec	1327	/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
mbed_official	121:7f86b4238bec	1328	#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
mbed_official	121:7f86b4238bec	1329
mbed_official	121:7f86b4238bec	1330	/* PIT module features */
mbed_official	121:7f86b4238bec	1331
mbed_official	121:7f86b4238bec	1332	/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
mbed_official	121:7f86b4238bec	1333	#define FSL_FEATURE_PIT_TIMER_COUNT (4)
mbed_official	121:7f86b4238bec	1334	/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
mbed_official	121:7f86b4238bec	1335	#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
mbed_official	121:7f86b4238bec	1336	/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
mbed_official	121:7f86b4238bec	1337	#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
mbed_official	121:7f86b4238bec	1338	/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
mbed_official	121:7f86b4238bec	1339	#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
mbed_official	121:7f86b4238bec	1340
mbed_official	121:7f86b4238bec	1341	/* PMC module features */
mbed_official	121:7f86b4238bec	1342
mbed_official	121:7f86b4238bec	1343	/* @brief Has Bandgap Enable In VLPx Operation support. */
mbed_official	121:7f86b4238bec	1344	#define FSL_FEATURE_PMC_HAS_BGEN (1)
mbed_official	121:7f86b4238bec	1345	/* @brief Has Bandgap Buffer Enable. */
mbed_official	121:7f86b4238bec	1346	#define FSL_FEATURE_PMC_HAS_BGBE (1)
mbed_official	121:7f86b4238bec	1347	/* @brief Has Bandgap Buffer Drive Select. */
mbed_official	121:7f86b4238bec	1348	#define FSL_FEATURE_PMC_HAS_BGBDS (0)
mbed_official	121:7f86b4238bec	1349	/* @brief Has Low-Voltage Detect Voltage Select support. */
mbed_official	121:7f86b4238bec	1350	#define FSL_FEATURE_PMC_HAS_LVDV (1)
mbed_official	121:7f86b4238bec	1351	/* @brief Has Low-Voltage Warning Voltage Select support. */
mbed_official	121:7f86b4238bec	1352	#define FSL_FEATURE_PMC_HAS_LVWV (1)
mbed_official	121:7f86b4238bec	1353	/* @brief Has LPO. */
mbed_official	121:7f86b4238bec	1354	#define FSL_FEATURE_PMC_HAS_LPO (0)
mbed_official	121:7f86b4238bec	1355	/* @brief Has VLPx option PMC_REGSC[VLPO]. */
mbed_official	121:7f86b4238bec	1356	#define FSL_FEATURE_PMC_HAS_VLPO (0)
mbed_official	121:7f86b4238bec	1357	/* @brief Has acknowledge isolation support. */
mbed_official	121:7f86b4238bec	1358	#define FSL_FEATURE_PMC_HAS_ACKISO (1)
mbed_official	121:7f86b4238bec	1359	/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
mbed_official	121:7f86b4238bec	1360	#define FSL_FEATURE_PMC_HAS_REGFPM (0)
mbed_official	121:7f86b4238bec	1361	/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
mbed_official	121:7f86b4238bec	1362	#define FSL_FEATURE_PMC_HAS_REGONS (1)
mbed_official	121:7f86b4238bec	1363	/* @brief Has PMC_HVDSC1. */
mbed_official	121:7f86b4238bec	1364	#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
mbed_official	121:7f86b4238bec	1365	/* @brief Has PMC_PARAM. */
mbed_official	121:7f86b4238bec	1366	#define FSL_FEATURE_PMC_HAS_PARAM (0)
mbed_official	121:7f86b4238bec	1367	/* @brief Has PMC_VERID. */
mbed_official	121:7f86b4238bec	1368	#define FSL_FEATURE_PMC_HAS_VERID (0)
mbed_official	121:7f86b4238bec	1369
mbed_official	121:7f86b4238bec	1370	/* PORT module features */
mbed_official	121:7f86b4238bec	1371
mbed_official	121:7f86b4238bec	1372	/* @brief Has control lock (register bit PCR[LK]). */
mbed_official	121:7f86b4238bec	1373	#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
mbed_official	121:7f86b4238bec	1374	/* @brief Has open drain control (register bit PCR[ODE]). */
mbed_official	121:7f86b4238bec	1375	#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
mbed_official	121:7f86b4238bec	1376	/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
mbed_official	121:7f86b4238bec	1377	#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
mbed_official	121:7f86b4238bec	1378	/* @brief Has DMA request (register bit field PCR[IRQC] values). */
mbed_official	121:7f86b4238bec	1379	#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
mbed_official	121:7f86b4238bec	1380	/* @brief Has pull resistor selection available. */
mbed_official	121:7f86b4238bec	1381	#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
mbed_official	121:7f86b4238bec	1382	/* @brief Has pull resistor enable (register bit PCR[PE]). */
mbed_official	121:7f86b4238bec	1383	#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
mbed_official	121:7f86b4238bec	1384	/* @brief Has slew rate control (register bit PCR[SRE]). */
mbed_official	121:7f86b4238bec	1385	#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
mbed_official	121:7f86b4238bec	1386	/* @brief Has passive filter (register bit field PCR[PFE]). */
mbed_official	121:7f86b4238bec	1387	#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
mbed_official	121:7f86b4238bec	1388	/* @brief Has drive strength control (register bit PCR[DSE]). */
mbed_official	121:7f86b4238bec	1389	#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
mbed_official	121:7f86b4238bec	1390	/* @brief Has separate drive strength register (HDRVE). */
mbed_official	121:7f86b4238bec	1391	#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
mbed_official	121:7f86b4238bec	1392	/* @brief Has glitch filter (register IOFLT). */
mbed_official	121:7f86b4238bec	1393	#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
mbed_official	121:7f86b4238bec	1394	/* @brief Defines width of PCR[MUX] field. */
mbed_official	121:7f86b4238bec	1395	#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
mbed_official	121:7f86b4238bec	1396	/* @brief Has dedicated interrupt vector. */
mbed_official	121:7f86b4238bec	1397	#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
mbed_official	121:7f86b4238bec	1398	/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
mbed_official	121:7f86b4238bec	1399	#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
mbed_official	121:7f86b4238bec	1400	/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
mbed_official	121:7f86b4238bec	1401	#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
mbed_official	121:7f86b4238bec	1402
mbed_official	121:7f86b4238bec	1403	/* GPIO module features */
mbed_official	121:7f86b4238bec	1404
mbed_official	121:7f86b4238bec	1405	/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
mbed_official	121:7f86b4238bec	1406	#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
mbed_official	121:7f86b4238bec	1407	/* @brief Has port input disable register (PIDR). */
mbed_official	121:7f86b4238bec	1408	#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
mbed_official	121:7f86b4238bec	1409	/* @brief Has dedicated interrupt vector. */
mbed_official	121:7f86b4238bec	1410	#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
mbed_official	121:7f86b4238bec	1411
mbed_official	121:7f86b4238bec	1412	/* RCM module features */
mbed_official	121:7f86b4238bec	1413
mbed_official	121:7f86b4238bec	1414	/* @brief Has Loss-of-Lock Reset support. */
mbed_official	121:7f86b4238bec	1415	#define FSL_FEATURE_RCM_HAS_LOL (1)
mbed_official	121:7f86b4238bec	1416	/* @brief Has Loss-of-Clock Reset support. */
mbed_official	121:7f86b4238bec	1417	#define FSL_FEATURE_RCM_HAS_LOC (1)
mbed_official	121:7f86b4238bec	1418	/* @brief Has JTAG generated Reset support. */
mbed_official	121:7f86b4238bec	1419	#define FSL_FEATURE_RCM_HAS_JTAG (1)
mbed_official	121:7f86b4238bec	1420	/* @brief Has EzPort generated Reset support. */
mbed_official	121:7f86b4238bec	1421	#define FSL_FEATURE_RCM_HAS_EZPORT (1)
mbed_official	121:7f86b4238bec	1422	/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
mbed_official	121:7f86b4238bec	1423	#define FSL_FEATURE_RCM_HAS_EZPMS (1)
mbed_official	121:7f86b4238bec	1424	/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
mbed_official	121:7f86b4238bec	1425	#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
mbed_official	121:7f86b4238bec	1426	/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
mbed_official	121:7f86b4238bec	1427	#define FSL_FEATURE_RCM_HAS_SSRS (1)
mbed_official	121:7f86b4238bec	1428	/* @brief Has Version ID Register (RCM_VERID). */
mbed_official	121:7f86b4238bec	1429	#define FSL_FEATURE_RCM_HAS_VERID (0)
mbed_official	121:7f86b4238bec	1430	/* @brief Has Parameter Register (RCM_PARAM). */
mbed_official	121:7f86b4238bec	1431	#define FSL_FEATURE_RCM_HAS_PARAM (0)
mbed_official	121:7f86b4238bec	1432	/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
mbed_official	121:7f86b4238bec	1433	#define FSL_FEATURE_RCM_HAS_SRIE (0)
mbed_official	121:7f86b4238bec	1434	/* @brief Width of registers of the RCM. */
mbed_official	121:7f86b4238bec	1435	#define FSL_FEATURE_RCM_REG_WIDTH (8)
mbed_official	121:7f86b4238bec	1436	/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
mbed_official	121:7f86b4238bec	1437	#define FSL_FEATURE_RCM_HAS_CORE1 (0)
mbed_official	121:7f86b4238bec	1438	/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
mbed_official	121:7f86b4238bec	1439	#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
mbed_official	121:7f86b4238bec	1440	/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
mbed_official	121:7f86b4238bec	1441	#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
mbed_official	121:7f86b4238bec	1442
mbed_official	121:7f86b4238bec	1443	/* RTC module features */
mbed_official	121:7f86b4238bec	1444
mbed_official	121:7f86b4238bec	1445	/* @brief Has wakeup pin. */
mbed_official	121:7f86b4238bec	1446	#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
mbed_official	121:7f86b4238bec	1447	/* @brief Has wakeup pin selection (bit field CR[WPS]). */
mbed_official	121:7f86b4238bec	1448	#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
mbed_official	121:7f86b4238bec	1449	/* @brief Has low power features (registers MER, MCLR and MCHR). */
mbed_official	121:7f86b4238bec	1450	#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
mbed_official	121:7f86b4238bec	1451	/* @brief Has read/write access control (registers WAR and RAR). */
mbed_official	121:7f86b4238bec	1452	#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
mbed_official	121:7f86b4238bec	1453	/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
mbed_official	121:7f86b4238bec	1454	#define FSL_FEATURE_RTC_HAS_SECURITY (1)
mbed_official	121:7f86b4238bec	1455	/* @brief Has RTC_CLKIN available. */
mbed_official	121:7f86b4238bec	1456	#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
mbed_official	121:7f86b4238bec	1457	/* @brief Has prescaler adjust for LPO. */
mbed_official	121:7f86b4238bec	1458	#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
mbed_official	121:7f86b4238bec	1459	/* @brief Has Clock Pin Enable field. */
mbed_official	121:7f86b4238bec	1460	#define FSL_FEATURE_RTC_HAS_CPE (0)
mbed_official	121:7f86b4238bec	1461	/* @brief Has Timer Seconds Interrupt Configuration field. */
mbed_official	121:7f86b4238bec	1462	#define FSL_FEATURE_RTC_HAS_TSIC (0)
mbed_official	121:7f86b4238bec	1463	/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
mbed_official	121:7f86b4238bec	1464	#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
mbed_official	121:7f86b4238bec	1465
mbed_official	121:7f86b4238bec	1466	/* SIM module features */
mbed_official	121:7f86b4238bec	1467
mbed_official	121:7f86b4238bec	1468	/* @brief Has USB FS divider. */
mbed_official	121:7f86b4238bec	1469	#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
mbed_official	121:7f86b4238bec	1470	/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
mbed_official	121:7f86b4238bec	1471	#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
mbed_official	121:7f86b4238bec	1472	/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
mbed_official	121:7f86b4238bec	1473	#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
mbed_official	121:7f86b4238bec	1474	/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
mbed_official	121:7f86b4238bec	1475	#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
mbed_official	121:7f86b4238bec	1476	/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
mbed_official	121:7f86b4238bec	1477	#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
mbed_official	121:7f86b4238bec	1478	/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
mbed_official	121:7f86b4238bec	1479	#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
mbed_official	121:7f86b4238bec	1480	/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
mbed_official	121:7f86b4238bec	1481	#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
mbed_official	121:7f86b4238bec	1482	/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
mbed_official	121:7f86b4238bec	1483	#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
mbed_official	121:7f86b4238bec	1484	/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
mbed_official	121:7f86b4238bec	1485	#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
mbed_official	121:7f86b4238bec	1486	/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
mbed_official	121:7f86b4238bec	1487	#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
mbed_official	121:7f86b4238bec	1488	/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
mbed_official	121:7f86b4238bec	1489	#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
mbed_official	121:7f86b4238bec	1490	/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
mbed_official	121:7f86b4238bec	1491	#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
mbed_official	121:7f86b4238bec	1492	/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
mbed_official	121:7f86b4238bec	1493	#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
mbed_official	121:7f86b4238bec	1494	/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
mbed_official	121:7f86b4238bec	1495	#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
mbed_official	121:7f86b4238bec	1496	/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
mbed_official	121:7f86b4238bec	1497	#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1)
mbed_official	121:7f86b4238bec	1498	/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
mbed_official	121:7f86b4238bec	1499	#define FSL_FEATURE_SIM_OPT_UART_COUNT (3)
mbed_official	121:7f86b4238bec	1500	/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
mbed_official	121:7f86b4238bec	1501	#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
mbed_official	121:7f86b4238bec	1502	/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
mbed_official	121:7f86b4238bec	1503	#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
mbed_official	121:7f86b4238bec	1504	/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
mbed_official	121:7f86b4238bec	1505	#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
mbed_official	121:7f86b4238bec	1506	/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
mbed_official	121:7f86b4238bec	1507	#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
mbed_official	121:7f86b4238bec	1508	/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
mbed_official	121:7f86b4238bec	1509	#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
mbed_official	121:7f86b4238bec	1510	/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
mbed_official	121:7f86b4238bec	1511	#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
mbed_official	121:7f86b4238bec	1512	/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
mbed_official	121:7f86b4238bec	1513	#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
mbed_official	121:7f86b4238bec	1514	/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
mbed_official	121:7f86b4238bec	1515	#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
mbed_official	121:7f86b4238bec	1516	/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
mbed_official	121:7f86b4238bec	1517	#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
mbed_official	121:7f86b4238bec	1518	/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
mbed_official	121:7f86b4238bec	1519	#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
mbed_official	121:7f86b4238bec	1520	/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
mbed_official	121:7f86b4238bec	1521	#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
mbed_official	121:7f86b4238bec	1522	/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
mbed_official	121:7f86b4238bec	1523	#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
mbed_official	121:7f86b4238bec	1524	/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
mbed_official	121:7f86b4238bec	1525	#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
mbed_official	121:7f86b4238bec	1526	/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
mbed_official	121:7f86b4238bec	1527	#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
mbed_official	121:7f86b4238bec	1528	/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
mbed_official	121:7f86b4238bec	1529	#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
mbed_official	121:7f86b4238bec	1530	/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
mbed_official	121:7f86b4238bec	1531	#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
mbed_official	121:7f86b4238bec	1532	/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
mbed_official	121:7f86b4238bec	1533	#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
mbed_official	121:7f86b4238bec	1534	/* @brief Has FTM module(s) configuration. */
mbed_official	121:7f86b4238bec	1535	#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
mbed_official	121:7f86b4238bec	1536	/* @brief Number of FTM modules. */
mbed_official	121:7f86b4238bec	1537	#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
mbed_official	121:7f86b4238bec	1538	/* @brief Number of FTM triggers with selectable source. */
mbed_official	121:7f86b4238bec	1539	#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
mbed_official	121:7f86b4238bec	1540	/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
mbed_official	121:7f86b4238bec	1541	#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
mbed_official	121:7f86b4238bec	1542	/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
mbed_official	121:7f86b4238bec	1543	#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
mbed_official	121:7f86b4238bec	1544	/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
mbed_official	121:7f86b4238bec	1545	#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
mbed_official	121:7f86b4238bec	1546	/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
mbed_official	121:7f86b4238bec	1547	#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
mbed_official	121:7f86b4238bec	1548	/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
mbed_official	121:7f86b4238bec	1549	#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
mbed_official	121:7f86b4238bec	1550	/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
mbed_official	121:7f86b4238bec	1551	#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1)
mbed_official	121:7f86b4238bec	1552	/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
mbed_official	121:7f86b4238bec	1553	#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2)
mbed_official	121:7f86b4238bec	1554	/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
mbed_official	121:7f86b4238bec	1555	#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
mbed_official	121:7f86b4238bec	1556	/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
mbed_official	121:7f86b4238bec	1557	#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
mbed_official	121:7f86b4238bec	1558	/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
mbed_official	121:7f86b4238bec	1559	#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
mbed_official	121:7f86b4238bec	1560	/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
mbed_official	121:7f86b4238bec	1561	#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
mbed_official	121:7f86b4238bec	1562	/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
mbed_official	121:7f86b4238bec	1563	#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
mbed_official	121:7f86b4238bec	1564	/* @brief Has TPM module(s) configuration. */
mbed_official	121:7f86b4238bec	1565	#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
mbed_official	121:7f86b4238bec	1566	/* @brief The highest TPM module index. */
mbed_official	121:7f86b4238bec	1567	#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
mbed_official	121:7f86b4238bec	1568	/* @brief Has TPM module with index 0. */
mbed_official	121:7f86b4238bec	1569	#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
mbed_official	121:7f86b4238bec	1570	/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
mbed_official	121:7f86b4238bec	1571	#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
mbed_official	121:7f86b4238bec	1572	/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
mbed_official	121:7f86b4238bec	1573	#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
mbed_official	121:7f86b4238bec	1574	/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
mbed_official	121:7f86b4238bec	1575	#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
mbed_official	121:7f86b4238bec	1576	/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
mbed_official	121:7f86b4238bec	1577	#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
mbed_official	121:7f86b4238bec	1578	/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
mbed_official	121:7f86b4238bec	1579	#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
mbed_official	121:7f86b4238bec	1580	/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
mbed_official	121:7f86b4238bec	1581	#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
mbed_official	121:7f86b4238bec	1582	/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
mbed_official	121:7f86b4238bec	1583	#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
mbed_official	121:7f86b4238bec	1584	/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
mbed_official	121:7f86b4238bec	1585	#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
mbed_official	121:7f86b4238bec	1586	/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
mbed_official	121:7f86b4238bec	1587	#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
mbed_official	121:7f86b4238bec	1588	/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
mbed_official	121:7f86b4238bec	1589	#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
mbed_official	121:7f86b4238bec	1590	/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
mbed_official	121:7f86b4238bec	1591	#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
mbed_official	121:7f86b4238bec	1592	/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
mbed_official	121:7f86b4238bec	1593	#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
mbed_official	121:7f86b4238bec	1594	/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
mbed_official	121:7f86b4238bec	1595	#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
mbed_official	121:7f86b4238bec	1596	/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
mbed_official	121:7f86b4238bec	1597	#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
mbed_official	121:7f86b4238bec	1598	/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
mbed_official	121:7f86b4238bec	1599	#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
mbed_official	121:7f86b4238bec	1600	/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
mbed_official	121:7f86b4238bec	1601	#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
mbed_official	121:7f86b4238bec	1602	/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
mbed_official	121:7f86b4238bec	1603	#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
mbed_official	121:7f86b4238bec	1604	/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
mbed_official	121:7f86b4238bec	1605	#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
mbed_official	121:7f86b4238bec	1606	/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
mbed_official	121:7f86b4238bec	1607	#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1)
mbed_official	121:7f86b4238bec	1608	/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
mbed_official	121:7f86b4238bec	1609	#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
mbed_official	121:7f86b4238bec	1610	/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
mbed_official	121:7f86b4238bec	1611	#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
mbed_official	121:7f86b4238bec	1612	/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
mbed_official	121:7f86b4238bec	1613	#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
mbed_official	121:7f86b4238bec	1614	/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
mbed_official	121:7f86b4238bec	1615	#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
mbed_official	121:7f86b4238bec	1616	/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
mbed_official	121:7f86b4238bec	1617	#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
mbed_official	121:7f86b4238bec	1618	/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
mbed_official	121:7f86b4238bec	1619	#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
mbed_official	121:7f86b4238bec	1620	/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
mbed_official	121:7f86b4238bec	1621	#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
mbed_official	121:7f86b4238bec	1622	/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
mbed_official	121:7f86b4238bec	1623	#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
mbed_official	121:7f86b4238bec	1624	/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
mbed_official	121:7f86b4238bec	1625	#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1)
mbed_official	121:7f86b4238bec	1626	/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
mbed_official	121:7f86b4238bec	1627	#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
mbed_official	121:7f86b4238bec	1628	/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
mbed_official	121:7f86b4238bec	1629	#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
mbed_official	121:7f86b4238bec	1630	/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
mbed_official	121:7f86b4238bec	1631	#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
mbed_official	121:7f86b4238bec	1632	/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
mbed_official	121:7f86b4238bec	1633	#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
mbed_official	121:7f86b4238bec	1634	/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
mbed_official	121:7f86b4238bec	1635	#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
mbed_official	121:7f86b4238bec	1636	/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
mbed_official	121:7f86b4238bec	1637	#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
mbed_official	121:7f86b4238bec	1638	/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
mbed_official	121:7f86b4238bec	1639	#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
mbed_official	121:7f86b4238bec	1640	/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
mbed_official	121:7f86b4238bec	1641	#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
mbed_official	121:7f86b4238bec	1642	/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
mbed_official	121:7f86b4238bec	1643	#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
mbed_official	121:7f86b4238bec	1644	/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
mbed_official	121:7f86b4238bec	1645	#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
mbed_official	121:7f86b4238bec	1646	/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
mbed_official	121:7f86b4238bec	1647	#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
mbed_official	121:7f86b4238bec	1648	/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
mbed_official	121:7f86b4238bec	1649	#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
mbed_official	121:7f86b4238bec	1650	/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
mbed_official	121:7f86b4238bec	1651	#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
mbed_official	121:7f86b4238bec	1652	/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
mbed_official	121:7f86b4238bec	1653	#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
mbed_official	121:7f86b4238bec	1654	/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
mbed_official	121:7f86b4238bec	1655	#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
mbed_official	121:7f86b4238bec	1656	/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
mbed_official	121:7f86b4238bec	1657	#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
mbed_official	121:7f86b4238bec	1658	/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
mbed_official	121:7f86b4238bec	1659	#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
mbed_official	121:7f86b4238bec	1660	/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
mbed_official	121:7f86b4238bec	1661	#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
mbed_official	121:7f86b4238bec	1662	/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
mbed_official	121:7f86b4238bec	1663	#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
mbed_official	121:7f86b4238bec	1664	/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
mbed_official	121:7f86b4238bec	1665	#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
mbed_official	121:7f86b4238bec	1666	/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
mbed_official	121:7f86b4238bec	1667	#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
mbed_official	121:7f86b4238bec	1668	/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
mbed_official	121:7f86b4238bec	1669	#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
mbed_official	121:7f86b4238bec	1670	/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
mbed_official	121:7f86b4238bec	1671	#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
mbed_official	121:7f86b4238bec	1672	/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
mbed_official	121:7f86b4238bec	1673	#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
mbed_official	121:7f86b4238bec	1674	/* @brief Has device die ID (register bit field SDID[DIEID]). */
mbed_official	121:7f86b4238bec	1675	#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
mbed_official	121:7f86b4238bec	1676	/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
mbed_official	121:7f86b4238bec	1677	#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
mbed_official	121:7f86b4238bec	1678	/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
mbed_official	121:7f86b4238bec	1679	#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
mbed_official	121:7f86b4238bec	1680	/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
mbed_official	121:7f86b4238bec	1681	#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
mbed_official	121:7f86b4238bec	1682	/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
mbed_official	121:7f86b4238bec	1683	#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
mbed_official	121:7f86b4238bec	1684	/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
mbed_official	121:7f86b4238bec	1685	#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
mbed_official	121:7f86b4238bec	1686	/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
mbed_official	121:7f86b4238bec	1687	#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
mbed_official	121:7f86b4238bec	1688	/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
mbed_official	121:7f86b4238bec	1689	#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
mbed_official	121:7f86b4238bec	1690	/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
mbed_official	121:7f86b4238bec	1691	#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
mbed_official	121:7f86b4238bec	1692	/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
mbed_official	121:7f86b4238bec	1693	#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
mbed_official	121:7f86b4238bec	1694	/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
mbed_official	121:7f86b4238bec	1695	#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
mbed_official	121:7f86b4238bec	1696	/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
mbed_official	121:7f86b4238bec	1697	#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
mbed_official	121:7f86b4238bec	1698	/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
mbed_official	121:7f86b4238bec	1699	#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
mbed_official	121:7f86b4238bec	1700	/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
mbed_official	121:7f86b4238bec	1701	#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
mbed_official	121:7f86b4238bec	1702	/* @brief Has miscellanious control register (register MCR). */
mbed_official	121:7f86b4238bec	1703	#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
mbed_official	121:7f86b4238bec	1704	/* @brief Has COP watchdog (registers COPC and SRVCOP). */
mbed_official	121:7f86b4238bec	1705	#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
mbed_official	121:7f86b4238bec	1706	/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
mbed_official	121:7f86b4238bec	1707	#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
mbed_official	121:7f86b4238bec	1708	/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
mbed_official	121:7f86b4238bec	1709	#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
mbed_official	121:7f86b4238bec	1710
mbed_official	121:7f86b4238bec	1711	/* SMC module features */
mbed_official	121:7f86b4238bec	1712
mbed_official	121:7f86b4238bec	1713	/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
mbed_official	121:7f86b4238bec	1714	#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
mbed_official	121:7f86b4238bec	1715	/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
mbed_official	121:7f86b4238bec	1716	#define FSL_FEATURE_SMC_HAS_LPOPO (0)
mbed_official	121:7f86b4238bec	1717	/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
mbed_official	121:7f86b4238bec	1718	#define FSL_FEATURE_SMC_HAS_PORPO (1)
mbed_official	121:7f86b4238bec	1719	/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
mbed_official	121:7f86b4238bec	1720	#define FSL_FEATURE_SMC_HAS_LPWUI (0)
mbed_official	121:7f86b4238bec	1721	/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
mbed_official	121:7f86b4238bec	1722	#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
mbed_official	121:7f86b4238bec	1723	/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
mbed_official	121:7f86b4238bec	1724	#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
mbed_official	121:7f86b4238bec	1725	/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
mbed_official	121:7f86b4238bec	1726	#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
mbed_official	121:7f86b4238bec	1727	/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
mbed_official	121:7f86b4238bec	1728	#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
mbed_official	121:7f86b4238bec	1729	/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
mbed_official	121:7f86b4238bec	1730	#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
mbed_official	121:7f86b4238bec	1731	/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
mbed_official	121:7f86b4238bec	1732	#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
mbed_official	121:7f86b4238bec	1733	/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
mbed_official	121:7f86b4238bec	1734	#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
mbed_official	121:7f86b4238bec	1735	/* @brief Has stop submode. */
mbed_official	121:7f86b4238bec	1736	#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
mbed_official	121:7f86b4238bec	1737	/* @brief Has stop submode 0(VLLS0). */
mbed_official	121:7f86b4238bec	1738	#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
mbed_official	121:7f86b4238bec	1739	/* @brief Has stop submode 2(VLLS2). */
mbed_official	121:7f86b4238bec	1740	#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
mbed_official	121:7f86b4238bec	1741	/* @brief Has SMC_PARAM. */
mbed_official	121:7f86b4238bec	1742	#define FSL_FEATURE_SMC_HAS_PARAM (0)
mbed_official	121:7f86b4238bec	1743	/* @brief Has SMC_VERID. */
mbed_official	121:7f86b4238bec	1744	#define FSL_FEATURE_SMC_HAS_VERID (0)
mbed_official	121:7f86b4238bec	1745
mbed_official	121:7f86b4238bec	1746	/* DSPI module features */
mbed_official	121:7f86b4238bec	1747
mbed_official	121:7f86b4238bec	1748	#if defined(CPU_MK22FN512CAP12) \|\| defined(CPU_MK22FN512VLH12) \|\| defined(CPU_MK22FN512VMP12)
mbed_official	121:7f86b4238bec	1749	/* @brief Receive/transmit FIFO size in number of items. */
mbed_official	121:7f86b4238bec	1750	#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
mbed_official	121:7f86b4238bec	1751	((x) == DSPI0 ? (4) : \
mbed_official	121:7f86b4238bec	1752	((x) == DSPI1 ? (1) : (-1)))
mbed_official	121:7f86b4238bec	1753	/* @brief Maximum transfer data width in bits. */
mbed_official	121:7f86b4238bec	1754	#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
mbed_official	121:7f86b4238bec	1755	/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
mbed_official	121:7f86b4238bec	1756	#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official	121:7f86b4238bec	1757	/* @brief Number of chip select pins. */
mbed_official	121:7f86b4238bec	1758	#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
mbed_official	121:7f86b4238bec	1759	/* @brief Has chip select strobe capability on the PCS5 pin. */
mbed_official	121:7f86b4238bec	1760	#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official	121:7f86b4238bec	1761	/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
mbed_official	121:7f86b4238bec	1762	#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
mbed_official	121:7f86b4238bec	1763	/* @brief Has 16-bit data transfer support. */
mbed_official	121:7f86b4238bec	1764	#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
mbed_official	121:7f86b4238bec	1765	/* @brief Has separate DMA RX and TX requests. */
mbed_official	121:7f86b4238bec	1766	#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
mbed_official	121:7f86b4238bec	1767	((x) == DSPI0 ? (1) : \
mbed_official	121:7f86b4238bec	1768	((x) == DSPI1 ? (0) : (-1)))
mbed_official	121:7f86b4238bec	1769	#elif defined(CPU_MK22FN512VDC12) \|\| defined(CPU_MK22FN512VLL12)
mbed_official	121:7f86b4238bec	1770	/* @brief Receive/transmit FIFO size in number of items. */
mbed_official	121:7f86b4238bec	1771	#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
mbed_official	121:7f86b4238bec	1772	((x) == DSPI0 ? (4) : \
mbed_official	121:7f86b4238bec	1773	((x) == DSPI1 ? (1) : (-1)))
mbed_official	121:7f86b4238bec	1774	/* @brief Maximum transfer data width in bits. */
mbed_official	121:7f86b4238bec	1775	#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
mbed_official	121:7f86b4238bec	1776	/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
mbed_official	121:7f86b4238bec	1777	#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
mbed_official	121:7f86b4238bec	1778	/* @brief Number of chip select pins. */
mbed_official	121:7f86b4238bec	1779	#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
mbed_official	121:7f86b4238bec	1780	/* @brief Has chip select strobe capability on the PCS5 pin. */
mbed_official	121:7f86b4238bec	1781	#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
mbed_official	121:7f86b4238bec	1782	/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
mbed_official	121:7f86b4238bec	1783	#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
mbed_official	121:7f86b4238bec	1784	/* @brief Has 16-bit data transfer support. */
mbed_official	121:7f86b4238bec	1785	#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
mbed_official	121:7f86b4238bec	1786	/* @brief Has separate DMA RX and TX requests. */
mbed_official	121:7f86b4238bec	1787	#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
mbed_official	121:7f86b4238bec	1788	((x) == DSPI0 ? (1) : \
mbed_official	121:7f86b4238bec	1789	((x) == DSPI1 ? (0) : (-1)))
mbed_official	121:7f86b4238bec	1790	#endif /* defined(CPU_MK22FN512CAP12) \|\| defined(CPU_MK22FN512VLH12) \|\| defined(CPU_MK22FN512VMP12) */
mbed_official	121:7f86b4238bec	1791
mbed_official	121:7f86b4238bec	1792	/* SysTick module features */
mbed_official	121:7f86b4238bec	1793
mbed_official	121:7f86b4238bec	1794	/* @brief Systick has external reference clock. */
mbed_official	121:7f86b4238bec	1795	#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
mbed_official	121:7f86b4238bec	1796	/* @brief Systick external reference clock is core clock divided by this value. */
mbed_official	121:7f86b4238bec	1797	#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
mbed_official	121:7f86b4238bec	1798
mbed_official	121:7f86b4238bec	1799	/* UART module features */
mbed_official	121:7f86b4238bec	1800
mbed_official	121:7f86b4238bec	1801	/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official	121:7f86b4238bec	1802	#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
mbed_official	121:7f86b4238bec	1803	/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official	121:7f86b4238bec	1804	#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
mbed_official	121:7f86b4238bec	1805	/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official	121:7f86b4238bec	1806	#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
mbed_official	121:7f86b4238bec	1807	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official	121:7f86b4238bec	1808	#define FSL_FEATURE_UART_HAS_FIFO (1)
mbed_official	121:7f86b4238bec	1809	/* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official	121:7f86b4238bec	1810	#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
mbed_official	121:7f86b4238bec	1811	/* @brief Infrared (modulation) is supported. */
mbed_official	121:7f86b4238bec	1812	#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
mbed_official	121:7f86b4238bec	1813	/* @brief 2 bits long stop bit is available. */
mbed_official	121:7f86b4238bec	1814	#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
mbed_official	121:7f86b4238bec	1815	/* @brief Maximal data width without parity bit. */
mbed_official	121:7f86b4238bec	1816	#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
mbed_official	121:7f86b4238bec	1817	/* @brief Baud rate fine adjustment is available. */
mbed_official	121:7f86b4238bec	1818	#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
mbed_official	121:7f86b4238bec	1819	/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official	121:7f86b4238bec	1820	#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
mbed_official	121:7f86b4238bec	1821	/* @brief Baud rate oversampling is available. */
mbed_official	121:7f86b4238bec	1822	#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
mbed_official	121:7f86b4238bec	1823	/* @brief Baud rate oversampling is available. */
mbed_official	121:7f86b4238bec	1824	#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
mbed_official	121:7f86b4238bec	1825	/* @brief Peripheral type. */
mbed_official	121:7f86b4238bec	1826	#define FSL_FEATURE_UART_IS_SCI (0)
mbed_official	121:7f86b4238bec	1827	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official	121:7f86b4238bec	1828	#define FSL_FEATURE_UART_FIFO_SIZEn(x) \
mbed_official	121:7f86b4238bec	1829	((x) == UART0 ? (8) : \
mbed_official	121:7f86b4238bec	1830	((x) == UART1 ? (1) : \
mbed_official	121:7f86b4238bec	1831	((x) == UART2 ? (1) : (-1))))
mbed_official	121:7f86b4238bec	1832	/* @brief Maximal data width without parity bit. */
mbed_official	121:7f86b4238bec	1833	#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
mbed_official	121:7f86b4238bec	1834	/* @brief Maximal data width with parity bit. */
mbed_official	121:7f86b4238bec	1835	#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
mbed_official	121:7f86b4238bec	1836	/* @brief Supports two match addresses to filter incoming frames. */
mbed_official	121:7f86b4238bec	1837	#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
mbed_official	121:7f86b4238bec	1838	/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official	121:7f86b4238bec	1839	#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
mbed_official	121:7f86b4238bec	1840	/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official	121:7f86b4238bec	1841	#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
mbed_official	121:7f86b4238bec	1842	/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official	121:7f86b4238bec	1843	#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
mbed_official	121:7f86b4238bec	1844	/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official	121:7f86b4238bec	1845	#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
mbed_official	121:7f86b4238bec	1846	/* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official	121:7f86b4238bec	1847	#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1)
mbed_official	121:7f86b4238bec	1848	/* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official	121:7f86b4238bec	1849	#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
mbed_official	121:7f86b4238bec	1850	/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official	121:7f86b4238bec	1851	#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
mbed_official	121:7f86b4238bec	1852	/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
mbed_official	121:7f86b4238bec	1853	#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
mbed_official	121:7f86b4238bec	1854	/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
mbed_official	121:7f86b4238bec	1855	#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
mbed_official	121:7f86b4238bec	1856	/* @brief Has separate DMA RX and TX requests. */
mbed_official	121:7f86b4238bec	1857	#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
mbed_official	121:7f86b4238bec	1858
mbed_official	121:7f86b4238bec	1859	/* USB module features */
mbed_official	121:7f86b4238bec	1860
mbed_official	121:7f86b4238bec	1861	/* @brief HOST mode enabled */
mbed_official	121:7f86b4238bec	1862	#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
mbed_official	121:7f86b4238bec	1863	/* @brief OTG mode enabled */
mbed_official	121:7f86b4238bec	1864	#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
mbed_official	121:7f86b4238bec	1865	/* @brief Size of the USB dedicated RAM */
mbed_official	121:7f86b4238bec	1866	#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
mbed_official	121:7f86b4238bec	1867	/* @brief Has KEEP_ALIVE_CTRL register */
mbed_official	121:7f86b4238bec	1868	#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
mbed_official	121:7f86b4238bec	1869	/* @brief Has the Dynamic SOF threshold compare support */
mbed_official	121:7f86b4238bec	1870	#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
mbed_official	121:7f86b4238bec	1871	/* @brief Has the VBUS detect support */
mbed_official	121:7f86b4238bec	1872	#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
mbed_official	121:7f86b4238bec	1873	/* @brief Has the IRC48M module clock support */
mbed_official	121:7f86b4238bec	1874	#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
mbed_official	121:7f86b4238bec	1875	/* @brief Number of endpoints supported */
mbed_official	121:7f86b4238bec	1876	#define FSL_FEATURE_USB_ENDPT_COUNT (16)
mbed_official	121:7f86b4238bec	1877
mbed_official	121:7f86b4238bec	1878	/* VREF module features */
mbed_official	121:7f86b4238bec	1879
mbed_official	121:7f86b4238bec	1880	/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
mbed_official	121:7f86b4238bec	1881	#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
mbed_official	121:7f86b4238bec	1882	/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
mbed_official	121:7f86b4238bec	1883	#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
mbed_official	121:7f86b4238bec	1884	/* @brief Describes the set of SC[MODE_LV] bitfield values */
mbed_official	121:7f86b4238bec	1885	#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
mbed_official	121:7f86b4238bec	1886	/* @brief Module has also low reference (registers VREFL/VREFH) */
mbed_official	121:7f86b4238bec	1887	#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
mbed_official	121:7f86b4238bec	1888	/* @brief Has VREF_TRM4. */
mbed_official	121:7f86b4238bec	1889	#define FSL_FEATURE_VREF_HAS_TRM4 (0)
mbed_official	121:7f86b4238bec	1890
mbed_official	121:7f86b4238bec	1891	/* WDOG module features */
mbed_official	121:7f86b4238bec	1892
mbed_official	121:7f86b4238bec	1893	/* @brief Watchdog is available. */
mbed_official	121:7f86b4238bec	1894	#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
mbed_official	121:7f86b4238bec	1895	/* @brief Has Wait mode support. */
mbed_official	121:7f86b4238bec	1896	#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
mbed_official	121:7f86b4238bec	1897
mbed_official	121:7f86b4238bec	1898	#endif /* _MK22F51212_FEATURES_H_ */
mbed_official	121:7f86b4238bec	1899

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
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Followers:	1

targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212_features.h@121:7f86b4238bec, 2016-05-03 (annotated)

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