mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_uart.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l4xx_hal_uart.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of UART HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32L4xx_HAL_UART_H
bogdanm	0:9b334a45a8ff	40	#define __STM32L4xx_HAL_UART_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32l4xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32L4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup UART
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/** @defgroup UART_Exported_Types UART Exported Types
bogdanm	0:9b334a45a8ff	59	* @{
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61
bogdanm	0:9b334a45a8ff	62	/**
bogdanm	0:9b334a45a8ff	63	* @brief UART Init Structure definition
bogdanm	0:9b334a45a8ff	64	*/
bogdanm	0:9b334a45a8ff	65	typedef struct
bogdanm	0:9b334a45a8ff	66	{
bogdanm	0:9b334a45a8ff	67	uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
bogdanm	0:9b334a45a8ff	68	The baud rate register is computed using the following formula:
bogdanm	0:9b334a45a8ff	69	- If oversampling is 16 or in LIN mode,
bogdanm	0:9b334a45a8ff	70	Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
bogdanm	0:9b334a45a8ff	71	- If oversampling is 8,
bogdanm	0:9b334a45a8ff	72	- - Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
bogdanm	0:9b334a45a8ff	73	- - Baud Rate Register[3] = 0
bogdanm	0:9b334a45a8ff	74	- - Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
bogdanm	0:9b334a45a8ff	75
bogdanm	0:9b334a45a8ff	76	uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
bogdanm	0:9b334a45a8ff	77	This parameter can be a value of @ref UARTEx_Word_Length. */
bogdanm	0:9b334a45a8ff	78
bogdanm	0:9b334a45a8ff	79	uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
bogdanm	0:9b334a45a8ff	80	This parameter can be a value of @ref UART_Stop_Bits. */
bogdanm	0:9b334a45a8ff	81
bogdanm	0:9b334a45a8ff	82	uint32_t Parity; /*!< Specifies the parity mode.
bogdanm	0:9b334a45a8ff	83	This parameter can be a value of @ref UART_Parity
bogdanm	0:9b334a45a8ff	84	@note When parity is enabled, the computed parity is inserted
bogdanm	0:9b334a45a8ff	85	at the MSB position of the transmitted data (9th bit when
bogdanm	0:9b334a45a8ff	86	the word length is set to 9 data bits; 8th bit when the
bogdanm	0:9b334a45a8ff	87	word length is set to 8 data bits). */
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
bogdanm	0:9b334a45a8ff	90	This parameter can be a value of @ref UART_Mode. */
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
bogdanm	0:9b334a45a8ff	93	or disabled.
bogdanm	0:9b334a45a8ff	94	This parameter can be a value of @ref UART_Hardware_Flow_Control. */
bogdanm	0:9b334a45a8ff	95
bogdanm	0:9b334a45a8ff	96	uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
bogdanm	0:9b334a45a8ff	97	This parameter can be a value of @ref UART_Over_Sampling. */
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
bogdanm	0:9b334a45a8ff	100	Selecting the single sample method increases the receiver tolerance to clock
bogdanm	0:9b334a45a8ff	101	deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
bogdanm	0:9b334a45a8ff	102	}UART_InitTypeDef;
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	/**
bogdanm	0:9b334a45a8ff	105	* @brief UART Advanced Features initalization structure definition
bogdanm	0:9b334a45a8ff	106	*/
bogdanm	0:9b334a45a8ff	107	typedef struct
bogdanm	0:9b334a45a8ff	108	{
bogdanm	0:9b334a45a8ff	109	uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
bogdanm	0:9b334a45a8ff	110	Advanced Features may be initialized at the same time .
bogdanm	0:9b334a45a8ff	111	This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
bogdanm	0:9b334a45a8ff	112
bogdanm	0:9b334a45a8ff	113	uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
bogdanm	0:9b334a45a8ff	114	This parameter can be a value of @ref UART_Tx_Inv. */
bogdanm	0:9b334a45a8ff	115
bogdanm	0:9b334a45a8ff	116	uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
bogdanm	0:9b334a45a8ff	117	This parameter can be a value of @ref UART_Rx_Inv. */
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
bogdanm	0:9b334a45a8ff	120	vs negative/inverted logic).
bogdanm	0:9b334a45a8ff	121	This parameter can be a value of @ref UART_Data_Inv. */
bogdanm	0:9b334a45a8ff	122
bogdanm	0:9b334a45a8ff	123	uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
bogdanm	0:9b334a45a8ff	124	This parameter can be a value of @ref UART_Rx_Tx_Swap. */
bogdanm	0:9b334a45a8ff	125
bogdanm	0:9b334a45a8ff	126	uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
bogdanm	0:9b334a45a8ff	127	This parameter can be a value of @ref UART_Overrun_Disable. */
bogdanm	0:9b334a45a8ff	128
bogdanm	0:9b334a45a8ff	129	uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
bogdanm	0:9b334a45a8ff	130	This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132	uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
bogdanm	0:9b334a45a8ff	133	This parameter can be a value of @ref UART_AutoBaudRate_Enable */
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
bogdanm	0:9b334a45a8ff	136	detection is carried out.
bogdanm	0:9b334a45a8ff	137	This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
bogdanm	0:9b334a45a8ff	138
bogdanm	0:9b334a45a8ff	139	uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
bogdanm	0:9b334a45a8ff	140	This parameter can be a value of @ref UART_MSB_First. */
bogdanm	0:9b334a45a8ff	141	} UART_AdvFeatureInitTypeDef;
bogdanm	0:9b334a45a8ff	142
bogdanm	0:9b334a45a8ff	143
bogdanm	0:9b334a45a8ff	144
bogdanm	0:9b334a45a8ff	145	/**
bogdanm	0:9b334a45a8ff	146	* @brief HAL UART State structures definition
bogdanm	0:9b334a45a8ff	147	*/
bogdanm	0:9b334a45a8ff	148	typedef enum
bogdanm	0:9b334a45a8ff	149	{
bogdanm	0:9b334a45a8ff	150	HAL_UART_STATE_RESET = 0x00, /!< Peripheral is not initialized /
bogdanm	0:9b334a45a8ff	151	HAL_UART_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	0:9b334a45a8ff	152	HAL_UART_STATE_BUSY = 0x02, /!< an internal process is ongoing /
bogdanm	0:9b334a45a8ff	153	HAL_UART_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
bogdanm	0:9b334a45a8ff	154	HAL_UART_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
bogdanm	0:9b334a45a8ff	155	HAL_UART_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
bogdanm	0:9b334a45a8ff	156	HAL_UART_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	0:9b334a45a8ff	157	HAL_UART_STATE_ERROR = 0x04 /!< Error /
bogdanm	0:9b334a45a8ff	158	}HAL_UART_StateTypeDef;
bogdanm	0:9b334a45a8ff	159
bogdanm	0:9b334a45a8ff	160	/**
bogdanm	0:9b334a45a8ff	161	* @brief HAL UART Error Code structure definition
bogdanm	0:9b334a45a8ff	162	*/
bogdanm	0:9b334a45a8ff	163	typedef enum
bogdanm	0:9b334a45a8ff	164	{
bogdanm	0:9b334a45a8ff	165	HAL_UART_ERROR_NONE = 0x00, /!< No error /
bogdanm	0:9b334a45a8ff	166	HAL_UART_ERROR_PE = 0x01, /!< Parity error /
bogdanm	0:9b334a45a8ff	167	HAL_UART_ERROR_NE = 0x02, /!< Noise error /
bogdanm	0:9b334a45a8ff	168	HAL_UART_ERROR_FE = 0x04, /!< frame error /
bogdanm	0:9b334a45a8ff	169	HAL_UART_ERROR_ORE = 0x08, /!< Overrun error /
bogdanm	0:9b334a45a8ff	170	HAL_UART_ERROR_DMA = 0x10 /!< DMA transfer error /
bogdanm	0:9b334a45a8ff	171	}HAL_UART_ErrorTypeDef;
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	/**
bogdanm	0:9b334a45a8ff	174	* @brief UART clock sources definition
bogdanm	0:9b334a45a8ff	175	*/
bogdanm	0:9b334a45a8ff	176	typedef enum
bogdanm	0:9b334a45a8ff	177	{
bogdanm	0:9b334a45a8ff	178	UART_CLOCKSOURCE_PCLK1 = 0x00, /!< PCLK1 clock source /
bogdanm	0:9b334a45a8ff	179	UART_CLOCKSOURCE_PCLK2 = 0x01, /!< PCLK2 clock source /
bogdanm	0:9b334a45a8ff	180	UART_CLOCKSOURCE_HSI = 0x02, /!< HSI clock source /
bogdanm	0:9b334a45a8ff	181	UART_CLOCKSOURCE_SYSCLK = 0x04, /!< SYSCLK clock source /
bogdanm	0:9b334a45a8ff	182	UART_CLOCKSOURCE_LSE = 0x08, /!< LSE clock source /
bogdanm	0:9b334a45a8ff	183	UART_CLOCKSOURCE_UNDEFINED = 0x10 /!< Undefined clock source /
bogdanm	0:9b334a45a8ff	184	}UART_ClockSourceTypeDef;
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	/**
bogdanm	0:9b334a45a8ff	187	* @brief UART handle Structure definition
bogdanm	0:9b334a45a8ff	188	*/
bogdanm	0:9b334a45a8ff	189	typedef struct
bogdanm	0:9b334a45a8ff	190	{
bogdanm	0:9b334a45a8ff	191	USART_TypeDef Instance; /!< UART registers base address */
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	UART_InitTypeDef Init; /!< UART communication parameters /
bogdanm	0:9b334a45a8ff	194
bogdanm	0:9b334a45a8ff	195	UART_AdvFeatureInitTypeDef AdvancedInit; /!< UART Advanced Features initialization parameters /
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197	uint8_t pTxBuffPtr; /!< Pointer to UART Tx transfer Buffer */
bogdanm	0:9b334a45a8ff	198
bogdanm	0:9b334a45a8ff	199	uint16_t TxXferSize; /!< UART Tx Transfer size /
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	uint16_t TxXferCount; /!< UART Tx Transfer Counter /
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	uint8_t pRxBuffPtr; /!< Pointer to UART Rx transfer Buffer */
bogdanm	0:9b334a45a8ff	204
bogdanm	0:9b334a45a8ff	205	uint16_t RxXferSize; /!< UART Rx Transfer size /
bogdanm	0:9b334a45a8ff	206
bogdanm	0:9b334a45a8ff	207	uint16_t RxXferCount; /!< UART Rx Transfer Counter /
bogdanm	0:9b334a45a8ff	208
bogdanm	0:9b334a45a8ff	209	uint16_t Mask; /!< UART Rx RDR register mask /
bogdanm	0:9b334a45a8ff	210
bogdanm	0:9b334a45a8ff	211	DMA_HandleTypeDef hdmatx; /!< UART Tx DMA Handle parameters */
bogdanm	0:9b334a45a8ff	212
bogdanm	0:9b334a45a8ff	213	DMA_HandleTypeDef hdmarx; /!< UART Rx DMA Handle parameters */
bogdanm	0:9b334a45a8ff	214
bogdanm	0:9b334a45a8ff	215	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	0:9b334a45a8ff	216
bogdanm	0:9b334a45a8ff	217	__IO HAL_UART_StateTypeDef State; /!< UART communication state /
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	__IO uint32_t ErrorCode; /!< UART Error code /
bogdanm	0:9b334a45a8ff	220
bogdanm	0:9b334a45a8ff	221	}UART_HandleTypeDef;
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	/**
bogdanm	0:9b334a45a8ff	224	* @}
bogdanm	0:9b334a45a8ff	225	*/
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	228	/** @defgroup UART_Exported_Constants UART Exported Constants
bogdanm	0:9b334a45a8ff	229	* @{
bogdanm	0:9b334a45a8ff	230	*/
bogdanm	0:9b334a45a8ff	231
bogdanm	0:9b334a45a8ff	232	/** @defgroup UART_Stop_Bits UART Number of Stop Bits
bogdanm	0:9b334a45a8ff	233	* @{
bogdanm	0:9b334a45a8ff	234	*/
bogdanm	0:9b334a45a8ff	235	#define UART_STOPBITS_1 ((uint32_t)0x00000000) /!< UART frame with 1 stop bit /
bogdanm	0:9b334a45a8ff	236	#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 \| USART_CR2_STOP_1)) /!< UART frame with 1.5 stop bits /
bogdanm	0:9b334a45a8ff	237	#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /!< UART frame with 2 stop bits /
bogdanm	0:9b334a45a8ff	238	/**
bogdanm	0:9b334a45a8ff	239	* @}
bogdanm	0:9b334a45a8ff	240	*/
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	/** @defgroup UART_Parity UART Parity
bogdanm	0:9b334a45a8ff	243	* @{
bogdanm	0:9b334a45a8ff	244	*/
bogdanm	0:9b334a45a8ff	245	#define UART_PARITY_NONE ((uint32_t)0x00000000) /!< No parity /
bogdanm	0:9b334a45a8ff	246	#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /!< Even parity /
bogdanm	0:9b334a45a8ff	247	#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE \| USART_CR1_PS)) /!< Odd parity /
bogdanm	0:9b334a45a8ff	248	/**
bogdanm	0:9b334a45a8ff	249	* @}
bogdanm	0:9b334a45a8ff	250	*/
bogdanm	0:9b334a45a8ff	251
bogdanm	0:9b334a45a8ff	252	/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
bogdanm	0:9b334a45a8ff	253	* @{
bogdanm	0:9b334a45a8ff	254	*/
bogdanm	0:9b334a45a8ff	255	#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) /!< No hardware control /
bogdanm	0:9b334a45a8ff	256	#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /!< Request To Send /
bogdanm	0:9b334a45a8ff	257	#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /!< Clear To Send /
bogdanm	0:9b334a45a8ff	258	#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE \| USART_CR3_CTSE)) /!< Request and Clear To Send /
bogdanm	0:9b334a45a8ff	259	/**
bogdanm	0:9b334a45a8ff	260	* @}
bogdanm	0:9b334a45a8ff	261	*/
bogdanm	0:9b334a45a8ff	262
bogdanm	0:9b334a45a8ff	263	/** @defgroup UART_Mode UART Transfer Mode
bogdanm	0:9b334a45a8ff	264	* @{
bogdanm	0:9b334a45a8ff	265	*/
bogdanm	0:9b334a45a8ff	266	#define UART_MODE_RX ((uint32_t)USART_CR1_RE) /!< RX mode /
bogdanm	0:9b334a45a8ff	267	#define UART_MODE_TX ((uint32_t)USART_CR1_TE) /!< TX mode /
bogdanm	0:9b334a45a8ff	268	#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE \|USART_CR1_RE)) /!< RX and TX mode /
bogdanm	0:9b334a45a8ff	269	/**
bogdanm	0:9b334a45a8ff	270	* @}
bogdanm	0:9b334a45a8ff	271	*/
bogdanm	0:9b334a45a8ff	272
bogdanm	0:9b334a45a8ff	273	/** @defgroup UART_State UART State
bogdanm	0:9b334a45a8ff	274	* @{
bogdanm	0:9b334a45a8ff	275	*/
bogdanm	0:9b334a45a8ff	276	#define UART_STATE_DISABLE ((uint32_t)0x00000000) /!< UART disabled /
bogdanm	0:9b334a45a8ff	277	#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /!< UART enabled /
bogdanm	0:9b334a45a8ff	278	/**
bogdanm	0:9b334a45a8ff	279	* @}
bogdanm	0:9b334a45a8ff	280	*/
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282	/** @defgroup UART_Over_Sampling UART Over Sampling
bogdanm	0:9b334a45a8ff	283	* @{
bogdanm	0:9b334a45a8ff	284	*/
bogdanm	0:9b334a45a8ff	285	#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) /!< Oversampling by 16 /
bogdanm	0:9b334a45a8ff	286	#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /!< Oversampling by 8 /
bogdanm	0:9b334a45a8ff	287	/**
bogdanm	0:9b334a45a8ff	288	* @}
bogdanm	0:9b334a45a8ff	289	*/
bogdanm	0:9b334a45a8ff	290
bogdanm	0:9b334a45a8ff	291	/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
bogdanm	0:9b334a45a8ff	292	* @{
bogdanm	0:9b334a45a8ff	293	*/
bogdanm	0:9b334a45a8ff	294	#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /!< One-bit sampling disable /
bogdanm	0:9b334a45a8ff	295	#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /!< One-bit sampling enable /
bogdanm	0:9b334a45a8ff	296	/**
bogdanm	0:9b334a45a8ff	297	* @}
bogdanm	0:9b334a45a8ff	298	*/
bogdanm	0:9b334a45a8ff	299
bogdanm	0:9b334a45a8ff	300	/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
bogdanm	0:9b334a45a8ff	301	* @{
bogdanm	0:9b334a45a8ff	302	*/
bogdanm	0:9b334a45a8ff	303	#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000) /!< Auto Baud rate detection on start bit /
bogdanm	0:9b334a45a8ff	304	#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /!< Auto Baud rate detection on falling edge /
bogdanm	0:9b334a45a8ff	305	#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /!< Auto Baud rate detection on 0x7F frame detection /
bogdanm	0:9b334a45a8ff	306	#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /!< Auto Baud rate detection on 0x55 frame detection /
bogdanm	0:9b334a45a8ff	307	/**
bogdanm	0:9b334a45a8ff	308	* @}
bogdanm	0:9b334a45a8ff	309	*/
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311	/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
bogdanm	0:9b334a45a8ff	312	* @{
bogdanm	0:9b334a45a8ff	313	*/
bogdanm	0:9b334a45a8ff	314	#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) /!< UART receiver timeout disable /
bogdanm	0:9b334a45a8ff	315	#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /!< UART receiver timeout enable /
bogdanm	0:9b334a45a8ff	316	/**
bogdanm	0:9b334a45a8ff	317	* @}
bogdanm	0:9b334a45a8ff	318	*/
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320	/** @defgroup UART_LIN UART Local Interconnection Network mode
bogdanm	0:9b334a45a8ff	321	* @{
bogdanm	0:9b334a45a8ff	322	*/
bogdanm	0:9b334a45a8ff	323	#define UART_LIN_DISABLE ((uint32_t)0x00000000) /!< Local Interconnect Network disable /
bogdanm	0:9b334a45a8ff	324	#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /!< Local Interconnect Network enable /
bogdanm	0:9b334a45a8ff	325	/**
bogdanm	0:9b334a45a8ff	326	* @}
bogdanm	0:9b334a45a8ff	327	*/
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
bogdanm	0:9b334a45a8ff	330	* @{
bogdanm	0:9b334a45a8ff	331	*/
bogdanm	0:9b334a45a8ff	332	#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) /!< LIN 10-bit break detection length /
bogdanm	0:9b334a45a8ff	333	#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /!< LIN 11-bit break detection length /
bogdanm	0:9b334a45a8ff	334	/**
bogdanm	0:9b334a45a8ff	335	* @}
bogdanm	0:9b334a45a8ff	336	*/
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	/** @defgroup UART_DMA_Tx UART DMA Tx
bogdanm	0:9b334a45a8ff	339	* @{
bogdanm	0:9b334a45a8ff	340	*/
bogdanm	0:9b334a45a8ff	341	#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) /!< UART DMA TX disabled /
bogdanm	0:9b334a45a8ff	342	#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /!< UART DMA TX enabled /
bogdanm	0:9b334a45a8ff	343	/**
bogdanm	0:9b334a45a8ff	344	* @}
bogdanm	0:9b334a45a8ff	345	*/
bogdanm	0:9b334a45a8ff	346
bogdanm	0:9b334a45a8ff	347	/** @defgroup UART_DMA_Rx UART DMA Rx
bogdanm	0:9b334a45a8ff	348	* @{
bogdanm	0:9b334a45a8ff	349	*/
bogdanm	0:9b334a45a8ff	350	#define UART_DMA_RX_DISABLE ((uint32_t)0x0000) /!< UART DMA RX disabled /
bogdanm	0:9b334a45a8ff	351	#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /!< UART DMA RX enabled /
bogdanm	0:9b334a45a8ff	352	/**
bogdanm	0:9b334a45a8ff	353	* @}
bogdanm	0:9b334a45a8ff	354	*/
bogdanm	0:9b334a45a8ff	355
bogdanm	0:9b334a45a8ff	356	/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
bogdanm	0:9b334a45a8ff	357	* @{
bogdanm	0:9b334a45a8ff	358	*/
bogdanm	0:9b334a45a8ff	359	#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000) /!< UART half-duplex disabled /
bogdanm	0:9b334a45a8ff	360	#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /!< UART half-duplex enabled /
bogdanm	0:9b334a45a8ff	361	/**
bogdanm	0:9b334a45a8ff	362	* @}
bogdanm	0:9b334a45a8ff	363	*/
bogdanm	0:9b334a45a8ff	364
bogdanm	0:9b334a45a8ff	365	/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
bogdanm	0:9b334a45a8ff	366	* @{
bogdanm	0:9b334a45a8ff	367	*/
bogdanm	0:9b334a45a8ff	368	#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) /!< UART wake-up on idle line /
bogdanm	0:9b334a45a8ff	369	#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /!< UART wake-up on address mark /
bogdanm	0:9b334a45a8ff	370	/**
bogdanm	0:9b334a45a8ff	371	* @}
bogdanm	0:9b334a45a8ff	372	*/
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/** @defgroup UART_Request_Parameters UART Request Parameters
bogdanm	0:9b334a45a8ff	375	* @{
bogdanm	0:9b334a45a8ff	376	*/
bogdanm	0:9b334a45a8ff	377	#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /!< Auto-Baud Rate Request /
bogdanm	0:9b334a45a8ff	378	#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /!< Send Break Request /
bogdanm	0:9b334a45a8ff	379	#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /!< Mute Mode Request /
bogdanm	0:9b334a45a8ff	380	#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /!< Receive Data flush Request /
bogdanm	0:9b334a45a8ff	381	#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /!< Transmit data flush Request /
bogdanm	0:9b334a45a8ff	382	/**
bogdanm	0:9b334a45a8ff	383	* @}
bogdanm	0:9b334a45a8ff	384	*/
bogdanm	0:9b334a45a8ff	385
bogdanm	0:9b334a45a8ff	386	/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
bogdanm	0:9b334a45a8ff	387	* @{
bogdanm	0:9b334a45a8ff	388	*/
bogdanm	0:9b334a45a8ff	389	#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /!< No advanced feature initialization /
bogdanm	0:9b334a45a8ff	390	#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /!< TX pin active level inversion /
bogdanm	0:9b334a45a8ff	391	#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /!< RX pin active level inversion /
bogdanm	0:9b334a45a8ff	392	#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /!< Binary data inversion /
bogdanm	0:9b334a45a8ff	393	#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /!< TX/RX pins swap /
bogdanm	0:9b334a45a8ff	394	#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /!< RX overrun disable /
bogdanm	0:9b334a45a8ff	395	#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /!< DMA disable on Reception Error /
bogdanm	0:9b334a45a8ff	396	#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) /!< Auto Baud rate detection initialization /
bogdanm	0:9b334a45a8ff	397	#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /!< Most significant bit sent/received first /
bogdanm	0:9b334a45a8ff	398	/**
bogdanm	0:9b334a45a8ff	399	* @}
bogdanm	0:9b334a45a8ff	400	*/
bogdanm	0:9b334a45a8ff	401
bogdanm	0:9b334a45a8ff	402	/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
bogdanm	0:9b334a45a8ff	403	* @{
bogdanm	0:9b334a45a8ff	404	*/
bogdanm	0:9b334a45a8ff	405	#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /!< TX pin active level inversion disable /
bogdanm	0:9b334a45a8ff	406	#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /!< TX pin active level inversion enable /
bogdanm	0:9b334a45a8ff	407	/**
bogdanm	0:9b334a45a8ff	408	* @}
bogdanm	0:9b334a45a8ff	409	*/
bogdanm	0:9b334a45a8ff	410
bogdanm	0:9b334a45a8ff	411	/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
bogdanm	0:9b334a45a8ff	412	* @{
bogdanm	0:9b334a45a8ff	413	*/
bogdanm	0:9b334a45a8ff	414	#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /!< RX pin active level inversion disable /
bogdanm	0:9b334a45a8ff	415	#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /!< RX pin active level inversion enable /
bogdanm	0:9b334a45a8ff	416	/**
bogdanm	0:9b334a45a8ff	417	* @}
bogdanm	0:9b334a45a8ff	418	*/
bogdanm	0:9b334a45a8ff	419
bogdanm	0:9b334a45a8ff	420	/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
bogdanm	0:9b334a45a8ff	421	* @{
bogdanm	0:9b334a45a8ff	422	*/
bogdanm	0:9b334a45a8ff	423	#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /!< Binary data inversion disable /
bogdanm	0:9b334a45a8ff	424	#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /!< Binary data inversion enable /
bogdanm	0:9b334a45a8ff	425	/**
bogdanm	0:9b334a45a8ff	426	* @}
bogdanm	0:9b334a45a8ff	427	*/
bogdanm	0:9b334a45a8ff	428
bogdanm	0:9b334a45a8ff	429	/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
bogdanm	0:9b334a45a8ff	430	* @{
bogdanm	0:9b334a45a8ff	431	*/
bogdanm	0:9b334a45a8ff	432	#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /!< TX/RX pins swap disable /
bogdanm	0:9b334a45a8ff	433	#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /!< TX/RX pins swap enable /
bogdanm	0:9b334a45a8ff	434	/**
bogdanm	0:9b334a45a8ff	435	* @}
bogdanm	0:9b334a45a8ff	436	*/
bogdanm	0:9b334a45a8ff	437
bogdanm	0:9b334a45a8ff	438	/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
bogdanm	0:9b334a45a8ff	439	* @{
bogdanm	0:9b334a45a8ff	440	*/
bogdanm	0:9b334a45a8ff	441	#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /!< RX overrun enable /
bogdanm	0:9b334a45a8ff	442	#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /!< RX overrun disable /
bogdanm	0:9b334a45a8ff	443	/**
bogdanm	0:9b334a45a8ff	444	* @}
bogdanm	0:9b334a45a8ff	445	*/
bogdanm	0:9b334a45a8ff	446
bogdanm	0:9b334a45a8ff	447	/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
bogdanm	0:9b334a45a8ff	448	* @{
bogdanm	0:9b334a45a8ff	449	*/
bogdanm	0:9b334a45a8ff	450	#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) /!< RX Auto Baud rate detection enable /
bogdanm	0:9b334a45a8ff	451	#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /!< RX Auto Baud rate detection disable /
bogdanm	0:9b334a45a8ff	452	/**
bogdanm	0:9b334a45a8ff	453	* @}
bogdanm	0:9b334a45a8ff	454	*/
bogdanm	0:9b334a45a8ff	455
bogdanm	0:9b334a45a8ff	456	/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
bogdanm	0:9b334a45a8ff	457	* @{
bogdanm	0:9b334a45a8ff	458	*/
bogdanm	0:9b334a45a8ff	459	#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /!< DMA enable on Reception Error /
bogdanm	0:9b334a45a8ff	460	#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /!< DMA disable on Reception Error /
bogdanm	0:9b334a45a8ff	461	/**
bogdanm	0:9b334a45a8ff	462	* @}
bogdanm	0:9b334a45a8ff	463	*/
bogdanm	0:9b334a45a8ff	464
bogdanm	0:9b334a45a8ff	465	/** @defgroup UART_MSB_First UART Advanced Feature MSB First
bogdanm	0:9b334a45a8ff	466	* @{
bogdanm	0:9b334a45a8ff	467	*/
bogdanm	0:9b334a45a8ff	468	#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /!< Most significant bit sent/received first disable /
bogdanm	0:9b334a45a8ff	469	#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /!< Most significant bit sent/received first enable /
bogdanm	0:9b334a45a8ff	470	/**
bogdanm	0:9b334a45a8ff	471	* @}
bogdanm	0:9b334a45a8ff	472	*/
bogdanm	0:9b334a45a8ff	473
bogdanm	0:9b334a45a8ff	474	/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
bogdanm	0:9b334a45a8ff	475	* @{
bogdanm	0:9b334a45a8ff	476	*/
bogdanm	0:9b334a45a8ff	477	#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) /!< UART stop mode disable /
bogdanm	0:9b334a45a8ff	478	#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /!< UART stop mode enable /
bogdanm	0:9b334a45a8ff	479	/**
bogdanm	0:9b334a45a8ff	480	* @}
bogdanm	0:9b334a45a8ff	481	*/
bogdanm	0:9b334a45a8ff	482
bogdanm	0:9b334a45a8ff	483	/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
bogdanm	0:9b334a45a8ff	484	* @{
bogdanm	0:9b334a45a8ff	485	*/
bogdanm	0:9b334a45a8ff	486	#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) /!< UART mute mode disable /
bogdanm	0:9b334a45a8ff	487	#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /!< UART mute mode enable /
bogdanm	0:9b334a45a8ff	488	/**
bogdanm	0:9b334a45a8ff	489	* @}
bogdanm	0:9b334a45a8ff	490	*/
bogdanm	0:9b334a45a8ff	491
bogdanm	0:9b334a45a8ff	492	/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
bogdanm	0:9b334a45a8ff	493	* @{
bogdanm	0:9b334a45a8ff	494	*/
bogdanm	0:9b334a45a8ff	495	#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24) /!< UART address-matching LSB position in CR2 register /
bogdanm	0:9b334a45a8ff	496	/**
bogdanm	0:9b334a45a8ff	497	* @}
bogdanm	0:9b334a45a8ff	498	*/
bogdanm	0:9b334a45a8ff	499
bogdanm	0:9b334a45a8ff	500	/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
bogdanm	0:9b334a45a8ff	501	* @{
bogdanm	0:9b334a45a8ff	502	*/
bogdanm	0:9b334a45a8ff	503	#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000) /!< UART wake-up on address /
bogdanm	0:9b334a45a8ff	504	#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /!< UART wake-up on start bit /
bogdanm	0:9b334a45a8ff	505	#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /!< UART wake-up on receive data register not empty /
bogdanm	0:9b334a45a8ff	506	/**
bogdanm	0:9b334a45a8ff	507	* @}
bogdanm	0:9b334a45a8ff	508	*/
bogdanm	0:9b334a45a8ff	509
bogdanm	0:9b334a45a8ff	510	/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
bogdanm	0:9b334a45a8ff	511	* @{
bogdanm	0:9b334a45a8ff	512	*/
bogdanm	0:9b334a45a8ff	513	#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) /!< Driver enable signal is active high /
bogdanm	0:9b334a45a8ff	514	#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /!< Driver enable signal is active low /
bogdanm	0:9b334a45a8ff	515	/**
bogdanm	0:9b334a45a8ff	516	* @}
bogdanm	0:9b334a45a8ff	517	*/
bogdanm	0:9b334a45a8ff	518
bogdanm	0:9b334a45a8ff	519	/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
bogdanm	0:9b334a45a8ff	520	* @{
bogdanm	0:9b334a45a8ff	521	*/
bogdanm	0:9b334a45a8ff	522	#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) /!< UART Driver Enable assertion time LSB position in CR1 register /
bogdanm	0:9b334a45a8ff	523	/**
bogdanm	0:9b334a45a8ff	524	* @}
bogdanm	0:9b334a45a8ff	525	*/
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
bogdanm	0:9b334a45a8ff	528	* @{
bogdanm	0:9b334a45a8ff	529	*/
bogdanm	0:9b334a45a8ff	530	#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) /!< UART Driver Enable de-assertion time LSB position in CR1 register /
bogdanm	0:9b334a45a8ff	531	/**
bogdanm	0:9b334a45a8ff	532	* @}
bogdanm	0:9b334a45a8ff	533	*/
bogdanm	0:9b334a45a8ff	534
bogdanm	0:9b334a45a8ff	535	/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
bogdanm	0:9b334a45a8ff	536	* @{
bogdanm	0:9b334a45a8ff	537	*/
bogdanm	0:9b334a45a8ff	538	#define UART_IT_MASK ((uint32_t)0x001F) /!< UART interruptions flags mask /
bogdanm	0:9b334a45a8ff	539	/**
bogdanm	0:9b334a45a8ff	540	* @}
bogdanm	0:9b334a45a8ff	541	*/
bogdanm	0:9b334a45a8ff	542
bogdanm	0:9b334a45a8ff	543	/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
bogdanm	0:9b334a45a8ff	544	* @{
bogdanm	0:9b334a45a8ff	545	*/
bogdanm	0:9b334a45a8ff	546	#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF /!< UART polling-based communications time-out value /
bogdanm	0:9b334a45a8ff	547	/**
bogdanm	0:9b334a45a8ff	548	* @}
bogdanm	0:9b334a45a8ff	549	*/
bogdanm	0:9b334a45a8ff	550
bogdanm	0:9b334a45a8ff	551	/** @defgroup UART_Flags UART Status Flags
bogdanm	0:9b334a45a8ff	552	* Elements values convention: 0xXXXX
bogdanm	0:9b334a45a8ff	553	* - 0xXXXX : Flag mask in the ISR register
bogdanm	0:9b334a45a8ff	554	* @{
bogdanm	0:9b334a45a8ff	555	*/
bogdanm	0:9b334a45a8ff	556	#define UART_FLAG_REACK ((uint32_t)0x00400000) /!< UART receive enable acknowledge flag /
bogdanm	0:9b334a45a8ff	557	#define UART_FLAG_TEACK ((uint32_t)0x00200000) /!< UART transmit enable acknowledge flag /
bogdanm	0:9b334a45a8ff	558	#define UART_FLAG_WUF ((uint32_t)0x00100000) /!< UART wake-up from stop mode flag /
bogdanm	0:9b334a45a8ff	559	#define UART_FLAG_RWU ((uint32_t)0x00080000) /!< UART receiver wake-up from mute mode flag /
bogdanm	0:9b334a45a8ff	560	#define UART_FLAG_SBKF ((uint32_t)0x00040000) /!< UART send break flag /
bogdanm	0:9b334a45a8ff	561	#define UART_FLAG_CMF ((uint32_t)0x00020000) /!< UART character match flag /
bogdanm	0:9b334a45a8ff	562	#define UART_FLAG_BUSY ((uint32_t)0x00010000) /!< UART busy flag /
bogdanm	0:9b334a45a8ff	563	#define UART_FLAG_ABRF ((uint32_t)0x00008000) /!< UART auto Baud rate flag /
bogdanm	0:9b334a45a8ff	564	#define UART_FLAG_ABRE ((uint32_t)0x00004000) /!< UART uto Baud rate error /
bogdanm	0:9b334a45a8ff	565	#define UART_FLAG_EOBF ((uint32_t)0x00001000) /!< UART end of block flag /
bogdanm	0:9b334a45a8ff	566	#define UART_FLAG_RTOF ((uint32_t)0x00000800) /!< UART receiver timeout flag /
bogdanm	0:9b334a45a8ff	567	#define UART_FLAG_CTS ((uint32_t)0x00000400) /!< UART clear to send flag /
bogdanm	0:9b334a45a8ff	568	#define UART_FLAG_CTSIF ((uint32_t)0x00000200) /!< UART clear to send interrupt flag /
bogdanm	0:9b334a45a8ff	569	#define UART_FLAG_LBDF ((uint32_t)0x00000100) /!< UART LIN break detection flag /
bogdanm	0:9b334a45a8ff	570	#define UART_FLAG_TXE ((uint32_t)0x00000080) /!< UART transmit data register empty /
bogdanm	0:9b334a45a8ff	571	#define UART_FLAG_TC ((uint32_t)0x00000040) /!< UART transmission complete /
bogdanm	0:9b334a45a8ff	572	#define UART_FLAG_RXNE ((uint32_t)0x00000020) /!< UART read data register not empty /
bogdanm	0:9b334a45a8ff	573	#define UART_FLAG_IDLE ((uint32_t)0x00000010) /!< UART idle flag /
bogdanm	0:9b334a45a8ff	574	#define UART_FLAG_ORE ((uint32_t)0x00000008) /!< UART overrun error /
bogdanm	0:9b334a45a8ff	575	#define UART_FLAG_NE ((uint32_t)0x00000004) /!< UART noise error /
bogdanm	0:9b334a45a8ff	576	#define UART_FLAG_FE ((uint32_t)0x00000002) /!< UART frame error /
bogdanm	0:9b334a45a8ff	577	#define UART_FLAG_PE ((uint32_t)0x00000001) /!< UART parity error /
bogdanm	0:9b334a45a8ff	578	/**
bogdanm	0:9b334a45a8ff	579	* @}
bogdanm	0:9b334a45a8ff	580	*/
bogdanm	0:9b334a45a8ff	581
bogdanm	0:9b334a45a8ff	582	/** @defgroup UART_Interrupt_definition UART Interrupts Definition
bogdanm	0:9b334a45a8ff	583	* Elements values convention: 000ZZZZZ0XXYYYYYb
bogdanm	0:9b334a45a8ff	584	* - YYYYY : Interrupt source position in the XX register (5bits)
bogdanm	0:9b334a45a8ff	585	* - XX : Interrupt source register (2bits)
bogdanm	0:9b334a45a8ff	586	* - 01: CR1 register
bogdanm	0:9b334a45a8ff	587	* - 10: CR2 register
bogdanm	0:9b334a45a8ff	588	* - 11: CR3 register
bogdanm	0:9b334a45a8ff	589	* - ZZZZZ : Flag position in the ISR register(5bits)
bogdanm	0:9b334a45a8ff	590	* @{
bogdanm	0:9b334a45a8ff	591	*/
bogdanm	0:9b334a45a8ff	592	#define UART_IT_PE ((uint32_t)0x0028) /!< UART parity error interruption /
bogdanm	0:9b334a45a8ff	593	#define UART_IT_TXE ((uint32_t)0x0727) /!< UART transmit data register empty interruption /
bogdanm	0:9b334a45a8ff	594	#define UART_IT_TC ((uint32_t)0x0626) /!< UART transmission complete interruption /
bogdanm	0:9b334a45a8ff	595	#define UART_IT_RXNE ((uint32_t)0x0525) /!< UART read data register not empty interruption /
bogdanm	0:9b334a45a8ff	596	#define UART_IT_IDLE ((uint32_t)0x0424) /!< UART idle interruption /
bogdanm	0:9b334a45a8ff	597	#define UART_IT_LBD ((uint32_t)0x0846) /!< UART LIN break detection interruption /
bogdanm	0:9b334a45a8ff	598	#define UART_IT_CTS ((uint32_t)0x096A) /!< UART CTS interruption /
bogdanm	0:9b334a45a8ff	599	#define UART_IT_CM ((uint32_t)0x112E) /!< UART character match interruption /
bogdanm	0:9b334a45a8ff	600	#define UART_IT_WUF ((uint32_t)0x1476) /!< UART wake-up from stop mode interruption /
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	/* Elements values convention: 000000000XXYYYYYb
bogdanm	0:9b334a45a8ff	603	- YYYYY : Interrupt source position in the XX register (5bits)
bogdanm	0:9b334a45a8ff	604	- XX : Interrupt source register (2bits)
bogdanm	0:9b334a45a8ff	605	- 01: CR1 register
bogdanm	0:9b334a45a8ff	606	- 10: CR2 register
bogdanm	0:9b334a45a8ff	607	- 11: CR3 register */
bogdanm	0:9b334a45a8ff	608	#define UART_IT_ERR ((uint32_t)0x0060) /!< UART error interruption /
bogdanm	0:9b334a45a8ff	609
bogdanm	0:9b334a45a8ff	610	/* Elements values convention: 0000ZZZZ00000000b
bogdanm	0:9b334a45a8ff	611	- ZZZZ : Flag position in the ISR register(4bits) */
bogdanm	0:9b334a45a8ff	612	#define UART_IT_ORE ((uint32_t)0x0300) /!< UART overrun error interruption /
bogdanm	0:9b334a45a8ff	613	#define UART_IT_NE ((uint32_t)0x0200) /!< UART noise error interruption /
bogdanm	0:9b334a45a8ff	614	#define UART_IT_FE ((uint32_t)0x0100) /!< UART frame error interruption /
bogdanm	0:9b334a45a8ff	615	/**
bogdanm	0:9b334a45a8ff	616	* @}
bogdanm	0:9b334a45a8ff	617	*/
bogdanm	0:9b334a45a8ff	618
bogdanm	0:9b334a45a8ff	619	/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
bogdanm	0:9b334a45a8ff	620	* @{
bogdanm	0:9b334a45a8ff	621	*/
bogdanm	0:9b334a45a8ff	622	#define UART_CLEAR_PEF USART_ICR_PECF /!< Parity Error Clear Flag /
bogdanm	0:9b334a45a8ff	623	#define UART_CLEAR_FEF USART_ICR_FECF /!< Framing Error Clear Flag /
bogdanm	0:9b334a45a8ff	624	#define UART_CLEAR_NEF USART_ICR_NCF /!< Noise detected Clear Flag /
bogdanm	0:9b334a45a8ff	625	#define UART_CLEAR_OREF USART_ICR_ORECF /!< OverRun Error Clear Flag /
bogdanm	0:9b334a45a8ff	626	#define UART_CLEAR_IDLEF USART_ICR_IDLECF /!< IDLE line detected Clear Flag /
bogdanm	0:9b334a45a8ff	627	#define UART_CLEAR_TCF USART_ICR_TCCF /!< Transmission Complete Clear Flag /
bogdanm	0:9b334a45a8ff	628	#define UART_CLEAR_LBDF USART_ICR_LBDCF /!< LIN Break Detection Clear Flag /
bogdanm	0:9b334a45a8ff	629	#define UART_CLEAR_CTSF USART_ICR_CTSCF /!< CTS Interrupt Clear Flag /
bogdanm	0:9b334a45a8ff	630	#define UART_CLEAR_RTOF USART_ICR_RTOCF /!< Receiver Time Out Clear Flag /
bogdanm	0:9b334a45a8ff	631	#define UART_CLEAR_EOBF USART_ICR_EOBCF /!< End Of Block Clear Flag /
bogdanm	0:9b334a45a8ff	632	#define UART_CLEAR_CMF USART_ICR_CMCF /!< Character Match Clear Flag /
bogdanm	0:9b334a45a8ff	633	#define UART_CLEAR_WUF USART_ICR_WUCF /!< Wake Up from stop mode Clear Flag /
bogdanm	0:9b334a45a8ff	634	/**
bogdanm	0:9b334a45a8ff	635	* @}
bogdanm	0:9b334a45a8ff	636	*/
bogdanm	0:9b334a45a8ff	637
bogdanm	0:9b334a45a8ff	638
bogdanm	0:9b334a45a8ff	639	/**
bogdanm	0:9b334a45a8ff	640	* @}
bogdanm	0:9b334a45a8ff	641	*/
bogdanm	0:9b334a45a8ff	642
bogdanm	0:9b334a45a8ff	643	/* Exported macros -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	644	/** @defgroup UART_Exported_Macros UART Exported Macros
bogdanm	0:9b334a45a8ff	645	* @{
bogdanm	0:9b334a45a8ff	646	*/
bogdanm	0:9b334a45a8ff	647
bogdanm	0:9b334a45a8ff	648	/** @brief Reset UART handle state.
bogdanm	0:9b334a45a8ff	649	* @param __HANDLE__: UART handle.
bogdanm	0:9b334a45a8ff	650	* @retval None
bogdanm	0:9b334a45a8ff	651	*/
bogdanm	0:9b334a45a8ff	652	#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
bogdanm	0:9b334a45a8ff	653
bogdanm	0:9b334a45a8ff	654	/** @brief Flush the UART Data registers.
bogdanm	0:9b334a45a8ff	655	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	656	* @retval None
bogdanm	0:9b334a45a8ff	657	*/
bogdanm	0:9b334a45a8ff	658	#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
bogdanm	0:9b334a45a8ff	659	do{ \
bogdanm	0:9b334a45a8ff	660	SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
bogdanm	0:9b334a45a8ff	661	SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
bogdanm	0:9b334a45a8ff	662	} while(0)
bogdanm	0:9b334a45a8ff	663
bogdanm	0:9b334a45a8ff	664	/** @brief Clear the specified UART pending flag.
bogdanm	0:9b334a45a8ff	665	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	666	* @param __FLAG__: specifies the flag to check.
bogdanm	0:9b334a45a8ff	667	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	668	* @arg UART_CLEAR_PEF, Parity Error Clear Flag
bogdanm	0:9b334a45a8ff	669	* @arg UART_CLEAR_FEF, Framing Error Clear Flag
bogdanm	0:9b334a45a8ff	670	* @arg UART_CLEAR_NEF, Noise detected Clear Flag
bogdanm	0:9b334a45a8ff	671	* @arg UART_CLEAR_OREF, OverRun Error Clear Flag
bogdanm	0:9b334a45a8ff	672	* @arg UART_CLEAR_IDLEF, IDLE line detected Clear Flag
bogdanm	0:9b334a45a8ff	673	* @arg UART_CLEAR_TCF, Transmission Complete Clear Flag
bogdanm	0:9b334a45a8ff	674	* @arg UART_CLEAR_LBDF, LIN Break Detection Clear Flag
bogdanm	0:9b334a45a8ff	675	* @arg UART_CLEAR_CTSF, CTS Interrupt Clear Flag
bogdanm	0:9b334a45a8ff	676	* @arg UART_CLEAR_RTOF, Receiver Time Out Clear Flag
bogdanm	0:9b334a45a8ff	677	* @arg UART_CLEAR_EOBF, End Of Block Clear Flag
bogdanm	0:9b334a45a8ff	678	* @arg UART_CLEAR_CMF, Character Match Clear Flag
bogdanm	0:9b334a45a8ff	679	* @arg UART_CLEAR_WUF, Wake Up from stop mode Clear Flag
bogdanm	0:9b334a45a8ff	680	* @retval None
bogdanm	0:9b334a45a8ff	681	*/
bogdanm	0:9b334a45a8ff	682	#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
bogdanm	0:9b334a45a8ff	683
bogdanm	0:9b334a45a8ff	684	/** @brief Clear the UART PE pending flag.
bogdanm	0:9b334a45a8ff	685	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	686	* @retval None
bogdanm	0:9b334a45a8ff	687	*/
bogdanm	0:9b334a45a8ff	688	#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	/** @brief Clear the UART FE pending flag.
bogdanm	0:9b334a45a8ff	691	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	692	* @retval None
bogdanm	0:9b334a45a8ff	693	*/
bogdanm	0:9b334a45a8ff	694	#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	/** @brief Clear the UART NE pending flag.
bogdanm	0:9b334a45a8ff	697	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	698	* @retval None
bogdanm	0:9b334a45a8ff	699	*/
bogdanm	0:9b334a45a8ff	700	#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
bogdanm	0:9b334a45a8ff	701
bogdanm	0:9b334a45a8ff	702	/** @brief Clear the UART ORE pending flag.
bogdanm	0:9b334a45a8ff	703	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	704	* @retval None
bogdanm	0:9b334a45a8ff	705	*/
bogdanm	0:9b334a45a8ff	706	#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
bogdanm	0:9b334a45a8ff	707
bogdanm	0:9b334a45a8ff	708	/** @brief Clear the UART IDLE pending flag.
bogdanm	0:9b334a45a8ff	709	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	710	* @retval None
bogdanm	0:9b334a45a8ff	711	*/
bogdanm	0:9b334a45a8ff	712	#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
bogdanm	0:9b334a45a8ff	713
bogdanm	0:9b334a45a8ff	714	/** @brief Check whether the specified UART flag is set or not.
bogdanm	0:9b334a45a8ff	715	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	716	* @param __FLAG__: specifies the flag to check.
bogdanm	0:9b334a45a8ff	717	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	718	* @arg UART_FLAG_REACK: Receive enable acknowledge flag
bogdanm	0:9b334a45a8ff	719	* @arg UART_FLAG_TEACK: Transmit enable acknowledge flag
bogdanm	0:9b334a45a8ff	720	* @arg UART_FLAG_WUF: Wake up from stop mode flag
bogdanm	0:9b334a45a8ff	721	* @arg UART_FLAG_RWU: Receiver wake up flag (if the UART in mute mode)
bogdanm	0:9b334a45a8ff	722	* @arg UART_FLAG_SBKF: Send Break flag
bogdanm	0:9b334a45a8ff	723	* @arg UART_FLAG_CMF: Character match flag
bogdanm	0:9b334a45a8ff	724	* @arg UART_FLAG_BUSY: Busy flag
bogdanm	0:9b334a45a8ff	725	* @arg UART_FLAG_ABRF: Auto Baud rate detection flag
bogdanm	0:9b334a45a8ff	726	* @arg UART_FLAG_ABRE: Auto Baud rate detection error flag
bogdanm	0:9b334a45a8ff	727	* @arg UART_FLAG_EOBF: End of block flag
bogdanm	0:9b334a45a8ff	728	* @arg UART_FLAG_RTOF: Receiver timeout flag
bogdanm	0:9b334a45a8ff	729	* @arg UART_FLAG_CTS: CTS Change flag
bogdanm	0:9b334a45a8ff	730	* @arg UART_FLAG_LBD: LIN Break detection flag
bogdanm	0:9b334a45a8ff	731	* @arg UART_FLAG_TXE: Transmit data register empty flag
bogdanm	0:9b334a45a8ff	732	* @arg UART_FLAG_TC: Transmission Complete flag
bogdanm	0:9b334a45a8ff	733	* @arg UART_FLAG_RXNE: Receive data register not empty flag
bogdanm	0:9b334a45a8ff	734	* @arg UART_FLAG_IDLE: Idle Line detection flag
bogdanm	0:9b334a45a8ff	735	* @arg UART_FLAG_ORE: OverRun Error flag
bogdanm	0:9b334a45a8ff	736	* @arg UART_FLAG_NE: Noise Error flag
bogdanm	0:9b334a45a8ff	737	* @arg UART_FLAG_FE: Framing Error flag
bogdanm	0:9b334a45a8ff	738	* @arg UART_FLAG_PE: Parity Error flag
bogdanm	0:9b334a45a8ff	739	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	740	*/
bogdanm	0:9b334a45a8ff	741	#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	742
bogdanm	0:9b334a45a8ff	743	/** @brief Enable the specified UART interrupt.
bogdanm	0:9b334a45a8ff	744	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	745	* @param __INTERRUPT__: specifies the UART interrupt source to enable.
bogdanm	0:9b334a45a8ff	746	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	747	* @arg UART_IT_WUF: Wakeup from stop mode interrupt
bogdanm	0:9b334a45a8ff	748	* @arg UART_IT_CM: Character match interrupt
bogdanm	0:9b334a45a8ff	749	* @arg UART_IT_CTS: CTS change interrupt
bogdanm	0:9b334a45a8ff	750	* @arg UART_IT_LBD: LIN Break detection interrupt
bogdanm	0:9b334a45a8ff	751	* @arg UART_IT_TXE: Transmit Data Register empty interrupt
bogdanm	0:9b334a45a8ff	752	* @arg UART_IT_TC: Transmission complete interrupt
bogdanm	0:9b334a45a8ff	753	* @arg UART_IT_RXNE: Receive Data register not empty interrupt
bogdanm	0:9b334a45a8ff	754	* @arg UART_IT_IDLE: Idle line detection interrupt
bogdanm	0:9b334a45a8ff	755	* @arg UART_IT_PE: Parity Error interrupt
bogdanm	0:9b334a45a8ff	756	* @arg UART_IT_ERR: Error interrupt (Frame error, noise error, overrun error)
bogdanm	0:9b334a45a8ff	757	* @retval None
bogdanm	0:9b334a45a8ff	758	*/
bogdanm	0:9b334a45a8ff	759	#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 \|= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
bogdanm	0:9b334a45a8ff	760	((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 \|= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
bogdanm	0:9b334a45a8ff	761	((__HANDLE__)->Instance->CR3 \|= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
bogdanm	0:9b334a45a8ff	762
bogdanm	0:9b334a45a8ff	763
bogdanm	0:9b334a45a8ff	764	/** @brief Disable the specified UART interrupt.
bogdanm	0:9b334a45a8ff	765	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	766	* @param __INTERRUPT__: specifies the UART interrupt source to disable.
bogdanm	0:9b334a45a8ff	767	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	768	* @arg UART_IT_WUF: Wakeup from stop mode interrupt
bogdanm	0:9b334a45a8ff	769	* @arg UART_IT_CM: Character match interrupt
bogdanm	0:9b334a45a8ff	770	* @arg UART_IT_CTS: CTS change interrupt
bogdanm	0:9b334a45a8ff	771	* @arg UART_IT_LBD: LIN Break detection interrupt
bogdanm	0:9b334a45a8ff	772	* @arg UART_IT_TXE: Transmit Data Register empty interrupt
bogdanm	0:9b334a45a8ff	773	* @arg UART_IT_TC: Transmission complete interrupt
bogdanm	0:9b334a45a8ff	774	* @arg UART_IT_RXNE: Receive Data register not empty interrupt
bogdanm	0:9b334a45a8ff	775	* @arg UART_IT_IDLE: Idle line detection interrupt
bogdanm	0:9b334a45a8ff	776	* @arg UART_IT_PE: Parity Error interrupt
bogdanm	0:9b334a45a8ff	777	* @arg UART_IT_ERR: Error interrupt (Frame error, noise error, overrun error)
bogdanm	0:9b334a45a8ff	778	* @retval None
bogdanm	0:9b334a45a8ff	779	*/
bogdanm	0:9b334a45a8ff	780	#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
bogdanm	0:9b334a45a8ff	781	((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
bogdanm	0:9b334a45a8ff	782	((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
bogdanm	0:9b334a45a8ff	783
bogdanm	0:9b334a45a8ff	784	/** @brief Check whether the specified UART interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	785	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	786	* @param __IT__: specifies the UART interrupt to check.
bogdanm	0:9b334a45a8ff	787	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	788	* @arg UART_IT_WUF: Wakeup from stop mode interrupt
bogdanm	0:9b334a45a8ff	789	* @arg UART_IT_CM: Character match interrupt
bogdanm	0:9b334a45a8ff	790	* @arg UART_IT_CTS: CTS change interrupt
bogdanm	0:9b334a45a8ff	791	* @arg UART_IT_LBD: LIN Break detection interrupt
bogdanm	0:9b334a45a8ff	792	* @arg UART_IT_TXE: Transmit Data Register empty interrupt
bogdanm	0:9b334a45a8ff	793	* @arg UART_IT_TC: Transmission complete interrupt
bogdanm	0:9b334a45a8ff	794	* @arg UART_IT_RXNE: Receive Data register not empty interrupt
bogdanm	0:9b334a45a8ff	795	* @arg UART_IT_IDLE: Idle line detection interrupt
bogdanm	0:9b334a45a8ff	796	* @arg UART_IT_ORE: OverRun Error interrupt
bogdanm	0:9b334a45a8ff	797	* @arg UART_IT_NE: Noise Error interrupt
bogdanm	0:9b334a45a8ff	798	* @arg UART_IT_FE: Framing Error interrupt
bogdanm	0:9b334a45a8ff	799	* @arg UART_IT_PE: Parity Error interrupt
bogdanm	0:9b334a45a8ff	800	* @retval The new state of __IT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	801	*/
bogdanm	0:9b334a45a8ff	802	#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
bogdanm	0:9b334a45a8ff	803
bogdanm	0:9b334a45a8ff	804	/** @brief Check whether the specified UART interrupt source is enabled or not.
bogdanm	0:9b334a45a8ff	805	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	806	* @param __IT__: specifies the UART interrupt source to check.
bogdanm	0:9b334a45a8ff	807	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	808	* @arg UART_IT_WUF: Wakeup from stop mode interrupt
bogdanm	0:9b334a45a8ff	809	* @arg UART_IT_CM: Character match interrupt
bogdanm	0:9b334a45a8ff	810	* @arg UART_IT_CTS: CTS change interrupt
bogdanm	0:9b334a45a8ff	811	* @arg UART_IT_LBD: LIN Break detection interrupt
bogdanm	0:9b334a45a8ff	812	* @arg UART_IT_TXE: Transmit Data Register empty interrupt
bogdanm	0:9b334a45a8ff	813	* @arg UART_IT_TC: Transmission complete interrupt
bogdanm	0:9b334a45a8ff	814	* @arg UART_IT_RXNE: Receive Data register not empty interrupt
bogdanm	0:9b334a45a8ff	815	* @arg UART_IT_IDLE: Idle line detection interrupt
bogdanm	0:9b334a45a8ff	816	* @arg UART_IT_ORE: OverRun Error interrupt
bogdanm	0:9b334a45a8ff	817	* @arg UART_IT_NE: Noise Error interrupt
bogdanm	0:9b334a45a8ff	818	* @arg UART_IT_FE: Framing Error interrupt
bogdanm	0:9b334a45a8ff	819	* @arg UART_IT_PE: Parity Error interrupt
bogdanm	0:9b334a45a8ff	820	* @retval The new state of __IT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	821	*/
bogdanm	0:9b334a45a8ff	822	#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
bogdanm	0:9b334a45a8ff	823	(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
bogdanm	0:9b334a45a8ff	824
bogdanm	0:9b334a45a8ff	825	/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
bogdanm	0:9b334a45a8ff	826	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	827	* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
bogdanm	0:9b334a45a8ff	828	* to clear the corresponding interrupt
bogdanm	0:9b334a45a8ff	829	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	830	* @arg UART_CLEAR_PEF: Parity Error Clear Flag
bogdanm	0:9b334a45a8ff	831	* @arg UART_CLEAR_FEF: Framing Error Clear Flag
bogdanm	0:9b334a45a8ff	832	* @arg UART_CLEAR_NEF: Noise detected Clear Flag
bogdanm	0:9b334a45a8ff	833	* @arg UART_CLEAR_OREF: OverRun Error Clear Flag
bogdanm	0:9b334a45a8ff	834	* @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
bogdanm	0:9b334a45a8ff	835	* @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
bogdanm	0:9b334a45a8ff	836	* @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag
bogdanm	0:9b334a45a8ff	837	* @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
bogdanm	0:9b334a45a8ff	838	* @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
bogdanm	0:9b334a45a8ff	839	* @arg UART_CLEAR_EOBF: End Of Block Clear Flag
bogdanm	0:9b334a45a8ff	840	* @arg UART_CLEAR_CMF: Character Match Clear Flag
bogdanm	0:9b334a45a8ff	841	* @arg UART_CLEAR_WUF: Wake Up from stop mode Clear Flag
bogdanm	0:9b334a45a8ff	842	* @retval None
bogdanm	0:9b334a45a8ff	843	*/
bogdanm	0:9b334a45a8ff	844	#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
bogdanm	0:9b334a45a8ff	845
bogdanm	0:9b334a45a8ff	846	/** @brief Set a specific UART request flag.
bogdanm	0:9b334a45a8ff	847	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	848	* @param __REQ__: specifies the request flag to set
bogdanm	0:9b334a45a8ff	849	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	850	* @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
bogdanm	0:9b334a45a8ff	851	* @arg UART_SENDBREAK_REQUEST: Send Break Request
bogdanm	0:9b334a45a8ff	852	* @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
bogdanm	0:9b334a45a8ff	853	* @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
bogdanm	0:9b334a45a8ff	854	* @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
bogdanm	0:9b334a45a8ff	855	* @retval None
bogdanm	0:9b334a45a8ff	856	*/
bogdanm	0:9b334a45a8ff	857	#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR \|= (uint32_t)(__REQ__))
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	/** @brief Enable the UART one bit sample method.
bogdanm	0:9b334a45a8ff	860	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	861	* @retval None
bogdanm	0:9b334a45a8ff	862	*/
bogdanm	0:9b334a45a8ff	863	#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\|= USART_CR3_ONEBIT)
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	/** @brief Disable the UART one bit sample method.
bogdanm	0:9b334a45a8ff	866	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	867	* @retval None
bogdanm	0:9b334a45a8ff	868	*/
bogdanm	0:9b334a45a8ff	869	#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
bogdanm	0:9b334a45a8ff	870
bogdanm	0:9b334a45a8ff	871	/** @brief Enable UART.
bogdanm	0:9b334a45a8ff	872	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	873	* @retval None
bogdanm	0:9b334a45a8ff	874	*/
bogdanm	0:9b334a45a8ff	875	#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 \|= USART_CR1_UE)
bogdanm	0:9b334a45a8ff	876
bogdanm	0:9b334a45a8ff	877	/** @brief Disable UART.
bogdanm	0:9b334a45a8ff	878	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	879	* @retval None
bogdanm	0:9b334a45a8ff	880	*/
bogdanm	0:9b334a45a8ff	881	#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
bogdanm	0:9b334a45a8ff	882
bogdanm	0:9b334a45a8ff	883	/** @brief Enable CTS flow control.
bogdanm	0:9b334a45a8ff	884	* @note This macro allows to enable CTS hardware flow control for a given UART instance,
bogdanm	0:9b334a45a8ff	885	* without need to call HAL_UART_Init() function.
bogdanm	0:9b334a45a8ff	886	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
bogdanm	0:9b334a45a8ff	887	* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
bogdanm	0:9b334a45a8ff	888	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
bogdanm	0:9b334a45a8ff	889	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
bogdanm	0:9b334a45a8ff	890	* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
bogdanm	0:9b334a45a8ff	891	* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
bogdanm	0:9b334a45a8ff	892	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	893	* @retval None
bogdanm	0:9b334a45a8ff	894	*/
bogdanm	0:9b334a45a8ff	895	#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	896	do{ \
bogdanm	0:9b334a45a8ff	897	SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
bogdanm	0:9b334a45a8ff	898	(__HANDLE__)->Init.HwFlowCtl \|= USART_CR3_CTSE; \
bogdanm	0:9b334a45a8ff	899	} while(0)
bogdanm	0:9b334a45a8ff	900
bogdanm	0:9b334a45a8ff	901	/** @brief Disable CTS flow control.
bogdanm	0:9b334a45a8ff	902	* @note This macro allows to disable CTS hardware flow control for a given UART instance,
bogdanm	0:9b334a45a8ff	903	* without need to call HAL_UART_Init() function.
bogdanm	0:9b334a45a8ff	904	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
bogdanm	0:9b334a45a8ff	905	* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
bogdanm	0:9b334a45a8ff	906	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
bogdanm	0:9b334a45a8ff	907	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
bogdanm	0:9b334a45a8ff	908	* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
bogdanm	0:9b334a45a8ff	909	* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
bogdanm	0:9b334a45a8ff	910	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	911	* @retval None
bogdanm	0:9b334a45a8ff	912	*/
bogdanm	0:9b334a45a8ff	913	#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	914	do{ \
bogdanm	0:9b334a45a8ff	915	CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
bogdanm	0:9b334a45a8ff	916	(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
bogdanm	0:9b334a45a8ff	917	} while(0)
bogdanm	0:9b334a45a8ff	918
bogdanm	0:9b334a45a8ff	919	/** @brief Enable RTS flow control.
bogdanm	0:9b334a45a8ff	920	* @note This macro allows to enable RTS hardware flow control for a given UART instance,
bogdanm	0:9b334a45a8ff	921	* without need to call HAL_UART_Init() function.
bogdanm	0:9b334a45a8ff	922	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
bogdanm	0:9b334a45a8ff	923	* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
bogdanm	0:9b334a45a8ff	924	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
bogdanm	0:9b334a45a8ff	925	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
bogdanm	0:9b334a45a8ff	926	* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
bogdanm	0:9b334a45a8ff	927	* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
bogdanm	0:9b334a45a8ff	928	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	929	* @retval None
bogdanm	0:9b334a45a8ff	930	*/
bogdanm	0:9b334a45a8ff	931	#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	932	do{ \
bogdanm	0:9b334a45a8ff	933	SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
bogdanm	0:9b334a45a8ff	934	(__HANDLE__)->Init.HwFlowCtl \|= USART_CR3_RTSE; \
bogdanm	0:9b334a45a8ff	935	} while(0)
bogdanm	0:9b334a45a8ff	936
bogdanm	0:9b334a45a8ff	937	/** @brief Disable RTS flow control.
bogdanm	0:9b334a45a8ff	938	* @note This macro allows to disable RTS hardware flow control for a given UART instance,
bogdanm	0:9b334a45a8ff	939	* without need to call HAL_UART_Init() function.
bogdanm	0:9b334a45a8ff	940	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
bogdanm	0:9b334a45a8ff	941	* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
bogdanm	0:9b334a45a8ff	942	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
bogdanm	0:9b334a45a8ff	943	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
bogdanm	0:9b334a45a8ff	944	* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
bogdanm	0:9b334a45a8ff	945	* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
bogdanm	0:9b334a45a8ff	946	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	947	* @retval None
bogdanm	0:9b334a45a8ff	948	*/
bogdanm	0:9b334a45a8ff	949	#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
bogdanm	0:9b334a45a8ff	950	do{ \
bogdanm	0:9b334a45a8ff	951	CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
bogdanm	0:9b334a45a8ff	952	(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
bogdanm	0:9b334a45a8ff	953	} while(0)
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	/**
bogdanm	0:9b334a45a8ff	956	* @}
bogdanm	0:9b334a45a8ff	957	*/
bogdanm	0:9b334a45a8ff	958
bogdanm	0:9b334a45a8ff	959	/* Private macros --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	960	/** @defgroup UART_Private_Macros UART Private Macros
bogdanm	0:9b334a45a8ff	961	* @{
bogdanm	0:9b334a45a8ff	962	*/
bogdanm	0:9b334a45a8ff	963	/** @brief BRR division operation to set BRR register with LPUART.
bogdanm	0:9b334a45a8ff	964	* @param __PCLK__: LPUART clock.
bogdanm	0:9b334a45a8ff	965	* @param __BAUD__: Baud rate set by the user.
bogdanm	0:9b334a45a8ff	966	* @retval Division result
bogdanm	0:9b334a45a8ff	967	*/
bogdanm	0:9b334a45a8ff	968	#define UART_DIV_LPUART(__PCLK__, __BAUD__) (((uint64_t)(__PCLK__)*256)/((__BAUD__)))
bogdanm	0:9b334a45a8ff	969
bogdanm	0:9b334a45a8ff	970	/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
bogdanm	0:9b334a45a8ff	971	* @param __PCLK__: UART clock.
bogdanm	0:9b334a45a8ff	972	* @param __BAUD__: Baud rate set by the user.
bogdanm	0:9b334a45a8ff	973	* @retval Division result
bogdanm	0:9b334a45a8ff	974	*/
bogdanm	0:9b334a45a8ff	975	#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) (((__PCLK__)*2)/((__BAUD__)))
bogdanm	0:9b334a45a8ff	976
bogdanm	0:9b334a45a8ff	977	/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
bogdanm	0:9b334a45a8ff	978	* @param __PCLK__: UART clock.
bogdanm	0:9b334a45a8ff	979	* @param __BAUD__: Baud rate set by the user.
bogdanm	0:9b334a45a8ff	980	* @retval Division result
bogdanm	0:9b334a45a8ff	981	*/
bogdanm	0:9b334a45a8ff	982	#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__))/((__BAUD__)))
bogdanm	0:9b334a45a8ff	983
bogdanm	0:9b334a45a8ff	984	/** @brief Check whether or not UART instance is Low Power UART.
bogdanm	0:9b334a45a8ff	985	* @param __HANDLE__: specifies the UART Handle.
bogdanm	0:9b334a45a8ff	986	* @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
bogdanm	0:9b334a45a8ff	987	*/
bogdanm	0:9b334a45a8ff	988	#define UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )
bogdanm	0:9b334a45a8ff	989
bogdanm	0:9b334a45a8ff	990	/** @brief Check UART Baud rate.
bogdanm	0:9b334a45a8ff	991	* @param __BAUDRATE__: Baudrate specified by the user.
bogdanm	0:9b334a45a8ff	992	* The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz)
bogdanm	0:9b334a45a8ff	993	* divided by the smallest oversampling used on the USART (i.e. 8)
bogdanm	0:9b334a45a8ff	994	* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
bogdanm	0:9b334a45a8ff	995	*/
bogdanm	0:9b334a45a8ff	996	#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001)
bogdanm	0:9b334a45a8ff	997
bogdanm	0:9b334a45a8ff	998	/** @brief Check UART assertion time.
bogdanm	0:9b334a45a8ff	999	* @param __TIME__: 5-bit value assertion time.
bogdanm	0:9b334a45a8ff	1000	* @retval Test result (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1001	*/
bogdanm	0:9b334a45a8ff	1002	#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
bogdanm	0:9b334a45a8ff	1003
bogdanm	0:9b334a45a8ff	1004	/** @brief Check UART deassertion time.
bogdanm	0:9b334a45a8ff	1005	* @param __TIME__: 5-bit value deassertion time.
bogdanm	0:9b334a45a8ff	1006	* @retval Test result (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1007	*/
bogdanm	0:9b334a45a8ff	1008	#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
bogdanm	0:9b334a45a8ff	1009
bogdanm	0:9b334a45a8ff	1010	/**
bogdanm	0:9b334a45a8ff	1011	* @brief Ensure that UART frame number of stop bits is valid.
bogdanm	0:9b334a45a8ff	1012	* @param __STOPBITS__: UART frame number of stop bits.
bogdanm	0:9b334a45a8ff	1013	* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
bogdanm	0:9b334a45a8ff	1014	*/
bogdanm	0:9b334a45a8ff	1015	#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) \|\| \
bogdanm	0:9b334a45a8ff	1016	((__STOPBITS__) == UART_STOPBITS_2) \|\| \
bogdanm	0:9b334a45a8ff	1017	((__STOPBITS__) == UART_STOPBITS_1_5))
bogdanm	0:9b334a45a8ff	1018
bogdanm	0:9b334a45a8ff	1019	/**
bogdanm	0:9b334a45a8ff	1020	* @brief Ensure that UART frame parity is valid.
bogdanm	0:9b334a45a8ff	1021	* @param __PARITY__: UART frame parity.
bogdanm	0:9b334a45a8ff	1022	* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
bogdanm	0:9b334a45a8ff	1023	*/
bogdanm	0:9b334a45a8ff	1024	#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1025	((__PARITY__) == UART_PARITY_EVEN) \|\| \
bogdanm	0:9b334a45a8ff	1026	((__PARITY__) == UART_PARITY_ODD))
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	/**
bogdanm	0:9b334a45a8ff	1029	* @brief Ensure that UART hardware flow control is valid.
bogdanm	0:9b334a45a8ff	1030	* @param __CONTROL__: UART hardware flow control.
bogdanm	0:9b334a45a8ff	1031	* @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
bogdanm	0:9b334a45a8ff	1032	*/
bogdanm	0:9b334a45a8ff	1033	#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
bogdanm	0:9b334a45a8ff	1034	(((__CONTROL__) == UART_HWCONTROL_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1035	((__CONTROL__) == UART_HWCONTROL_RTS) \|\| \
bogdanm	0:9b334a45a8ff	1036	((__CONTROL__) == UART_HWCONTROL_CTS) \|\| \
bogdanm	0:9b334a45a8ff	1037	((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039	/**
bogdanm	0:9b334a45a8ff	1040	* @brief Ensure that UART communication mode is valid.
bogdanm	0:9b334a45a8ff	1041	* @param __MODE__: UART communication mode.
bogdanm	0:9b334a45a8ff	1042	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
bogdanm	0:9b334a45a8ff	1043	*/
bogdanm	0:9b334a45a8ff	1044	#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
bogdanm	0:9b334a45a8ff	1045
bogdanm	0:9b334a45a8ff	1046	/**
bogdanm	0:9b334a45a8ff	1047	* @brief Ensure that UART state is valid.
bogdanm	0:9b334a45a8ff	1048	* @param __STATE__: UART state.
bogdanm	0:9b334a45a8ff	1049	* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
bogdanm	0:9b334a45a8ff	1050	*/
bogdanm	0:9b334a45a8ff	1051	#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1052	((__STATE__) == UART_STATE_ENABLE))
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	/**
bogdanm	0:9b334a45a8ff	1055	* @brief Ensure that UART oversampling is valid.
bogdanm	0:9b334a45a8ff	1056	* @param __SAMPLING__: UART oversampling.
bogdanm	0:9b334a45a8ff	1057	* @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
bogdanm	0:9b334a45a8ff	1058	*/
bogdanm	0:9b334a45a8ff	1059	#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) \|\| \
bogdanm	0:9b334a45a8ff	1060	((__SAMPLING__) == UART_OVERSAMPLING_8))
bogdanm	0:9b334a45a8ff	1061
bogdanm	0:9b334a45a8ff	1062	/**
bogdanm	0:9b334a45a8ff	1063	* @brief Ensure that UART frame sampling is valid.
bogdanm	0:9b334a45a8ff	1064	* @param __ONEBIT__: UART frame sampling.
bogdanm	0:9b334a45a8ff	1065	* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
bogdanm	0:9b334a45a8ff	1066	*/
bogdanm	0:9b334a45a8ff	1067	#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1068	((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
bogdanm	0:9b334a45a8ff	1069
bogdanm	0:9b334a45a8ff	1070	/**
bogdanm	0:9b334a45a8ff	1071	* @brief Ensure that UART auto Baud rate detection mode is valid.
bogdanm	0:9b334a45a8ff	1072	* @param __MODE__: UART auto Baud rate detection mode.
bogdanm	0:9b334a45a8ff	1073	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
bogdanm	0:9b334a45a8ff	1074	*/
bogdanm	0:9b334a45a8ff	1075	#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) \|\| \
bogdanm	0:9b334a45a8ff	1076	((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) \|\| \
bogdanm	0:9b334a45a8ff	1077	((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) \|\| \
bogdanm	0:9b334a45a8ff	1078	((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
bogdanm	0:9b334a45a8ff	1079
bogdanm	0:9b334a45a8ff	1080	/**
bogdanm	0:9b334a45a8ff	1081	* @brief Ensure that UART receiver timeout setting is valid.
bogdanm	0:9b334a45a8ff	1082	* @param __TIMEOUT__: UART receiver timeout setting.
bogdanm	0:9b334a45a8ff	1083	* @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
bogdanm	0:9b334a45a8ff	1084	*/
bogdanm	0:9b334a45a8ff	1085	#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1086	((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088	/**
bogdanm	0:9b334a45a8ff	1089	* @brief Ensure that UART LIN state is valid.
bogdanm	0:9b334a45a8ff	1090	* @param __LIN__: UART LIN state.
bogdanm	0:9b334a45a8ff	1091	* @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
bogdanm	0:9b334a45a8ff	1092	*/
bogdanm	0:9b334a45a8ff	1093	#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1094	((__LIN__) == UART_LIN_ENABLE))
bogdanm	0:9b334a45a8ff	1095
bogdanm	0:9b334a45a8ff	1096	/**
bogdanm	0:9b334a45a8ff	1097	* @brief Ensure that UART LIN break detection length is valid.
bogdanm	0:9b334a45a8ff	1098	* @param __LENGTH__: UART LIN break detection length.
bogdanm	0:9b334a45a8ff	1099	* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
bogdanm	0:9b334a45a8ff	1100	*/
bogdanm	0:9b334a45a8ff	1101	#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) \|\| \
bogdanm	0:9b334a45a8ff	1102	((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
bogdanm	0:9b334a45a8ff	1103
bogdanm	0:9b334a45a8ff	1104	/**
bogdanm	0:9b334a45a8ff	1105	* @brief Ensure that UART DMA TX state is valid.
bogdanm	0:9b334a45a8ff	1106	* @param __DMATX__: UART DMA TX state.
bogdanm	0:9b334a45a8ff	1107	* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
bogdanm	0:9b334a45a8ff	1108	*/
bogdanm	0:9b334a45a8ff	1109	#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1110	((__DMATX__) == UART_DMA_TX_ENABLE))
bogdanm	0:9b334a45a8ff	1111
bogdanm	0:9b334a45a8ff	1112	/**
bogdanm	0:9b334a45a8ff	1113	* @brief Ensure that UART DMA RX state is valid.
bogdanm	0:9b334a45a8ff	1114	* @param __DMARX__: UART DMA RX state.
bogdanm	0:9b334a45a8ff	1115	* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
bogdanm	0:9b334a45a8ff	1116	*/
bogdanm	0:9b334a45a8ff	1117	#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1118	((__DMARX__) == UART_DMA_RX_ENABLE))
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	/**
bogdanm	0:9b334a45a8ff	1121	* @brief Ensure that UART half-duplex state is valid.
bogdanm	0:9b334a45a8ff	1122	* @param __HDSEL__: UART half-duplex state.
bogdanm	0:9b334a45a8ff	1123	* @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
bogdanm	0:9b334a45a8ff	1124	*/
bogdanm	0:9b334a45a8ff	1125	#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1126	((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
bogdanm	0:9b334a45a8ff	1127
bogdanm	0:9b334a45a8ff	1128	/**
bogdanm	0:9b334a45a8ff	1129	* @brief Ensure that UART wake-up method is valid.
bogdanm	0:9b334a45a8ff	1130	* @param __WAKEUP__: UART wake-up method .
bogdanm	0:9b334a45a8ff	1131	* @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
bogdanm	0:9b334a45a8ff	1132	*/
bogdanm	0:9b334a45a8ff	1133	#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) \|\| \
bogdanm	0:9b334a45a8ff	1134	((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
bogdanm	0:9b334a45a8ff	1135
bogdanm	0:9b334a45a8ff	1136	/**
bogdanm	0:9b334a45a8ff	1137	* @brief Ensure that UART request parameter is valid.
bogdanm	0:9b334a45a8ff	1138	* @param __PARAM__: UART request parameter.
bogdanm	0:9b334a45a8ff	1139	* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
bogdanm	0:9b334a45a8ff	1140	*/
bogdanm	0:9b334a45a8ff	1141	#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) \|\| \
bogdanm	0:9b334a45a8ff	1142	((__PARAM__) == UART_SENDBREAK_REQUEST) \|\| \
bogdanm	0:9b334a45a8ff	1143	((__PARAM__) == UART_MUTE_MODE_REQUEST) \|\| \
bogdanm	0:9b334a45a8ff	1144	((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) \|\| \
bogdanm	0:9b334a45a8ff	1145	((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
bogdanm	0:9b334a45a8ff	1146
bogdanm	0:9b334a45a8ff	1147	/**
bogdanm	0:9b334a45a8ff	1148	* @brief Ensure that UART advanced features initialization is valid.
bogdanm	0:9b334a45a8ff	1149	* @param __INIT__: UART advanced features initialization.
bogdanm	0:9b334a45a8ff	1150	* @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
bogdanm	0:9b334a45a8ff	1151	*/
bogdanm	0:9b334a45a8ff	1152	#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT \| \
bogdanm	0:9b334a45a8ff	1153	UART_ADVFEATURE_TXINVERT_INIT \| \
bogdanm	0:9b334a45a8ff	1154	UART_ADVFEATURE_RXINVERT_INIT \| \
bogdanm	0:9b334a45a8ff	1155	UART_ADVFEATURE_DATAINVERT_INIT \| \
bogdanm	0:9b334a45a8ff	1156	UART_ADVFEATURE_SWAP_INIT \| \
bogdanm	0:9b334a45a8ff	1157	UART_ADVFEATURE_RXOVERRUNDISABLE_INIT \| \
bogdanm	0:9b334a45a8ff	1158	UART_ADVFEATURE_DMADISABLEONERROR_INIT \| \
bogdanm	0:9b334a45a8ff	1159	UART_ADVFEATURE_AUTOBAUDRATE_INIT \| \
bogdanm	0:9b334a45a8ff	1160	UART_ADVFEATURE_MSBFIRST_INIT))
bogdanm	0:9b334a45a8ff	1161
bogdanm	0:9b334a45a8ff	1162	/**
bogdanm	0:9b334a45a8ff	1163	* @brief Ensure that UART frame TX inversion setting is valid.
bogdanm	0:9b334a45a8ff	1164	* @param __TXINV__: UART frame TX inversion setting.
bogdanm	0:9b334a45a8ff	1165	* @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
bogdanm	0:9b334a45a8ff	1166	*/
bogdanm	0:9b334a45a8ff	1167	#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1168	((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
bogdanm	0:9b334a45a8ff	1169
bogdanm	0:9b334a45a8ff	1170	/**
bogdanm	0:9b334a45a8ff	1171	* @brief Ensure that UART frame RX inversion setting is valid.
bogdanm	0:9b334a45a8ff	1172	* @param __RXINV__: UART frame RX inversion setting.
bogdanm	0:9b334a45a8ff	1173	* @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
bogdanm	0:9b334a45a8ff	1174	*/
bogdanm	0:9b334a45a8ff	1175	#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1176	((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
bogdanm	0:9b334a45a8ff	1177
bogdanm	0:9b334a45a8ff	1178	/**
bogdanm	0:9b334a45a8ff	1179	* @brief Ensure that UART frame data inversion setting is valid.
bogdanm	0:9b334a45a8ff	1180	* @param __DATAINV__: UART frame data inversion setting.
bogdanm	0:9b334a45a8ff	1181	* @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
bogdanm	0:9b334a45a8ff	1182	*/
bogdanm	0:9b334a45a8ff	1183	#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1184	((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
bogdanm	0:9b334a45a8ff	1185
bogdanm	0:9b334a45a8ff	1186	/**
bogdanm	0:9b334a45a8ff	1187	* @brief Ensure that UART frame RX/TX pins swap setting is valid.
bogdanm	0:9b334a45a8ff	1188	* @param __SWAP__: UART frame RX/TX pins swap setting.
bogdanm	0:9b334a45a8ff	1189	* @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
bogdanm	0:9b334a45a8ff	1190	*/
bogdanm	0:9b334a45a8ff	1191	#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1192	((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	/**
bogdanm	0:9b334a45a8ff	1195	* @brief Ensure that UART frame overrun setting is valid.
bogdanm	0:9b334a45a8ff	1196	* @param __OVERRUN__: UART frame overrun setting.
bogdanm	0:9b334a45a8ff	1197	* @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
bogdanm	0:9b334a45a8ff	1198	*/
bogdanm	0:9b334a45a8ff	1199	#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1200	((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
bogdanm	0:9b334a45a8ff	1201
bogdanm	0:9b334a45a8ff	1202	/**
bogdanm	0:9b334a45a8ff	1203	* @brief Ensure that UART auto Baud rate state is valid.
bogdanm	0:9b334a45a8ff	1204	* @param __AUTOBAUDRATE__: UART auto Baud rate state.
bogdanm	0:9b334a45a8ff	1205	* @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
bogdanm	0:9b334a45a8ff	1206	*/
bogdanm	0:9b334a45a8ff	1207	#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1208	((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
bogdanm	0:9b334a45a8ff	1209
bogdanm	0:9b334a45a8ff	1210	/**
bogdanm	0:9b334a45a8ff	1211	* @brief Ensure that UART DMA enabling or disabling on error setting is valid.
bogdanm	0:9b334a45a8ff	1212	* @param __DMA__: UART DMA enabling or disabling on error setting.
bogdanm	0:9b334a45a8ff	1213	* @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
bogdanm	0:9b334a45a8ff	1214	*/
bogdanm	0:9b334a45a8ff	1215	#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) \|\| \
bogdanm	0:9b334a45a8ff	1216	((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
bogdanm	0:9b334a45a8ff	1217
bogdanm	0:9b334a45a8ff	1218	/**
bogdanm	0:9b334a45a8ff	1219	* @brief Ensure that UART frame MSB first setting is valid.
bogdanm	0:9b334a45a8ff	1220	* @param __MSBFIRST__: UART frame MSB first setting.
bogdanm	0:9b334a45a8ff	1221	* @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
bogdanm	0:9b334a45a8ff	1222	*/
bogdanm	0:9b334a45a8ff	1223	#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1224	((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
bogdanm	0:9b334a45a8ff	1225
bogdanm	0:9b334a45a8ff	1226	/**
bogdanm	0:9b334a45a8ff	1227	* @brief Ensure that UART stop mode state is valid.
bogdanm	0:9b334a45a8ff	1228	* @param __STOPMODE__: UART stop mode state.
bogdanm	0:9b334a45a8ff	1229	* @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
bogdanm	0:9b334a45a8ff	1230	*/
bogdanm	0:9b334a45a8ff	1231	#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1232	((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	/**
bogdanm	0:9b334a45a8ff	1235	* @brief Ensure that UART mute mode state is valid.
bogdanm	0:9b334a45a8ff	1236	* @param __MUTE__: UART mute mode state.
bogdanm	0:9b334a45a8ff	1237	* @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
bogdanm	0:9b334a45a8ff	1238	*/
bogdanm	0:9b334a45a8ff	1239	#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1240	((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
bogdanm	0:9b334a45a8ff	1241
bogdanm	0:9b334a45a8ff	1242	/**
bogdanm	0:9b334a45a8ff	1243	* @brief Ensure that UART wake-up selection is valid.
bogdanm	0:9b334a45a8ff	1244	* @param __WAKE__: UART wake-up selection.
bogdanm	0:9b334a45a8ff	1245	* @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
bogdanm	0:9b334a45a8ff	1246	*/
bogdanm	0:9b334a45a8ff	1247	#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) \|\| \
bogdanm	0:9b334a45a8ff	1248	((__WAKE__) == UART_WAKEUP_ON_STARTBIT) \|\| \
bogdanm	0:9b334a45a8ff	1249	((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
bogdanm	0:9b334a45a8ff	1250
bogdanm	0:9b334a45a8ff	1251	/**
bogdanm	0:9b334a45a8ff	1252	* @brief Ensure that UART driver enable polarity is valid.
bogdanm	0:9b334a45a8ff	1253	* @param __POLARITY__: UART driver enable polarity.
bogdanm	0:9b334a45a8ff	1254	* @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
bogdanm	0:9b334a45a8ff	1255	*/
bogdanm	0:9b334a45a8ff	1256	#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	1257	((__POLARITY__) == UART_DE_POLARITY_LOW))
bogdanm	0:9b334a45a8ff	1258
bogdanm	0:9b334a45a8ff	1259	/**
bogdanm	0:9b334a45a8ff	1260	* @brief Ensure that LPUART frame number of stop bits is valid.
bogdanm	0:9b334a45a8ff	1261	* @param __STOPBITS__: LPUART frame number of stop bits.
bogdanm	0:9b334a45a8ff	1262	* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
bogdanm	0:9b334a45a8ff	1263	*/
bogdanm	0:9b334a45a8ff	1264	#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) \|\| \
bogdanm	0:9b334a45a8ff	1265	((__STOPBITS__) == UART_STOPBITS_2))
bogdanm	0:9b334a45a8ff	1266
bogdanm	0:9b334a45a8ff	1267	/**
bogdanm	0:9b334a45a8ff	1268	* @}
bogdanm	0:9b334a45a8ff	1269	*/
bogdanm	0:9b334a45a8ff	1270
bogdanm	0:9b334a45a8ff	1271	/* Include UART HAL Extended module */
bogdanm	0:9b334a45a8ff	1272	#include "stm32l4xx_hal_uart_ex.h"
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1275	/** @addtogroup UART_Exported_Functions UART Exported Functions
bogdanm	0:9b334a45a8ff	1276	* @{
bogdanm	0:9b334a45a8ff	1277	*/
bogdanm	0:9b334a45a8ff	1278
bogdanm	0:9b334a45a8ff	1279	/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	1280	* @{
bogdanm	0:9b334a45a8ff	1281	*/
bogdanm	0:9b334a45a8ff	1282
bogdanm	0:9b334a45a8ff	1283	/* Initialization and de-initialization functions ****************************/
bogdanm	0:9b334a45a8ff	1284	HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1285	HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1286	HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
bogdanm	0:9b334a45a8ff	1287	HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
bogdanm	0:9b334a45a8ff	1288	HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1289	void HAL_UART_MspInit(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1290	void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	/**
bogdanm	0:9b334a45a8ff	1293	* @}
bogdanm	0:9b334a45a8ff	1294	*/
bogdanm	0:9b334a45a8ff	1295
bogdanm	0:9b334a45a8ff	1296	/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	1297	* @{
bogdanm	0:9b334a45a8ff	1298	*/
bogdanm	0:9b334a45a8ff	1299
bogdanm	0:9b334a45a8ff	1300	/* IO operation functions *****************************************************/
bogdanm	0:9b334a45a8ff	1301	HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	1302	HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	1303	HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
bogdanm	0:9b334a45a8ff	1304	HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
bogdanm	0:9b334a45a8ff	1305	HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
bogdanm	0:9b334a45a8ff	1306	HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
bogdanm	0:9b334a45a8ff	1307	HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1308	HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1309	HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1310	void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1311	void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1312	void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1313	void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1314	void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1315	void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1316
bogdanm	0:9b334a45a8ff	1317	/**
bogdanm	0:9b334a45a8ff	1318	* @}
bogdanm	0:9b334a45a8ff	1319	*/
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1322	* @{
bogdanm	0:9b334a45a8ff	1323	*/
bogdanm	0:9b334a45a8ff	1324
bogdanm	0:9b334a45a8ff	1325	/* Peripheral Control functions ************************************************/
bogdanm	0:9b334a45a8ff	1326	HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1327	HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1328	HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1329	void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1330	HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1331	HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333	/**
bogdanm	0:9b334a45a8ff	1334	* @}
bogdanm	0:9b334a45a8ff	1335	*/
bogdanm	0:9b334a45a8ff	1336
bogdanm	0:9b334a45a8ff	1337	/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
bogdanm	0:9b334a45a8ff	1338	* @{
bogdanm	0:9b334a45a8ff	1339	*/
bogdanm	0:9b334a45a8ff	1340
bogdanm	0:9b334a45a8ff	1341	/* Peripheral State and Errors functions **************************************************/
bogdanm	0:9b334a45a8ff	1342	HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1343	uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	/**
bogdanm	0:9b334a45a8ff	1346	* @}
bogdanm	0:9b334a45a8ff	1347	*/
bogdanm	0:9b334a45a8ff	1348
bogdanm	0:9b334a45a8ff	1349	/**
bogdanm	0:9b334a45a8ff	1350	* @}
bogdanm	0:9b334a45a8ff	1351	*/
bogdanm	0:9b334a45a8ff	1352
bogdanm	0:9b334a45a8ff	1353	/* Private functions -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1354	/** @addtogroup UART_Private_Functions UART Private Functions
bogdanm	0:9b334a45a8ff	1355	* @{
bogdanm	0:9b334a45a8ff	1356	*/
bogdanm	0:9b334a45a8ff	1357
bogdanm	0:9b334a45a8ff	1358	HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1359	HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1360	HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	1361	void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
bogdanm	0:9b334a45a8ff	1362
bogdanm	0:9b334a45a8ff	1363	/**
bogdanm	0:9b334a45a8ff	1364	* @}
bogdanm	0:9b334a45a8ff	1365	*/
bogdanm	0:9b334a45a8ff	1366
bogdanm	0:9b334a45a8ff	1367	/**
bogdanm	0:9b334a45a8ff	1368	* @}
bogdanm	0:9b334a45a8ff	1369	*/
bogdanm	0:9b334a45a8ff	1370
bogdanm	0:9b334a45a8ff	1371	/**
bogdanm	0:9b334a45a8ff	1372	* @}
bogdanm	0:9b334a45a8ff	1373	*/
bogdanm	0:9b334a45a8ff	1374
bogdanm	0:9b334a45a8ff	1375	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1376	}
bogdanm	0:9b334a45a8ff	1377	#endif
bogdanm	0:9b334a45a8ff	1378
bogdanm	0:9b334a45a8ff	1379	#endif /* __STM32L4xx_HAL_UART_H */
bogdanm	0:9b334a45a8ff	1380
bogdanm	0:9b334a45a8ff	1381	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_uart.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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