fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l4xx_hal_flash.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief Header file of FLASH HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32L4xx_HAL_FLASH_H
bogdanm 0:9b334a45a8ff 40 #define __STM32L4xx_HAL_FLASH_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32l4xx_hal_def.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32L4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @addtogroup FLASH
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Exported types ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58 /** @defgroup FLASH_Exported_Types FLASH Exported Types
bogdanm 0:9b334a45a8ff 59 * @{
bogdanm 0:9b334a45a8ff 60 */
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 /**
bogdanm 0:9b334a45a8ff 63 * @brief FLASH Erase structure definition
bogdanm 0:9b334a45a8ff 64 */
bogdanm 0:9b334a45a8ff 65 typedef struct
bogdanm 0:9b334a45a8ff 66 {
bogdanm 0:9b334a45a8ff 67 uint32_t TypeErase; /*!< Mass erase or page erase.
bogdanm 0:9b334a45a8ff 68 This parameter can be a value of @ref FLASH_Type_Erase */
bogdanm 0:9b334a45a8ff 69 uint32_t Banks; /*!< Select bank to erase.
bogdanm 0:9b334a45a8ff 70 This parameter must be a value of @ref FLASH_Banks
bogdanm 0:9b334a45a8ff 71 (FLASH_BANK_BOTH should be used only for mass erase) */
bogdanm 0:9b334a45a8ff 72 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled
bogdanm 0:9b334a45a8ff 73 This parameter must be a value between 0 and (max number of pages in the bank - 1)
bogdanm 0:9b334a45a8ff 74 (eg : 255 for 1MB dual bank) */
bogdanm 0:9b334a45a8ff 75 uint32_t NbPages; /*!< Number of pages to be erased.
bogdanm 0:9b334a45a8ff 76 This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
bogdanm 0:9b334a45a8ff 77 } FLASH_EraseInitTypeDef;
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 /**
bogdanm 0:9b334a45a8ff 80 * @brief FLASH Option Bytes Program structure definition
bogdanm 0:9b334a45a8ff 81 */
bogdanm 0:9b334a45a8ff 82 typedef struct
bogdanm 0:9b334a45a8ff 83 {
bogdanm 0:9b334a45a8ff 84 uint32_t OptionType; /*!< Option byte to be configured.
bogdanm 0:9b334a45a8ff 85 This parameter can be a combination of the values of @ref FLASH_OB_Type */
bogdanm 0:9b334a45a8ff 86 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
bogdanm 0:9b334a45a8ff 87 Only one WRP area could be programmed at the same time.
bogdanm 0:9b334a45a8ff 88 This parameter can be value of @ref FLASH_OB_WRP_Area */
bogdanm 0:9b334a45a8ff 89 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
bogdanm 0:9b334a45a8ff 90 This parameter must be a value between 0 and (max number of pages in the bank - 1)
bogdanm 0:9b334a45a8ff 91 (eg : 25 for 1MB dual bank) */
bogdanm 0:9b334a45a8ff 92 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
bogdanm 0:9b334a45a8ff 93 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
bogdanm 0:9b334a45a8ff 94 uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
bogdanm 0:9b334a45a8ff 95 This parameter can be a value of @ref FLASH_OB_Read_Protection */
bogdanm 0:9b334a45a8ff 96 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
bogdanm 0:9b334a45a8ff 97 This parameter can be a combination of @ref FLASH_OB_USER_Type */
bogdanm 0:9b334a45a8ff 98 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
bogdanm 0:9b334a45a8ff 99 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
bogdanm 0:9b334a45a8ff 100 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
bogdanm 0:9b334a45a8ff 101 @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
bogdanm 0:9b334a45a8ff 102 @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
bogdanm 0:9b334a45a8ff 103 @ref FLASH_OB_USER_BFB2, @ref IS_OB_USER_DUALBANK,
bogdanm 0:9b334a45a8ff 104 @ref IS_OB_USER_BOOT1, @ref FLASH_OB_USER_SRAM2_PE and
bogdanm 0:9b334a45a8ff 105 @ref FLASH_OB_USER_SRAM2_RST */
bogdanm 0:9b334a45a8ff 106 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
bogdanm 0:9b334a45a8ff 107 This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
bogdanm 0:9b334a45a8ff 108 and @ref FLASH_OB_PCROP_RDP */
bogdanm 0:9b334a45a8ff 109 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
bogdanm 0:9b334a45a8ff 110 This parameter must be a value between begin and end of bank
bogdanm 0:9b334a45a8ff 111 => Be careful of the bank swapping for the address */
bogdanm 0:9b334a45a8ff 112 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
bogdanm 0:9b334a45a8ff 113 This parameter must be a value between PCROP Start address and end of bank */
bogdanm 0:9b334a45a8ff 114 } FLASH_OBProgramInitTypeDef;
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /**
bogdanm 0:9b334a45a8ff 117 * @brief FLASH Procedure structure definition
bogdanm 0:9b334a45a8ff 118 */
bogdanm 0:9b334a45a8ff 119 typedef enum
bogdanm 0:9b334a45a8ff 120 {
bogdanm 0:9b334a45a8ff 121 FLASH_PROC_NONE = 0,
bogdanm 0:9b334a45a8ff 122 FLASH_PROC_PAGE_ERASE,
bogdanm 0:9b334a45a8ff 123 FLASH_PROC_MASS_ERASE,
bogdanm 0:9b334a45a8ff 124 FLASH_PROC_PROGRAM,
bogdanm 0:9b334a45a8ff 125 FLASH_PROC_PROGRAM_LAST
bogdanm 0:9b334a45a8ff 126 } FLASH_ProcedureTypeDef;
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /**
bogdanm 0:9b334a45a8ff 129 * @brief FLASH handle Structure definition
bogdanm 0:9b334a45a8ff 130 */
bogdanm 0:9b334a45a8ff 131 typedef struct
bogdanm 0:9b334a45a8ff 132 {
bogdanm 0:9b334a45a8ff 133 HAL_LockTypeDef Lock; /* FLASH locking object */
bogdanm 0:9b334a45a8ff 134 __IO uint32_t ErrorCode; /* FLASH error code */
bogdanm 0:9b334a45a8ff 135 __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
bogdanm 0:9b334a45a8ff 136 __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */
bogdanm 0:9b334a45a8ff 137 __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */
bogdanm 0:9b334a45a8ff 138 __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
bogdanm 0:9b334a45a8ff 139 __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
bogdanm 0:9b334a45a8ff 140 }FLASH_ProcessTypeDef;
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /**
bogdanm 0:9b334a45a8ff 143 * @}
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 147 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
bogdanm 0:9b334a45a8ff 148 * @{
bogdanm 0:9b334a45a8ff 149 */
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 /** @defgroup FLASH_Error FLASH Error
bogdanm 0:9b334a45a8ff 152 * @{
bogdanm 0:9b334a45a8ff 153 */
bogdanm 0:9b334a45a8ff 154 #define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 155 #define HAL_FLASH_ERROR_OP ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 156 #define HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 157 #define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 158 #define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 159 #define HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 160 #define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 161 #define HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 162 #define HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 163 #define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 164 #define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 165 #define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 166 /**
bogdanm 0:9b334a45a8ff 167 * @}
bogdanm 0:9b334a45a8ff 168 */
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /** @defgroup FLASH_Type_Erase FLASH Erase Type
bogdanm 0:9b334a45a8ff 171 * @{
bogdanm 0:9b334a45a8ff 172 */
bogdanm 0:9b334a45a8ff 173 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
bogdanm 0:9b334a45a8ff 174 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/
bogdanm 0:9b334a45a8ff 175 /**
bogdanm 0:9b334a45a8ff 176 * @}
bogdanm 0:9b334a45a8ff 177 */
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179 /** @defgroup FLASH_Banks FLASH Banks
bogdanm 0:9b334a45a8ff 180 * @{
bogdanm 0:9b334a45a8ff 181 */
bogdanm 0:9b334a45a8ff 182 #define FLASH_BANK_1 ((uint32_t)0x01) /*!< Bank 1 */
bogdanm 0:9b334a45a8ff 183 #define FLASH_BANK_2 ((uint32_t)0x02) /*!< Bank 2 */
bogdanm 0:9b334a45a8ff 184 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */
bogdanm 0:9b334a45a8ff 185 /**
bogdanm 0:9b334a45a8ff 186 * @}
bogdanm 0:9b334a45a8ff 187 */
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /** @defgroup FLASH_Type_Program FLASH Program Type
bogdanm 0:9b334a45a8ff 191 * @{
bogdanm 0:9b334a45a8ff 192 */
bogdanm 0:9b334a45a8ff 193 #define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00) /*!<Program a double-word (64-bit) at a specified address.*/
bogdanm 0:9b334a45a8ff 194 #define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01) /*!<Fast program a 32 row double-word (64-bit) at a specified address.
bogdanm 0:9b334a45a8ff 195 And another 32 row double-word (64-bit) will be programmed */
bogdanm 0:9b334a45a8ff 196 #define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02) /*!<Fast program a 32 row double-word (64-bit) at a specified address.
bogdanm 0:9b334a45a8ff 197 And this is the last 32 row double-word (64-bit) programmed */
bogdanm 0:9b334a45a8ff 198 /**
bogdanm 0:9b334a45a8ff 199 * @}
bogdanm 0:9b334a45a8ff 200 */
bogdanm 0:9b334a45a8ff 201
bogdanm 0:9b334a45a8ff 202 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type
bogdanm 0:9b334a45a8ff 203 * @{
bogdanm 0:9b334a45a8ff 204 */
bogdanm 0:9b334a45a8ff 205 #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */
bogdanm 0:9b334a45a8ff 206 #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */
bogdanm 0:9b334a45a8ff 207 #define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */
bogdanm 0:9b334a45a8ff 208 #define OPTIONBYTE_PCROP ((uint32_t)0x08) /*!< PCROP option byte configuration */
bogdanm 0:9b334a45a8ff 209 /**
bogdanm 0:9b334a45a8ff 210 * @}
bogdanm 0:9b334a45a8ff 211 */
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
bogdanm 0:9b334a45a8ff 214 * @{
bogdanm 0:9b334a45a8ff 215 */
bogdanm 0:9b334a45a8ff 216 #define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /*!< Flash Bank 1 Area A */
bogdanm 0:9b334a45a8ff 217 #define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /*!< Flash Bank 1 Area B */
bogdanm 0:9b334a45a8ff 218 #define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /*!< Flash Bank 2 Area A */
bogdanm 0:9b334a45a8ff 219 #define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /*!< Flash Bank 2 Area B */
bogdanm 0:9b334a45a8ff 220 /**
bogdanm 0:9b334a45a8ff 221 * @}
bogdanm 0:9b334a45a8ff 222 */
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
bogdanm 0:9b334a45a8ff 225 * @{
bogdanm 0:9b334a45a8ff 226 */
bogdanm 0:9b334a45a8ff 227 #define OB_RDP_LEVEL_0 ((uint32_t)0xAA)
bogdanm 0:9b334a45a8ff 228 #define OB_RDP_LEVEL_1 ((uint32_t)0xBB)
bogdanm 0:9b334a45a8ff 229 #define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2
bogdanm 0:9b334a45a8ff 230 it's no more possible to go back to level 1 or 0 */
bogdanm 0:9b334a45a8ff 231 /**
bogdanm 0:9b334a45a8ff 232 * @}
bogdanm 0:9b334a45a8ff 233 */
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
bogdanm 0:9b334a45a8ff 236 * @{
bogdanm 0:9b334a45a8ff 237 */
bogdanm 0:9b334a45a8ff 238 #define OB_USER_BOR_LEV ((uint32_t)0x001) /*!< BOR reset Level */
bogdanm 0:9b334a45a8ff 239 #define OB_USER_nRST_STOP ((uint32_t)0x002) /*!< Reset generated when entering the stop mode */
bogdanm 0:9b334a45a8ff 240 #define OB_USER_nRST_STDBY ((uint32_t)0x004) /*!< Reset generated when entering the standby mode */
bogdanm 0:9b334a45a8ff 241 #define OB_USER_IWDG_SW ((uint32_t)0x008) /*!< Independent watchdog selection */
bogdanm 0:9b334a45a8ff 242 #define OB_USER_IWDG_STOP ((uint32_t)0x010) /*!< Independent watchdog counter freeze in stop mode */
bogdanm 0:9b334a45a8ff 243 #define OB_USER_IWDG_STDBY ((uint32_t)0x020) /*!< Independent watchdog counter freeze in standby mode */
bogdanm 0:9b334a45a8ff 244 #define OB_USER_WWDG_SW ((uint32_t)0x040) /*!< Window watchdog selection */
bogdanm 0:9b334a45a8ff 245 #define OB_USER_BFB2 ((uint32_t)0x080) /*!< Dual-bank boot */
bogdanm 0:9b334a45a8ff 246 #define OB_USER_DUALBANK ((uint32_t)0x100) /*!< Dual-Bank on 512KB or 256KB Flash memory devices */
bogdanm 0:9b334a45a8ff 247 #define OB_USER_nBOOT1 ((uint32_t)0x200) /*!< Boot configuration */
bogdanm 0:9b334a45a8ff 248 #define OB_USER_SRAM2_PE ((uint32_t)0x400) /*!< SRAM2 parity check enable */
bogdanm 0:9b334a45a8ff 249 #define OB_USER_SRAM2_RST ((uint32_t)0x800) /*!< SRAM2 Erase when system reset */
bogdanm 0:9b334a45a8ff 250 /**
bogdanm 0:9b334a45a8ff 251 * @}
bogdanm 0:9b334a45a8ff 252 */
bogdanm 0:9b334a45a8ff 253
bogdanm 0:9b334a45a8ff 254 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
bogdanm 0:9b334a45a8ff 255 * @{
bogdanm 0:9b334a45a8ff 256 */
bogdanm 0:9b334a45a8ff 257 #define OB_BOR_LEVEL_0 ((uint32_t)0x0000) /*!< Reset level threshold is around 1.7V */
bogdanm 0:9b334a45a8ff 258 #define OB_BOR_LEVEL_1 ((uint32_t)0x0100) /*!< Reset level threshold is around 2.0V */
bogdanm 0:9b334a45a8ff 259 #define OB_BOR_LEVEL_2 ((uint32_t)0x0200) /*!< Reset level threshold is around 2.2V */
bogdanm 0:9b334a45a8ff 260 #define OB_BOR_LEVEL_3 ((uint32_t)0x0300) /*!< Reset level threshold is around 2.5V */
bogdanm 0:9b334a45a8ff 261 #define OB_BOR_LEVEL_4 ((uint32_t)0x0400) /*!< Reset level threshold is around 2.8V */
bogdanm 0:9b334a45a8ff 262 /**
bogdanm 0:9b334a45a8ff 263 * @}
bogdanm 0:9b334a45a8ff 264 */
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
bogdanm 0:9b334a45a8ff 267 * @{
bogdanm 0:9b334a45a8ff 268 */
bogdanm 0:9b334a45a8ff 269 #define OB_STOP_RST ((uint32_t)0x0000) /*!< Reset generated when entering the stop mode */
bogdanm 0:9b334a45a8ff 270 #define OB_STOP_NORST ((uint32_t)0x1000) /*!< No reset generated when entering the stop mode */
bogdanm 0:9b334a45a8ff 271 /**
bogdanm 0:9b334a45a8ff 272 * @}
bogdanm 0:9b334a45a8ff 273 */
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
bogdanm 0:9b334a45a8ff 276 * @{
bogdanm 0:9b334a45a8ff 277 */
bogdanm 0:9b334a45a8ff 278 #define OB_STANDBY_RST ((uint32_t)0x0000) /*!< Reset generated when entering the standby mode */
bogdanm 0:9b334a45a8ff 279 #define OB_STANDBY_NORST ((uint32_t)0x2000) /*!< No reset generated when entering the standby mode */
bogdanm 0:9b334a45a8ff 280 /**
bogdanm 0:9b334a45a8ff 281 * @}
bogdanm 0:9b334a45a8ff 282 */
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
bogdanm 0:9b334a45a8ff 285 * @{
bogdanm 0:9b334a45a8ff 286 */
bogdanm 0:9b334a45a8ff 287 #define OB_IWDG_HW ((uint32_t)0x00000) /*!< Hardware independent watchdog */
bogdanm 0:9b334a45a8ff 288 #define OB_IWDG_SW ((uint32_t)0x10000) /*!< Software independent watchdog */
bogdanm 0:9b334a45a8ff 289 /**
bogdanm 0:9b334a45a8ff 290 * @}
bogdanm 0:9b334a45a8ff 291 */
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
bogdanm 0:9b334a45a8ff 294 * @{
bogdanm 0:9b334a45a8ff 295 */
bogdanm 0:9b334a45a8ff 296 #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Stop mode */
bogdanm 0:9b334a45a8ff 297 #define OB_IWDG_STOP_RUN ((uint32_t)0x20000) /*!< Independent watchdog counter is running in Stop mode */
bogdanm 0:9b334a45a8ff 298 /**
bogdanm 0:9b334a45a8ff 299 * @}
bogdanm 0:9b334a45a8ff 300 */
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
bogdanm 0:9b334a45a8ff 303 * @{
bogdanm 0:9b334a45a8ff 304 */
bogdanm 0:9b334a45a8ff 305 #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Standby mode */
bogdanm 0:9b334a45a8ff 306 #define OB_IWDG_STDBY_RUN ((uint32_t)0x40000) /*!< Independent watchdog counter is running in Standby mode */
bogdanm 0:9b334a45a8ff 307 /**
bogdanm 0:9b334a45a8ff 308 * @}
bogdanm 0:9b334a45a8ff 309 */
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
bogdanm 0:9b334a45a8ff 312 * @{
bogdanm 0:9b334a45a8ff 313 */
bogdanm 0:9b334a45a8ff 314 #define OB_WWDG_HW ((uint32_t)0x00000) /*!< Hardware window watchdog */
bogdanm 0:9b334a45a8ff 315 #define OB_WWDG_SW ((uint32_t)0x80000) /*!< Software window watchdog */
bogdanm 0:9b334a45a8ff 316 /**
bogdanm 0:9b334a45a8ff 317 * @}
bogdanm 0:9b334a45a8ff 318 */
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
bogdanm 0:9b334a45a8ff 321 * @{
bogdanm 0:9b334a45a8ff 322 */
bogdanm 0:9b334a45a8ff 323 #define OB_BFB2_DISABLE ((uint32_t)0x000000) /*!< Dual-bank boot disable */
bogdanm 0:9b334a45a8ff 324 #define OB_BFB2_ENABLE ((uint32_t)0x100000) /*!< Dual-bank boot enable */
bogdanm 0:9b334a45a8ff 325 /**
bogdanm 0:9b334a45a8ff 326 * @}
bogdanm 0:9b334a45a8ff 327 */
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
bogdanm 0:9b334a45a8ff 330 * @{
bogdanm 0:9b334a45a8ff 331 */
bogdanm 0:9b334a45a8ff 332 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 256 KB/512 KB Single-bank Flash */
bogdanm 0:9b334a45a8ff 333 #define OB_DUALBANK_DUAL ((uint32_t)0x200000) /*!< 256 KB/512 KB Dual-bank Flash */
bogdanm 0:9b334a45a8ff 334 /**
bogdanm 0:9b334a45a8ff 335 * @}
bogdanm 0:9b334a45a8ff 336 */
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
bogdanm 0:9b334a45a8ff 339 * @{
bogdanm 0:9b334a45a8ff 340 */
bogdanm 0:9b334a45a8ff 341 #define OB_BOOT1_SRAM ((uint32_t)0x000000) /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
bogdanm 0:9b334a45a8ff 342 #define OB_BOOT1_SYSTEM ((uint32_t)0x800000) /*!< System memory is selected as boot space (if BOOT0=1) */
bogdanm 0:9b334a45a8ff 343 /**
bogdanm 0:9b334a45a8ff 344 * @}
bogdanm 0:9b334a45a8ff 345 */
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 /** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type
bogdanm 0:9b334a45a8ff 348 * @{
bogdanm 0:9b334a45a8ff 349 */
bogdanm 0:9b334a45a8ff 350 #define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000) /*!< SRAM2 parity check enable */
bogdanm 0:9b334a45a8ff 351 #define OB_SRAM2_PARITY_DISABLE ((uint32_t)0x1000000) /*!< SRAM2 parity check disable */
bogdanm 0:9b334a45a8ff 352 /**
bogdanm 0:9b334a45a8ff 353 * @}
bogdanm 0:9b334a45a8ff 354 */
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type
bogdanm 0:9b334a45a8ff 357 * @{
bogdanm 0:9b334a45a8ff 358 */
bogdanm 0:9b334a45a8ff 359 #define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000) /*!< SRAM2 erased when a system reset occurs */
bogdanm 0:9b334a45a8ff 360 #define OB_SRAM2_RST_NOT_ERASE ((uint32_t)0x2000000) /*!< SRAM2 is not erased when a system reset occurs */
bogdanm 0:9b334a45a8ff 361 /**
bogdanm 0:9b334a45a8ff 362 * @}
bogdanm 0:9b334a45a8ff 363 */
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
bogdanm 0:9b334a45a8ff 366 * @{
bogdanm 0:9b334a45a8ff 367 */
bogdanm 0:9b334a45a8ff 368 #define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000) /*!< PCROP area is not erased when the RDP level
bogdanm 0:9b334a45a8ff 369 is decreased from Level 1 to Level 0 */
bogdanm 0:9b334a45a8ff 370 #define OB_PCROP_RDP_ERASE ((uint32_t)0x80000000) /*!< PCROP area is erased when the RDP level is
bogdanm 0:9b334a45a8ff 371 decreased from Level 1 to Level 0 (full mass erase) */
bogdanm 0:9b334a45a8ff 372 /**
bogdanm 0:9b334a45a8ff 373 * @}
bogdanm 0:9b334a45a8ff 374 */
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /** @defgroup FLASH_Latency FLASH Latency
bogdanm 0:9b334a45a8ff 377 * @{
bogdanm 0:9b334a45a8ff 378 */
bogdanm 0:9b334a45a8ff 379 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
bogdanm 0:9b334a45a8ff 380 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
bogdanm 0:9b334a45a8ff 381 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
bogdanm 0:9b334a45a8ff 382 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
bogdanm 0:9b334a45a8ff 383 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
bogdanm 0:9b334a45a8ff 384 /**
bogdanm 0:9b334a45a8ff 385 * @}
bogdanm 0:9b334a45a8ff 386 */
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 /** @defgroup FLASH_Keys FLASH Keys
bogdanm 0:9b334a45a8ff 389 * @{
bogdanm 0:9b334a45a8ff 390 */
bogdanm 0:9b334a45a8ff 391 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash key1 */
bogdanm 0:9b334a45a8ff 392 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash key2: used with FLASH_KEY1
bogdanm 0:9b334a45a8ff 393 to unlock the FLASH registers access */
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 #define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */
bogdanm 0:9b334a45a8ff 396 #define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1
bogdanm 0:9b334a45a8ff 397 to unlock the RUN_PD bit in FLASH_ACR */
bogdanm 0:9b334a45a8ff 398
bogdanm 0:9b334a45a8ff 399 #define FLASH_OPTKEY1 ((uint32_t)0x08192A3B) /*!< Flash option byte key1 */
bogdanm 0:9b334a45a8ff 400 #define FLASH_OPTKEY2 ((uint32_t)0x4C5D6E7F) /*!< Flash option byte key2: used with FLASH_OPTKEY1
bogdanm 0:9b334a45a8ff 401 to allow option bytes operations */
bogdanm 0:9b334a45a8ff 402 /**
bogdanm 0:9b334a45a8ff 403 * @}
bogdanm 0:9b334a45a8ff 404 */
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 /** @defgroup FLASH_Flags FLASH Flags Definition
bogdanm 0:9b334a45a8ff 407 * @{
bogdanm 0:9b334a45a8ff 408 */
bogdanm 0:9b334a45a8ff 409 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */
bogdanm 0:9b334a45a8ff 410 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */
bogdanm 0:9b334a45a8ff 411 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */
bogdanm 0:9b334a45a8ff 412 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */
bogdanm 0:9b334a45a8ff 413 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */
bogdanm 0:9b334a45a8ff 414 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
bogdanm 0:9b334a45a8ff 415 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */
bogdanm 0:9b334a45a8ff 416 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */
bogdanm 0:9b334a45a8ff 417 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */
bogdanm 0:9b334a45a8ff 418 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */
bogdanm 0:9b334a45a8ff 419 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */
bogdanm 0:9b334a45a8ff 420 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
bogdanm 0:9b334a45a8ff 421 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */
bogdanm 0:9b334a45a8ff 422 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
bogdanm 0:9b334a45a8ff 425 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
bogdanm 0:9b334a45a8ff 426 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
bogdanm 0:9b334a45a8ff 427 FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD)
bogdanm 0:9b334a45a8ff 428 /**
bogdanm 0:9b334a45a8ff 429 * @}
bogdanm 0:9b334a45a8ff 430 */
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
bogdanm 0:9b334a45a8ff 433 * @brief FLASH Interrupt definition
bogdanm 0:9b334a45a8ff 434 * @{
bogdanm 0:9b334a45a8ff 435 */
bogdanm 0:9b334a45a8ff 436 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
bogdanm 0:9b334a45a8ff 437 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */
bogdanm 0:9b334a45a8ff 438 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/
bogdanm 0:9b334a45a8ff 439 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24)/*!< ECC Correction Interrupt source */
bogdanm 0:9b334a45a8ff 440 /**
bogdanm 0:9b334a45a8ff 441 * @}
bogdanm 0:9b334a45a8ff 442 */
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 /**
bogdanm 0:9b334a45a8ff 445 * @}
bogdanm 0:9b334a45a8ff 446 */
bogdanm 0:9b334a45a8ff 447
bogdanm 0:9b334a45a8ff 448 /* Exported macros -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 449 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
bogdanm 0:9b334a45a8ff 450 * @brief macros to control FLASH features
bogdanm 0:9b334a45a8ff 451 * @{
bogdanm 0:9b334a45a8ff 452 */
bogdanm 0:9b334a45a8ff 453
bogdanm 0:9b334a45a8ff 454 /**
bogdanm 0:9b334a45a8ff 455 * @brief Set the FLASH Latency.
bogdanm 0:9b334a45a8ff 456 * @param __LATENCY__: FLASH Latency
bogdanm 0:9b334a45a8ff 457 * This parameter can be one of the following values :
bogdanm 0:9b334a45a8ff 458 * @arg FLASH_LATENCY_0: FLASH Zero wait state
bogdanm 0:9b334a45a8ff 459 * @arg FLASH_LATENCY_1: FLASH One wait state
bogdanm 0:9b334a45a8ff 460 * @arg FLASH_LATENCY_2: FLASH Two wait states
bogdanm 0:9b334a45a8ff 461 * @arg FLASH_LATENCY_3: FLASH Three wait states
bogdanm 0:9b334a45a8ff 462 * @arg FLASH_LATENCY_4: FLASH Four wait states
bogdanm 0:9b334a45a8ff 463 * @retval None
bogdanm 0:9b334a45a8ff 464 */
bogdanm 0:9b334a45a8ff 465 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = IS_FLASH_LATENCY(__LATENCY__) ? \
bogdanm 0:9b334a45a8ff 466 (FLASH->ACR & (~FLASH_ACR_LATENCY)) | (__LATENCY__) : FLASH->ACR)
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 /**
bogdanm 0:9b334a45a8ff 469 * @brief Get the FLASH Latency.
bogdanm 0:9b334a45a8ff 470 * @retval FLASH Latency
bogdanm 0:9b334a45a8ff 471 * This parameter can be one of the following values :
bogdanm 0:9b334a45a8ff 472 * @arg FLASH_LATENCY_0: FLASH Zero wait state
bogdanm 0:9b334a45a8ff 473 * @arg FLASH_LATENCY_1: FLASH One wait state
bogdanm 0:9b334a45a8ff 474 * @arg FLASH_LATENCY_2: FLASH Two wait states
bogdanm 0:9b334a45a8ff 475 * @arg FLASH_LATENCY_3: FLASH Three wait states
bogdanm 0:9b334a45a8ff 476 * @arg FLASH_LATENCY_4: FLASH Four wait states
bogdanm 0:9b334a45a8ff 477 */
bogdanm 0:9b334a45a8ff 478 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 /**
bogdanm 0:9b334a45a8ff 481 * @brief Enable the FLASH prefetch buffer.
bogdanm 0:9b334a45a8ff 482 * @retval None
bogdanm 0:9b334a45a8ff 483 */
bogdanm 0:9b334a45a8ff 484 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 /**
bogdanm 0:9b334a45a8ff 487 * @brief Disable the FLASH prefetch buffer.
bogdanm 0:9b334a45a8ff 488 * @retval None
bogdanm 0:9b334a45a8ff 489 */
bogdanm 0:9b334a45a8ff 490 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
bogdanm 0:9b334a45a8ff 491
bogdanm 0:9b334a45a8ff 492 /**
bogdanm 0:9b334a45a8ff 493 * @brief Enable the FLASH instruction cache.
bogdanm 0:9b334a45a8ff 494 * @retval none
bogdanm 0:9b334a45a8ff 495 */
bogdanm 0:9b334a45a8ff 496 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 /**
bogdanm 0:9b334a45a8ff 499 * @brief Disable the FLASH instruction cache.
bogdanm 0:9b334a45a8ff 500 * @retval none
bogdanm 0:9b334a45a8ff 501 */
bogdanm 0:9b334a45a8ff 502 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504 /**
bogdanm 0:9b334a45a8ff 505 * @brief Enable the FLASH data cache.
bogdanm 0:9b334a45a8ff 506 * @retval none
bogdanm 0:9b334a45a8ff 507 */
bogdanm 0:9b334a45a8ff 508 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /**
bogdanm 0:9b334a45a8ff 511 * @brief Disable the FLASH data cache.
bogdanm 0:9b334a45a8ff 512 * @retval none
bogdanm 0:9b334a45a8ff 513 */
bogdanm 0:9b334a45a8ff 514 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 /**
bogdanm 0:9b334a45a8ff 517 * @brief Reset the FLASH instruction Cache.
bogdanm 0:9b334a45a8ff 518 * @note This function must be used only when the Instruction Cache is disabled.
bogdanm 0:9b334a45a8ff 519 * @retval None
bogdanm 0:9b334a45a8ff 520 */
bogdanm 0:9b334a45a8ff 521 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() SET_BIT(FLASH->ACR, FLASH_ACR_ICRST)
bogdanm 0:9b334a45a8ff 522
bogdanm 0:9b334a45a8ff 523 /**
bogdanm 0:9b334a45a8ff 524 * @brief Reset the FLASH data Cache.
bogdanm 0:9b334a45a8ff 525 * @note This function must be used only when the data Cache is disabled.
bogdanm 0:9b334a45a8ff 526 * @retval None
bogdanm 0:9b334a45a8ff 527 */
bogdanm 0:9b334a45a8ff 528 #define __HAL_FLASH_DATA_CACHE_RESET() SET_BIT(FLASH->ACR, FLASH_ACR_DCRST)
bogdanm 0:9b334a45a8ff 529
bogdanm 0:9b334a45a8ff 530 /**
bogdanm 0:9b334a45a8ff 531 * @brief Enable the FLASH power down during Low-power run mode.
bogdanm 0:9b334a45a8ff 532 * @note Writing this bit to 0 this bit, automatically the keys are
bogdanm 0:9b334a45a8ff 533 * loss and a new unlock sequence is necessary to re-write it to 1.
bogdanm 0:9b334a45a8ff 534 */
bogdanm 0:9b334a45a8ff 535 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
bogdanm 0:9b334a45a8ff 536 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
bogdanm 0:9b334a45a8ff 537 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
bogdanm 0:9b334a45a8ff 538 } while (0)
bogdanm 0:9b334a45a8ff 539
bogdanm 0:9b334a45a8ff 540 /**
bogdanm 0:9b334a45a8ff 541 * @brief Disable the FLASH power down during Low-power run mode.
bogdanm 0:9b334a45a8ff 542 * @note Writing this bit to 0 this bit, automatically the keys are
bogdanm 0:9b334a45a8ff 543 * loss and a new unlock sequence is necessary to re-write it to 1.
bogdanm 0:9b334a45a8ff 544 */
bogdanm 0:9b334a45a8ff 545 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
bogdanm 0:9b334a45a8ff 546 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
bogdanm 0:9b334a45a8ff 547 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
bogdanm 0:9b334a45a8ff 548 } while (0)
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 /**
bogdanm 0:9b334a45a8ff 551 * @brief Enable the FLASH power down during Low-Power sleep mode
bogdanm 0:9b334a45a8ff 552 * @retval none
bogdanm 0:9b334a45a8ff 553 */
bogdanm 0:9b334a45a8ff 554 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556 /**
bogdanm 0:9b334a45a8ff 557 * @brief Disable the FLASH power down during Low-Power sleep mode
bogdanm 0:9b334a45a8ff 558 * @retval none
bogdanm 0:9b334a45a8ff 559 */
bogdanm 0:9b334a45a8ff 560 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
bogdanm 0:9b334a45a8ff 561
bogdanm 0:9b334a45a8ff 562 /**
bogdanm 0:9b334a45a8ff 563 * @}
bogdanm 0:9b334a45a8ff 564 */
bogdanm 0:9b334a45a8ff 565
bogdanm 0:9b334a45a8ff 566 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros
bogdanm 0:9b334a45a8ff 567 * @brief macros to handle FLASH interrupts
bogdanm 0:9b334a45a8ff 568 * @{
bogdanm 0:9b334a45a8ff 569 */
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571 /**
bogdanm 0:9b334a45a8ff 572 * @brief Enable the specified FLASH interrupt.
bogdanm 0:9b334a45a8ff 573 * @param __INTERRUPT__: FLASH interrupt
bogdanm 0:9b334a45a8ff 574 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 575 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
bogdanm 0:9b334a45a8ff 576 * @arg FLASH_IT_OPERR: Error Interrupt
bogdanm 0:9b334a45a8ff 577 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
bogdanm 0:9b334a45a8ff 578 * @arg FLASH_IT_ECCC: ECC Correction Interrupt
bogdanm 0:9b334a45a8ff 579 * @retval none
bogdanm 0:9b334a45a8ff 580 */
bogdanm 0:9b334a45a8ff 581 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
bogdanm 0:9b334a45a8ff 582 if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
bogdanm 0:9b334a45a8ff 583 } while(0)
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 /**
bogdanm 0:9b334a45a8ff 586 * @brief Disable the specified FLASH interrupt.
bogdanm 0:9b334a45a8ff 587 * @param __INTERRUPT__: FLASH interrupt
bogdanm 0:9b334a45a8ff 588 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 589 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
bogdanm 0:9b334a45a8ff 590 * @arg FLASH_IT_OPERR: Error Interrupt
bogdanm 0:9b334a45a8ff 591 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
bogdanm 0:9b334a45a8ff 592 * @arg FLASH_IT_ECCC: ECC Correction Interrupt
bogdanm 0:9b334a45a8ff 593 * @retval none
bogdanm 0:9b334a45a8ff 594 */
bogdanm 0:9b334a45a8ff 595 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
bogdanm 0:9b334a45a8ff 596 if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
bogdanm 0:9b334a45a8ff 597 } while(0)
bogdanm 0:9b334a45a8ff 598
bogdanm 0:9b334a45a8ff 599 /**
bogdanm 0:9b334a45a8ff 600 * @brief Check whether the specified FLASH flag is set or not.
bogdanm 0:9b334a45a8ff 601 * @param __FLAG__: specifies the FLASH flag to check.
bogdanm 0:9b334a45a8ff 602 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 603 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
bogdanm 0:9b334a45a8ff 604 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
bogdanm 0:9b334a45a8ff 605 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
bogdanm 0:9b334a45a8ff 606 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
bogdanm 0:9b334a45a8ff 607 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
bogdanm 0:9b334a45a8ff 608 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
bogdanm 0:9b334a45a8ff 609 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
bogdanm 0:9b334a45a8ff 610 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
bogdanm 0:9b334a45a8ff 611 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
bogdanm 0:9b334a45a8ff 612 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
bogdanm 0:9b334a45a8ff 613 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
bogdanm 0:9b334a45a8ff 614 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
bogdanm 0:9b334a45a8ff 615 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
bogdanm 0:9b334a45a8ff 616 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
bogdanm 0:9b334a45a8ff 617 * @retval The new state of FLASH_FLAG (SET or RESET).
bogdanm 0:9b334a45a8ff 618 */
bogdanm 0:9b334a45a8ff 619 #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \
bogdanm 0:9b334a45a8ff 620 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
bogdanm 0:9b334a45a8ff 621 (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
bogdanm 0:9b334a45a8ff 622
bogdanm 0:9b334a45a8ff 623 /**
bogdanm 0:9b334a45a8ff 624 * @brief Clear the FLASH's pending flags.
bogdanm 0:9b334a45a8ff 625 * @param __FLAG__: specifies the FLASH flags to clear.
bogdanm 0:9b334a45a8ff 626 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 627 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
bogdanm 0:9b334a45a8ff 628 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
bogdanm 0:9b334a45a8ff 629 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
bogdanm 0:9b334a45a8ff 630 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
bogdanm 0:9b334a45a8ff 631 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
bogdanm 0:9b334a45a8ff 632 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
bogdanm 0:9b334a45a8ff 633 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
bogdanm 0:9b334a45a8ff 634 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
bogdanm 0:9b334a45a8ff 635 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
bogdanm 0:9b334a45a8ff 636 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
bogdanm 0:9b334a45a8ff 637 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
bogdanm 0:9b334a45a8ff 638 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
bogdanm 0:9b334a45a8ff 639 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
bogdanm 0:9b334a45a8ff 640 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
bogdanm 0:9b334a45a8ff 641 * @retval None
bogdanm 0:9b334a45a8ff 642 */
bogdanm 0:9b334a45a8ff 643 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
bogdanm 0:9b334a45a8ff 644 if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
bogdanm 0:9b334a45a8ff 645 } while(0)
bogdanm 0:9b334a45a8ff 646 /**
bogdanm 0:9b334a45a8ff 647 * @}
bogdanm 0:9b334a45a8ff 648 */
bogdanm 0:9b334a45a8ff 649
bogdanm 0:9b334a45a8ff 650 /* Include FLASH HAL Extended module */
bogdanm 0:9b334a45a8ff 651 #include "stm32l4xx_hal_flash_ex.h"
bogdanm 0:9b334a45a8ff 652 #include "stm32l4xx_hal_flash_ramfunc.h"
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 655 /** @addtogroup FLASH_Exported_Functions
bogdanm 0:9b334a45a8ff 656 * @{
bogdanm 0:9b334a45a8ff 657 */
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 /* Program operation functions ***********************************************/
bogdanm 0:9b334a45a8ff 660 /** @addtogroup FLASH_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 661 * @{
bogdanm 0:9b334a45a8ff 662 */
bogdanm 0:9b334a45a8ff 663 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
bogdanm 0:9b334a45a8ff 664 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
bogdanm 0:9b334a45a8ff 665 /* FLASH IRQ handler method */
bogdanm 0:9b334a45a8ff 666 void HAL_FLASH_IRQHandler(void);
bogdanm 0:9b334a45a8ff 667 /* Callbacks in non blocking modes */
bogdanm 0:9b334a45a8ff 668 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
bogdanm 0:9b334a45a8ff 669 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
bogdanm 0:9b334a45a8ff 670 /**
bogdanm 0:9b334a45a8ff 671 * @}
bogdanm 0:9b334a45a8ff 672 */
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 /* Peripheral Control functions **********************************************/
bogdanm 0:9b334a45a8ff 675 /** @addtogroup FLASH_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 676 * @{
bogdanm 0:9b334a45a8ff 677 */
bogdanm 0:9b334a45a8ff 678 HAL_StatusTypeDef HAL_FLASH_Unlock(void);
bogdanm 0:9b334a45a8ff 679 HAL_StatusTypeDef HAL_FLASH_Lock(void);
bogdanm 0:9b334a45a8ff 680 /* Option bytes control */
bogdanm 0:9b334a45a8ff 681 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
bogdanm 0:9b334a45a8ff 682 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
bogdanm 0:9b334a45a8ff 683 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
bogdanm 0:9b334a45a8ff 684 /**
bogdanm 0:9b334a45a8ff 685 * @}
bogdanm 0:9b334a45a8ff 686 */
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 /* Peripheral State functions ************************************************/
bogdanm 0:9b334a45a8ff 689 /** @addtogroup FLASH_Exported_Functions_Group3
bogdanm 0:9b334a45a8ff 690 * @{
bogdanm 0:9b334a45a8ff 691 */
bogdanm 0:9b334a45a8ff 692 uint32_t HAL_FLASH_GetError(void);
bogdanm 0:9b334a45a8ff 693 /**
bogdanm 0:9b334a45a8ff 694 * @}
bogdanm 0:9b334a45a8ff 695 */
bogdanm 0:9b334a45a8ff 696
bogdanm 0:9b334a45a8ff 697 /**
bogdanm 0:9b334a45a8ff 698 * @}
bogdanm 0:9b334a45a8ff 699 */
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 /* Private constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 702 /** @defgroup FLASH_Private_Constants FLASH Private Constants
bogdanm 0:9b334a45a8ff 703 * @{
bogdanm 0:9b334a45a8ff 704 */
bogdanm 0:9b334a45a8ff 705 #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
bogdanm 0:9b334a45a8ff 706
bogdanm 0:9b334a45a8ff 707 #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \
bogdanm 0:9b334a45a8ff 708 (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
bogdanm 0:9b334a45a8ff 709
bogdanm 0:9b334a45a8ff 710 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1)
bogdanm 0:9b334a45a8ff 711
bogdanm 0:9b334a45a8ff 712 #define FLASH_PAGE_SIZE ((uint32_t)0x800)
bogdanm 0:9b334a45a8ff 713
bogdanm 0:9b334a45a8ff 714 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
bogdanm 0:9b334a45a8ff 715 /**
bogdanm 0:9b334a45a8ff 716 * @}
bogdanm 0:9b334a45a8ff 717 */
bogdanm 0:9b334a45a8ff 718
bogdanm 0:9b334a45a8ff 719 /* Private macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 720 /** @defgroup FLASH_Private_Macros FLASH Private Macros
bogdanm 0:9b334a45a8ff 721 * @{
bogdanm 0:9b334a45a8ff 722 */
bogdanm 0:9b334a45a8ff 723
bogdanm 0:9b334a45a8ff 724 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
bogdanm 0:9b334a45a8ff 725 ((VALUE) == FLASH_TYPEERASE_MASSERASE))
bogdanm 0:9b334a45a8ff 726
bogdanm 0:9b334a45a8ff 727 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
bogdanm 0:9b334a45a8ff 728 ((BANK) == FLASH_BANK_2) || \
bogdanm 0:9b334a45a8ff 729 ((BANK) == FLASH_BANK_BOTH))
bogdanm 0:9b334a45a8ff 730
bogdanm 0:9b334a45a8ff 731 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
bogdanm 0:9b334a45a8ff 732 ((BANK) == FLASH_BANK_2))
bogdanm 0:9b334a45a8ff 733
bogdanm 0:9b334a45a8ff 734 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
bogdanm 0:9b334a45a8ff 735 ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
bogdanm 0:9b334a45a8ff 736 ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
bogdanm 0:9b334a45a8ff 737
bogdanm 0:9b334a45a8ff 738 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \
bogdanm 0:9b334a45a8ff 739 ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \
bogdanm 0:9b334a45a8ff 740 ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \
bogdanm 0:9b334a45a8ff 741 ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF)))))
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))
bogdanm 0:9b334a45a8ff 744
bogdanm 0:9b334a45a8ff 745 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
bogdanm 0:9b334a45a8ff 746
bogdanm 0:9b334a45a8ff 747 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \
bogdanm 0:9b334a45a8ff 748 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \
bogdanm 0:9b334a45a8ff 749 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \
bogdanm 0:9b334a45a8ff 750 ((PAGE) < 256)))))
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
bogdanm 0:9b334a45a8ff 755 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
bogdanm 0:9b334a45a8ff 756
bogdanm 0:9b334a45a8ff 757 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
bogdanm 0:9b334a45a8ff 758 ((LEVEL) == OB_RDP_LEVEL_1)/* ||\
bogdanm 0:9b334a45a8ff 759 ((LEVEL) == OB_RDP_LEVEL_2)*/)
bogdanm 0:9b334a45a8ff 760
bogdanm 0:9b334a45a8ff 761 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFF) && ((TYPE) != 0))
bogdanm 0:9b334a45a8ff 762
bogdanm 0:9b334a45a8ff 763 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
bogdanm 0:9b334a45a8ff 764 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
bogdanm 0:9b334a45a8ff 765 ((LEVEL) == OB_BOR_LEVEL_4))
bogdanm 0:9b334a45a8ff 766
bogdanm 0:9b334a45a8ff 767 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
bogdanm 0:9b334a45a8ff 768
bogdanm 0:9b334a45a8ff 769 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
bogdanm 0:9b334a45a8ff 770
bogdanm 0:9b334a45a8ff 771 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
bogdanm 0:9b334a45a8ff 772
bogdanm 0:9b334a45a8ff 773 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
bogdanm 0:9b334a45a8ff 774
bogdanm 0:9b334a45a8ff 775 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
bogdanm 0:9b334a45a8ff 776
bogdanm 0:9b334a45a8ff 777 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
bogdanm 0:9b334a45a8ff 778
bogdanm 0:9b334a45a8ff 779 #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
bogdanm 0:9b334a45a8ff 780
bogdanm 0:9b334a45a8ff 781 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
bogdanm 0:9b334a45a8ff 782
bogdanm 0:9b334a45a8ff 783 #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
bogdanm 0:9b334a45a8ff 784
bogdanm 0:9b334a45a8ff 785 #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))
bogdanm 0:9b334a45a8ff 786
bogdanm 0:9b334a45a8ff 787 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
bogdanm 0:9b334a45a8ff 788
bogdanm 0:9b334a45a8ff 789 #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
bogdanm 0:9b334a45a8ff 790
bogdanm 0:9b334a45a8ff 791 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
bogdanm 0:9b334a45a8ff 792 ((LATENCY) == FLASH_LATENCY_1) || \
bogdanm 0:9b334a45a8ff 793 ((LATENCY) == FLASH_LATENCY_2) || \
bogdanm 0:9b334a45a8ff 794 ((LATENCY) == FLASH_LATENCY_3) || \
bogdanm 0:9b334a45a8ff 795 ((LATENCY) == FLASH_LATENCY_4))
bogdanm 0:9b334a45a8ff 796 /**
bogdanm 0:9b334a45a8ff 797 * @}
bogdanm 0:9b334a45a8ff 798 */
bogdanm 0:9b334a45a8ff 799
bogdanm 0:9b334a45a8ff 800 /**
bogdanm 0:9b334a45a8ff 801 * @}
bogdanm 0:9b334a45a8ff 802 */
bogdanm 0:9b334a45a8ff 803
bogdanm 0:9b334a45a8ff 804 /**
bogdanm 0:9b334a45a8ff 805 * @}
bogdanm 0:9b334a45a8ff 806 */
bogdanm 0:9b334a45a8ff 807
bogdanm 0:9b334a45a8ff 808 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 809 }
bogdanm 0:9b334a45a8ff 810 #endif
bogdanm 0:9b334a45a8ff 811
bogdanm 0:9b334a45a8ff 812 #endif /* __STM32L4xx_HAL_FLASH_H */
bogdanm 0:9b334a45a8ff 813
bogdanm 0:9b334a45a8ff 814 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/