en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/system_stm32l4xx.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file system_stm32l4xx.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides two functions and one global variable to be called from
bogdanm 0:9b334a45a8ff 10 * user application:
bogdanm 0:9b334a45a8ff 11 * - SystemInit(): This function is called at startup just after reset and
bogdanm 0:9b334a45a8ff 12 * before branch to main program. This call is made inside
bogdanm 0:9b334a45a8ff 13 * the "startup_stm32l4xx.s" file.
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
bogdanm 0:9b334a45a8ff 16 * by the user application to setup the SysTick
bogdanm 0:9b334a45a8ff 17 * timer or configure other parameters.
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
bogdanm 0:9b334a45a8ff 20 * be called whenever the core clock is changed
bogdanm 0:9b334a45a8ff 21 * during program execution.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 * After each device reset the MSI (4 MHz) is used as system clock source.
bogdanm 0:9b334a45a8ff 24 * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
bogdanm 0:9b334a45a8ff 25 * configure the system clock before to branch to main program.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * This file configures the system clock as follows:
bogdanm 0:9b334a45a8ff 28 *=============================================================================
bogdanm 0:9b334a45a8ff 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
bogdanm 0:9b334a45a8ff 30 * | (external 8 MHz clock) | (internal 16 MHz)
bogdanm 0:9b334a45a8ff 31 * | 2- PLL_HSE_XTAL | or PLL_MSI
bogdanm 0:9b334a45a8ff 32 * | (external 8 MHz xtal) | (internal 4 MHz)
bogdanm 0:9b334a45a8ff 33 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 34 * SYSCLK(MHz) | 48 | 80
bogdanm 0:9b334a45a8ff 35 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 36 * AHBCLK (MHz) | 48 | 80
bogdanm 0:9b334a45a8ff 37 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 38 * APB1CLK (MHz) | 48 | 80
bogdanm 0:9b334a45a8ff 39 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 40 * APB2CLK (MHz) | 48 | 80
bogdanm 0:9b334a45a8ff 41 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 42 * USB capable (48 MHz precise clock) | YES | NO
bogdanm 0:9b334a45a8ff 43 *-----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 44 *=============================================================================
bogdanm 0:9b334a45a8ff 45 ******************************************************************************
bogdanm 0:9b334a45a8ff 46 * @attention
bogdanm 0:9b334a45a8ff 47 *
bogdanm 0:9b334a45a8ff 48 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 49 *
bogdanm 0:9b334a45a8ff 50 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 51 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 52 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 53 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 54 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 55 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 56 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 57 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 58 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 59 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 60 *
bogdanm 0:9b334a45a8ff 61 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 62 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 64 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 67 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 68 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 69 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 70 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 71 *
bogdanm 0:9b334a45a8ff 72 ******************************************************************************
bogdanm 0:9b334a45a8ff 73 */
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 /** @addtogroup CMSIS
bogdanm 0:9b334a45a8ff 76 * @{
bogdanm 0:9b334a45a8ff 77 */
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 /** @addtogroup stm32l4xx_system
bogdanm 0:9b334a45a8ff 80 * @{
bogdanm 0:9b334a45a8ff 81 */
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 /** @addtogroup STM32L4xx_System_Private_Includes
bogdanm 0:9b334a45a8ff 84 * @{
bogdanm 0:9b334a45a8ff 85 */
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 #include "stm32l4xx.h"
bogdanm 0:9b334a45a8ff 88 #include "hal_tick.h"
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 #if !defined (HSE_VALUE)
bogdanm 0:9b334a45a8ff 91 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
bogdanm 0:9b334a45a8ff 92 #endif /* HSE_VALUE */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 #if !defined (MSI_VALUE)
bogdanm 0:9b334a45a8ff 95 #define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
bogdanm 0:9b334a45a8ff 96 #endif /* MSI_VALUE */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 #if !defined (HSI_VALUE)
bogdanm 0:9b334a45a8ff 99 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
bogdanm 0:9b334a45a8ff 100 #endif /* HSI_VALUE */
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /**
bogdanm 0:9b334a45a8ff 103 * @}
bogdanm 0:9b334a45a8ff 104 */
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /** @addtogroup STM32L4xx_System_Private_TypesDefinitions
bogdanm 0:9b334a45a8ff 107 * @{
bogdanm 0:9b334a45a8ff 108 */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 /**
bogdanm 0:9b334a45a8ff 111 * @}
bogdanm 0:9b334a45a8ff 112 */
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /** @addtogroup STM32L4xx_System_Private_Defines
bogdanm 0:9b334a45a8ff 115 * @{
bogdanm 0:9b334a45a8ff 116 */
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 /************************* Miscellaneous Configuration ************************/
bogdanm 0:9b334a45a8ff 119 /*!< Uncomment the following line if you need to relocate your vector Table in
bogdanm 0:9b334a45a8ff 120 Internal SRAM. */
bogdanm 0:9b334a45a8ff 121 /* #define VECT_TAB_SRAM */
bogdanm 0:9b334a45a8ff 122 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
bogdanm 0:9b334a45a8ff 123 This value must be a multiple of 0x200. */
bogdanm 0:9b334a45a8ff 124 /******************************************************************************/
bogdanm 0:9b334a45a8ff 125 /**
bogdanm 0:9b334a45a8ff 126 * @}
bogdanm 0:9b334a45a8ff 127 */
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /** @addtogroup STM32L4xx_System_Private_Macros
bogdanm 0:9b334a45a8ff 130 * @{
bogdanm 0:9b334a45a8ff 131 */
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 // Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
bogdanm 0:9b334a45a8ff 134 #define USE_PLL_HSE_EXTC (1) // Use external clock
bogdanm 0:9b334a45a8ff 135 #define USE_PLL_HSE_XTAL (0) // Use external xtal
bogdanm 0:9b334a45a8ff 136 #define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
bogdanm 0:9b334a45a8ff 137 #define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
bogdanm 0:9b334a45a8ff 138 /**
bogdanm 0:9b334a45a8ff 139 * @}
bogdanm 0:9b334a45a8ff 140 */
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /** @addtogroup STM32L4xx_System_Private_Variables
bogdanm 0:9b334a45a8ff 143 * @{
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145 /* This variable is updated in three ways:
bogdanm 0:9b334a45a8ff 146 1) by calling CMSIS function SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 147 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
bogdanm 0:9b334a45a8ff 148 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
bogdanm 0:9b334a45a8ff 149 Note: If you use this function to configure the system clock; then there
bogdanm 0:9b334a45a8ff 150 is no need to call the 2 first functions listed above, since SystemCoreClock
bogdanm 0:9b334a45a8ff 151 variable is updated automatically.
bogdanm 0:9b334a45a8ff 152 */
bogdanm 0:9b334a45a8ff 153 uint32_t SystemCoreClock = 4000000;
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm 0:9b334a45a8ff 156 const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
bogdanm 0:9b334a45a8ff 157 4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
bogdanm 0:9b334a45a8ff 158 /**
bogdanm 0:9b334a45a8ff 159 * @}
bogdanm 0:9b334a45a8ff 160 */
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 /** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
bogdanm 0:9b334a45a8ff 163 * @{
bogdanm 0:9b334a45a8ff 164 */
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 167 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
bogdanm 0:9b334a45a8ff 168 #endif
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 #if (USE_PLL_HSI != 0)
bogdanm 0:9b334a45a8ff 171 uint8_t SetSysClock_PLL_HSI(void);
bogdanm 0:9b334a45a8ff 172 #endif
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 uint8_t SetSysClock_PLL_MSI(void);
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 /**
bogdanm 0:9b334a45a8ff 177 * @}
bogdanm 0:9b334a45a8ff 178 */
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /** @addtogroup STM32L4xx_System_Private_Functions
bogdanm 0:9b334a45a8ff 181 * @{
bogdanm 0:9b334a45a8ff 182 */
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 /**
bogdanm 0:9b334a45a8ff 185 * @brief Setup the microcontroller system.
bogdanm 0:9b334a45a8ff 186 * @param None
bogdanm 0:9b334a45a8ff 187 * @retval None
bogdanm 0:9b334a45a8ff 188 */
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 void SystemInit(void)
bogdanm 0:9b334a45a8ff 191 {
bogdanm 0:9b334a45a8ff 192 /* FPU settings ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 193 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
bogdanm 0:9b334a45a8ff 194 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
bogdanm 0:9b334a45a8ff 195 #endif
bogdanm 0:9b334a45a8ff 196 /* Reset the RCC clock configuration to the default reset state ------------*/
bogdanm 0:9b334a45a8ff 197 /* Set MSION bit */
bogdanm 0:9b334a45a8ff 198 RCC->CR |= RCC_CR_MSION;
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 /* Reset CFGR register */
bogdanm 0:9b334a45a8ff 201 RCC->CFGR = 0x00000000;
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 /* Reset HSEON, CSSON , HSION, and PLLON bits */
bogdanm 0:9b334a45a8ff 204 RCC->CR &= (uint32_t)0xEAF6FFFF;
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /* Reset PLLCFGR register */
bogdanm 0:9b334a45a8ff 207 RCC->PLLCFGR = 0x00000800;
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /* Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 210 RCC->CR &= (uint32_t)0xFFFBFFFF;
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 /* Disable all interrupts */
bogdanm 0:9b334a45a8ff 213 RCC->CIER = 0x00000000;
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /* Configure the Vector Table location add offset address ------------------*/
bogdanm 0:9b334a45a8ff 216 #ifdef VECT_TAB_SRAM
bogdanm 0:9b334a45a8ff 217 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
bogdanm 0:9b334a45a8ff 218 #else
bogdanm 0:9b334a45a8ff 219 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
bogdanm 0:9b334a45a8ff 220 #endif
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 /* Configure the Cube driver */
bogdanm 0:9b334a45a8ff 223 SystemCoreClock = MSI_VALUE; // At this stage the MSI is used as system clock
bogdanm 0:9b334a45a8ff 224 HAL_Init();
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /* Configure the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 227 AHB/APBx prescalers and Flash settings */
bogdanm 0:9b334a45a8ff 228 SetSysClock();
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /* Reset the timer to avoid issues after the RAM initialization */
bogdanm 0:9b334a45a8ff 231 TIM_MST_RESET_ON;
bogdanm 0:9b334a45a8ff 232 TIM_MST_RESET_OFF;
bogdanm 0:9b334a45a8ff 233 }
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 /**
bogdanm 0:9b334a45a8ff 236 * @brief Update SystemCoreClock variable according to Clock Register Values.
bogdanm 0:9b334a45a8ff 237 * The SystemCoreClock variable contains the core clock (HCLK), it can
bogdanm 0:9b334a45a8ff 238 * be used by the user application to setup the SysTick timer or configure
bogdanm 0:9b334a45a8ff 239 * other parameters.
bogdanm 0:9b334a45a8ff 240 *
bogdanm 0:9b334a45a8ff 241 * @note Each time the core clock (HCLK) changes, this function must be called
bogdanm 0:9b334a45a8ff 242 * to update SystemCoreClock variable value. Otherwise, any configuration
bogdanm 0:9b334a45a8ff 243 * based on this variable will be incorrect.
bogdanm 0:9b334a45a8ff 244 *
bogdanm 0:9b334a45a8ff 245 * @note - The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 246 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 247 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 248 *
bogdanm 0:9b334a45a8ff 249 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
bogdanm 0:9b334a45a8ff 250 *
bogdanm 0:9b334a45a8ff 251 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
bogdanm 0:9b334a45a8ff 252 *
bogdanm 0:9b334a45a8ff 253 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
bogdanm 0:9b334a45a8ff 254 *
bogdanm 0:9b334a45a8ff 255 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
bogdanm 0:9b334a45a8ff 256 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
bogdanm 0:9b334a45a8ff 257 *
bogdanm 0:9b334a45a8ff 258 * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
bogdanm 0:9b334a45a8ff 259 * 4 MHz) but the real value may vary depending on the variations
bogdanm 0:9b334a45a8ff 260 * in voltage and temperature.
bogdanm 0:9b334a45a8ff 261 *
bogdanm 0:9b334a45a8ff 262 * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
bogdanm 0:9b334a45a8ff 263 * 16 MHz) but the real value may vary depending on the variations
bogdanm 0:9b334a45a8ff 264 * in voltage and temperature.
bogdanm 0:9b334a45a8ff 265 *
bogdanm 0:9b334a45a8ff 266 * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
bogdanm 0:9b334a45a8ff 267 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm 0:9b334a45a8ff 268 * frequency of the crystal used. Otherwise, this function may
bogdanm 0:9b334a45a8ff 269 * have wrong result.
bogdanm 0:9b334a45a8ff 270 *
bogdanm 0:9b334a45a8ff 271 * - The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 272 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 273 *
bogdanm 0:9b334a45a8ff 274 * @param None
bogdanm 0:9b334a45a8ff 275 * @retval None
bogdanm 0:9b334a45a8ff 276 */
bogdanm 0:9b334a45a8ff 277 void SystemCoreClockUpdate(void)
bogdanm 0:9b334a45a8ff 278 {
bogdanm 0:9b334a45a8ff 279 uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
bogdanm 0:9b334a45a8ff 280
bogdanm 0:9b334a45a8ff 281 /* Get MSI Range frequency--------------------------------------------------*/
bogdanm 0:9b334a45a8ff 282 if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
bogdanm 0:9b334a45a8ff 283 { /* MSISRANGE from RCC_CSR applies */
bogdanm 0:9b334a45a8ff 284 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
bogdanm 0:9b334a45a8ff 285 }
bogdanm 0:9b334a45a8ff 286 else
bogdanm 0:9b334a45a8ff 287 { /* MSIRANGE from RCC_CR applies */
bogdanm 0:9b334a45a8ff 288 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
bogdanm 0:9b334a45a8ff 289 }
bogdanm 0:9b334a45a8ff 290 /*MSI frequency range in HZ*/
bogdanm 0:9b334a45a8ff 291 msirange = MSIRangeTable[msirange];
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 294 switch (RCC->CFGR & RCC_CFGR_SWS)
bogdanm 0:9b334a45a8ff 295 {
bogdanm 0:9b334a45a8ff 296 case 0x00: /* MSI used as system clock source */
bogdanm 0:9b334a45a8ff 297 SystemCoreClock = msirange;
bogdanm 0:9b334a45a8ff 298 break;
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 case 0x04: /* HSI used as system clock source */
bogdanm 0:9b334a45a8ff 301 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 302 break;
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 case 0x08: /* HSE used as system clock source */
bogdanm 0:9b334a45a8ff 305 SystemCoreClock = HSE_VALUE;
bogdanm 0:9b334a45a8ff 306 break;
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 case 0x0C: /* PLL used as system clock source */
bogdanm 0:9b334a45a8ff 309 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
bogdanm 0:9b334a45a8ff 310 SYSCLK = PLL_VCO / PLLR
bogdanm 0:9b334a45a8ff 311 */
bogdanm 0:9b334a45a8ff 312 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
bogdanm 0:9b334a45a8ff 313 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315 switch (pllsource)
bogdanm 0:9b334a45a8ff 316 {
bogdanm 0:9b334a45a8ff 317 case 0x02: /* HSI used as PLL clock source */
bogdanm 0:9b334a45a8ff 318 pllvco = (HSI_VALUE / pllm);
bogdanm 0:9b334a45a8ff 319 break;
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321 case 0x03: /* HSE used as PLL clock source */
bogdanm 0:9b334a45a8ff 322 pllvco = (HSE_VALUE / pllm);
bogdanm 0:9b334a45a8ff 323 break;
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 default: /* MSI used as PLL clock source */
bogdanm 0:9b334a45a8ff 326 pllvco = (msirange / pllm);
bogdanm 0:9b334a45a8ff 327 break;
bogdanm 0:9b334a45a8ff 328 }
bogdanm 0:9b334a45a8ff 329 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
bogdanm 0:9b334a45a8ff 330 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
bogdanm 0:9b334a45a8ff 331 SystemCoreClock = pllvco/pllr;
bogdanm 0:9b334a45a8ff 332 break;
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 default:
bogdanm 0:9b334a45a8ff 335 SystemCoreClock = msirange;
bogdanm 0:9b334a45a8ff 336 break;
bogdanm 0:9b334a45a8ff 337 }
bogdanm 0:9b334a45a8ff 338 /* Compute HCLK clock frequency --------------------------------------------*/
bogdanm 0:9b334a45a8ff 339 /* Get HCLK prescaler */
bogdanm 0:9b334a45a8ff 340 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
bogdanm 0:9b334a45a8ff 341 /* HCLK clock frequency */
bogdanm 0:9b334a45a8ff 342 SystemCoreClock >>= tmp;
bogdanm 0:9b334a45a8ff 343 }
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 /**
bogdanm 0:9b334a45a8ff 346 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 347 * AHB/APBx prescalers and Flash settings
bogdanm 0:9b334a45a8ff 348 * @note This function should be called only once the RCC clock configuration
bogdanm 0:9b334a45a8ff 349 * is reset to the default reset state (done in SystemInit() function).
bogdanm 0:9b334a45a8ff 350 * @param None
bogdanm 0:9b334a45a8ff 351 * @retval None
bogdanm 0:9b334a45a8ff 352 */
bogdanm 0:9b334a45a8ff 353 void SetSysClock(void)
bogdanm 0:9b334a45a8ff 354 {
bogdanm 0:9b334a45a8ff 355 /* 1- Try to start with HSE and external clock */
bogdanm 0:9b334a45a8ff 356 #if USE_PLL_HSE_EXTC != 0
bogdanm 0:9b334a45a8ff 357 if (SetSysClock_PLL_HSE(1) == 0)
bogdanm 0:9b334a45a8ff 358 #endif
bogdanm 0:9b334a45a8ff 359 {
bogdanm 0:9b334a45a8ff 360 /* 2- If fail try to start with HSE and external xtal */
bogdanm 0:9b334a45a8ff 361 #if USE_PLL_HSE_XTAL != 0
bogdanm 0:9b334a45a8ff 362 if (SetSysClock_PLL_HSE(0) == 0)
bogdanm 0:9b334a45a8ff 363 #endif
bogdanm 0:9b334a45a8ff 364 {
bogdanm 0:9b334a45a8ff 365 /* 3- If fail start with HSI or MSI clock */
bogdanm 0:9b334a45a8ff 366 #if (USE_PLL_HSI != 0)
bogdanm 0:9b334a45a8ff 367 if (SetSysClock_PLL_HSI() == 0)
bogdanm 0:9b334a45a8ff 368 #else
bogdanm 0:9b334a45a8ff 369 if (SetSysClock_PLL_MSI() == 0)
bogdanm 0:9b334a45a8ff 370 #endif
bogdanm 0:9b334a45a8ff 371 {
bogdanm 0:9b334a45a8ff 372 while(1)
bogdanm 0:9b334a45a8ff 373 {
bogdanm 0:9b334a45a8ff 374 // [TODO] Put something here to tell the user that a problem occured...
bogdanm 0:9b334a45a8ff 375 }
bogdanm 0:9b334a45a8ff 376 }
bogdanm 0:9b334a45a8ff 377 }
bogdanm 0:9b334a45a8ff 378 }
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 // Output clock on MCO1 pin(PA8) for debugging purpose
bogdanm 0:9b334a45a8ff 381 #if DEBUG_MCO == 1
bogdanm 0:9b334a45a8ff 382 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
bogdanm 0:9b334a45a8ff 383 #endif
bogdanm 0:9b334a45a8ff 384 }
bogdanm 0:9b334a45a8ff 385
bogdanm 0:9b334a45a8ff 386 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
bogdanm 0:9b334a45a8ff 387 /******************************************************************************/
bogdanm 0:9b334a45a8ff 388 /* PLL (clocked by HSE) used as System clock source */
bogdanm 0:9b334a45a8ff 389 /******************************************************************************/
bogdanm 0:9b334a45a8ff 390 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
bogdanm 0:9b334a45a8ff 391 {
bogdanm 0:9b334a45a8ff 392 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
bogdanm 0:9b334a45a8ff 393 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 // Used to gain time after DeepSleep in case HSI is used
bogdanm 0:9b334a45a8ff 396 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
bogdanm 0:9b334a45a8ff 397 {
bogdanm 0:9b334a45a8ff 398 return 0;
bogdanm 0:9b334a45a8ff 399 }
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 // Select MSI as system clock source to allow modification of the PLL configuration
bogdanm 0:9b334a45a8ff 402 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
bogdanm 0:9b334a45a8ff 403 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
bogdanm 0:9b334a45a8ff 404 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 // Enable HSE oscillator and activate PLL with HSE as source
bogdanm 0:9b334a45a8ff 407 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
bogdanm 0:9b334a45a8ff 408 if (bypass == 0)
bogdanm 0:9b334a45a8ff 409 {
bogdanm 0:9b334a45a8ff 410 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
bogdanm 0:9b334a45a8ff 411 }
bogdanm 0:9b334a45a8ff 412 else
bogdanm 0:9b334a45a8ff 413 {
bogdanm 0:9b334a45a8ff 414 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
bogdanm 0:9b334a45a8ff 415 }
bogdanm 0:9b334a45a8ff 416 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
bogdanm 0:9b334a45a8ff 417 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
bogdanm 0:9b334a45a8ff 418 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 // Non-USB configuration : sysclock = 80MHz
bogdanm 0:9b334a45a8ff 421 //RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
bogdanm 0:9b334a45a8ff 422 //RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
bogdanm 0:9b334a45a8ff 423 //RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
bogdanm 0:9b334a45a8ff 424 //RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
bogdanm 0:9b334a45a8ff 425 //RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 // USB configuration : sysclock = 48 MHz
bogdanm 0:9b334a45a8ff 428 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
bogdanm 0:9b334a45a8ff 429 RCC_OscInitStruct.PLL.PLLN = 24; // VCO output clock = 192 MHz (8 MHz * 24)
bogdanm 0:9b334a45a8ff 430 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
bogdanm 0:9b334a45a8ff 431 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
bogdanm 0:9b334a45a8ff 432 RCC_OscInitStruct.PLL.PLLR = 4; // PLL clock = 48 MHz (192 MHz / 4)
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 435 {
bogdanm 0:9b334a45a8ff 436 return 0; // FAIL
bogdanm 0:9b334a45a8ff 437 }
bogdanm 0:9b334a45a8ff 438
bogdanm 0:9b334a45a8ff 439 // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
bogdanm 0:9b334a45a8ff 440 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
bogdanm 0:9b334a45a8ff 441 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
bogdanm 0:9b334a45a8ff 442 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
bogdanm 0:9b334a45a8ff 443 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
bogdanm 0:9b334a45a8ff 444 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
bogdanm 0:9b334a45a8ff 445 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
bogdanm 0:9b334a45a8ff 446 {
bogdanm 0:9b334a45a8ff 447 return 0; // FAIL
bogdanm 0:9b334a45a8ff 448 }
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 // Disable MSI Oscillator
bogdanm 0:9b334a45a8ff 451 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
bogdanm 0:9b334a45a8ff 452 RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
bogdanm 0:9b334a45a8ff 453 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
bogdanm 0:9b334a45a8ff 454 HAL_RCC_OscConfig(&RCC_OscInitStruct);
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 // Output clock on MCO1 pin(PA8) for debugging purpose
bogdanm 0:9b334a45a8ff 457 #if DEBUG_MCO == 2
bogdanm 0:9b334a45a8ff 458 if (bypass == 0)
bogdanm 0:9b334a45a8ff 459 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
bogdanm 0:9b334a45a8ff 460 else
bogdanm 0:9b334a45a8ff 461 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
bogdanm 0:9b334a45a8ff 462 #endif
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 return 1; // OK
bogdanm 0:9b334a45a8ff 465 }
bogdanm 0:9b334a45a8ff 466 #endif
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 #if (USE_PLL_HSI != 0)
bogdanm 0:9b334a45a8ff 469 /******************************************************************************/
bogdanm 0:9b334a45a8ff 470 /* PLL (clocked by HSI) used as System clock source */
bogdanm 0:9b334a45a8ff 471 /******************************************************************************/
bogdanm 0:9b334a45a8ff 472 uint8_t SetSysClock_PLL_HSI(void)
bogdanm 0:9b334a45a8ff 473 {
bogdanm 0:9b334a45a8ff 474 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
bogdanm 0:9b334a45a8ff 475 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 // Select MSI as system clock source to allow modification of the PLL configuration
bogdanm 0:9b334a45a8ff 478 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
bogdanm 0:9b334a45a8ff 479 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
bogdanm 0:9b334a45a8ff 480 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
bogdanm 0:9b334a45a8ff 481
bogdanm 0:9b334a45a8ff 482 // Enable HSI oscillator and activate PLL with HSI as source
bogdanm 0:9b334a45a8ff 483 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 484 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
bogdanm 0:9b334a45a8ff 485 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
bogdanm 0:9b334a45a8ff 486 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
bogdanm 0:9b334a45a8ff 487 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 488 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
bogdanm 0:9b334a45a8ff 489 RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
bogdanm 0:9b334a45a8ff 490 RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
bogdanm 0:9b334a45a8ff 491 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
bogdanm 0:9b334a45a8ff 492 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
bogdanm 0:9b334a45a8ff 493 RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
bogdanm 0:9b334a45a8ff 494 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 495 {
bogdanm 0:9b334a45a8ff 496 return 0; // FAIL
bogdanm 0:9b334a45a8ff 497 }
bogdanm 0:9b334a45a8ff 498
bogdanm 0:9b334a45a8ff 499 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
bogdanm 0:9b334a45a8ff 500 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
bogdanm 0:9b334a45a8ff 501 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
bogdanm 0:9b334a45a8ff 502 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
bogdanm 0:9b334a45a8ff 503 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
bogdanm 0:9b334a45a8ff 504 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
bogdanm 0:9b334a45a8ff 505 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
bogdanm 0:9b334a45a8ff 506 {
bogdanm 0:9b334a45a8ff 507 return 0; // FAIL
bogdanm 0:9b334a45a8ff 508 }
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 // Disable MSI Oscillator
bogdanm 0:9b334a45a8ff 511 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
bogdanm 0:9b334a45a8ff 512 RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
bogdanm 0:9b334a45a8ff 513 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
bogdanm 0:9b334a45a8ff 514 HAL_RCC_OscConfig(&RCC_OscInitStruct);
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 // Output clock on MCO1 pin(PA8) for debugging purpose
bogdanm 0:9b334a45a8ff 517 #if DEBUG_MCO == 3
bogdanm 0:9b334a45a8ff 518 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
bogdanm 0:9b334a45a8ff 519 #endif
bogdanm 0:9b334a45a8ff 520
bogdanm 0:9b334a45a8ff 521 return 1; // OK
bogdanm 0:9b334a45a8ff 522 }
bogdanm 0:9b334a45a8ff 523 #endif
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 /******************************************************************************/
bogdanm 0:9b334a45a8ff 526 /* PLL (clocked by MSI) used as System clock source */
bogdanm 0:9b334a45a8ff 527 /******************************************************************************/
bogdanm 0:9b334a45a8ff 528 uint8_t SetSysClock_PLL_MSI(void)
bogdanm 0:9b334a45a8ff 529 {
bogdanm 0:9b334a45a8ff 530 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
bogdanm 0:9b334a45a8ff 531 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 // Enable LSE Oscillator to automatically calibrate the MSI clock
bogdanm 0:9b334a45a8ff 534 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
bogdanm 0:9b334a45a8ff 535 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
bogdanm 0:9b334a45a8ff 536 RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
bogdanm 0:9b334a45a8ff 537 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
bogdanm 0:9b334a45a8ff 538 RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
bogdanm 0:9b334a45a8ff 539 }
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541 // Enable MSI oscillator and activate PLL with MSI as source
bogdanm 0:9b334a45a8ff 542 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 543 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
bogdanm 0:9b334a45a8ff 544 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
bogdanm 0:9b334a45a8ff 545 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
bogdanm 0:9b334a45a8ff 546 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
bogdanm 0:9b334a45a8ff 547 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
bogdanm 0:9b334a45a8ff 548 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 549 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; // 4 MHz
bogdanm 0:9b334a45a8ff 550 RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 4 MHz (4 MHz / 1)
bogdanm 0:9b334a45a8ff 551 RCC_OscInitStruct.PLL.PLLN = 40; // VCO output clock = 160 MHz (4 MHz * 40)
bogdanm 0:9b334a45a8ff 552 RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22.86 MHz (160 MHz / 7)
bogdanm 0:9b334a45a8ff 553 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
bogdanm 0:9b334a45a8ff 554 RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
bogdanm 0:9b334a45a8ff 555 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
bogdanm 0:9b334a45a8ff 556 {
bogdanm 0:9b334a45a8ff 557 return 0; // FAIL
bogdanm 0:9b334a45a8ff 558 }
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
bogdanm 0:9b334a45a8ff 561 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
bogdanm 0:9b334a45a8ff 562 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
bogdanm 0:9b334a45a8ff 563 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
bogdanm 0:9b334a45a8ff 564 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
bogdanm 0:9b334a45a8ff 565 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
bogdanm 0:9b334a45a8ff 566 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
bogdanm 0:9b334a45a8ff 567 {
bogdanm 0:9b334a45a8ff 568 return 0; // FAIL
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571 // Output clock on MCO1 pin(PA8) for debugging purpose
bogdanm 0:9b334a45a8ff 572 #if DEBUG_MCO == 4
bogdanm 0:9b334a45a8ff 573 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
bogdanm 0:9b334a45a8ff 574 #endif
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 return 1; // OK
bogdanm 0:9b334a45a8ff 577 }
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /**
bogdanm 0:9b334a45a8ff 580 * @}
bogdanm 0:9b334a45a8ff 581 */
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 /**
bogdanm 0:9b334a45a8ff 584 * @}
bogdanm 0:9b334a45a8ff 585 */
bogdanm 0:9b334a45a8ff 586
bogdanm 0:9b334a45a8ff 587 /**
bogdanm 0:9b334a45a8ff 588 * @}
bogdanm 0:9b334a45a8ff 589 */
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/