mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l1xx_hal_adc.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application conversion
bogdanm	0:9b334a45a8ff	5	* @version V1.0.0
bogdanm	0:9b334a45a8ff	6	* @date 5-September-2014
bogdanm	0:9b334a45a8ff	7	* @brief This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	8	* functionalities of the Analog to Digital Convertor (ADC)
bogdanm	0:9b334a45a8ff	9	* peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* ++ Initialization and Configuration of ADC
bogdanm	0:9b334a45a8ff	12	* + Operation functions
bogdanm	0:9b334a45a8ff	13	* ++ Start, stop, get result of conversions of regular
bogdanm	0:9b334a45a8ff	14	* group, using 3 possible modes: polling, interruption or DMA.
bogdanm	0:9b334a45a8ff	15	* + Control functions
bogdanm	0:9b334a45a8ff	16	* ++ Analog Watchdog configuration
bogdanm	0:9b334a45a8ff	17	* ++ Channels configuration on regular group
bogdanm	0:9b334a45a8ff	18	* + State functions
bogdanm	0:9b334a45a8ff	19	* ++ ADC state machine management
bogdanm	0:9b334a45a8ff	20	* ++ Interrupts and flags management
bogdanm	0:9b334a45a8ff	21	* Other functions (extended functions) are available in file
bogdanm	0:9b334a45a8ff	22	* "stm32l1xx_hal_adc_ex.c".
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	@verbatim
bogdanm	0:9b334a45a8ff	25	==============================================================================
bogdanm	0:9b334a45a8ff	26	##### ADC specific features #####
bogdanm	0:9b334a45a8ff	27	==============================================================================
bogdanm	0:9b334a45a8ff	28	[..]
bogdanm	0:9b334a45a8ff	29	(#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
bogdanm	0:9b334a45a8ff	30
bogdanm	0:9b334a45a8ff	31	(#) Interrupt generation at the end of regular conversion, end of injected
bogdanm	0:9b334a45a8ff	32	conversion, and in case of analog watchdog or overrun events.
bogdanm	0:9b334a45a8ff	33
bogdanm	0:9b334a45a8ff	34	(#) Single and continuous conversion modes.
bogdanm	0:9b334a45a8ff	35
bogdanm	0:9b334a45a8ff	36	(#) Scan mode for automatic conversion of channel 0 to channel 'n'.
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	(#) Data alignment with in-built data coherency.
bogdanm	0:9b334a45a8ff	39
bogdanm	0:9b334a45a8ff	40	(#) Channel-wise programmable sampling time.
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	(#) ADC conversion Regular or Injected groups.
bogdanm	0:9b334a45a8ff	43
bogdanm	0:9b334a45a8ff	44	(#) External trigger (timer or EXTI) with configurable polarity for both
bogdanm	0:9b334a45a8ff	45	regular and injected groups.
bogdanm	0:9b334a45a8ff	46
bogdanm	0:9b334a45a8ff	47	(#) DMA request generation for transfer of conversions data of regular group.
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	(#) ADC calibration
bogdanm	0:9b334a45a8ff	50
bogdanm	0:9b334a45a8ff	51	(#) ADC offset on injected channels
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	(#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
bogdanm	0:9b334a45a8ff	54	slower speed.
bogdanm	0:9b334a45a8ff	55
bogdanm	0:9b334a45a8ff	56	(#) ADC input range: from Vref (connected to Vssa) to Vref+ (connected to
bogdanm	0:9b334a45a8ff	57	Vdda or to an external voltage reference).
bogdanm	0:9b334a45a8ff	58
bogdanm	0:9b334a45a8ff	59
bogdanm	0:9b334a45a8ff	60	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	61	==============================================================================
bogdanm	0:9b334a45a8ff	62	[..]
bogdanm	0:9b334a45a8ff	63
bogdanm	0:9b334a45a8ff	64	(#) Enable the ADC interface
bogdanm	0:9b334a45a8ff	65	As prerequisite, ADC clock must be configured at RCC top level.
bogdanm	0:9b334a45a8ff	66	Two clocks settings are mandatory:
bogdanm	0:9b334a45a8ff	67	- ADC clock (core clock):
bogdanm	0:9b334a45a8ff	68	Example:
bogdanm	0:9b334a45a8ff	69	Into HAL_ADC_MspInit() (recommended code location):
bogdanm	0:9b334a45a8ff	70	__ADC1_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	- ADC clock (conversions clock):
bogdanm	0:9b334a45a8ff	73	Only one possible clock source: derived from HSI RC 16MHz oscillator
bogdanm	0:9b334a45a8ff	74	(HSI).
bogdanm	0:9b334a45a8ff	75	Example:
bogdanm	0:9b334a45a8ff	76	Into HAL_ADC_MspInit() or with main setting of RCC:
bogdanm	0:9b334a45a8ff	77	RCC_OscInitTypeDef RCC_OscInitStructure;
bogdanm	0:9b334a45a8ff	78	HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
bogdanm	0:9b334a45a8ff	79	RCC_OscInitStructure.OscillatorType = (... \| RCC_OSCILLATORTYPE_HSI);
bogdanm	0:9b334a45a8ff	80	RCC_OscInitStructure.HSIState = RCC_HSI_ON;
bogdanm	0:9b334a45a8ff	81	RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
bogdanm	0:9b334a45a8ff	82	RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE;
bogdanm	0:9b334a45a8ff	83	RCC_OscInitStructure.PLL.PLLSource = ...
bogdanm	0:9b334a45a8ff	84	RCC_OscInitStructure.PLL...
bogdanm	0:9b334a45a8ff	85	HAL_RCC_OscConfig(&RCC_OscInitStructure);
bogdanm	0:9b334a45a8ff	86
bogdanm	0:9b334a45a8ff	87	Note: ADC is connected directly to HSI RC 16MHz oscillator.
bogdanm	0:9b334a45a8ff	88	Therefore, RCC PLL setting has no impact on ADC.
bogdanm	0:9b334a45a8ff	89	PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or
bogdanm	0:9b334a45a8ff	90	enabled with HSI16 as clock source
bogdanm	0:9b334a45a8ff	91	(".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device
bogdanm	0:9b334a45a8ff	92	main clock source SYSCLK.
bogdanm	0:9b334a45a8ff	93	The only mandatory setting is ".HSIState = RCC_HSI_ON"
bogdanm	0:9b334a45a8ff	94
bogdanm	0:9b334a45a8ff	95	Note: ADC clock prescaler is configured at ADC level with
bogdanm	0:9b334a45a8ff	96	parameter "ClockPrescaler" using function HAL_ADC_Init().
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	(#) ADC pins configuration
bogdanm	0:9b334a45a8ff	99	(++) Enable the clock for the ADC GPIOs using the following function:
bogdanm	0:9b334a45a8ff	100	__GPIOx_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	101	(++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
bogdanm	0:9b334a45a8ff	102
bogdanm	0:9b334a45a8ff	103	(#) Configure the ADC parameters (conversion resolution, data alignment,
bogdanm	0:9b334a45a8ff	104	continuous mode, ...) using the HAL_ADC_Init() function.
bogdanm	0:9b334a45a8ff	105
bogdanm	0:9b334a45a8ff	106	(#) Activate the ADC peripheral using one of the start functions:
bogdanm	0:9b334a45a8ff	107	HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA().
bogdanm	0:9b334a45a8ff	108
bogdanm	0:9b334a45a8ff	109	* Channels configuration to regular group *
bogdanm	0:9b334a45a8ff	110	================================================
bogdanm	0:9b334a45a8ff	111	[..]
bogdanm	0:9b334a45a8ff	112	(+) To configure the ADC regular group features, use
bogdanm	0:9b334a45a8ff	113	HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
bogdanm	0:9b334a45a8ff	114	(+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
bogdanm	0:9b334a45a8ff	115
bogdanm	0:9b334a45a8ff	116	* DMA for regular group configuration *
bogdanm	0:9b334a45a8ff	117	===========================================
bogdanm	0:9b334a45a8ff	118	[..]
bogdanm	0:9b334a45a8ff	119	(+) To enable the DMA mode for regular group, use the
bogdanm	0:9b334a45a8ff	120	HAL_ADC_Start_DMA() function.
bogdanm	0:9b334a45a8ff	121	(+) To enable the generation of DMA requests continuously at the end of
bogdanm	0:9b334a45a8ff	122	the last DMA transfer, use the HAL_ADC_Init() function.
bogdanm	0:9b334a45a8ff	123
bogdanm	0:9b334a45a8ff	124	@endverbatim
bogdanm	0:9b334a45a8ff	125	******************************************************************************
bogdanm	0:9b334a45a8ff	126	* @attention
bogdanm	0:9b334a45a8ff	127	*
bogdanm	0:9b334a45a8ff	128	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	129	*
bogdanm	0:9b334a45a8ff	130	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	131	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	132	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	133	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	134	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	135	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	136	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	137	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	138	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	139	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	140	*
bogdanm	0:9b334a45a8ff	141	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	142	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	143	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	144	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	145	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	146	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	147	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	148	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	149	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	150	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	151	*
bogdanm	0:9b334a45a8ff	152	******************************************************************************
bogdanm	0:9b334a45a8ff	153	*/
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	156	#include "stm32l1xx_hal.h"
bogdanm	0:9b334a45a8ff	157
bogdanm	0:9b334a45a8ff	158	/** @addtogroup STM32L1xx_HAL_Driver
bogdanm	0:9b334a45a8ff	159	* @{
bogdanm	0:9b334a45a8ff	160	*/
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	/** @defgroup ADC ADC
bogdanm	0:9b334a45a8ff	163	* @brief ADC HAL module driver
bogdanm	0:9b334a45a8ff	164	* @{
bogdanm	0:9b334a45a8ff	165	*/
bogdanm	0:9b334a45a8ff	166
bogdanm	0:9b334a45a8ff	167	#ifdef HAL_ADC_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	168
bogdanm	0:9b334a45a8ff	169	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	170	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	171	/** @defgroup ADC_Private_Constants ADC Private Constants
bogdanm	0:9b334a45a8ff	172	* @{
bogdanm	0:9b334a45a8ff	173	*/
bogdanm	0:9b334a45a8ff	174
bogdanm	0:9b334a45a8ff	175	/* Fixed timeout values for ADC calibration, enable settling time. */
bogdanm	0:9b334a45a8ff	176	/* Values defined to be higher than worst cases: low clocks freq, */
bogdanm	0:9b334a45a8ff	177	/* maximum prescaler. */
bogdanm	0:9b334a45a8ff	178	/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
bogdanm	0:9b334a45a8ff	179	/* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */
bogdanm	0:9b334a45a8ff	180	/* Unit: ms */
bogdanm	0:9b334a45a8ff	181	#define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
bogdanm	0:9b334a45a8ff	182	#define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	/* Delay for ADC stabilization time. */
bogdanm	0:9b334a45a8ff	185	/* Maximum delay is 3.5us (refer to device datasheet, parameter tSTAB). */
bogdanm	0:9b334a45a8ff	186	/* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 32MHz to */
bogdanm	0:9b334a45a8ff	187	/* have the minimum number of CPU cycles to fulfill this delay. */
bogdanm	0:9b334a45a8ff	188	#define ADC_STAB_DELAY_CPU_CYCLES ((uint32_t)112)
bogdanm	0:9b334a45a8ff	189	/**
bogdanm	0:9b334a45a8ff	190	* @}
bogdanm	0:9b334a45a8ff	191	*/
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	194	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	195	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	196	/** @defgroup ADC_Private_Functions ADC Private Functions
bogdanm	0:9b334a45a8ff	197	* @{
bogdanm	0:9b334a45a8ff	198	*/
bogdanm	0:9b334a45a8ff	199	static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	200	static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	201	static void ADC_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	202	/**
bogdanm	0:9b334a45a8ff	203	* @}
bogdanm	0:9b334a45a8ff	204	*/
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	207
bogdanm	0:9b334a45a8ff	208	/** @defgroup ADC_Exported_Functions ADC Exported Functions
bogdanm	0:9b334a45a8ff	209	* @{
bogdanm	0:9b334a45a8ff	210	*/
bogdanm	0:9b334a45a8ff	211
bogdanm	0:9b334a45a8ff	212	/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	213	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	214	*
bogdanm	0:9b334a45a8ff	215	@verbatim
bogdanm	0:9b334a45a8ff	216	===============================================================================
bogdanm	0:9b334a45a8ff	217	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	218	===============================================================================
bogdanm	0:9b334a45a8ff	219	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	220	(+) Initialize and configure the ADC.
bogdanm	0:9b334a45a8ff	221	(+) De-initialize the ADC
bogdanm	0:9b334a45a8ff	222	@endverbatim
bogdanm	0:9b334a45a8ff	223	* @{
bogdanm	0:9b334a45a8ff	224	*/
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	/**
bogdanm	0:9b334a45a8ff	227	* @brief Initializes the ADC peripheral and regular group according to
bogdanm	0:9b334a45a8ff	228	* parameters specified in structure "ADC_InitTypeDef".
bogdanm	0:9b334a45a8ff	229	* @note As prerequisite, ADC clock must be configured at RCC top level
bogdanm	0:9b334a45a8ff	230	* (clock source APB2).
bogdanm	0:9b334a45a8ff	231	* See commented example code below that can be copied and uncommented
bogdanm	0:9b334a45a8ff	232	* into HAL_ADC_MspInit().
bogdanm	0:9b334a45a8ff	233	* @note Possibility to update parameters on the fly:
bogdanm	0:9b334a45a8ff	234	* This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
bogdanm	0:9b334a45a8ff	235	* coming from ADC state reset. Following calls to this function can
bogdanm	0:9b334a45a8ff	236	* be used to reconfigure some parameters of ADC_InitTypeDef
bogdanm	0:9b334a45a8ff	237	* structure on the fly, without modifying MSP configuration. If ADC
bogdanm	0:9b334a45a8ff	238	* MSP has to be modified again, HAL_ADC_DeInit() must be called
bogdanm	0:9b334a45a8ff	239	* before HAL_ADC_Init().
bogdanm	0:9b334a45a8ff	240	* The setting of these parameters is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	241	* For parameters constraints, see comments of structure
bogdanm	0:9b334a45a8ff	242	* "ADC_InitTypeDef".
bogdanm	0:9b334a45a8ff	243	* @note This function configures the ADC within 2 scopes: scope of entire
bogdanm	0:9b334a45a8ff	244	* ADC and scope of regular group. For parameters details, see comments
bogdanm	0:9b334a45a8ff	245	* of structure "ADC_InitTypeDef".
bogdanm	0:9b334a45a8ff	246	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	247	* @retval HAL status
bogdanm	0:9b334a45a8ff	248	*/
bogdanm	0:9b334a45a8ff	249	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	250	{
bogdanm	0:9b334a45a8ff	251	HAL_StatusTypeDef tmpHALStatus = HAL_OK;
bogdanm	0:9b334a45a8ff	252	uint32_t tmp_cr1 = 0;
bogdanm	0:9b334a45a8ff	253	uint32_t tmp_cr2 = 0;
bogdanm	0:9b334a45a8ff	254
bogdanm	0:9b334a45a8ff	255	/* Check ADC handle */
bogdanm	0:9b334a45a8ff	256	if(hadc == HAL_NULL)
bogdanm	0:9b334a45a8ff	257	{
bogdanm	0:9b334a45a8ff	258	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	259	}
bogdanm	0:9b334a45a8ff	260
bogdanm	0:9b334a45a8ff	261	/* Check the parameters */
bogdanm	0:9b334a45a8ff	262	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	263	assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
bogdanm	0:9b334a45a8ff	264	assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
bogdanm	0:9b334a45a8ff	265	assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
bogdanm	0:9b334a45a8ff	266	assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
bogdanm	0:9b334a45a8ff	267	assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
bogdanm	0:9b334a45a8ff	268	assert_param(IS_ADC_AUTOWAIT(hadc->Init.LowPowerAutoWait));
bogdanm	0:9b334a45a8ff	269	assert_param(IS_ADC_AUTOPOWEROFF(hadc->Init.LowPowerAutoPowerOff));
bogdanm	0:9b334a45a8ff	270	assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank));
bogdanm	0:9b334a45a8ff	271	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	272	assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
bogdanm	0:9b334a45a8ff	273	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
bogdanm	0:9b334a45a8ff	274
bogdanm	0:9b334a45a8ff	275	if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
bogdanm	0:9b334a45a8ff	276	{
bogdanm	0:9b334a45a8ff	277	assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
bogdanm	0:9b334a45a8ff	278	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
bogdanm	0:9b334a45a8ff	279	assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
bogdanm	0:9b334a45a8ff	280	}
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282	if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
bogdanm	0:9b334a45a8ff	283	{
bogdanm	0:9b334a45a8ff	284	assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
bogdanm	0:9b334a45a8ff	285	}
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	/* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
bogdanm	0:9b334a45a8ff	289	/* at RCC top level. */
bogdanm	0:9b334a45a8ff	290	/* Refer to header of this file for more details on clock enabling */
bogdanm	0:9b334a45a8ff	291	/* procedure. */
bogdanm	0:9b334a45a8ff	292
bogdanm	0:9b334a45a8ff	293	/* Actions performed only if ADC is coming from state reset: */
bogdanm	0:9b334a45a8ff	294	/* - Initialization of ADC MSP */
bogdanm	0:9b334a45a8ff	295	if (hadc->State == HAL_ADC_STATE_RESET)
bogdanm	0:9b334a45a8ff	296	{
bogdanm	0:9b334a45a8ff	297	/* Enable SYSCFG clock to control the routing Interface (RI) */
bogdanm	0:9b334a45a8ff	298	__SYSCFG_CLK_ENABLE();
bogdanm	0:9b334a45a8ff	299
bogdanm	0:9b334a45a8ff	300	/* Init the low level hardware */
bogdanm	0:9b334a45a8ff	301	HAL_ADC_MspInit(hadc);
bogdanm	0:9b334a45a8ff	302	}
bogdanm	0:9b334a45a8ff	303
bogdanm	0:9b334a45a8ff	304	/* Configuration of ADC parameters if previous preliminary actions are */
bogdanm	0:9b334a45a8ff	305	/* correctly completed. */
bogdanm	0:9b334a45a8ff	306	if (tmpHALStatus != HAL_ERROR)
bogdanm	0:9b334a45a8ff	307	{
bogdanm	0:9b334a45a8ff	308	/* Initialize the ADC state */
bogdanm	0:9b334a45a8ff	309	hadc->State = HAL_ADC_STATE_BUSY;
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311	/* Set ADC parameters */
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	/* Configuration of common ADC clock: clock source HSI with selectable */
bogdanm	0:9b334a45a8ff	314	/* prescaler */
bogdanm	0:9b334a45a8ff	315	MODIFY_REG(ADC->CCR ,
bogdanm	0:9b334a45a8ff	316	ADC_CCR_ADCPRE ,
bogdanm	0:9b334a45a8ff	317	hadc->Init.ClockPrescaler );
bogdanm	0:9b334a45a8ff	318
bogdanm	0:9b334a45a8ff	319	/* Configuration of ADC: */
bogdanm	0:9b334a45a8ff	320	/* - external trigger polarity */
bogdanm	0:9b334a45a8ff	321	/* - End of conversion selection */
bogdanm	0:9b334a45a8ff	322	/* - DMA continuous request */
bogdanm	0:9b334a45a8ff	323	/* - Channels bank (Banks availability depends on devices categories) */
bogdanm	0:9b334a45a8ff	324	/* - continuous conversion mode */
bogdanm	0:9b334a45a8ff	325	tmp_cr2 \|= (hadc->Init.DataAlign \|
bogdanm	0:9b334a45a8ff	326	hadc->Init.EOCSelection \|
bogdanm	0:9b334a45a8ff	327	__ADC_CR2_DMACONTREQ(hadc->Init.DMAContinuousRequests) \|
bogdanm	0:9b334a45a8ff	328	hadc->Init.ChannelsBank \|
bogdanm	0:9b334a45a8ff	329	__ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
bogdanm	0:9b334a45a8ff	330
bogdanm	0:9b334a45a8ff	331	/* Enable external trigger if trigger selection is different of software */
bogdanm	0:9b334a45a8ff	332	/* start. */
bogdanm	0:9b334a45a8ff	333	/* Note: This configuration keeps the hardware feature of parameter */
bogdanm	0:9b334a45a8ff	334	/* ExternalTrigConvEdge "trigger edge none" equivalent to */
bogdanm	0:9b334a45a8ff	335	/* software start. */
bogdanm	0:9b334a45a8ff	336	if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
bogdanm	0:9b334a45a8ff	337	{
bogdanm	0:9b334a45a8ff	338	tmp_cr2 \|= ( hadc->Init.ExternalTrigConv \|
bogdanm	0:9b334a45a8ff	339	hadc->Init.ExternalTrigConvEdge );
bogdanm	0:9b334a45a8ff	340	}
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	/* Parameters update conditioned to ADC state: */
bogdanm	0:9b334a45a8ff	343	/* Parameters that can be updated only when ADC is disabled: */
bogdanm	0:9b334a45a8ff	344	/* - delay selection (LowPowerAutoWait mode) */
bogdanm	0:9b334a45a8ff	345	/* - resolution */
bogdanm	0:9b334a45a8ff	346	/* - auto power off (LowPowerAutoPowerOff mode) */
bogdanm	0:9b334a45a8ff	347	/* - scan mode */
bogdanm	0:9b334a45a8ff	348	/* - discontinuous mode disable/enable */
bogdanm	0:9b334a45a8ff	349	/* - discontinuous mode number of conversions */
bogdanm	0:9b334a45a8ff	350	if ((__HAL_ADC_IS_ENABLED(hadc) == RESET))
bogdanm	0:9b334a45a8ff	351	{
bogdanm	0:9b334a45a8ff	352	tmp_cr2 \|= hadc->Init.LowPowerAutoWait;
bogdanm	0:9b334a45a8ff	353
bogdanm	0:9b334a45a8ff	354	tmp_cr1 \|= (hadc->Init.Resolution \|
bogdanm	0:9b334a45a8ff	355	hadc->Init.LowPowerAutoPowerOff \|
bogdanm	0:9b334a45a8ff	356	__ADC_CR1_SCAN(hadc->Init.ScanConvMode) );
bogdanm	0:9b334a45a8ff	357
bogdanm	0:9b334a45a8ff	358	/* Enable discontinuous mode only if continuous mode is disabled */
bogdanm	0:9b334a45a8ff	359	if ((hadc->Init.DiscontinuousConvMode == ENABLE) &&
bogdanm	0:9b334a45a8ff	360	(hadc->Init.ContinuousConvMode == DISABLE) )
bogdanm	0:9b334a45a8ff	361	{
bogdanm	0:9b334a45a8ff	362	/* Enable discontinuous mode of regular group */
bogdanm	0:9b334a45a8ff	363	/* Set the number of channels to be converted in discontinuous mode */
bogdanm	0:9b334a45a8ff	364	tmp_cr1 \|= ((ADC_CR1_DISCEN) \|
bogdanm	0:9b334a45a8ff	365	__ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion));
bogdanm	0:9b334a45a8ff	366	}
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/* Update ADC configuration register CR1 with previous settings */
bogdanm	0:9b334a45a8ff	369	MODIFY_REG(hadc->Instance->CR1,
bogdanm	0:9b334a45a8ff	370	ADC_CR1_RES \|
bogdanm	0:9b334a45a8ff	371	ADC_CR1_PDI \|
bogdanm	0:9b334a45a8ff	372	ADC_CR1_PDD \|
bogdanm	0:9b334a45a8ff	373	ADC_CR1_DISCNUM \|
bogdanm	0:9b334a45a8ff	374	ADC_CR1_DISCEN \|
bogdanm	0:9b334a45a8ff	375	ADC_CR1_SCAN ,
bogdanm	0:9b334a45a8ff	376	tmp_cr1 );
bogdanm	0:9b334a45a8ff	377	}
bogdanm	0:9b334a45a8ff	378
bogdanm	0:9b334a45a8ff	379	/* Update ADC configuration register CR2 with previous settings */
bogdanm	0:9b334a45a8ff	380	MODIFY_REG(hadc->Instance->CR2 ,
bogdanm	0:9b334a45a8ff	381	__ADC_CR2_MASK_ADCINIT() ,
bogdanm	0:9b334a45a8ff	382	tmp_cr2 );
bogdanm	0:9b334a45a8ff	383
bogdanm	0:9b334a45a8ff	384	/* Configuration of regular group sequencer: */
bogdanm	0:9b334a45a8ff	385	/* - if scan mode is disabled, regular channels sequence length is set to */
bogdanm	0:9b334a45a8ff	386	/* 0x00: 1 channel converted (channel on regular rank 1) */
bogdanm	0:9b334a45a8ff	387	/* Parameter "NbrOfConversion" is discarded. */
bogdanm	0:9b334a45a8ff	388	/* Note: Scan mode is present by hardware on this device and, if */
bogdanm	0:9b334a45a8ff	389	/* disabled, discards automatically nb of conversions. Anyway, nb of */
bogdanm	0:9b334a45a8ff	390	/* conversions is forced to 0x00 for alignment over all STM32 devices. */
bogdanm	0:9b334a45a8ff	391	/* - if scan mode is enabled, regular channels sequence length is set to */
bogdanm	0:9b334a45a8ff	392	/* parameter "NbrOfConversion" */
bogdanm	0:9b334a45a8ff	393	if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
bogdanm	0:9b334a45a8ff	394	{
bogdanm	0:9b334a45a8ff	395	MODIFY_REG(hadc->Instance->SQR1 ,
bogdanm	0:9b334a45a8ff	396	ADC_SQR1_L ,
bogdanm	0:9b334a45a8ff	397	__ADC_SQR1_L(hadc->Init.NbrOfConversion) );
bogdanm	0:9b334a45a8ff	398	}
bogdanm	0:9b334a45a8ff	399	else
bogdanm	0:9b334a45a8ff	400	{
bogdanm	0:9b334a45a8ff	401	MODIFY_REG(hadc->Instance->SQR1,
bogdanm	0:9b334a45a8ff	402	ADC_SQR1_L ,
bogdanm	0:9b334a45a8ff	403	0x00000000 );
bogdanm	0:9b334a45a8ff	404	}
bogdanm	0:9b334a45a8ff	405
bogdanm	0:9b334a45a8ff	406	/* Check back that ADC registers have effectively been configured to */
bogdanm	0:9b334a45a8ff	407	/* ensure of no potential problem of ADC core IP clocking. */
bogdanm	0:9b334a45a8ff	408	/* Check through register CR2 (excluding execution control bits ADON, */
bogdanm	0:9b334a45a8ff	409	/* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL). */
bogdanm	0:9b334a45a8ff	410	if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON \|
bogdanm	0:9b334a45a8ff	411	ADC_CR2_SWSTART \| ADC_CR2_JSWSTART \|
bogdanm	0:9b334a45a8ff	412	ADC_CR2_JEXTEN \| ADC_CR2_JEXTSEL ))
bogdanm	0:9b334a45a8ff	413	== tmp_cr2)
bogdanm	0:9b334a45a8ff	414	{
bogdanm	0:9b334a45a8ff	415	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	416	__HAL_ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	417
bogdanm	0:9b334a45a8ff	418	/* Initialize the ADC state */
bogdanm	0:9b334a45a8ff	419	hadc->State = HAL_ADC_STATE_READY;
bogdanm	0:9b334a45a8ff	420	}
bogdanm	0:9b334a45a8ff	421	else
bogdanm	0:9b334a45a8ff	422	{
bogdanm	0:9b334a45a8ff	423	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	424	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	425
bogdanm	0:9b334a45a8ff	426	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	427	hadc->ErrorCode \|= HAL_ADC_ERROR_INTERNAL;
bogdanm	0:9b334a45a8ff	428
bogdanm	0:9b334a45a8ff	429	tmpHALStatus = HAL_ERROR;
bogdanm	0:9b334a45a8ff	430	}
bogdanm	0:9b334a45a8ff	431
bogdanm	0:9b334a45a8ff	432	}
bogdanm	0:9b334a45a8ff	433	else
bogdanm	0:9b334a45a8ff	434	{
bogdanm	0:9b334a45a8ff	435	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	436	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	437
bogdanm	0:9b334a45a8ff	438	tmpHALStatus = HAL_ERROR;
bogdanm	0:9b334a45a8ff	439	}
bogdanm	0:9b334a45a8ff	440
bogdanm	0:9b334a45a8ff	441	/* Return function status */
bogdanm	0:9b334a45a8ff	442	return tmpHALStatus;
bogdanm	0:9b334a45a8ff	443	}
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	/**
bogdanm	0:9b334a45a8ff	446	* @brief Deinitialize the ADC peripheral registers to its default reset values.
bogdanm	0:9b334a45a8ff	447	* @note To not impact other ADCs, reset of common ADC registers have been
bogdanm	0:9b334a45a8ff	448	* left commented below.
bogdanm	0:9b334a45a8ff	449	* If needed, the example code can be copied and uncommented into
bogdanm	0:9b334a45a8ff	450	* function HAL_ADC_MspDeInit().
bogdanm	0:9b334a45a8ff	451	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	452	* @retval HAL status
bogdanm	0:9b334a45a8ff	453	*/
bogdanm	0:9b334a45a8ff	454	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	455	{
bogdanm	0:9b334a45a8ff	456	HAL_StatusTypeDef tmpHALStatus = HAL_OK;
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	/* Check ADC handle */
bogdanm	0:9b334a45a8ff	459	if(hadc == HAL_NULL)
bogdanm	0:9b334a45a8ff	460	{
bogdanm	0:9b334a45a8ff	461	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	462	}
bogdanm	0:9b334a45a8ff	463
bogdanm	0:9b334a45a8ff	464	/* Check the parameters */
bogdanm	0:9b334a45a8ff	465	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	466
bogdanm	0:9b334a45a8ff	467	/* Change ADC state */
bogdanm	0:9b334a45a8ff	468	hadc->State = HAL_ADC_STATE_BUSY;
bogdanm	0:9b334a45a8ff	469
bogdanm	0:9b334a45a8ff	470	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	471	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	472	tmpHALStatus = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	473
bogdanm	0:9b334a45a8ff	474
bogdanm	0:9b334a45a8ff	475	/* Configuration of ADC parameters if previous preliminary actions are */
bogdanm	0:9b334a45a8ff	476	/* correctly completed. */
bogdanm	0:9b334a45a8ff	477	if (tmpHALStatus != HAL_ERROR)
bogdanm	0:9b334a45a8ff	478	{
bogdanm	0:9b334a45a8ff	479	/* ========== Reset ADC registers ========== */
bogdanm	0:9b334a45a8ff	480	/* Reset register SR */
bogdanm	0:9b334a45a8ff	481	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD \| ADC_FLAG_JEOC \| ADC_FLAG_EOC \|
bogdanm	0:9b334a45a8ff	482	ADC_FLAG_JSTRT \| ADC_FLAG_STRT));
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	/* Reset register CR1 */
bogdanm	0:9b334a45a8ff	485	CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_OVRIE \| ADC_CR1_RES \| ADC_CR1_AWDEN \|
bogdanm	0:9b334a45a8ff	486	ADC_CR1_JAWDEN \| ADC_CR1_PDI \| ADC_CR1_PDD \|
bogdanm	0:9b334a45a8ff	487	ADC_CR1_DISCNUM \| ADC_CR1_JDISCEN \| ADC_CR1_DISCEN \|
bogdanm	0:9b334a45a8ff	488	ADC_CR1_JAUTO \| ADC_CR1_AWDSGL \| ADC_CR1_SCAN \|
bogdanm	0:9b334a45a8ff	489	ADC_CR1_JEOCIE \| ADC_CR1_AWDIE \| ADC_CR1_EOCIE \|
bogdanm	0:9b334a45a8ff	490	ADC_CR1_AWDCH ));
bogdanm	0:9b334a45a8ff	491
bogdanm	0:9b334a45a8ff	492	/* Reset register CR2 */
bogdanm	0:9b334a45a8ff	493	__ADC_CR2_CLEAR(hadc);
bogdanm	0:9b334a45a8ff	494
bogdanm	0:9b334a45a8ff	495	/* Reset register SMPR0 */
bogdanm	0:9b334a45a8ff	496	__ADC_SMPR0_CLEAR(hadc);
bogdanm	0:9b334a45a8ff	497
bogdanm	0:9b334a45a8ff	498	/* Reset register SMPR1 */
bogdanm	0:9b334a45a8ff	499	CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP29 \| ADC_SMPR1_SMP28 \| ADC_SMPR1_SMP27 \|
bogdanm	0:9b334a45a8ff	500	ADC_SMPR1_SMP26 \| ADC_SMPR1_SMP25 \| ADC_SMPR1_SMP24 \|
bogdanm	0:9b334a45a8ff	501	ADC_SMPR1_SMP23 \| ADC_SMPR1_SMP22 \| ADC_SMPR1_SMP21 \|
bogdanm	0:9b334a45a8ff	502	ADC_SMPR1_SMP20 ));
bogdanm	0:9b334a45a8ff	503
bogdanm	0:9b334a45a8ff	504	/* Reset register SMPR2 */
bogdanm	0:9b334a45a8ff	505	CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP19 \| ADC_SMPR2_SMP18 \| ADC_SMPR2_SMP17 \|
bogdanm	0:9b334a45a8ff	506	ADC_SMPR2_SMP16 \| ADC_SMPR2_SMP15 \| ADC_SMPR2_SMP14 \|
bogdanm	0:9b334a45a8ff	507	ADC_SMPR2_SMP13 \| ADC_SMPR2_SMP12 \| ADC_SMPR2_SMP11 \|
bogdanm	0:9b334a45a8ff	508	ADC_SMPR2_SMP10 ));
bogdanm	0:9b334a45a8ff	509
bogdanm	0:9b334a45a8ff	510	/* Reset register SMPR3 */
bogdanm	0:9b334a45a8ff	511	CLEAR_BIT(hadc->Instance->SMPR3, (ADC_SMPR3_SMP9 \| ADC_SMPR3_SMP8 \| ADC_SMPR3_SMP7 \|
bogdanm	0:9b334a45a8ff	512	ADC_SMPR3_SMP6 \| ADC_SMPR3_SMP5 \| ADC_SMPR3_SMP4 \|
bogdanm	0:9b334a45a8ff	513	ADC_SMPR3_SMP3 \| ADC_SMPR3_SMP2 \| ADC_SMPR3_SMP1 \|
bogdanm	0:9b334a45a8ff	514	ADC_SMPR3_SMP0 ));
bogdanm	0:9b334a45a8ff	515
bogdanm	0:9b334a45a8ff	516	/* Reset register JOFR1 */
bogdanm	0:9b334a45a8ff	517	CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
bogdanm	0:9b334a45a8ff	518	/* Reset register JOFR2 */
bogdanm	0:9b334a45a8ff	519	CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
bogdanm	0:9b334a45a8ff	520	/* Reset register JOFR3 */
bogdanm	0:9b334a45a8ff	521	CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
bogdanm	0:9b334a45a8ff	522	/* Reset register JOFR4 */
bogdanm	0:9b334a45a8ff	523	CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525	/* Reset register HTR */
bogdanm	0:9b334a45a8ff	526	CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
bogdanm	0:9b334a45a8ff	527	/* Reset register LTR */
bogdanm	0:9b334a45a8ff	528	CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
bogdanm	0:9b334a45a8ff	529
bogdanm	0:9b334a45a8ff	530	/* Reset register SQR1 */
bogdanm	0:9b334a45a8ff	531	CLEAR_BIT(hadc->Instance->SQR1, (ADC_SQR1_L \| __ADC_SQR1_SQXX));
bogdanm	0:9b334a45a8ff	532
bogdanm	0:9b334a45a8ff	533	/* Reset register SQR2 */
bogdanm	0:9b334a45a8ff	534	CLEAR_BIT(hadc->Instance->SQR2, (ADC_SQR2_SQ24 \| ADC_SQR2_SQ23 \| ADC_SQR2_SQ22 \|
bogdanm	0:9b334a45a8ff	535	ADC_SQR2_SQ21 \| ADC_SQR2_SQ20 \| ADC_SQR2_SQ19 ));
bogdanm	0:9b334a45a8ff	536
bogdanm	0:9b334a45a8ff	537	/* Reset register SQR3 */
bogdanm	0:9b334a45a8ff	538	CLEAR_BIT(hadc->Instance->SQR3, (ADC_SQR3_SQ18 \| ADC_SQR3_SQ17 \| ADC_SQR3_SQ16 \|
bogdanm	0:9b334a45a8ff	539	ADC_SQR3_SQ15 \| ADC_SQR3_SQ14 \| ADC_SQR3_SQ13 ));
bogdanm	0:9b334a45a8ff	540
bogdanm	0:9b334a45a8ff	541	/* Reset register SQR4 */
bogdanm	0:9b334a45a8ff	542	CLEAR_BIT(hadc->Instance->SQR4, (ADC_SQR4_SQ12 \| ADC_SQR4_SQ11 \| ADC_SQR4_SQ10 \|
bogdanm	0:9b334a45a8ff	543	ADC_SQR4_SQ9 \| ADC_SQR4_SQ8 \| ADC_SQR4_SQ7 ));
bogdanm	0:9b334a45a8ff	544
bogdanm	0:9b334a45a8ff	545	/* Reset register SQR5 */
bogdanm	0:9b334a45a8ff	546	CLEAR_BIT(hadc->Instance->SQR5, (ADC_SQR5_SQ6 \| ADC_SQR5_SQ5 \| ADC_SQR5_SQ4 \|
bogdanm	0:9b334a45a8ff	547	ADC_SQR5_SQ3 \| ADC_SQR5_SQ2 \| ADC_SQR5_SQ1 ));
bogdanm	0:9b334a45a8ff	548
bogdanm	0:9b334a45a8ff	549
bogdanm	0:9b334a45a8ff	550	/* Reset register JSQR */
bogdanm	0:9b334a45a8ff	551	CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL \|
bogdanm	0:9b334a45a8ff	552	ADC_JSQR_JSQ4 \| ADC_JSQR_JSQ3 \|
bogdanm	0:9b334a45a8ff	553	ADC_JSQR_JSQ2 \| ADC_JSQR_JSQ1 ));
bogdanm	0:9b334a45a8ff	554
bogdanm	0:9b334a45a8ff	555	/* Reset register JSQR */
bogdanm	0:9b334a45a8ff	556	CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL \|
bogdanm	0:9b334a45a8ff	557	ADC_JSQR_JSQ4 \| ADC_JSQR_JSQ3 \|
bogdanm	0:9b334a45a8ff	558	ADC_JSQR_JSQ2 \| ADC_JSQR_JSQ1 ));
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	/* Reset register DR */
bogdanm	0:9b334a45a8ff	561	/* bits in access mode read only, no direct reset applicable*/
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	/* Reset registers JDR1, JDR2, JDR3, JDR4 */
bogdanm	0:9b334a45a8ff	564	/* bits in access mode read only, no direct reset applicable*/
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566	/* Reset register CCR */
bogdanm	0:9b334a45a8ff	567	CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE);
bogdanm	0:9b334a45a8ff	568
bogdanm	0:9b334a45a8ff	569	/* ========== Hard reset ADC peripheral ========== */
bogdanm	0:9b334a45a8ff	570	/* Performs a global reset of the entire ADC peripheral: ADC state is */
bogdanm	0:9b334a45a8ff	571	/* forced to a similar state after device power-on. */
bogdanm	0:9b334a45a8ff	572	/* If needed, copy-paste and uncomment the following reset code into */
bogdanm	0:9b334a45a8ff	573	/* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
bogdanm	0:9b334a45a8ff	574	/* */
bogdanm	0:9b334a45a8ff	575	/* __ADC1_FORCE_RESET() */
bogdanm	0:9b334a45a8ff	576	/* __ADC1_RELEASE_RESET() */
bogdanm	0:9b334a45a8ff	577
bogdanm	0:9b334a45a8ff	578	/* DeInit the low level hardware */
bogdanm	0:9b334a45a8ff	579	HAL_ADC_MspDeInit(hadc);
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	582	__HAL_ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	583
bogdanm	0:9b334a45a8ff	584	/* Change ADC state */
bogdanm	0:9b334a45a8ff	585	hadc->State = HAL_ADC_STATE_RESET;
bogdanm	0:9b334a45a8ff	586
bogdanm	0:9b334a45a8ff	587	}
bogdanm	0:9b334a45a8ff	588
bogdanm	0:9b334a45a8ff	589	/* Process unlocked */
bogdanm	0:9b334a45a8ff	590	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	/* Return function status */
bogdanm	0:9b334a45a8ff	593	return tmpHALStatus;
bogdanm	0:9b334a45a8ff	594	}
bogdanm	0:9b334a45a8ff	595
bogdanm	0:9b334a45a8ff	596	/**
bogdanm	0:9b334a45a8ff	597	* @brief Initializes the ADC MSP.
bogdanm	0:9b334a45a8ff	598	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	599	* @retval None
bogdanm	0:9b334a45a8ff	600	*/
bogdanm	0:9b334a45a8ff	601	__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	602	{
bogdanm	0:9b334a45a8ff	603	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	604	function HAL_ADC_MspInit must be implemented in the user file.
bogdanm	0:9b334a45a8ff	605	*/
bogdanm	0:9b334a45a8ff	606	}
bogdanm	0:9b334a45a8ff	607
bogdanm	0:9b334a45a8ff	608	/**
bogdanm	0:9b334a45a8ff	609	* @brief DeInitializes the ADC MSP.
bogdanm	0:9b334a45a8ff	610	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	611	* @retval None
bogdanm	0:9b334a45a8ff	612	*/
bogdanm	0:9b334a45a8ff	613	__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	614	{
bogdanm	0:9b334a45a8ff	615	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	616	function HAL_ADC_MspDeInit must be implemented in the user file.
bogdanm	0:9b334a45a8ff	617	*/
bogdanm	0:9b334a45a8ff	618	}
bogdanm	0:9b334a45a8ff	619
bogdanm	0:9b334a45a8ff	620	/**
bogdanm	0:9b334a45a8ff	621	* @}
bogdanm	0:9b334a45a8ff	622	*/
bogdanm	0:9b334a45a8ff	623
bogdanm	0:9b334a45a8ff	624	/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	625	* @brief IO operation functions
bogdanm	0:9b334a45a8ff	626	*
bogdanm	0:9b334a45a8ff	627	@verbatim
bogdanm	0:9b334a45a8ff	628	===============================================================================
bogdanm	0:9b334a45a8ff	629	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	630	===============================================================================
bogdanm	0:9b334a45a8ff	631	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	632	(+) Start conversion of regular group.
bogdanm	0:9b334a45a8ff	633	(+) Stop conversion of regular group.
bogdanm	0:9b334a45a8ff	634	(+) Poll for conversion complete on regular group.
bogdanm	0:9b334a45a8ff	635	(+) Poll for conversion event.
bogdanm	0:9b334a45a8ff	636	(+) Get result of regular channel conversion.
bogdanm	0:9b334a45a8ff	637	(+) Start conversion of regular group and enable interruptions.
bogdanm	0:9b334a45a8ff	638	(+) Stop conversion of regular group and disable interruptions.
bogdanm	0:9b334a45a8ff	639	(+) Handle ADC interrupt request
bogdanm	0:9b334a45a8ff	640	(+) Start conversion of regular group and enable DMA transfer.
bogdanm	0:9b334a45a8ff	641	(+) Stop conversion of regular group and disable ADC DMA transfer.
bogdanm	0:9b334a45a8ff	642	@endverbatim
bogdanm	0:9b334a45a8ff	643	* @{
bogdanm	0:9b334a45a8ff	644	*/
bogdanm	0:9b334a45a8ff	645
bogdanm	0:9b334a45a8ff	646	/**
bogdanm	0:9b334a45a8ff	647	* @brief Enables ADC, starts conversion of regular group.
bogdanm	0:9b334a45a8ff	648	* Interruptions enabled in this function: None.
bogdanm	0:9b334a45a8ff	649	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	650	* @retval HAL status
bogdanm	0:9b334a45a8ff	651	*/
bogdanm	0:9b334a45a8ff	652	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	653	{
bogdanm	0:9b334a45a8ff	654	HAL_StatusTypeDef tmpHALStatus = HAL_OK;
bogdanm	0:9b334a45a8ff	655
bogdanm	0:9b334a45a8ff	656	/* Check the parameters */
bogdanm	0:9b334a45a8ff	657	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	658
bogdanm	0:9b334a45a8ff	659	/* Process locked */
bogdanm	0:9b334a45a8ff	660	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	661
bogdanm	0:9b334a45a8ff	662	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	663	tmpHALStatus = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	664
bogdanm	0:9b334a45a8ff	665	/* Start conversion if ADC is effectively enabled */
bogdanm	0:9b334a45a8ff	666	if (tmpHALStatus != HAL_ERROR)
bogdanm	0:9b334a45a8ff	667	{
bogdanm	0:9b334a45a8ff	668	/* State machine update: Check if an injected conversion is ongoing */
bogdanm	0:9b334a45a8ff	669	if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
bogdanm	0:9b334a45a8ff	670	{
bogdanm	0:9b334a45a8ff	671	/* Change ADC state */
bogdanm	0:9b334a45a8ff	672	hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
bogdanm	0:9b334a45a8ff	673	}
bogdanm	0:9b334a45a8ff	674	else
bogdanm	0:9b334a45a8ff	675	{
bogdanm	0:9b334a45a8ff	676	/* Change ADC state */
bogdanm	0:9b334a45a8ff	677	hadc->State = HAL_ADC_STATE_BUSY_REG;
bogdanm	0:9b334a45a8ff	678	}
bogdanm	0:9b334a45a8ff	679
bogdanm	0:9b334a45a8ff	680	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	681	__HAL_ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	682
bogdanm	0:9b334a45a8ff	683	/* Clear regular group conversion flag and overrun flag */
bogdanm	0:9b334a45a8ff	684	/* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm	0:9b334a45a8ff	685	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	686
bogdanm	0:9b334a45a8ff	687	/* Start conversion of regular group if software start has been selected. */
bogdanm	0:9b334a45a8ff	688	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	689	/* trigger event. */
bogdanm	0:9b334a45a8ff	690	if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc))
bogdanm	0:9b334a45a8ff	691	{
bogdanm	0:9b334a45a8ff	692	/* Start ADC conversion on regular group */
bogdanm	0:9b334a45a8ff	693	SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
bogdanm	0:9b334a45a8ff	694	}
bogdanm	0:9b334a45a8ff	695	}
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697	/* Process unlocked */
bogdanm	0:9b334a45a8ff	698	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	699
bogdanm	0:9b334a45a8ff	700	/* Return function status */
bogdanm	0:9b334a45a8ff	701	return tmpHALStatus;
bogdanm	0:9b334a45a8ff	702	}
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	/**
bogdanm	0:9b334a45a8ff	705	* @brief Stop ADC conversion of regular group (and injected channels in
bogdanm	0:9b334a45a8ff	706	* case of auto_injection mode), disable ADC peripheral.
bogdanm	0:9b334a45a8ff	707	* @note: ADC peripheral disable is forcing interruption of potential
bogdanm	0:9b334a45a8ff	708	* conversion on injected group. If injected group is under use, it
bogdanm	0:9b334a45a8ff	709	* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
bogdanm	0:9b334a45a8ff	710	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	711	* @retval HAL status.
bogdanm	0:9b334a45a8ff	712	*/
bogdanm	0:9b334a45a8ff	713	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	714	{
bogdanm	0:9b334a45a8ff	715	HAL_StatusTypeDef tmpHALStatus = HAL_OK;
bogdanm	0:9b334a45a8ff	716
bogdanm	0:9b334a45a8ff	717	/* Check the parameters */
bogdanm	0:9b334a45a8ff	718	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	719
bogdanm	0:9b334a45a8ff	720	/* Process locked */
bogdanm	0:9b334a45a8ff	721	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	722
bogdanm	0:9b334a45a8ff	723	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	724	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	725	tmpHALStatus = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	726
bogdanm	0:9b334a45a8ff	727	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	728	if (tmpHALStatus != HAL_ERROR)
bogdanm	0:9b334a45a8ff	729	{
bogdanm	0:9b334a45a8ff	730	/* Change ADC state */
bogdanm	0:9b334a45a8ff	731	hadc->State = HAL_ADC_STATE_READY;
bogdanm	0:9b334a45a8ff	732	}
bogdanm	0:9b334a45a8ff	733
bogdanm	0:9b334a45a8ff	734	/* Process unlocked */
bogdanm	0:9b334a45a8ff	735	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	736
bogdanm	0:9b334a45a8ff	737	/* Return function status */
bogdanm	0:9b334a45a8ff	738	return tmpHALStatus;
bogdanm	0:9b334a45a8ff	739	}
bogdanm	0:9b334a45a8ff	740
bogdanm	0:9b334a45a8ff	741	/**
bogdanm	0:9b334a45a8ff	742	* @brief Wait for regular group conversion to be completed.
bogdanm	0:9b334a45a8ff	743	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	744	* @param Timeout: Timeout value in millisecond.
bogdanm	0:9b334a45a8ff	745	* @retval HAL status
bogdanm	0:9b334a45a8ff	746	*/
bogdanm	0:9b334a45a8ff	747	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	748	{
bogdanm	0:9b334a45a8ff	749	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	750
bogdanm	0:9b334a45a8ff	751	/* Check the parameters */
bogdanm	0:9b334a45a8ff	752	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	753
bogdanm	0:9b334a45a8ff	754	/* Get timeout */
bogdanm	0:9b334a45a8ff	755	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	/* Wait until End of Conversion flag is raised */
bogdanm	0:9b334a45a8ff	758	while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
bogdanm	0:9b334a45a8ff	759	{
bogdanm	0:9b334a45a8ff	760	/* Check if timeout is disabled (set to infinite wait) */
bogdanm	0:9b334a45a8ff	761	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	762	{
bogdanm	0:9b334a45a8ff	763	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	764	{
bogdanm	0:9b334a45a8ff	765	/* Update ADC state machine to timeout */
bogdanm	0:9b334a45a8ff	766	hadc->State = HAL_ADC_STATE_TIMEOUT;
bogdanm	0:9b334a45a8ff	767
bogdanm	0:9b334a45a8ff	768	/* Process unlocked */
bogdanm	0:9b334a45a8ff	769	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	770
bogdanm	0:9b334a45a8ff	771	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	772	}
bogdanm	0:9b334a45a8ff	773	}
bogdanm	0:9b334a45a8ff	774	}
bogdanm	0:9b334a45a8ff	775
bogdanm	0:9b334a45a8ff	776	/* Clear end of conversion flag of regular group if low power feature "Auto */
bogdanm	0:9b334a45a8ff	777	/* Wait" is disabled, to not interfere with this feature until data */
bogdanm	0:9b334a45a8ff	778	/* register is read using function HAL_ADC_GetValue(). */
bogdanm	0:9b334a45a8ff	779	if (hadc->Init.LowPowerAutoWait == DISABLE)
bogdanm	0:9b334a45a8ff	780	{
bogdanm	0:9b334a45a8ff	781	/* Clear regular group conversion flag */
bogdanm	0:9b334a45a8ff	782	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT \| ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	783	}
bogdanm	0:9b334a45a8ff	784
bogdanm	0:9b334a45a8ff	785	/* Update state machine on conversion status if not in error state */
bogdanm	0:9b334a45a8ff	786	if(hadc->State != HAL_ADC_STATE_ERROR)
bogdanm	0:9b334a45a8ff	787	{
bogdanm	0:9b334a45a8ff	788	/* Update ADC state machine */
bogdanm	0:9b334a45a8ff	789	if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
bogdanm	0:9b334a45a8ff	790	{
bogdanm	0:9b334a45a8ff	791	/* Check if a conversion is ready on injected group */
bogdanm	0:9b334a45a8ff	792	if(hadc->State == HAL_ADC_STATE_EOC_INJ)
bogdanm	0:9b334a45a8ff	793	{
bogdanm	0:9b334a45a8ff	794	/* Change ADC state */
bogdanm	0:9b334a45a8ff	795	hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm	0:9b334a45a8ff	796	}
bogdanm	0:9b334a45a8ff	797	else
bogdanm	0:9b334a45a8ff	798	{
bogdanm	0:9b334a45a8ff	799	/* Change ADC state */
bogdanm	0:9b334a45a8ff	800	hadc->State = HAL_ADC_STATE_EOC_REG;
bogdanm	0:9b334a45a8ff	801	}
bogdanm	0:9b334a45a8ff	802	}
bogdanm	0:9b334a45a8ff	803	}
bogdanm	0:9b334a45a8ff	804
bogdanm	0:9b334a45a8ff	805	/* Return ADC state */
bogdanm	0:9b334a45a8ff	806	return HAL_OK;
bogdanm	0:9b334a45a8ff	807	}
bogdanm	0:9b334a45a8ff	808
bogdanm	0:9b334a45a8ff	809	/**
bogdanm	0:9b334a45a8ff	810	* @brief Poll for conversion event.
bogdanm	0:9b334a45a8ff	811	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	812	* @param EventType: the ADC event type.
bogdanm	0:9b334a45a8ff	813	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	814	* @arg AWD_EVENT: ADC Analog watchdog event.
bogdanm	0:9b334a45a8ff	815	* @arg OVR_EVENT: ADC Overrun event
bogdanm	0:9b334a45a8ff	816	* @param Timeout: Timeout value in millisecond.
bogdanm	0:9b334a45a8ff	817	* @retval HAL status
bogdanm	0:9b334a45a8ff	818	*/
bogdanm	0:9b334a45a8ff	819	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	820	{
bogdanm	0:9b334a45a8ff	821	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	/* Check the parameters */
bogdanm	0:9b334a45a8ff	824	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	825	assert_param(IS_ADC_EVENT_TYPE(EventType));
bogdanm	0:9b334a45a8ff	826
bogdanm	0:9b334a45a8ff	827	/* Get timeout */
bogdanm	0:9b334a45a8ff	828	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	/* Check selected event flag */
bogdanm	0:9b334a45a8ff	831	while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
bogdanm	0:9b334a45a8ff	832	{
bogdanm	0:9b334a45a8ff	833	/* Check if timeout is disabled (set to infinite wait) */
bogdanm	0:9b334a45a8ff	834	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	835	{
bogdanm	0:9b334a45a8ff	836	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	837	{
bogdanm	0:9b334a45a8ff	838	/* Update ADC state machine to timeout */
bogdanm	0:9b334a45a8ff	839	hadc->State = HAL_ADC_STATE_TIMEOUT;
bogdanm	0:9b334a45a8ff	840
bogdanm	0:9b334a45a8ff	841	/* Process unlocked */
bogdanm	0:9b334a45a8ff	842	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	845	}
bogdanm	0:9b334a45a8ff	846	}
bogdanm	0:9b334a45a8ff	847	}
bogdanm	0:9b334a45a8ff	848
bogdanm	0:9b334a45a8ff	849	switch(EventType)
bogdanm	0:9b334a45a8ff	850	{
bogdanm	0:9b334a45a8ff	851	/* Analog watchdog (level out of window) event */
bogdanm	0:9b334a45a8ff	852	case AWD_EVENT:
bogdanm	0:9b334a45a8ff	853	/* Change ADC state */
bogdanm	0:9b334a45a8ff	854	hadc->State = HAL_ADC_STATE_AWD;
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	/* Clear ADC analog watchdog flag */
bogdanm	0:9b334a45a8ff	857	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
bogdanm	0:9b334a45a8ff	858	break;
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	/* Overrun event */
bogdanm	0:9b334a45a8ff	861	default: /* Case OVR_EVENT */
bogdanm	0:9b334a45a8ff	862	/* Change ADC state */
bogdanm	0:9b334a45a8ff	863	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	/* Set ADC error code to overrun */
bogdanm	0:9b334a45a8ff	866	hadc->ErrorCode \|= HAL_ADC_ERROR_OVR;
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	/* Clear ADC Overrun flag */
bogdanm	0:9b334a45a8ff	869	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
bogdanm	0:9b334a45a8ff	870	break;
bogdanm	0:9b334a45a8ff	871	}
bogdanm	0:9b334a45a8ff	872
bogdanm	0:9b334a45a8ff	873	/* Return ADC state */
bogdanm	0:9b334a45a8ff	874	return HAL_OK;
bogdanm	0:9b334a45a8ff	875	}
bogdanm	0:9b334a45a8ff	876
bogdanm	0:9b334a45a8ff	877	/**
bogdanm	0:9b334a45a8ff	878	* @brief Enables ADC, starts conversion of regular group with interruption.
bogdanm	0:9b334a45a8ff	879	* Interruptions enabled in this function: EOC (end of conversion),
bogdanm	0:9b334a45a8ff	880	* overrun.
bogdanm	0:9b334a45a8ff	881	* Each of these interruptions has its dedicated callback function.
bogdanm	0:9b334a45a8ff	882	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	883	* @retval HAL status
bogdanm	0:9b334a45a8ff	884	*/
bogdanm	0:9b334a45a8ff	885	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	886	{
bogdanm	0:9b334a45a8ff	887	HAL_StatusTypeDef tmpHALStatus = HAL_OK;
bogdanm	0:9b334a45a8ff	888
bogdanm	0:9b334a45a8ff	889	/* Check the parameters */
bogdanm	0:9b334a45a8ff	890	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892	/* Process locked */
bogdanm	0:9b334a45a8ff	893	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	894
bogdanm	0:9b334a45a8ff	895	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	896	tmpHALStatus = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	897
bogdanm	0:9b334a45a8ff	898	/* Start conversion if ADC is effectively enabled */
bogdanm	0:9b334a45a8ff	899	if (tmpHALStatus != HAL_ERROR)
bogdanm	0:9b334a45a8ff	900	{
bogdanm	0:9b334a45a8ff	901	/* State machine update: Check if an injected conversion is ongoing */
bogdanm	0:9b334a45a8ff	902	if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
bogdanm	0:9b334a45a8ff	903	{
bogdanm	0:9b334a45a8ff	904	/* Change ADC state */
bogdanm	0:9b334a45a8ff	905	hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
bogdanm	0:9b334a45a8ff	906	}
bogdanm	0:9b334a45a8ff	907	else
bogdanm	0:9b334a45a8ff	908	{
bogdanm	0:9b334a45a8ff	909	/* Change ADC state */
bogdanm	0:9b334a45a8ff	910	hadc->State = HAL_ADC_STATE_BUSY_REG;
bogdanm	0:9b334a45a8ff	911	}
bogdanm	0:9b334a45a8ff	912
bogdanm	0:9b334a45a8ff	913	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	914	__HAL_ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	915
bogdanm	0:9b334a45a8ff	916	/* Clear regular group conversion flag and overrun flag */
bogdanm	0:9b334a45a8ff	917	/* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm	0:9b334a45a8ff	918	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	919
bogdanm	0:9b334a45a8ff	920	/* Enable end of conversion interrupt for regular group */
bogdanm	0:9b334a45a8ff	921	__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC \| ADC_IT_OVR));
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	/* Start conversion of regular group if software start has been selected. */
bogdanm	0:9b334a45a8ff	924	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	925	/* trigger event. */
bogdanm	0:9b334a45a8ff	926	if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc))
bogdanm	0:9b334a45a8ff	927	{
bogdanm	0:9b334a45a8ff	928	/* Start ADC conversion on regular group */
bogdanm	0:9b334a45a8ff	929	SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
bogdanm	0:9b334a45a8ff	930	}
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	}
bogdanm	0:9b334a45a8ff	933
bogdanm	0:9b334a45a8ff	934	/* Process unlocked */
bogdanm	0:9b334a45a8ff	935	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	936
bogdanm	0:9b334a45a8ff	937	/* Return function status */
bogdanm	0:9b334a45a8ff	938	return tmpHALStatus;
bogdanm	0:9b334a45a8ff	939	}
bogdanm	0:9b334a45a8ff	940
bogdanm	0:9b334a45a8ff	941	/**
bogdanm	0:9b334a45a8ff	942	* @brief Stop ADC conversion of regular group (and injected group in
bogdanm	0:9b334a45a8ff	943	* case of auto_injection mode), disable interrution of
bogdanm	0:9b334a45a8ff	944	* end-of-conversion, disable ADC peripheral.
bogdanm	0:9b334a45a8ff	945	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	946	* @retval None
bogdanm	0:9b334a45a8ff	947	*/
bogdanm	0:9b334a45a8ff	948	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	949	{
bogdanm	0:9b334a45a8ff	950	HAL_StatusTypeDef tmpHALStatus = HAL_OK;
bogdanm	0:9b334a45a8ff	951
bogdanm	0:9b334a45a8ff	952	/* Check the parameters */
bogdanm	0:9b334a45a8ff	953	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	/* Process locked */
bogdanm	0:9b334a45a8ff	956	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	959	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	960	tmpHALStatus = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	963	if (tmpHALStatus != HAL_ERROR)
bogdanm	0:9b334a45a8ff	964	{
bogdanm	0:9b334a45a8ff	965	/* Disable ADC end of conversion interrupt for regular group */
bogdanm	0:9b334a45a8ff	966	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	967
bogdanm	0:9b334a45a8ff	968	/* Change ADC state */
bogdanm	0:9b334a45a8ff	969	hadc->State = HAL_ADC_STATE_READY;
bogdanm	0:9b334a45a8ff	970	}
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/* Process unlocked */
bogdanm	0:9b334a45a8ff	973	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	974
bogdanm	0:9b334a45a8ff	975	/* Return function status */
bogdanm	0:9b334a45a8ff	976	return tmpHALStatus;
bogdanm	0:9b334a45a8ff	977	}
bogdanm	0:9b334a45a8ff	978
bogdanm	0:9b334a45a8ff	979	/**
bogdanm	0:9b334a45a8ff	980	* @brief Enables ADC, starts conversion of regular group and transfers result
bogdanm	0:9b334a45a8ff	981	* through DMA.
bogdanm	0:9b334a45a8ff	982	* Interruptions enabled in this function:
bogdanm	0:9b334a45a8ff	983	* overrun, DMA half transfer, DMA transfer complete.
bogdanm	0:9b334a45a8ff	984	* Each of these interruptions has its dedicated callback function.
bogdanm	0:9b334a45a8ff	985	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	986	* @param pData: The destination Buffer address.
bogdanm	0:9b334a45a8ff	987	* @param Length: The length of data to be transferred from ADC peripheral to memory.
bogdanm	0:9b334a45a8ff	988	* @retval None
bogdanm	0:9b334a45a8ff	989	*/
bogdanm	0:9b334a45a8ff	990	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
bogdanm	0:9b334a45a8ff	991	{
bogdanm	0:9b334a45a8ff	992	HAL_StatusTypeDef tmpHALStatus = HAL_OK;
bogdanm	0:9b334a45a8ff	993
bogdanm	0:9b334a45a8ff	994	/* Check the parameters */
bogdanm	0:9b334a45a8ff	995	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997	/* Process locked */
bogdanm	0:9b334a45a8ff	998	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	999
bogdanm	0:9b334a45a8ff	1000	/* Enable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1001	tmpHALStatus = ADC_Enable(hadc);
bogdanm	0:9b334a45a8ff	1002
bogdanm	0:9b334a45a8ff	1003	/* Start conversion if ADC is effectively enabled */
bogdanm	0:9b334a45a8ff	1004	if (tmpHALStatus != HAL_ERROR)
bogdanm	0:9b334a45a8ff	1005	{
bogdanm	0:9b334a45a8ff	1006	/* State machine update: Check if an injected conversion is ongoing */
bogdanm	0:9b334a45a8ff	1007	if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
bogdanm	0:9b334a45a8ff	1008	{
bogdanm	0:9b334a45a8ff	1009	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1010	hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
bogdanm	0:9b334a45a8ff	1011	}
bogdanm	0:9b334a45a8ff	1012	else
bogdanm	0:9b334a45a8ff	1013	{
bogdanm	0:9b334a45a8ff	1014	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1015	hadc->State = HAL_ADC_STATE_BUSY_REG;
bogdanm	0:9b334a45a8ff	1016	}
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	1019	__HAL_ADC_CLEAR_ERRORCODE(hadc);
bogdanm	0:9b334a45a8ff	1020
bogdanm	0:9b334a45a8ff	1021
bogdanm	0:9b334a45a8ff	1022	/* Set the DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1023	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
bogdanm	0:9b334a45a8ff	1024
bogdanm	0:9b334a45a8ff	1025	/* Set the DMA half transfer complete callback */
bogdanm	0:9b334a45a8ff	1026	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
bogdanm	0:9b334a45a8ff	1027
bogdanm	0:9b334a45a8ff	1028	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1029	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
bogdanm	0:9b334a45a8ff	1030
bogdanm	0:9b334a45a8ff	1031
bogdanm	0:9b334a45a8ff	1032	/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
bogdanm	0:9b334a45a8ff	1033	/* start (in case of SW start): */
bogdanm	0:9b334a45a8ff	1034
bogdanm	0:9b334a45a8ff	1035	/* Clear regular group conversion flag and overrun flag */
bogdanm	0:9b334a45a8ff	1036	/* (To ensure of no unknown state from potential previous ADC operations) */
bogdanm	0:9b334a45a8ff	1037	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	1038
bogdanm	0:9b334a45a8ff	1039	/* Enable ADC overrun interrupt */
bogdanm	0:9b334a45a8ff	1040	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	1041
bogdanm	0:9b334a45a8ff	1042	/* Enable ADC DMA mode */
bogdanm	0:9b334a45a8ff	1043	hadc->Instance->CR2 \|= ADC_CR2_DMA;
bogdanm	0:9b334a45a8ff	1044
bogdanm	0:9b334a45a8ff	1045	/* Start the DMA channel */
bogdanm	0:9b334a45a8ff	1046	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	/* Start conversion of regular group if software start has been selected. */
bogdanm	0:9b334a45a8ff	1049	/* If external trigger has been selected, conversion will start at next */
bogdanm	0:9b334a45a8ff	1050	/* trigger event. */
bogdanm	0:9b334a45a8ff	1051	/* Note: Alternate trigger for single conversion could be to force an */
bogdanm	0:9b334a45a8ff	1052	/* additional set of bit ADON "hadc->Instance->CR2 \|= ADC_CR2_ADON;"*/
bogdanm	0:9b334a45a8ff	1053	if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc))
bogdanm	0:9b334a45a8ff	1054	{
bogdanm	0:9b334a45a8ff	1055	/* Start ADC conversion on regular group */
bogdanm	0:9b334a45a8ff	1056	SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
bogdanm	0:9b334a45a8ff	1057	}
bogdanm	0:9b334a45a8ff	1058	}
bogdanm	0:9b334a45a8ff	1059
bogdanm	0:9b334a45a8ff	1060	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1061	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	/* Return function status */
bogdanm	0:9b334a45a8ff	1064	return tmpHALStatus;
bogdanm	0:9b334a45a8ff	1065	}
bogdanm	0:9b334a45a8ff	1066
bogdanm	0:9b334a45a8ff	1067	/**
bogdanm	0:9b334a45a8ff	1068	* @brief Stop ADC conversion of regular group (and injected group in
bogdanm	0:9b334a45a8ff	1069	* case of auto_injection mode), disable ADC DMA transfer, disable
bogdanm	0:9b334a45a8ff	1070	* ADC peripheral.
bogdanm	0:9b334a45a8ff	1071	* @note: ADC peripheral disable is forcing interruption of potential
bogdanm	0:9b334a45a8ff	1072	* conversion on injected group. If injected group is under use, it
bogdanm	0:9b334a45a8ff	1073	* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
bogdanm	0:9b334a45a8ff	1074	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1075	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1076	*/
bogdanm	0:9b334a45a8ff	1077	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1078	{
bogdanm	0:9b334a45a8ff	1079	HAL_StatusTypeDef tmpHALStatus = HAL_OK;
bogdanm	0:9b334a45a8ff	1080
bogdanm	0:9b334a45a8ff	1081	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1082	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1083
bogdanm	0:9b334a45a8ff	1084	/* Process locked */
bogdanm	0:9b334a45a8ff	1085	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1086
bogdanm	0:9b334a45a8ff	1087	/* Stop potential conversion on going, on regular and injected groups */
bogdanm	0:9b334a45a8ff	1088	/* Disable ADC peripheral */
bogdanm	0:9b334a45a8ff	1089	tmpHALStatus = ADC_ConversionStop_Disable(hadc);
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	/* Check if ADC is effectively disabled */
bogdanm	0:9b334a45a8ff	1092	if (tmpHALStatus != HAL_ERROR)
bogdanm	0:9b334a45a8ff	1093	{
bogdanm	0:9b334a45a8ff	1094	/* Disable ADC DMA mode */
bogdanm	0:9b334a45a8ff	1095	hadc->Instance->CR2 &= ~ADC_CR2_DMA;
bogdanm	0:9b334a45a8ff	1096
bogdanm	0:9b334a45a8ff	1097	/* Disable the DMA channel (in case of DMA in circular mode or stop while */
bogdanm	0:9b334a45a8ff	1098	/* DMA transfer is on going) */
bogdanm	0:9b334a45a8ff	1099	tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle);
bogdanm	0:9b334a45a8ff	1100
bogdanm	0:9b334a45a8ff	1101	/* Check if DMA channel effectively disabled */
bogdanm	0:9b334a45a8ff	1102	if (tmpHALStatus != HAL_ERROR)
bogdanm	0:9b334a45a8ff	1103	{
bogdanm	0:9b334a45a8ff	1104	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1105	hadc->State = HAL_ADC_STATE_READY;
bogdanm	0:9b334a45a8ff	1106	}
bogdanm	0:9b334a45a8ff	1107	else
bogdanm	0:9b334a45a8ff	1108	{
bogdanm	0:9b334a45a8ff	1109	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1110	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1111	}
bogdanm	0:9b334a45a8ff	1112	}
bogdanm	0:9b334a45a8ff	1113
bogdanm	0:9b334a45a8ff	1114	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1115	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1116
bogdanm	0:9b334a45a8ff	1117	/* Return function status */
bogdanm	0:9b334a45a8ff	1118	return tmpHALStatus;
bogdanm	0:9b334a45a8ff	1119	}
bogdanm	0:9b334a45a8ff	1120
bogdanm	0:9b334a45a8ff	1121	/**
bogdanm	0:9b334a45a8ff	1122	* @brief Get ADC regular group conversion result.
bogdanm	0:9b334a45a8ff	1123	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1124	* @retval Converted value
bogdanm	0:9b334a45a8ff	1125	*/
bogdanm	0:9b334a45a8ff	1126	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1127	{
bogdanm	0:9b334a45a8ff	1128	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1129	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1130
bogdanm	0:9b334a45a8ff	1131	/* Note: EOC flag is not cleared here by software because automatically */
bogdanm	0:9b334a45a8ff	1132	/* cleared by hardware when reading register DR. */
bogdanm	0:9b334a45a8ff	1133
bogdanm	0:9b334a45a8ff	1134	/* Return ADC converted value */
bogdanm	0:9b334a45a8ff	1135	return hadc->Instance->DR;
bogdanm	0:9b334a45a8ff	1136	}
bogdanm	0:9b334a45a8ff	1137
bogdanm	0:9b334a45a8ff	1138	/**
bogdanm	0:9b334a45a8ff	1139	* @brief DMA transfer complete callback.
bogdanm	0:9b334a45a8ff	1140	* @param hdma: pointer to DMA handle.
bogdanm	0:9b334a45a8ff	1141	* @retval None
bogdanm	0:9b334a45a8ff	1142	*/
bogdanm	0:9b334a45a8ff	1143	static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1144	{
bogdanm	0:9b334a45a8ff	1145	/* Retrieve ADC handle corresponding to current DMA handle */
bogdanm	0:9b334a45a8ff	1146	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1147
bogdanm	0:9b334a45a8ff	1148	/* Update state machine on conversion status if not in error state */
bogdanm	0:9b334a45a8ff	1149	if(hadc->State != HAL_ADC_STATE_ERROR)
bogdanm	0:9b334a45a8ff	1150	{
bogdanm	0:9b334a45a8ff	1151	/* Update ADC state machine */
bogdanm	0:9b334a45a8ff	1152	if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
bogdanm	0:9b334a45a8ff	1153	{
bogdanm	0:9b334a45a8ff	1154	/* Check if a conversion is ready on injected group */
bogdanm	0:9b334a45a8ff	1155	if(hadc->State == HAL_ADC_STATE_EOC_INJ)
bogdanm	0:9b334a45a8ff	1156	{
bogdanm	0:9b334a45a8ff	1157	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1158	hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm	0:9b334a45a8ff	1159	}
bogdanm	0:9b334a45a8ff	1160	else
bogdanm	0:9b334a45a8ff	1161	{
bogdanm	0:9b334a45a8ff	1162	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1163	hadc->State = HAL_ADC_STATE_EOC_REG;
bogdanm	0:9b334a45a8ff	1164	}
bogdanm	0:9b334a45a8ff	1165	}
bogdanm	0:9b334a45a8ff	1166	}
bogdanm	0:9b334a45a8ff	1167
bogdanm	0:9b334a45a8ff	1168	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	1169	HAL_ADC_ConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1170	}
bogdanm	0:9b334a45a8ff	1171
bogdanm	0:9b334a45a8ff	1172	/**
bogdanm	0:9b334a45a8ff	1173	* @brief DMA half transfer complete callback.
bogdanm	0:9b334a45a8ff	1174	* @param hdma: pointer to DMA handle.
bogdanm	0:9b334a45a8ff	1175	* @retval None
bogdanm	0:9b334a45a8ff	1176	*/
bogdanm	0:9b334a45a8ff	1177	static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1178	{
bogdanm	0:9b334a45a8ff	1179	/* Retrieve ADC handle corresponding to current DMA handle */
bogdanm	0:9b334a45a8ff	1180	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	/* Half conversion callback */
bogdanm	0:9b334a45a8ff	1183	HAL_ADC_ConvHalfCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1184	}
bogdanm	0:9b334a45a8ff	1185
bogdanm	0:9b334a45a8ff	1186	/**
bogdanm	0:9b334a45a8ff	1187	* @brief DMA error callback
bogdanm	0:9b334a45a8ff	1188	* @param hdma: pointer to DMA handle.
bogdanm	0:9b334a45a8ff	1189	* @retval None
bogdanm	0:9b334a45a8ff	1190	*/
bogdanm	0:9b334a45a8ff	1191	static void ADC_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1192	{
bogdanm	0:9b334a45a8ff	1193	/* Retrieve ADC handle corresponding to current DMA handle */
bogdanm	0:9b334a45a8ff	1194	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1197	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1198
bogdanm	0:9b334a45a8ff	1199	/* Set ADC error code to DMA error */
bogdanm	0:9b334a45a8ff	1200	hadc->ErrorCode \|= HAL_ADC_ERROR_DMA;
bogdanm	0:9b334a45a8ff	1201
bogdanm	0:9b334a45a8ff	1202	/* Error callback */
bogdanm	0:9b334a45a8ff	1203	HAL_ADC_ErrorCallback(hadc);
bogdanm	0:9b334a45a8ff	1204	}
bogdanm	0:9b334a45a8ff	1205
bogdanm	0:9b334a45a8ff	1206	/**
bogdanm	0:9b334a45a8ff	1207	* @brief Handles ADC interrupt request
bogdanm	0:9b334a45a8ff	1208	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1209	* @retval None
bogdanm	0:9b334a45a8ff	1210	*/
bogdanm	0:9b334a45a8ff	1211	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1212	{
bogdanm	0:9b334a45a8ff	1213	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1214	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1215	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	1216	assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
bogdanm	0:9b334a45a8ff	1217
bogdanm	0:9b334a45a8ff	1218
bogdanm	0:9b334a45a8ff	1219	/* ========== Check End of Conversion flag for regular group ========== */
bogdanm	0:9b334a45a8ff	1220	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
bogdanm	0:9b334a45a8ff	1221	{
bogdanm	0:9b334a45a8ff	1222	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
bogdanm	0:9b334a45a8ff	1223	{
bogdanm	0:9b334a45a8ff	1224	/* Update state machine on conversion status if not in error state */
bogdanm	0:9b334a45a8ff	1225	if(hadc->State != HAL_ADC_STATE_ERROR)
bogdanm	0:9b334a45a8ff	1226	{
bogdanm	0:9b334a45a8ff	1227	/* Update ADC state machine */
bogdanm	0:9b334a45a8ff	1228	if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
bogdanm	0:9b334a45a8ff	1229	{
bogdanm	0:9b334a45a8ff	1230	/* Check if a conversion is ready on injected group */
bogdanm	0:9b334a45a8ff	1231	if(hadc->State == HAL_ADC_STATE_EOC_INJ)
bogdanm	0:9b334a45a8ff	1232	{
bogdanm	0:9b334a45a8ff	1233	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1234	hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm	0:9b334a45a8ff	1235	}
bogdanm	0:9b334a45a8ff	1236	else
bogdanm	0:9b334a45a8ff	1237	{
bogdanm	0:9b334a45a8ff	1238	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1239	hadc->State = HAL_ADC_STATE_EOC_REG;
bogdanm	0:9b334a45a8ff	1240	}
bogdanm	0:9b334a45a8ff	1241	}
bogdanm	0:9b334a45a8ff	1242	}
bogdanm	0:9b334a45a8ff	1243
bogdanm	0:9b334a45a8ff	1244	/* Disable interruption if no further conversion upcoming regular */
bogdanm	0:9b334a45a8ff	1245	/* external trigger or by continuous mode */
bogdanm	0:9b334a45a8ff	1246	if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
bogdanm	0:9b334a45a8ff	1247	(hadc->Init.ContinuousConvMode == DISABLE) )
bogdanm	0:9b334a45a8ff	1248	{
bogdanm	0:9b334a45a8ff	1249	/* Disable ADC end of single conversion interrupt */
bogdanm	0:9b334a45a8ff	1250	/* Note: Overrun interrupt was enabled with EOC interrupt in */
bogdanm	0:9b334a45a8ff	1251	/* HAL_ADC_Start_IT(), but is not disabled here because can be used by */
bogdanm	0:9b334a45a8ff	1252	/* overrun IRQ process below. */
bogdanm	0:9b334a45a8ff	1253	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	1254	}
bogdanm	0:9b334a45a8ff	1255
bogdanm	0:9b334a45a8ff	1256	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	1257	HAL_ADC_ConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1258
bogdanm	0:9b334a45a8ff	1259	/* Clear regular group conversion flag */
bogdanm	0:9b334a45a8ff	1260	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT \| ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	1261	}
bogdanm	0:9b334a45a8ff	1262	}
bogdanm	0:9b334a45a8ff	1263
bogdanm	0:9b334a45a8ff	1264	/* ========== Check End of Conversion flag for injected group ========== */
bogdanm	0:9b334a45a8ff	1265	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
bogdanm	0:9b334a45a8ff	1266	{
bogdanm	0:9b334a45a8ff	1267	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
bogdanm	0:9b334a45a8ff	1268	{
bogdanm	0:9b334a45a8ff	1269	/* Update state machine on conversion status if not in error state */
bogdanm	0:9b334a45a8ff	1270	if(hadc->State != HAL_ADC_STATE_ERROR)
bogdanm	0:9b334a45a8ff	1271	{
bogdanm	0:9b334a45a8ff	1272	/* Update ADC state machine */
bogdanm	0:9b334a45a8ff	1273	if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
bogdanm	0:9b334a45a8ff	1274	{
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	if(hadc->State == HAL_ADC_STATE_EOC_REG)
bogdanm	0:9b334a45a8ff	1277	{
bogdanm	0:9b334a45a8ff	1278	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1279	hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm	0:9b334a45a8ff	1280	}
bogdanm	0:9b334a45a8ff	1281	else
bogdanm	0:9b334a45a8ff	1282	{
bogdanm	0:9b334a45a8ff	1283	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1284	hadc->State = HAL_ADC_STATE_EOC_INJ;
bogdanm	0:9b334a45a8ff	1285	}
bogdanm	0:9b334a45a8ff	1286	}
bogdanm	0:9b334a45a8ff	1287	}
bogdanm	0:9b334a45a8ff	1288
bogdanm	0:9b334a45a8ff	1289	/* Disable interruption if no further conversion upcoming injected */
bogdanm	0:9b334a45a8ff	1290	/* external trigger or by automatic injected conversion with regular */
bogdanm	0:9b334a45a8ff	1291	/* group having no further conversion upcoming (same conditions as */
bogdanm	0:9b334a45a8ff	1292	/* regular group interruption disabling above). */
bogdanm	0:9b334a45a8ff	1293	if(__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) \|\|
bogdanm	0:9b334a45a8ff	1294	(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
bogdanm	0:9b334a45a8ff	1295	(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
bogdanm	0:9b334a45a8ff	1296	(hadc->Init.ContinuousConvMode == DISABLE) ) ) )
bogdanm	0:9b334a45a8ff	1297	{
bogdanm	0:9b334a45a8ff	1298	/* Disable ADC end of single conversion interrupt */
bogdanm	0:9b334a45a8ff	1299	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
bogdanm	0:9b334a45a8ff	1300	}
bogdanm	0:9b334a45a8ff	1301
bogdanm	0:9b334a45a8ff	1302	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	1303	HAL_ADCEx_InjectedConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1304
bogdanm	0:9b334a45a8ff	1305	/* Clear injected group conversion flag */
bogdanm	0:9b334a45a8ff	1306	__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT \| ADC_FLAG_JEOC));
bogdanm	0:9b334a45a8ff	1307	}
bogdanm	0:9b334a45a8ff	1308	}
bogdanm	0:9b334a45a8ff	1309
bogdanm	0:9b334a45a8ff	1310	/* ========== Check Analog watchdog flags ========== */
bogdanm	0:9b334a45a8ff	1311	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
bogdanm	0:9b334a45a8ff	1312	{
bogdanm	0:9b334a45a8ff	1313	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
bogdanm	0:9b334a45a8ff	1314	{
bogdanm	0:9b334a45a8ff	1315	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1316	hadc->State = HAL_ADC_STATE_AWD;
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	/* Clear the ADCx's Analog watchdog flag */
bogdanm	0:9b334a45a8ff	1319	__HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
bogdanm	0:9b334a45a8ff	1320
bogdanm	0:9b334a45a8ff	1321	/* Level out of window callback */
bogdanm	0:9b334a45a8ff	1322	HAL_ADC_LevelOutOfWindowCallback(hadc);
bogdanm	0:9b334a45a8ff	1323	}
bogdanm	0:9b334a45a8ff	1324	}
bogdanm	0:9b334a45a8ff	1325
bogdanm	0:9b334a45a8ff	1326	/* ========== Check Overrun flag ========== */
bogdanm	0:9b334a45a8ff	1327	if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
bogdanm	0:9b334a45a8ff	1328	{
bogdanm	0:9b334a45a8ff	1329	if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR))
bogdanm	0:9b334a45a8ff	1330	{
bogdanm	0:9b334a45a8ff	1331	/* Change ADC state to error state */
bogdanm	0:9b334a45a8ff	1332	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	/* Set ADC error code to overrun */
bogdanm	0:9b334a45a8ff	1335	hadc->ErrorCode \|= HAL_ADC_ERROR_OVR;
bogdanm	0:9b334a45a8ff	1336
bogdanm	0:9b334a45a8ff	1337	/* Error callback */
bogdanm	0:9b334a45a8ff	1338	HAL_ADC_ErrorCallback(hadc);
bogdanm	0:9b334a45a8ff	1339
bogdanm	0:9b334a45a8ff	1340	/* Clear the Overrun flag */
bogdanm	0:9b334a45a8ff	1341	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
bogdanm	0:9b334a45a8ff	1342	}
bogdanm	0:9b334a45a8ff	1343	}
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	}
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	/**
bogdanm	0:9b334a45a8ff	1348	* @brief Conversion complete callback in non blocking mode
bogdanm	0:9b334a45a8ff	1349	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1350	* @retval None
bogdanm	0:9b334a45a8ff	1351	*/
bogdanm	0:9b334a45a8ff	1352	__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1353	{
bogdanm	0:9b334a45a8ff	1354	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1355	function HAL_ADC_ConvCpltCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1356	*/
bogdanm	0:9b334a45a8ff	1357	}
bogdanm	0:9b334a45a8ff	1358
bogdanm	0:9b334a45a8ff	1359	/**
bogdanm	0:9b334a45a8ff	1360	* @brief Conversion DMA half-transfer callback in non blocking mode
bogdanm	0:9b334a45a8ff	1361	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1362	* @retval None
bogdanm	0:9b334a45a8ff	1363	*/
bogdanm	0:9b334a45a8ff	1364	__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1365	{
bogdanm	0:9b334a45a8ff	1366	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1367	function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1368	*/
bogdanm	0:9b334a45a8ff	1369	}
bogdanm	0:9b334a45a8ff	1370
bogdanm	0:9b334a45a8ff	1371	/**
bogdanm	0:9b334a45a8ff	1372	* @brief Analog watchdog callback in non blocking mode.
bogdanm	0:9b334a45a8ff	1373	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1374	* @retval None
bogdanm	0:9b334a45a8ff	1375	*/
bogdanm	0:9b334a45a8ff	1376	__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1377	{
bogdanm	0:9b334a45a8ff	1378	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1379	function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1380	*/
bogdanm	0:9b334a45a8ff	1381	}
bogdanm	0:9b334a45a8ff	1382
bogdanm	0:9b334a45a8ff	1383	/**
bogdanm	0:9b334a45a8ff	1384	* @brief ADC error callback in non blocking mode
bogdanm	0:9b334a45a8ff	1385	* (ADC conversion with interruption or transfer by DMA)
bogdanm	0:9b334a45a8ff	1386	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1387	* @retval None
bogdanm	0:9b334a45a8ff	1388	*/
bogdanm	0:9b334a45a8ff	1389	__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
bogdanm	0:9b334a45a8ff	1390	{
bogdanm	0:9b334a45a8ff	1391	/* NOTE : This function should not be modified. When the callback is needed,
bogdanm	0:9b334a45a8ff	1392	function HAL_ADC_ErrorCallback must be implemented in the user file.
bogdanm	0:9b334a45a8ff	1393	*/
bogdanm	0:9b334a45a8ff	1394	}
bogdanm	0:9b334a45a8ff	1395
bogdanm	0:9b334a45a8ff	1396
bogdanm	0:9b334a45a8ff	1397	/**
bogdanm	0:9b334a45a8ff	1398	* @}
bogdanm	0:9b334a45a8ff	1399	*/
bogdanm	0:9b334a45a8ff	1400
bogdanm	0:9b334a45a8ff	1401	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1402	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	1403	*
bogdanm	0:9b334a45a8ff	1404	@verbatim
bogdanm	0:9b334a45a8ff	1405	===============================================================================
bogdanm	0:9b334a45a8ff	1406	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	1407	===============================================================================
bogdanm	0:9b334a45a8ff	1408	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1409	(+) Configure channels on regular group
bogdanm	0:9b334a45a8ff	1410	(+) Configure the analog watchdog
bogdanm	0:9b334a45a8ff	1411
bogdanm	0:9b334a45a8ff	1412	@endverbatim
bogdanm	0:9b334a45a8ff	1413	* @{
bogdanm	0:9b334a45a8ff	1414	*/
bogdanm	0:9b334a45a8ff	1415
bogdanm	0:9b334a45a8ff	1416	/**
bogdanm	0:9b334a45a8ff	1417	* @brief Configures the the selected channel to be linked to the regular
bogdanm	0:9b334a45a8ff	1418	* group.
bogdanm	0:9b334a45a8ff	1419	* @note In case of usage of internal measurement channels:
bogdanm	0:9b334a45a8ff	1420	* Vbat/VrefInt/TempSensor.
bogdanm	0:9b334a45a8ff	1421	* These internal paths can be be disabled using function
bogdanm	0:9b334a45a8ff	1422	* HAL_ADC_DeInit().
bogdanm	0:9b334a45a8ff	1423	* @note Possibility to update parameters on the fly:
bogdanm	0:9b334a45a8ff	1424	* This function initializes channel into regular group, following
bogdanm	0:9b334a45a8ff	1425	* calls to this function can be used to reconfigure some parameters
bogdanm	0:9b334a45a8ff	1426	* of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
bogdanm	0:9b334a45a8ff	1427	* the ADC.
bogdanm	0:9b334a45a8ff	1428	* The setting of these parameters is conditioned to ADC state.
bogdanm	0:9b334a45a8ff	1429	* For parameters constraints, see comments of structure
bogdanm	0:9b334a45a8ff	1430	* "ADC_ChannelConfTypeDef".
bogdanm	0:9b334a45a8ff	1431	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1432	* @param sConfig: Structure of ADC channel for regular group.
bogdanm	0:9b334a45a8ff	1433	* @retval HAL status
bogdanm	0:9b334a45a8ff	1434	*/
bogdanm	0:9b334a45a8ff	1435	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
bogdanm	0:9b334a45a8ff	1436	{
bogdanm	0:9b334a45a8ff	1437	HAL_StatusTypeDef tmpHALStatus = HAL_OK;
bogdanm	0:9b334a45a8ff	1438
bogdanm	0:9b334a45a8ff	1439	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1440	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1441	assert_param(IS_ADC_CHANNEL(sConfig->Channel));
bogdanm	0:9b334a45a8ff	1442	assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
bogdanm	0:9b334a45a8ff	1443	assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
bogdanm	0:9b334a45a8ff	1444
bogdanm	0:9b334a45a8ff	1445	/* Process locked */
bogdanm	0:9b334a45a8ff	1446	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1447
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	/* Regular sequence configuration */
bogdanm	0:9b334a45a8ff	1450	/* For Rank 1 to 6 */
bogdanm	0:9b334a45a8ff	1451	if (sConfig->Rank < 7)
bogdanm	0:9b334a45a8ff	1452	{
bogdanm	0:9b334a45a8ff	1453	MODIFY_REG(hadc->Instance->SQR5,
bogdanm	0:9b334a45a8ff	1454	__ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank),
bogdanm	0:9b334a45a8ff	1455	__ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) );
bogdanm	0:9b334a45a8ff	1456	}
bogdanm	0:9b334a45a8ff	1457	/* For Rank 7 to 12 */
bogdanm	0:9b334a45a8ff	1458	else if (sConfig->Rank < 13)
bogdanm	0:9b334a45a8ff	1459	{
bogdanm	0:9b334a45a8ff	1460	MODIFY_REG(hadc->Instance->SQR4,
bogdanm	0:9b334a45a8ff	1461	__ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank),
bogdanm	0:9b334a45a8ff	1462	__ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
bogdanm	0:9b334a45a8ff	1463	}
bogdanm	0:9b334a45a8ff	1464	/* For Rank 13 to 18 */
bogdanm	0:9b334a45a8ff	1465	else if (sConfig->Rank < 19)
bogdanm	0:9b334a45a8ff	1466	{
bogdanm	0:9b334a45a8ff	1467	MODIFY_REG(hadc->Instance->SQR3,
bogdanm	0:9b334a45a8ff	1468	__ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank),
bogdanm	0:9b334a45a8ff	1469	__ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
bogdanm	0:9b334a45a8ff	1470	}
bogdanm	0:9b334a45a8ff	1471	/* For Rank 19 to 24 */
bogdanm	0:9b334a45a8ff	1472	else if (sConfig->Rank < 25)
bogdanm	0:9b334a45a8ff	1473	{
bogdanm	0:9b334a45a8ff	1474	MODIFY_REG(hadc->Instance->SQR2,
bogdanm	0:9b334a45a8ff	1475	__ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank),
bogdanm	0:9b334a45a8ff	1476	__ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
bogdanm	0:9b334a45a8ff	1477	}
bogdanm	0:9b334a45a8ff	1478	/* For Rank 25 to 28 */
bogdanm	0:9b334a45a8ff	1479	else
bogdanm	0:9b334a45a8ff	1480	{
bogdanm	0:9b334a45a8ff	1481	MODIFY_REG(hadc->Instance->SQR1,
bogdanm	0:9b334a45a8ff	1482	__ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank),
bogdanm	0:9b334a45a8ff	1483	__ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
bogdanm	0:9b334a45a8ff	1484	}
bogdanm	0:9b334a45a8ff	1485
bogdanm	0:9b334a45a8ff	1486
bogdanm	0:9b334a45a8ff	1487	/* Channel sampling time configuration */
bogdanm	0:9b334a45a8ff	1488	/* For channels 0 to 9 */
bogdanm	0:9b334a45a8ff	1489	if (sConfig->Channel < ADC_CHANNEL_10)
bogdanm	0:9b334a45a8ff	1490	{
bogdanm	0:9b334a45a8ff	1491	MODIFY_REG(hadc->Instance->SMPR3,
bogdanm	0:9b334a45a8ff	1492	__ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel),
bogdanm	0:9b334a45a8ff	1493	__ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) );
bogdanm	0:9b334a45a8ff	1494	}
bogdanm	0:9b334a45a8ff	1495	/* For channels 10 to 19 */
bogdanm	0:9b334a45a8ff	1496	else if (sConfig->Channel < ADC_CHANNEL_20)
bogdanm	0:9b334a45a8ff	1497	{
bogdanm	0:9b334a45a8ff	1498	MODIFY_REG(hadc->Instance->SMPR2,
bogdanm	0:9b334a45a8ff	1499	__ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel),
bogdanm	0:9b334a45a8ff	1500	__ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
bogdanm	0:9b334a45a8ff	1501	}
bogdanm	0:9b334a45a8ff	1502	/* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */
bogdanm	0:9b334a45a8ff	1503	/* For channels 20 to 29 for devices Cat4, Cat.5 */
bogdanm	0:9b334a45a8ff	1504	else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX)
bogdanm	0:9b334a45a8ff	1505	{
bogdanm	0:9b334a45a8ff	1506	MODIFY_REG(hadc->Instance->SMPR1,
bogdanm	0:9b334a45a8ff	1507	__ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel),
bogdanm	0:9b334a45a8ff	1508	__ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
bogdanm	0:9b334a45a8ff	1509	}
bogdanm	0:9b334a45a8ff	1510	/* For channels 30 to 31 for devices Cat4, Cat.5 */
bogdanm	0:9b334a45a8ff	1511	else
bogdanm	0:9b334a45a8ff	1512	{
bogdanm	0:9b334a45a8ff	1513	__ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel);
bogdanm	0:9b334a45a8ff	1514	}
bogdanm	0:9b334a45a8ff	1515
bogdanm	0:9b334a45a8ff	1516	/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
bogdanm	0:9b334a45a8ff	1517	/* and VREFINT measurement path. */
bogdanm	0:9b334a45a8ff	1518	if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) \|\|
bogdanm	0:9b334a45a8ff	1519	(sConfig->Channel == ADC_CHANNEL_VREFINT) )
bogdanm	0:9b334a45a8ff	1520	{
bogdanm	0:9b334a45a8ff	1521	SET_BIT(ADC->CCR, ADC_CCR_TSVREFE);
bogdanm	0:9b334a45a8ff	1522	}
bogdanm	0:9b334a45a8ff	1523
bogdanm	0:9b334a45a8ff	1524	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1525	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1526
bogdanm	0:9b334a45a8ff	1527	/* Return function status */
bogdanm	0:9b334a45a8ff	1528	return tmpHALStatus;
bogdanm	0:9b334a45a8ff	1529	}
bogdanm	0:9b334a45a8ff	1530
bogdanm	0:9b334a45a8ff	1531	/**
bogdanm	0:9b334a45a8ff	1532	* @brief Configures the analog watchdog.
bogdanm	0:9b334a45a8ff	1533	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1534	* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
bogdanm	0:9b334a45a8ff	1535	* @retval HAL status
bogdanm	0:9b334a45a8ff	1536	*/
bogdanm	0:9b334a45a8ff	1537	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
bogdanm	0:9b334a45a8ff	1538	{
bogdanm	0:9b334a45a8ff	1539	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1540	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	1541	assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
bogdanm	0:9b334a45a8ff	1542	assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
bogdanm	0:9b334a45a8ff	1543	assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
bogdanm	0:9b334a45a8ff	1544	assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
bogdanm	0:9b334a45a8ff	1545
bogdanm	0:9b334a45a8ff	1546	if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\|
bogdanm	0:9b334a45a8ff	1547	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\|
bogdanm	0:9b334a45a8ff	1548	(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) )
bogdanm	0:9b334a45a8ff	1549	{
bogdanm	0:9b334a45a8ff	1550	assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
bogdanm	0:9b334a45a8ff	1551	}
bogdanm	0:9b334a45a8ff	1552
bogdanm	0:9b334a45a8ff	1553	/* Process locked */
bogdanm	0:9b334a45a8ff	1554	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1555
bogdanm	0:9b334a45a8ff	1556	/* Analog watchdog configuration */
bogdanm	0:9b334a45a8ff	1557
bogdanm	0:9b334a45a8ff	1558	/* Configure ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	1559	if(AnalogWDGConfig->ITMode == ENABLE)
bogdanm	0:9b334a45a8ff	1560	{
bogdanm	0:9b334a45a8ff	1561	/* Enable the ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	1562	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
bogdanm	0:9b334a45a8ff	1563	}
bogdanm	0:9b334a45a8ff	1564	else
bogdanm	0:9b334a45a8ff	1565	{
bogdanm	0:9b334a45a8ff	1566	/* Disable the ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	1567	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
bogdanm	0:9b334a45a8ff	1568	}
bogdanm	0:9b334a45a8ff	1569
bogdanm	0:9b334a45a8ff	1570	/* Configuration of analog watchdog: */
bogdanm	0:9b334a45a8ff	1571	/* - Set the analog watchdog enable mode: regular and/or injected groups, */
bogdanm	0:9b334a45a8ff	1572	/* one or all channels. */
bogdanm	0:9b334a45a8ff	1573	/* - Set the Analog watchdog channel (is not used if watchdog */
bogdanm	0:9b334a45a8ff	1574	/* mode "all channels": ADC_CFGR_AWD1SGL=0). */
bogdanm	0:9b334a45a8ff	1575	hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL \|
bogdanm	0:9b334a45a8ff	1576	ADC_CR1_JAWDEN \|
bogdanm	0:9b334a45a8ff	1577	ADC_CR1_AWDEN \|
bogdanm	0:9b334a45a8ff	1578	ADC_CR1_AWDCH );
bogdanm	0:9b334a45a8ff	1579
bogdanm	0:9b334a45a8ff	1580	hadc->Instance->CR1 \|= ( AnalogWDGConfig->WatchdogMode \|
bogdanm	0:9b334a45a8ff	1581	AnalogWDGConfig->Channel );
bogdanm	0:9b334a45a8ff	1582
bogdanm	0:9b334a45a8ff	1583	/* Set the high threshold */
bogdanm	0:9b334a45a8ff	1584	hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
bogdanm	0:9b334a45a8ff	1585
bogdanm	0:9b334a45a8ff	1586	/* Set the low threshold */
bogdanm	0:9b334a45a8ff	1587	hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
bogdanm	0:9b334a45a8ff	1588
bogdanm	0:9b334a45a8ff	1589	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1590	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1591
bogdanm	0:9b334a45a8ff	1592	/* Return function status */
bogdanm	0:9b334a45a8ff	1593	return HAL_OK;
bogdanm	0:9b334a45a8ff	1594	}
bogdanm	0:9b334a45a8ff	1595
bogdanm	0:9b334a45a8ff	1596
bogdanm	0:9b334a45a8ff	1597	/**
bogdanm	0:9b334a45a8ff	1598	* @}
bogdanm	0:9b334a45a8ff	1599	*/
bogdanm	0:9b334a45a8ff	1600
bogdanm	0:9b334a45a8ff	1601
bogdanm	0:9b334a45a8ff	1602	/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
bogdanm	0:9b334a45a8ff	1603	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	1604	*
bogdanm	0:9b334a45a8ff	1605	@verbatim
bogdanm	0:9b334a45a8ff	1606	===============================================================================
bogdanm	0:9b334a45a8ff	1607	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1608	===============================================================================
bogdanm	0:9b334a45a8ff	1609	[..]
bogdanm	0:9b334a45a8ff	1610	This subsection provides functions to get in run-time the status of the
bogdanm	0:9b334a45a8ff	1611	peripheral.
bogdanm	0:9b334a45a8ff	1612	(+) Check the ADC state
bogdanm	0:9b334a45a8ff	1613	(+) Check the ADC error code
bogdanm	0:9b334a45a8ff	1614
bogdanm	0:9b334a45a8ff	1615	@endverbatim
bogdanm	0:9b334a45a8ff	1616	* @{
bogdanm	0:9b334a45a8ff	1617	*/
bogdanm	0:9b334a45a8ff	1618
bogdanm	0:9b334a45a8ff	1619	/**
bogdanm	0:9b334a45a8ff	1620	* @brief return the ADC state
bogdanm	0:9b334a45a8ff	1621	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1622	* @retval HAL state
bogdanm	0:9b334a45a8ff	1623	*/
bogdanm	0:9b334a45a8ff	1624	HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1625	{
bogdanm	0:9b334a45a8ff	1626	/* Return ADC state */
bogdanm	0:9b334a45a8ff	1627	return hadc->State;
bogdanm	0:9b334a45a8ff	1628	}
bogdanm	0:9b334a45a8ff	1629
bogdanm	0:9b334a45a8ff	1630	/**
bogdanm	0:9b334a45a8ff	1631	* @brief Return the ADC error code
bogdanm	0:9b334a45a8ff	1632	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1633	* @retval ADC Error Code
bogdanm	0:9b334a45a8ff	1634	*/
bogdanm	0:9b334a45a8ff	1635	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
bogdanm	0:9b334a45a8ff	1636	{
bogdanm	0:9b334a45a8ff	1637	return hadc->ErrorCode;
bogdanm	0:9b334a45a8ff	1638	}
bogdanm	0:9b334a45a8ff	1639
bogdanm	0:9b334a45a8ff	1640	/**
bogdanm	0:9b334a45a8ff	1641	* @}
bogdanm	0:9b334a45a8ff	1642	*/
bogdanm	0:9b334a45a8ff	1643
bogdanm	0:9b334a45a8ff	1644	/**
bogdanm	0:9b334a45a8ff	1645	* @}
bogdanm	0:9b334a45a8ff	1646	*/
bogdanm	0:9b334a45a8ff	1647
bogdanm	0:9b334a45a8ff	1648	/** @defgroup ADC_Private_Functions ADC Private Functions
bogdanm	0:9b334a45a8ff	1649	* @{
bogdanm	0:9b334a45a8ff	1650	*/
bogdanm	0:9b334a45a8ff	1651
bogdanm	0:9b334a45a8ff	1652	/**
bogdanm	0:9b334a45a8ff	1653	* @brief Enable the selected ADC.
bogdanm	0:9b334a45a8ff	1654	* @note Prerequisite condition to use this function: ADC must be disabled
bogdanm	0:9b334a45a8ff	1655	* and voltage regulator must be enabled (done into HAL_ADC_Init()).
bogdanm	0:9b334a45a8ff	1656	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1657	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1658	*/
bogdanm	0:9b334a45a8ff	1659	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1660	{
bogdanm	0:9b334a45a8ff	1661	uint32_t wait_loop_index = 0;
bogdanm	0:9b334a45a8ff	1662	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1663
bogdanm	0:9b334a45a8ff	1664	/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
bogdanm	0:9b334a45a8ff	1665	/* enabling phase not yet completed: flag ADC ready not yet set). */
bogdanm	0:9b334a45a8ff	1666	/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
bogdanm	0:9b334a45a8ff	1667	/* causes: ADC clock not running, ...). */
bogdanm	0:9b334a45a8ff	1668	if (__HAL_ADC_IS_ENABLED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1669	{
bogdanm	0:9b334a45a8ff	1670	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	1671	__ADC_ENABLE(hadc);
bogdanm	0:9b334a45a8ff	1672
bogdanm	0:9b334a45a8ff	1673	/* Delay for ADC stabilization time. */
bogdanm	0:9b334a45a8ff	1674	/* Delay fixed to worst case: maximum CPU frequency */
bogdanm	0:9b334a45a8ff	1675	while(wait_loop_index < ADC_STAB_DELAY_CPU_CYCLES)
bogdanm	0:9b334a45a8ff	1676	{
bogdanm	0:9b334a45a8ff	1677	wait_loop_index++;
bogdanm	0:9b334a45a8ff	1678	}
bogdanm	0:9b334a45a8ff	1679
bogdanm	0:9b334a45a8ff	1680	/* Get timeout */
bogdanm	0:9b334a45a8ff	1681	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1682
bogdanm	0:9b334a45a8ff	1683	/* Wait for ADC effectively enabled */
bogdanm	0:9b334a45a8ff	1684	while(__HAL_ADC_IS_ENABLED(hadc) == RESET)
bogdanm	0:9b334a45a8ff	1685	{
bogdanm	0:9b334a45a8ff	1686	if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT)
bogdanm	0:9b334a45a8ff	1687	{
bogdanm	0:9b334a45a8ff	1688	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1689	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1690
bogdanm	0:9b334a45a8ff	1691	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	1692	hadc->ErrorCode \|= HAL_ADC_ERROR_INTERNAL;
bogdanm	0:9b334a45a8ff	1693
bogdanm	0:9b334a45a8ff	1694	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1695	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1696
bogdanm	0:9b334a45a8ff	1697	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1698	}
bogdanm	0:9b334a45a8ff	1699	}
bogdanm	0:9b334a45a8ff	1700	}
bogdanm	0:9b334a45a8ff	1701
bogdanm	0:9b334a45a8ff	1702	/* Return HAL status */
bogdanm	0:9b334a45a8ff	1703	return HAL_OK;
bogdanm	0:9b334a45a8ff	1704	}
bogdanm	0:9b334a45a8ff	1705
bogdanm	0:9b334a45a8ff	1706	/**
bogdanm	0:9b334a45a8ff	1707	* @brief Stop ADC conversion and disable the selected ADC
bogdanm	0:9b334a45a8ff	1708	* @note Prerequisite condition to use this function: ADC conversions must be
bogdanm	0:9b334a45a8ff	1709	* stopped to disable the ADC.
bogdanm	0:9b334a45a8ff	1710	* @param hadc: ADC handle
bogdanm	0:9b334a45a8ff	1711	* @retval HAL status.
bogdanm	0:9b334a45a8ff	1712	*/
bogdanm	0:9b334a45a8ff	1713	HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1714	{
bogdanm	0:9b334a45a8ff	1715	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1716
bogdanm	0:9b334a45a8ff	1717	/* Verification if ADC is not already disabled: */
bogdanm	0:9b334a45a8ff	1718	if (__HAL_ADC_IS_ENABLED(hadc) != RESET)
bogdanm	0:9b334a45a8ff	1719	{
bogdanm	0:9b334a45a8ff	1720	/* Disable the ADC peripheral */
bogdanm	0:9b334a45a8ff	1721	__ADC_DISABLE(hadc);
bogdanm	0:9b334a45a8ff	1722
bogdanm	0:9b334a45a8ff	1723	/* Get timeout */
bogdanm	0:9b334a45a8ff	1724	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1725
bogdanm	0:9b334a45a8ff	1726	/* Wait for ADC effectively disabled */
bogdanm	0:9b334a45a8ff	1727	while(__HAL_ADC_IS_ENABLED(hadc) != RESET)
bogdanm	0:9b334a45a8ff	1728	{
bogdanm	0:9b334a45a8ff	1729	if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT)
bogdanm	0:9b334a45a8ff	1730	{
bogdanm	0:9b334a45a8ff	1731	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	1732	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1733
bogdanm	0:9b334a45a8ff	1734	/* Set ADC error code to ADC IP internal error */
bogdanm	0:9b334a45a8ff	1735	hadc->ErrorCode \|= HAL_ADC_ERROR_INTERNAL;
bogdanm	0:9b334a45a8ff	1736
bogdanm	0:9b334a45a8ff	1737	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1738	}
bogdanm	0:9b334a45a8ff	1739	}
bogdanm	0:9b334a45a8ff	1740	}
bogdanm	0:9b334a45a8ff	1741
bogdanm	0:9b334a45a8ff	1742	/* Return HAL status */
bogdanm	0:9b334a45a8ff	1743	return HAL_OK;
bogdanm	0:9b334a45a8ff	1744	}
bogdanm	0:9b334a45a8ff	1745
bogdanm	0:9b334a45a8ff	1746	/**
bogdanm	0:9b334a45a8ff	1747	* @}
bogdanm	0:9b334a45a8ff	1748	*/
bogdanm	0:9b334a45a8ff	1749
bogdanm	0:9b334a45a8ff	1750	#endif /* HAL_ADC_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1751	/**
bogdanm	0:9b334a45a8ff	1752	* @}
bogdanm	0:9b334a45a8ff	1753	*/
bogdanm	0:9b334a45a8ff	1754
bogdanm	0:9b334a45a8ff	1755	/**
bogdanm	0:9b334a45a8ff	1756	* @}
bogdanm	0:9b334a45a8ff	1757	*/
bogdanm	0:9b334a45a8ff	1758
bogdanm	0:9b334a45a8ff	1759	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning