fix LPC812 PWM
Fork of mbed-dev by
targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/system_stm32l1xx.c@129:2e517c56bcfb, 2016-05-16 (annotated)
- Committer:
- nameless129
- Date:
- Mon May 16 16:50:30 2016 +0000
- Revision:
- 129:2e517c56bcfb
- Parent:
- 67:4bcbbb9fcddf
PWM Fix:Duty 0%??H???????????????
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 67:4bcbbb9fcddf | 1 | /** |
mbed_official | 67:4bcbbb9fcddf | 2 | ****************************************************************************** |
mbed_official | 67:4bcbbb9fcddf | 3 | * @file system_stm32l1xx.c |
mbed_official | 67:4bcbbb9fcddf | 4 | * @author MCD Application Team |
mbed_official | 67:4bcbbb9fcddf | 5 | * @version V2.0.0 |
mbed_official | 67:4bcbbb9fcddf | 6 | * @date 5-September-2014 |
mbed_official | 67:4bcbbb9fcddf | 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. |
mbed_official | 67:4bcbbb9fcddf | 8 | * |
mbed_official | 67:4bcbbb9fcddf | 9 | * This file provides two functions and one global variable to be called from |
mbed_official | 67:4bcbbb9fcddf | 10 | * user application: |
mbed_official | 67:4bcbbb9fcddf | 11 | * - SystemInit(): This function is called at startup just after reset and |
mbed_official | 67:4bcbbb9fcddf | 12 | * before branch to main program. This call is made inside |
mbed_official | 67:4bcbbb9fcddf | 13 | * the "startup_stm32l1xx.s" file. |
mbed_official | 67:4bcbbb9fcddf | 14 | * |
mbed_official | 67:4bcbbb9fcddf | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
mbed_official | 67:4bcbbb9fcddf | 16 | * by the user application to setup the SysTick |
mbed_official | 67:4bcbbb9fcddf | 17 | * timer or configure other parameters. |
mbed_official | 67:4bcbbb9fcddf | 18 | * |
mbed_official | 67:4bcbbb9fcddf | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
mbed_official | 67:4bcbbb9fcddf | 20 | * be called whenever the core clock is changed |
mbed_official | 67:4bcbbb9fcddf | 21 | * during program execution. |
mbed_official | 67:4bcbbb9fcddf | 22 | * |
mbed_official | 67:4bcbbb9fcddf | 23 | * This file configures the system clock as follows: |
mbed_official | 67:4bcbbb9fcddf | 24 | *----------------------------------------------------------------------------- |
mbed_official | 67:4bcbbb9fcddf | 25 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
mbed_official | 67:4bcbbb9fcddf | 26 | * | (external 16 MHz clock) | (internal 16 MHz) |
mbed_official | 67:4bcbbb9fcddf | 27 | * | 2- PLL_HSE_XTAL | |
mbed_official | 67:4bcbbb9fcddf | 28 | * | (external 16 MHz xtal) | |
mbed_official | 67:4bcbbb9fcddf | 29 | *----------------------------------------------------------------------------- |
mbed_official | 67:4bcbbb9fcddf | 30 | * SYSCLK(MHz) | 32 | 32 |
mbed_official | 67:4bcbbb9fcddf | 31 | *----------------------------------------------------------------------------- |
mbed_official | 67:4bcbbb9fcddf | 32 | * AHBCLK (MHz) | 32 | 32 |
mbed_official | 67:4bcbbb9fcddf | 33 | *----------------------------------------------------------------------------- |
mbed_official | 67:4bcbbb9fcddf | 34 | * APB1CLK (MHz) | 32 | 32 |
mbed_official | 67:4bcbbb9fcddf | 35 | *----------------------------------------------------------------------------- |
mbed_official | 67:4bcbbb9fcddf | 36 | * APB2CLK (MHz) | 32 | 32 |
mbed_official | 67:4bcbbb9fcddf | 37 | *----------------------------------------------------------------------------- |
mbed_official | 67:4bcbbb9fcddf | 38 | * USB capable (48 MHz precise clock) | YES | NO |
mbed_official | 67:4bcbbb9fcddf | 39 | *----------------------------------------------------------------------------- |
mbed_official | 67:4bcbbb9fcddf | 40 | ****************************************************************************** |
mbed_official | 67:4bcbbb9fcddf | 41 | * @attention |
mbed_official | 67:4bcbbb9fcddf | 42 | * |
mbed_official | 67:4bcbbb9fcddf | 43 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
mbed_official | 67:4bcbbb9fcddf | 44 | * |
mbed_official | 67:4bcbbb9fcddf | 45 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 67:4bcbbb9fcddf | 46 | * are permitted provided that the following conditions are met: |
mbed_official | 67:4bcbbb9fcddf | 47 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 67:4bcbbb9fcddf | 48 | * this list of conditions and the following disclaimer. |
mbed_official | 67:4bcbbb9fcddf | 49 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 67:4bcbbb9fcddf | 50 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 67:4bcbbb9fcddf | 51 | * and/or other materials provided with the distribution. |
mbed_official | 67:4bcbbb9fcddf | 52 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 67:4bcbbb9fcddf | 53 | * may be used to endorse or promote products derived from this software |
mbed_official | 67:4bcbbb9fcddf | 54 | * without specific prior written permission. |
mbed_official | 67:4bcbbb9fcddf | 55 | * |
mbed_official | 67:4bcbbb9fcddf | 56 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 67:4bcbbb9fcddf | 57 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 67:4bcbbb9fcddf | 58 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 67:4bcbbb9fcddf | 59 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 67:4bcbbb9fcddf | 60 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 67:4bcbbb9fcddf | 61 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 67:4bcbbb9fcddf | 62 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 67:4bcbbb9fcddf | 63 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 67:4bcbbb9fcddf | 64 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 67:4bcbbb9fcddf | 65 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 67:4bcbbb9fcddf | 66 | * |
mbed_official | 67:4bcbbb9fcddf | 67 | ****************************************************************************** |
mbed_official | 67:4bcbbb9fcddf | 68 | */ |
mbed_official | 67:4bcbbb9fcddf | 69 | |
mbed_official | 67:4bcbbb9fcddf | 70 | /** @addtogroup CMSIS |
mbed_official | 67:4bcbbb9fcddf | 71 | * @{ |
mbed_official | 67:4bcbbb9fcddf | 72 | */ |
mbed_official | 67:4bcbbb9fcddf | 73 | |
mbed_official | 67:4bcbbb9fcddf | 74 | /** @addtogroup stm32l1xx_system |
mbed_official | 67:4bcbbb9fcddf | 75 | * @{ |
mbed_official | 67:4bcbbb9fcddf | 76 | */ |
mbed_official | 67:4bcbbb9fcddf | 77 | |
mbed_official | 67:4bcbbb9fcddf | 78 | /** @addtogroup STM32L1xx_System_Private_Includes |
mbed_official | 67:4bcbbb9fcddf | 79 | * @{ |
mbed_official | 67:4bcbbb9fcddf | 80 | */ |
mbed_official | 67:4bcbbb9fcddf | 81 | |
mbed_official | 67:4bcbbb9fcddf | 82 | #include "stm32l1xx.h" |
mbed_official | 67:4bcbbb9fcddf | 83 | #include "hal_tick.h" |
mbed_official | 67:4bcbbb9fcddf | 84 | |
mbed_official | 67:4bcbbb9fcddf | 85 | /** |
mbed_official | 67:4bcbbb9fcddf | 86 | * @} |
mbed_official | 67:4bcbbb9fcddf | 87 | */ |
mbed_official | 67:4bcbbb9fcddf | 88 | |
mbed_official | 67:4bcbbb9fcddf | 89 | /** @addtogroup STM32L1xx_System_Private_TypesDefinitions |
mbed_official | 67:4bcbbb9fcddf | 90 | * @{ |
mbed_official | 67:4bcbbb9fcddf | 91 | */ |
mbed_official | 67:4bcbbb9fcddf | 92 | |
mbed_official | 67:4bcbbb9fcddf | 93 | /** |
mbed_official | 67:4bcbbb9fcddf | 94 | * @} |
mbed_official | 67:4bcbbb9fcddf | 95 | */ |
mbed_official | 67:4bcbbb9fcddf | 96 | |
mbed_official | 67:4bcbbb9fcddf | 97 | /** @addtogroup STM32L1xx_System_Private_Defines |
mbed_official | 67:4bcbbb9fcddf | 98 | * @{ |
mbed_official | 67:4bcbbb9fcddf | 99 | */ |
mbed_official | 67:4bcbbb9fcddf | 100 | #if !defined (HSE_VALUE) |
mbed_official | 67:4bcbbb9fcddf | 101 | #define HSE_VALUE ((uint32_t)16000000) /*!< Default value of the External oscillator in Hz. |
mbed_official | 67:4bcbbb9fcddf | 102 | This value can be provided and adapted by the user application. */ |
mbed_official | 67:4bcbbb9fcddf | 103 | #endif /* HSE_VALUE */ |
mbed_official | 67:4bcbbb9fcddf | 104 | |
mbed_official | 67:4bcbbb9fcddf | 105 | #if !defined (HSI_VALUE) |
mbed_official | 67:4bcbbb9fcddf | 106 | #define HSI_VALUE ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz. |
mbed_official | 67:4bcbbb9fcddf | 107 | This value can be provided and adapted by the user application. */ |
mbed_official | 67:4bcbbb9fcddf | 108 | #endif /* HSI_VALUE */ |
mbed_official | 67:4bcbbb9fcddf | 109 | |
mbed_official | 67:4bcbbb9fcddf | 110 | /*!< Uncomment the following line if you need to use external SRAM mounted |
mbed_official | 67:4bcbbb9fcddf | 111 | on STM32L152D_EVAL board as data memory */ |
mbed_official | 67:4bcbbb9fcddf | 112 | /* #define DATA_IN_ExtSRAM */ |
mbed_official | 67:4bcbbb9fcddf | 113 | |
mbed_official | 67:4bcbbb9fcddf | 114 | /*!< Uncomment the following line if you need to relocate your vector Table in |
mbed_official | 67:4bcbbb9fcddf | 115 | Internal SRAM. */ |
mbed_official | 67:4bcbbb9fcddf | 116 | /* #define VECT_TAB_SRAM */ |
mbed_official | 67:4bcbbb9fcddf | 117 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. |
mbed_official | 67:4bcbbb9fcddf | 118 | This value must be a multiple of 0x200. */ |
mbed_official | 67:4bcbbb9fcddf | 119 | /** |
mbed_official | 67:4bcbbb9fcddf | 120 | * @} |
mbed_official | 67:4bcbbb9fcddf | 121 | */ |
mbed_official | 67:4bcbbb9fcddf | 122 | |
mbed_official | 67:4bcbbb9fcddf | 123 | /** @addtogroup STM32L1xx_System_Private_Macros |
mbed_official | 67:4bcbbb9fcddf | 124 | * @{ |
mbed_official | 67:4bcbbb9fcddf | 125 | */ |
mbed_official | 67:4bcbbb9fcddf | 126 | |
mbed_official | 67:4bcbbb9fcddf | 127 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
mbed_official | 67:4bcbbb9fcddf | 128 | #define USE_PLL_HSE_EXTC (0) /* Use external clock */ |
mbed_official | 67:4bcbbb9fcddf | 129 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
mbed_official | 67:4bcbbb9fcddf | 130 | |
mbed_official | 67:4bcbbb9fcddf | 131 | /** |
mbed_official | 67:4bcbbb9fcddf | 132 | * @} |
mbed_official | 67:4bcbbb9fcddf | 133 | */ |
mbed_official | 67:4bcbbb9fcddf | 134 | |
mbed_official | 67:4bcbbb9fcddf | 135 | /** @addtogroup STM32L1xx_System_Private_Variables |
mbed_official | 67:4bcbbb9fcddf | 136 | * @{ |
mbed_official | 67:4bcbbb9fcddf | 137 | */ |
mbed_official | 67:4bcbbb9fcddf | 138 | /* This variable is updated in three ways: |
mbed_official | 67:4bcbbb9fcddf | 139 | 1) by calling CMSIS function SystemCoreClockUpdate() |
mbed_official | 67:4bcbbb9fcddf | 140 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
mbed_official | 67:4bcbbb9fcddf | 141 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
mbed_official | 67:4bcbbb9fcddf | 142 | Note: If you use this function to configure the system clock; then there |
mbed_official | 67:4bcbbb9fcddf | 143 | is no need to call the 2 first functions listed above, since SystemCoreClock |
mbed_official | 67:4bcbbb9fcddf | 144 | variable is updated automatically. |
mbed_official | 67:4bcbbb9fcddf | 145 | */ |
mbed_official | 67:4bcbbb9fcddf | 146 | uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */ |
mbed_official | 67:4bcbbb9fcddf | 147 | const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; |
mbed_official | 67:4bcbbb9fcddf | 148 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
mbed_official | 67:4bcbbb9fcddf | 149 | |
mbed_official | 67:4bcbbb9fcddf | 150 | /** |
mbed_official | 67:4bcbbb9fcddf | 151 | * @} |
mbed_official | 67:4bcbbb9fcddf | 152 | */ |
mbed_official | 67:4bcbbb9fcddf | 153 | |
mbed_official | 67:4bcbbb9fcddf | 154 | /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes |
mbed_official | 67:4bcbbb9fcddf | 155 | * @{ |
mbed_official | 67:4bcbbb9fcddf | 156 | */ |
mbed_official | 67:4bcbbb9fcddf | 157 | |
mbed_official | 67:4bcbbb9fcddf | 158 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
mbed_official | 67:4bcbbb9fcddf | 159 | #ifdef DATA_IN_ExtSRAM |
mbed_official | 67:4bcbbb9fcddf | 160 | static void SystemInit_ExtMemCtl(void); |
mbed_official | 67:4bcbbb9fcddf | 161 | #endif /* DATA_IN_ExtSRAM */ |
mbed_official | 67:4bcbbb9fcddf | 162 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
mbed_official | 67:4bcbbb9fcddf | 163 | |
mbed_official | 67:4bcbbb9fcddf | 164 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
mbed_official | 67:4bcbbb9fcddf | 165 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
mbed_official | 67:4bcbbb9fcddf | 166 | #endif |
mbed_official | 67:4bcbbb9fcddf | 167 | |
mbed_official | 67:4bcbbb9fcddf | 168 | uint8_t SetSysClock_PLL_HSI(void); |
mbed_official | 67:4bcbbb9fcddf | 169 | |
mbed_official | 67:4bcbbb9fcddf | 170 | /** |
mbed_official | 67:4bcbbb9fcddf | 171 | * @} |
mbed_official | 67:4bcbbb9fcddf | 172 | */ |
mbed_official | 67:4bcbbb9fcddf | 173 | |
mbed_official | 67:4bcbbb9fcddf | 174 | /** @addtogroup STM32L1xx_System_Private_Functions |
mbed_official | 67:4bcbbb9fcddf | 175 | * @{ |
mbed_official | 67:4bcbbb9fcddf | 176 | */ |
mbed_official | 67:4bcbbb9fcddf | 177 | |
mbed_official | 67:4bcbbb9fcddf | 178 | /** |
mbed_official | 67:4bcbbb9fcddf | 179 | * @brief Setup the microcontroller system. |
mbed_official | 67:4bcbbb9fcddf | 180 | * Initialize the Embedded Flash Interface, the PLL and update the |
mbed_official | 67:4bcbbb9fcddf | 181 | * SystemCoreClock variable. |
mbed_official | 67:4bcbbb9fcddf | 182 | * @param None |
mbed_official | 67:4bcbbb9fcddf | 183 | * @retval None |
mbed_official | 67:4bcbbb9fcddf | 184 | */ |
mbed_official | 67:4bcbbb9fcddf | 185 | void SystemInit (void) |
mbed_official | 67:4bcbbb9fcddf | 186 | { |
mbed_official | 67:4bcbbb9fcddf | 187 | /*!< Set MSION bit */ |
mbed_official | 67:4bcbbb9fcddf | 188 | RCC->CR |= (uint32_t)0x00000100; |
mbed_official | 67:4bcbbb9fcddf | 189 | |
mbed_official | 67:4bcbbb9fcddf | 190 | /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ |
mbed_official | 67:4bcbbb9fcddf | 191 | RCC->CFGR &= (uint32_t)0x88FFC00C; |
mbed_official | 67:4bcbbb9fcddf | 192 | |
mbed_official | 67:4bcbbb9fcddf | 193 | /*!< Reset HSION, HSEON, CSSON and PLLON bits */ |
mbed_official | 67:4bcbbb9fcddf | 194 | RCC->CR &= (uint32_t)0xEEFEFFFE; |
mbed_official | 67:4bcbbb9fcddf | 195 | |
mbed_official | 67:4bcbbb9fcddf | 196 | /*!< Reset HSEBYP bit */ |
mbed_official | 67:4bcbbb9fcddf | 197 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
mbed_official | 67:4bcbbb9fcddf | 198 | |
mbed_official | 67:4bcbbb9fcddf | 199 | /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ |
mbed_official | 67:4bcbbb9fcddf | 200 | RCC->CFGR &= (uint32_t)0xFF02FFFF; |
mbed_official | 67:4bcbbb9fcddf | 201 | |
mbed_official | 67:4bcbbb9fcddf | 202 | /*!< Disable all interrupts */ |
mbed_official | 67:4bcbbb9fcddf | 203 | RCC->CIR = 0x00000000; |
mbed_official | 67:4bcbbb9fcddf | 204 | |
mbed_official | 67:4bcbbb9fcddf | 205 | #ifdef DATA_IN_ExtSRAM |
mbed_official | 67:4bcbbb9fcddf | 206 | SystemInit_ExtMemCtl(); |
mbed_official | 67:4bcbbb9fcddf | 207 | #endif /* DATA_IN_ExtSRAM */ |
mbed_official | 67:4bcbbb9fcddf | 208 | |
mbed_official | 67:4bcbbb9fcddf | 209 | #ifdef VECT_TAB_SRAM |
mbed_official | 67:4bcbbb9fcddf | 210 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ |
mbed_official | 67:4bcbbb9fcddf | 211 | #else |
mbed_official | 67:4bcbbb9fcddf | 212 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ |
mbed_official | 67:4bcbbb9fcddf | 213 | #endif |
mbed_official | 67:4bcbbb9fcddf | 214 | |
mbed_official | 67:4bcbbb9fcddf | 215 | /* Configure the Cube driver */ |
mbed_official | 67:4bcbbb9fcddf | 216 | SystemCoreClock = 16000000; // At this stage the HSI is used as system clock |
mbed_official | 67:4bcbbb9fcddf | 217 | HAL_Init(); |
mbed_official | 67:4bcbbb9fcddf | 218 | |
mbed_official | 67:4bcbbb9fcddf | 219 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
mbed_official | 67:4bcbbb9fcddf | 220 | AHB/APBx prescalers and Flash settings */ |
mbed_official | 67:4bcbbb9fcddf | 221 | SetSysClock(); |
mbed_official | 67:4bcbbb9fcddf | 222 | |
mbed_official | 67:4bcbbb9fcddf | 223 | /* Reset the timer to avoid issues after the RAM initialization */ |
mbed_official | 67:4bcbbb9fcddf | 224 | TIM_MST_RESET_ON; |
mbed_official | 67:4bcbbb9fcddf | 225 | TIM_MST_RESET_OFF; |
mbed_official | 67:4bcbbb9fcddf | 226 | } |
mbed_official | 67:4bcbbb9fcddf | 227 | |
mbed_official | 67:4bcbbb9fcddf | 228 | /** |
mbed_official | 67:4bcbbb9fcddf | 229 | * @brief Update SystemCoreClock according to Clock Register Values |
mbed_official | 67:4bcbbb9fcddf | 230 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
mbed_official | 67:4bcbbb9fcddf | 231 | * be used by the user application to setup the SysTick timer or configure |
mbed_official | 67:4bcbbb9fcddf | 232 | * other parameters. |
mbed_official | 67:4bcbbb9fcddf | 233 | * |
mbed_official | 67:4bcbbb9fcddf | 234 | * @note Each time the core clock (HCLK) changes, this function must be called |
mbed_official | 67:4bcbbb9fcddf | 235 | * to update SystemCoreClock variable value. Otherwise, any configuration |
mbed_official | 67:4bcbbb9fcddf | 236 | * based on this variable will be incorrect. |
mbed_official | 67:4bcbbb9fcddf | 237 | * |
mbed_official | 67:4bcbbb9fcddf | 238 | * @note - The system frequency computed by this function is not the real |
mbed_official | 67:4bcbbb9fcddf | 239 | * frequency in the chip. It is calculated based on the predefined |
mbed_official | 67:4bcbbb9fcddf | 240 | * constant and the selected clock source: |
mbed_official | 67:4bcbbb9fcddf | 241 | * |
mbed_official | 67:4bcbbb9fcddf | 242 | * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI |
mbed_official | 67:4bcbbb9fcddf | 243 | * value as defined by the MSI range. |
mbed_official | 67:4bcbbb9fcddf | 244 | * |
mbed_official | 67:4bcbbb9fcddf | 245 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
mbed_official | 67:4bcbbb9fcddf | 246 | * |
mbed_official | 67:4bcbbb9fcddf | 247 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 67:4bcbbb9fcddf | 248 | * |
mbed_official | 67:4bcbbb9fcddf | 249 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 67:4bcbbb9fcddf | 250 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
mbed_official | 67:4bcbbb9fcddf | 251 | * |
mbed_official | 67:4bcbbb9fcddf | 252 | * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value |
mbed_official | 67:4bcbbb9fcddf | 253 | * 16 MHz) but the real value may vary depending on the variations |
mbed_official | 67:4bcbbb9fcddf | 254 | * in voltage and temperature. |
mbed_official | 67:4bcbbb9fcddf | 255 | * |
mbed_official | 67:4bcbbb9fcddf | 256 | * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value |
mbed_official | 67:4bcbbb9fcddf | 257 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
mbed_official | 67:4bcbbb9fcddf | 258 | * frequency of the crystal used. Otherwise, this function may |
mbed_official | 67:4bcbbb9fcddf | 259 | * have wrong result. |
mbed_official | 67:4bcbbb9fcddf | 260 | * |
mbed_official | 67:4bcbbb9fcddf | 261 | * - The result of this function could be not correct when using fractional |
mbed_official | 67:4bcbbb9fcddf | 262 | * value for HSE crystal. |
mbed_official | 67:4bcbbb9fcddf | 263 | * @param None |
mbed_official | 67:4bcbbb9fcddf | 264 | * @retval None |
mbed_official | 67:4bcbbb9fcddf | 265 | */ |
mbed_official | 67:4bcbbb9fcddf | 266 | void SystemCoreClockUpdate (void) |
mbed_official | 67:4bcbbb9fcddf | 267 | { |
mbed_official | 67:4bcbbb9fcddf | 268 | uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; |
mbed_official | 67:4bcbbb9fcddf | 269 | |
mbed_official | 67:4bcbbb9fcddf | 270 | /* Get SYSCLK source -------------------------------------------------------*/ |
mbed_official | 67:4bcbbb9fcddf | 271 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
mbed_official | 67:4bcbbb9fcddf | 272 | |
mbed_official | 67:4bcbbb9fcddf | 273 | switch (tmp) |
mbed_official | 67:4bcbbb9fcddf | 274 | { |
mbed_official | 67:4bcbbb9fcddf | 275 | case 0x00: /* MSI used as system clock */ |
mbed_official | 67:4bcbbb9fcddf | 276 | msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; |
mbed_official | 67:4bcbbb9fcddf | 277 | SystemCoreClock = (32768 * (1 << (msirange + 1))); |
mbed_official | 67:4bcbbb9fcddf | 278 | break; |
mbed_official | 67:4bcbbb9fcddf | 279 | case 0x04: /* HSI used as system clock */ |
mbed_official | 67:4bcbbb9fcddf | 280 | SystemCoreClock = HSI_VALUE; |
mbed_official | 67:4bcbbb9fcddf | 281 | break; |
mbed_official | 67:4bcbbb9fcddf | 282 | case 0x08: /* HSE used as system clock */ |
mbed_official | 67:4bcbbb9fcddf | 283 | SystemCoreClock = HSE_VALUE; |
mbed_official | 67:4bcbbb9fcddf | 284 | break; |
mbed_official | 67:4bcbbb9fcddf | 285 | case 0x0C: /* PLL used as system clock */ |
mbed_official | 67:4bcbbb9fcddf | 286 | /* Get PLL clock source and multiplication factor ----------------------*/ |
mbed_official | 67:4bcbbb9fcddf | 287 | pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; |
mbed_official | 67:4bcbbb9fcddf | 288 | plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; |
mbed_official | 67:4bcbbb9fcddf | 289 | pllmul = PLLMulTable[(pllmul >> 18)]; |
mbed_official | 67:4bcbbb9fcddf | 290 | plldiv = (plldiv >> 22) + 1; |
mbed_official | 67:4bcbbb9fcddf | 291 | |
mbed_official | 67:4bcbbb9fcddf | 292 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
mbed_official | 67:4bcbbb9fcddf | 293 | |
mbed_official | 67:4bcbbb9fcddf | 294 | if (pllsource == 0x00) |
mbed_official | 67:4bcbbb9fcddf | 295 | { |
mbed_official | 67:4bcbbb9fcddf | 296 | /* HSI oscillator clock selected as PLL clock entry */ |
mbed_official | 67:4bcbbb9fcddf | 297 | SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); |
mbed_official | 67:4bcbbb9fcddf | 298 | } |
mbed_official | 67:4bcbbb9fcddf | 299 | else |
mbed_official | 67:4bcbbb9fcddf | 300 | { |
mbed_official | 67:4bcbbb9fcddf | 301 | /* HSE selected as PLL clock entry */ |
mbed_official | 67:4bcbbb9fcddf | 302 | SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); |
mbed_official | 67:4bcbbb9fcddf | 303 | } |
mbed_official | 67:4bcbbb9fcddf | 304 | break; |
mbed_official | 67:4bcbbb9fcddf | 305 | default: /* MSI used as system clock */ |
mbed_official | 67:4bcbbb9fcddf | 306 | msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; |
mbed_official | 67:4bcbbb9fcddf | 307 | SystemCoreClock = (32768 * (1 << (msirange + 1))); |
mbed_official | 67:4bcbbb9fcddf | 308 | break; |
mbed_official | 67:4bcbbb9fcddf | 309 | } |
mbed_official | 67:4bcbbb9fcddf | 310 | /* Compute HCLK clock frequency --------------------------------------------*/ |
mbed_official | 67:4bcbbb9fcddf | 311 | /* Get HCLK prescaler */ |
mbed_official | 67:4bcbbb9fcddf | 312 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
mbed_official | 67:4bcbbb9fcddf | 313 | /* HCLK clock frequency */ |
mbed_official | 67:4bcbbb9fcddf | 314 | SystemCoreClock >>= tmp; |
mbed_official | 67:4bcbbb9fcddf | 315 | } |
mbed_official | 67:4bcbbb9fcddf | 316 | |
mbed_official | 67:4bcbbb9fcddf | 317 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
mbed_official | 67:4bcbbb9fcddf | 318 | #ifdef DATA_IN_ExtSRAM |
mbed_official | 67:4bcbbb9fcddf | 319 | /** |
mbed_official | 67:4bcbbb9fcddf | 320 | * @brief Setup the external memory controller. |
mbed_official | 67:4bcbbb9fcddf | 321 | * Called in SystemInit() function before jump to main. |
mbed_official | 67:4bcbbb9fcddf | 322 | * This function configures the external SRAM mounted on STM32L152D_EVAL board |
mbed_official | 67:4bcbbb9fcddf | 323 | * This SRAM will be used as program data memory (including heap and stack). |
mbed_official | 67:4bcbbb9fcddf | 324 | * @param None |
mbed_official | 67:4bcbbb9fcddf | 325 | * @retval None |
mbed_official | 67:4bcbbb9fcddf | 326 | */ |
mbed_official | 67:4bcbbb9fcddf | 327 | void SystemInit_ExtMemCtl(void) |
mbed_official | 67:4bcbbb9fcddf | 328 | { |
mbed_official | 67:4bcbbb9fcddf | 329 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
mbed_official | 67:4bcbbb9fcddf | 330 | /* |
mbed_official | 67:4bcbbb9fcddf | 331 | +-------------------+--------------------+------------------+------------------+ |
mbed_official | 67:4bcbbb9fcddf | 332 | + SRAM pins assignment + |
mbed_official | 67:4bcbbb9fcddf | 333 | +-------------------+--------------------+------------------+------------------+ |
mbed_official | 67:4bcbbb9fcddf | 334 | | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | |
mbed_official | 67:4bcbbb9fcddf | 335 | | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | |
mbed_official | 67:4bcbbb9fcddf | 336 | | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | |
mbed_official | 67:4bcbbb9fcddf | 337 | | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | |
mbed_official | 67:4bcbbb9fcddf | 338 | | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | |
mbed_official | 67:4bcbbb9fcddf | 339 | | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | |
mbed_official | 67:4bcbbb9fcddf | 340 | | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 | |
mbed_official | 67:4bcbbb9fcddf | 341 | | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ |
mbed_official | 67:4bcbbb9fcddf | 342 | | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | |
mbed_official | 67:4bcbbb9fcddf | 343 | | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | |
mbed_official | 67:4bcbbb9fcddf | 344 | | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+ |
mbed_official | 67:4bcbbb9fcddf | 345 | | PD15 <-> FSMC_D1 |--------------------+ |
mbed_official | 67:4bcbbb9fcddf | 346 | +-------------------+ |
mbed_official | 67:4bcbbb9fcddf | 347 | */ |
mbed_official | 67:4bcbbb9fcddf | 348 | |
mbed_official | 67:4bcbbb9fcddf | 349 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
mbed_official | 67:4bcbbb9fcddf | 350 | RCC->AHBENR = 0x000080D8; |
mbed_official | 67:4bcbbb9fcddf | 351 | |
mbed_official | 67:4bcbbb9fcddf | 352 | /* Connect PDx pins to FSMC Alternate function */ |
mbed_official | 67:4bcbbb9fcddf | 353 | GPIOD->AFR[0] = 0x00CC00CC; |
mbed_official | 67:4bcbbb9fcddf | 354 | GPIOD->AFR[1] = 0xCCCCCCCC; |
mbed_official | 67:4bcbbb9fcddf | 355 | /* Configure PDx pins in Alternate function mode */ |
mbed_official | 67:4bcbbb9fcddf | 356 | GPIOD->MODER = 0xAAAA0A0A; |
mbed_official | 67:4bcbbb9fcddf | 357 | /* Configure PDx pins speed to 40 MHz */ |
mbed_official | 67:4bcbbb9fcddf | 358 | GPIOD->OSPEEDR = 0xFFFF0F0F; |
mbed_official | 67:4bcbbb9fcddf | 359 | /* Configure PDx pins Output type to push-pull */ |
mbed_official | 67:4bcbbb9fcddf | 360 | GPIOD->OTYPER = 0x00000000; |
mbed_official | 67:4bcbbb9fcddf | 361 | /* No pull-up, pull-down for PDx pins */ |
mbed_official | 67:4bcbbb9fcddf | 362 | GPIOD->PUPDR = 0x00000000; |
mbed_official | 67:4bcbbb9fcddf | 363 | |
mbed_official | 67:4bcbbb9fcddf | 364 | /* Connect PEx pins to FSMC Alternate function */ |
mbed_official | 67:4bcbbb9fcddf | 365 | GPIOE->AFR[0] = 0xC00000CC; |
mbed_official | 67:4bcbbb9fcddf | 366 | GPIOE->AFR[1] = 0xCCCCCCCC; |
mbed_official | 67:4bcbbb9fcddf | 367 | /* Configure PEx pins in Alternate function mode */ |
mbed_official | 67:4bcbbb9fcddf | 368 | GPIOE->MODER = 0xAAAA800A; |
mbed_official | 67:4bcbbb9fcddf | 369 | /* Configure PEx pins speed to 40 MHz */ |
mbed_official | 67:4bcbbb9fcddf | 370 | GPIOE->OSPEEDR = 0xFFFFC00F; |
mbed_official | 67:4bcbbb9fcddf | 371 | /* Configure PEx pins Output type to push-pull */ |
mbed_official | 67:4bcbbb9fcddf | 372 | GPIOE->OTYPER = 0x00000000; |
mbed_official | 67:4bcbbb9fcddf | 373 | /* No pull-up, pull-down for PEx pins */ |
mbed_official | 67:4bcbbb9fcddf | 374 | GPIOE->PUPDR = 0x00000000; |
mbed_official | 67:4bcbbb9fcddf | 375 | |
mbed_official | 67:4bcbbb9fcddf | 376 | /* Connect PFx pins to FSMC Alternate function */ |
mbed_official | 67:4bcbbb9fcddf | 377 | GPIOF->AFR[0] = 0x00CCCCCC; |
mbed_official | 67:4bcbbb9fcddf | 378 | GPIOF->AFR[1] = 0xCCCC0000; |
mbed_official | 67:4bcbbb9fcddf | 379 | /* Configure PFx pins in Alternate function mode */ |
mbed_official | 67:4bcbbb9fcddf | 380 | GPIOF->MODER = 0xAA000AAA; |
mbed_official | 67:4bcbbb9fcddf | 381 | /* Configure PFx pins speed to 40 MHz */ |
mbed_official | 67:4bcbbb9fcddf | 382 | GPIOF->OSPEEDR = 0xFF000FFF; |
mbed_official | 67:4bcbbb9fcddf | 383 | /* Configure PFx pins Output type to push-pull */ |
mbed_official | 67:4bcbbb9fcddf | 384 | GPIOF->OTYPER = 0x00000000; |
mbed_official | 67:4bcbbb9fcddf | 385 | /* No pull-up, pull-down for PFx pins */ |
mbed_official | 67:4bcbbb9fcddf | 386 | GPIOF->PUPDR = 0x00000000; |
mbed_official | 67:4bcbbb9fcddf | 387 | |
mbed_official | 67:4bcbbb9fcddf | 388 | /* Connect PGx pins to FSMC Alternate function */ |
mbed_official | 67:4bcbbb9fcddf | 389 | GPIOG->AFR[0] = 0x00CCCCCC; |
mbed_official | 67:4bcbbb9fcddf | 390 | GPIOG->AFR[1] = 0x00000C00; |
mbed_official | 67:4bcbbb9fcddf | 391 | /* Configure PGx pins in Alternate function mode */ |
mbed_official | 67:4bcbbb9fcddf | 392 | GPIOG->MODER = 0x00200AAA; |
mbed_official | 67:4bcbbb9fcddf | 393 | /* Configure PGx pins speed to 40 MHz */ |
mbed_official | 67:4bcbbb9fcddf | 394 | GPIOG->OSPEEDR = 0x00300FFF; |
mbed_official | 67:4bcbbb9fcddf | 395 | /* Configure PGx pins Output type to push-pull */ |
mbed_official | 67:4bcbbb9fcddf | 396 | GPIOG->OTYPER = 0x00000000; |
mbed_official | 67:4bcbbb9fcddf | 397 | /* No pull-up, pull-down for PGx pins */ |
mbed_official | 67:4bcbbb9fcddf | 398 | GPIOG->PUPDR = 0x00000000; |
mbed_official | 67:4bcbbb9fcddf | 399 | |
mbed_official | 67:4bcbbb9fcddf | 400 | /*-- FSMC Configuration ------------------------------------------------------*/ |
mbed_official | 67:4bcbbb9fcddf | 401 | /* Enable the FSMC interface clock */ |
mbed_official | 67:4bcbbb9fcddf | 402 | RCC->AHBENR = 0x400080D8; |
mbed_official | 67:4bcbbb9fcddf | 403 | |
mbed_official | 67:4bcbbb9fcddf | 404 | /* Configure and enable Bank1_SRAM3 */ |
mbed_official | 67:4bcbbb9fcddf | 405 | FSMC_Bank1->BTCR[4] = 0x00001011; |
mbed_official | 67:4bcbbb9fcddf | 406 | FSMC_Bank1->BTCR[5] = 0x00000300; |
mbed_official | 67:4bcbbb9fcddf | 407 | FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF; |
mbed_official | 67:4bcbbb9fcddf | 408 | /* |
mbed_official | 67:4bcbbb9fcddf | 409 | Bank1_SRAM3 is configured as follow: |
mbed_official | 67:4bcbbb9fcddf | 410 | |
mbed_official | 67:4bcbbb9fcddf | 411 | p.FSMC_AddressSetupTime = 0; |
mbed_official | 67:4bcbbb9fcddf | 412 | p.FSMC_AddressHoldTime = 0; |
mbed_official | 67:4bcbbb9fcddf | 413 | p.FSMC_DataSetupTime = 3; |
mbed_official | 67:4bcbbb9fcddf | 414 | p.FSMC_BusTurnAroundDuration = 0; |
mbed_official | 67:4bcbbb9fcddf | 415 | p.FSMC_CLKDivision = 0; |
mbed_official | 67:4bcbbb9fcddf | 416 | p.FSMC_DataLatency = 0; |
mbed_official | 67:4bcbbb9fcddf | 417 | p.FSMC_AccessMode = FSMC_AccessMode_A; |
mbed_official | 67:4bcbbb9fcddf | 418 | |
mbed_official | 67:4bcbbb9fcddf | 419 | FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; |
mbed_official | 67:4bcbbb9fcddf | 420 | FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; |
mbed_official | 67:4bcbbb9fcddf | 421 | FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; |
mbed_official | 67:4bcbbb9fcddf | 422 | FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; |
mbed_official | 67:4bcbbb9fcddf | 423 | FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; |
mbed_official | 67:4bcbbb9fcddf | 424 | FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; |
mbed_official | 67:4bcbbb9fcddf | 425 | FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; |
mbed_official | 67:4bcbbb9fcddf | 426 | FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; |
mbed_official | 67:4bcbbb9fcddf | 427 | FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; |
mbed_official | 67:4bcbbb9fcddf | 428 | FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; |
mbed_official | 67:4bcbbb9fcddf | 429 | FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; |
mbed_official | 67:4bcbbb9fcddf | 430 | FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; |
mbed_official | 67:4bcbbb9fcddf | 431 | FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; |
mbed_official | 67:4bcbbb9fcddf | 432 | FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; |
mbed_official | 67:4bcbbb9fcddf | 433 | FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; |
mbed_official | 67:4bcbbb9fcddf | 434 | |
mbed_official | 67:4bcbbb9fcddf | 435 | FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); |
mbed_official | 67:4bcbbb9fcddf | 436 | |
mbed_official | 67:4bcbbb9fcddf | 437 | FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); |
mbed_official | 67:4bcbbb9fcddf | 438 | */ |
mbed_official | 67:4bcbbb9fcddf | 439 | |
mbed_official | 67:4bcbbb9fcddf | 440 | } |
mbed_official | 67:4bcbbb9fcddf | 441 | #endif /* DATA_IN_ExtSRAM */ |
mbed_official | 67:4bcbbb9fcddf | 442 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
mbed_official | 67:4bcbbb9fcddf | 443 | |
mbed_official | 67:4bcbbb9fcddf | 444 | /** |
mbed_official | 67:4bcbbb9fcddf | 445 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
mbed_official | 67:4bcbbb9fcddf | 446 | * AHB/APBx prescalers and Flash settings |
mbed_official | 67:4bcbbb9fcddf | 447 | * @note This function should be called only once the RCC clock configuration |
mbed_official | 67:4bcbbb9fcddf | 448 | * is reset to the default reset state (done in SystemInit() function). |
mbed_official | 67:4bcbbb9fcddf | 449 | * @param None |
mbed_official | 67:4bcbbb9fcddf | 450 | * @retval None |
mbed_official | 67:4bcbbb9fcddf | 451 | */ |
mbed_official | 67:4bcbbb9fcddf | 452 | void SetSysClock(void) |
mbed_official | 67:4bcbbb9fcddf | 453 | { |
mbed_official | 67:4bcbbb9fcddf | 454 | /* 1- Try to start with HSE and external clock */ |
mbed_official | 67:4bcbbb9fcddf | 455 | #if USE_PLL_HSE_EXTC != 0 |
mbed_official | 67:4bcbbb9fcddf | 456 | if (SetSysClock_PLL_HSE(1) == 0) |
mbed_official | 67:4bcbbb9fcddf | 457 | #endif |
mbed_official | 67:4bcbbb9fcddf | 458 | { |
mbed_official | 67:4bcbbb9fcddf | 459 | /* 2- If fail try to start with HSE and external xtal */ |
mbed_official | 67:4bcbbb9fcddf | 460 | #if USE_PLL_HSE_XTAL != 0 |
mbed_official | 67:4bcbbb9fcddf | 461 | if (SetSysClock_PLL_HSE(0) == 0) |
mbed_official | 67:4bcbbb9fcddf | 462 | #endif |
mbed_official | 67:4bcbbb9fcddf | 463 | { |
mbed_official | 67:4bcbbb9fcddf | 464 | /* 3- If fail start with HSI clock */ |
mbed_official | 67:4bcbbb9fcddf | 465 | if (SetSysClock_PLL_HSI() == 0) |
mbed_official | 67:4bcbbb9fcddf | 466 | { |
mbed_official | 67:4bcbbb9fcddf | 467 | while(1) |
mbed_official | 67:4bcbbb9fcddf | 468 | { |
mbed_official | 67:4bcbbb9fcddf | 469 | // [TODO] Put something here to tell the user that a problem occured... |
mbed_official | 67:4bcbbb9fcddf | 470 | } |
mbed_official | 67:4bcbbb9fcddf | 471 | } |
mbed_official | 67:4bcbbb9fcddf | 472 | } |
mbed_official | 67:4bcbbb9fcddf | 473 | } |
mbed_official | 67:4bcbbb9fcddf | 474 | |
mbed_official | 67:4bcbbb9fcddf | 475 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
mbed_official | 67:4bcbbb9fcddf | 476 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); |
mbed_official | 67:4bcbbb9fcddf | 477 | } |
mbed_official | 67:4bcbbb9fcddf | 478 | |
mbed_official | 67:4bcbbb9fcddf | 479 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
mbed_official | 67:4bcbbb9fcddf | 480 | /******************************************************************************/ |
mbed_official | 67:4bcbbb9fcddf | 481 | /* PLL (clocked by HSE) used as System clock source */ |
mbed_official | 67:4bcbbb9fcddf | 482 | /******************************************************************************/ |
mbed_official | 67:4bcbbb9fcddf | 483 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
mbed_official | 67:4bcbbb9fcddf | 484 | { |
mbed_official | 67:4bcbbb9fcddf | 485 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
mbed_official | 67:4bcbbb9fcddf | 486 | RCC_OscInitTypeDef RCC_OscInitStruct; |
mbed_official | 67:4bcbbb9fcddf | 487 | |
mbed_official | 67:4bcbbb9fcddf | 488 | /* Used to gain time after DeepSleep in case HSI is used */ |
mbed_official | 67:4bcbbb9fcddf | 489 | if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) |
mbed_official | 67:4bcbbb9fcddf | 490 | { |
mbed_official | 67:4bcbbb9fcddf | 491 | return 0; |
mbed_official | 67:4bcbbb9fcddf | 492 | } |
mbed_official | 67:4bcbbb9fcddf | 493 | |
mbed_official | 67:4bcbbb9fcddf | 494 | /* The voltage scaling allows optimizing the power consumption when the device is |
mbed_official | 67:4bcbbb9fcddf | 495 | clocked below the maximum system frequency, to update the voltage scaling value |
mbed_official | 67:4bcbbb9fcddf | 496 | regarding system frequency refer to product datasheet. */ |
mbed_official | 67:4bcbbb9fcddf | 497 | __PWR_CLK_ENABLE(); |
mbed_official | 67:4bcbbb9fcddf | 498 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
mbed_official | 67:4bcbbb9fcddf | 499 | |
mbed_official | 67:4bcbbb9fcddf | 500 | /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ |
mbed_official | 67:4bcbbb9fcddf | 501 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; |
mbed_official | 67:4bcbbb9fcddf | 502 | if (bypass == 0) |
mbed_official | 67:4bcbbb9fcddf | 503 | { |
mbed_official | 67:4bcbbb9fcddf | 504 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 16 MHz xtal on OSC_IN/OSC_OUT */ |
mbed_official | 67:4bcbbb9fcddf | 505 | } |
mbed_official | 67:4bcbbb9fcddf | 506 | else |
mbed_official | 67:4bcbbb9fcddf | 507 | { |
mbed_official | 67:4bcbbb9fcddf | 508 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 16 MHz clock on OSC_IN */ |
mbed_official | 67:4bcbbb9fcddf | 509 | } |
mbed_official | 67:4bcbbb9fcddf | 510 | RCC_OscInitStruct.HSIState = RCC_HSI_OFF; |
mbed_official | 67:4bcbbb9fcddf | 511 | // SYSCLK = 32 MHz ((16 MHz * 6) / 3) |
mbed_official | 67:4bcbbb9fcddf | 512 | // USBCLK = 48 MHz ((16 MHz * 6) / 2) --> USB OK |
mbed_official | 67:4bcbbb9fcddf | 513 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
mbed_official | 67:4bcbbb9fcddf | 514 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
mbed_official | 67:4bcbbb9fcddf | 515 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; |
mbed_official | 67:4bcbbb9fcddf | 516 | RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3; |
mbed_official | 67:4bcbbb9fcddf | 517 | |
mbed_official | 67:4bcbbb9fcddf | 518 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
mbed_official | 67:4bcbbb9fcddf | 519 | { |
mbed_official | 67:4bcbbb9fcddf | 520 | return 0; // FAIL |
mbed_official | 67:4bcbbb9fcddf | 521 | } |
mbed_official | 67:4bcbbb9fcddf | 522 | |
mbed_official | 67:4bcbbb9fcddf | 523 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
mbed_official | 67:4bcbbb9fcddf | 524 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
mbed_official | 67:4bcbbb9fcddf | 525 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz |
mbed_official | 67:4bcbbb9fcddf | 526 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz |
mbed_official | 67:4bcbbb9fcddf | 527 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
mbed_official | 67:4bcbbb9fcddf | 528 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
mbed_official | 67:4bcbbb9fcddf | 529 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) |
mbed_official | 67:4bcbbb9fcddf | 530 | { |
mbed_official | 67:4bcbbb9fcddf | 531 | return 0; // FAIL |
mbed_official | 67:4bcbbb9fcddf | 532 | } |
mbed_official | 67:4bcbbb9fcddf | 533 | |
mbed_official | 67:4bcbbb9fcddf | 534 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
mbed_official | 67:4bcbbb9fcddf | 535 | //if (bypass == 0) |
mbed_official | 67:4bcbbb9fcddf | 536 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz |
mbed_official | 67:4bcbbb9fcddf | 537 | //else |
mbed_official | 67:4bcbbb9fcddf | 538 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz |
mbed_official | 67:4bcbbb9fcddf | 539 | |
mbed_official | 67:4bcbbb9fcddf | 540 | return 1; // OK |
mbed_official | 67:4bcbbb9fcddf | 541 | } |
mbed_official | 67:4bcbbb9fcddf | 542 | #endif |
mbed_official | 67:4bcbbb9fcddf | 543 | |
mbed_official | 67:4bcbbb9fcddf | 544 | /******************************************************************************/ |
mbed_official | 67:4bcbbb9fcddf | 545 | /* PLL (clocked by HSI) used as System clock source */ |
mbed_official | 67:4bcbbb9fcddf | 546 | /******************************************************************************/ |
mbed_official | 67:4bcbbb9fcddf | 547 | uint8_t SetSysClock_PLL_HSI(void) |
mbed_official | 67:4bcbbb9fcddf | 548 | { |
mbed_official | 67:4bcbbb9fcddf | 549 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
mbed_official | 67:4bcbbb9fcddf | 550 | RCC_OscInitTypeDef RCC_OscInitStruct; |
mbed_official | 67:4bcbbb9fcddf | 551 | |
mbed_official | 67:4bcbbb9fcddf | 552 | /* The voltage scaling allows optimizing the power consumption when the device is |
mbed_official | 67:4bcbbb9fcddf | 553 | clocked below the maximum system frequency, to update the voltage scaling value |
mbed_official | 67:4bcbbb9fcddf | 554 | regarding system frequency refer to product datasheet. */ |
mbed_official | 67:4bcbbb9fcddf | 555 | __PWR_CLK_ENABLE(); |
mbed_official | 67:4bcbbb9fcddf | 556 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
mbed_official | 67:4bcbbb9fcddf | 557 | |
mbed_official | 67:4bcbbb9fcddf | 558 | /* Enable HSI oscillator and activate PLL with HSI as source */ |
mbed_official | 67:4bcbbb9fcddf | 559 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
mbed_official | 67:4bcbbb9fcddf | 560 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
mbed_official | 67:4bcbbb9fcddf | 561 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
mbed_official | 67:4bcbbb9fcddf | 562 | // SYSCLK = 32 MHz ((16 MHz * 4) / 2) |
mbed_official | 67:4bcbbb9fcddf | 563 | // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible |
mbed_official | 67:4bcbbb9fcddf | 564 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
mbed_official | 67:4bcbbb9fcddf | 565 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; |
mbed_official | 67:4bcbbb9fcddf | 566 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; |
mbed_official | 67:4bcbbb9fcddf | 567 | RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2; |
mbed_official | 67:4bcbbb9fcddf | 568 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
mbed_official | 67:4bcbbb9fcddf | 569 | { |
mbed_official | 67:4bcbbb9fcddf | 570 | return 0; // FAIL |
mbed_official | 67:4bcbbb9fcddf | 571 | } |
mbed_official | 67:4bcbbb9fcddf | 572 | |
mbed_official | 67:4bcbbb9fcddf | 573 | /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */ |
mbed_official | 67:4bcbbb9fcddf | 574 | while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {}; |
mbed_official | 67:4bcbbb9fcddf | 575 | |
mbed_official | 67:4bcbbb9fcddf | 576 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
mbed_official | 67:4bcbbb9fcddf | 577 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
mbed_official | 67:4bcbbb9fcddf | 578 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz |
mbed_official | 67:4bcbbb9fcddf | 579 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz |
mbed_official | 67:4bcbbb9fcddf | 580 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
mbed_official | 67:4bcbbb9fcddf | 581 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
mbed_official | 67:4bcbbb9fcddf | 582 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) |
mbed_official | 67:4bcbbb9fcddf | 583 | { |
mbed_official | 67:4bcbbb9fcddf | 584 | return 0; // FAIL |
mbed_official | 67:4bcbbb9fcddf | 585 | } |
mbed_official | 67:4bcbbb9fcddf | 586 | |
mbed_official | 67:4bcbbb9fcddf | 587 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
mbed_official | 67:4bcbbb9fcddf | 588 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz |
mbed_official | 67:4bcbbb9fcddf | 589 | |
mbed_official | 67:4bcbbb9fcddf | 590 | return 1; // OK |
mbed_official | 67:4bcbbb9fcddf | 591 | } |
mbed_official | 67:4bcbbb9fcddf | 592 | |
mbed_official | 67:4bcbbb9fcddf | 593 | /** |
mbed_official | 67:4bcbbb9fcddf | 594 | * @} |
mbed_official | 67:4bcbbb9fcddf | 595 | */ |
mbed_official | 67:4bcbbb9fcddf | 596 | |
mbed_official | 67:4bcbbb9fcddf | 597 | /** |
mbed_official | 67:4bcbbb9fcddf | 598 | * @} |
mbed_official | 67:4bcbbb9fcddf | 599 | */ |
mbed_official | 67:4bcbbb9fcddf | 600 | |
mbed_official | 67:4bcbbb9fcddf | 601 | /** |
mbed_official | 67:4bcbbb9fcddf | 602 | * @} |
mbed_official | 67:4bcbbb9fcddf | 603 | */ |
mbed_official | 67:4bcbbb9fcddf | 604 | |
mbed_official | 67:4bcbbb9fcddf | 605 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |