mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 113:b3775bf36a83

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l0xx_hal_i2s.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	113:b3775bf36a83	5	* @version V1.5.0
mbed_official	113:b3775bf36a83	6	* @date 8-January-2016
bogdanm	0:9b334a45a8ff	7	* @brief I2S HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Integrated Interchip Sound (I2S) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + IO operation functions
bogdanm	0:9b334a45a8ff	12	* + Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	13	@verbatim
bogdanm	0:9b334a45a8ff	14	===============================================================================
bogdanm	0:9b334a45a8ff	15	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	16	===============================================================================
bogdanm	0:9b334a45a8ff	17	[..]
bogdanm	0:9b334a45a8ff	18	The I2S HAL driver can be used as follow:
bogdanm	0:9b334a45a8ff	19
bogdanm	0:9b334a45a8ff	20	(#) Declare a I2S_HandleTypeDef handle structure.
bogdanm	0:9b334a45a8ff	21	(#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
bogdanm	0:9b334a45a8ff	22	(##) Enable the SPIx interface clock.
bogdanm	0:9b334a45a8ff	23	(##) I2S pins configuration:
bogdanm	0:9b334a45a8ff	24	(+++) Enable the clock for the I2S GPIOs.
bogdanm	0:9b334a45a8ff	25	(+++) Configure these I2S pins as alternate function.
bogdanm	0:9b334a45a8ff	26	(##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
bogdanm	0:9b334a45a8ff	27	and HAL_I2S_Receive_IT() APIs).
bogdanm	0:9b334a45a8ff	28	(+++) Configure the I2Sx interrupt priority.
bogdanm	0:9b334a45a8ff	29	(+++) Enable the NVIC I2S IRQ handle.
bogdanm	0:9b334a45a8ff	30	(##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
bogdanm	0:9b334a45a8ff	31	and HAL_I2S_Receive_DMA() APIs:
bogdanm	0:9b334a45a8ff	32	(+++) Declare a DMA handle structure for the Tx/Rx Channel.
bogdanm	0:9b334a45a8ff	33	(+++) Enable the DMAx interface clock.
bogdanm	0:9b334a45a8ff	34	(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
bogdanm	0:9b334a45a8ff	35	(+++) Configure the DMA Tx/Rx Channel.
bogdanm	0:9b334a45a8ff	36	(+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
bogdanm	0:9b334a45a8ff	37	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
bogdanm	0:9b334a45a8ff	38	DMA Tx/Rx Channel.
bogdanm	0:9b334a45a8ff	39
bogdanm	0:9b334a45a8ff	40	(#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
bogdanm	0:9b334a45a8ff	41	using HAL_I2S_Init() function.
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	-@- The specific I2S interrupts (Transmission complete interrupt,
bogdanm	0:9b334a45a8ff	44	RXNE interrupt and Error Interrupts) will be managed using the macros
bogdanm	0:9b334a45a8ff	45	__HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
bogdanm	0:9b334a45a8ff	46	-@- Make sure that either:
bogdanm	0:9b334a45a8ff	47	(+@) External clock source is configured after setting correctly
bogdanm	0:9b334a45a8ff	48	the define constant HSE_VALUE in the stm32l0xx_hal_conf.h file.
bogdanm	0:9b334a45a8ff	49
bogdanm	0:9b334a45a8ff	50	(#) Three mode of operations are available within this driver :
bogdanm	0:9b334a45a8ff	51
bogdanm	0:9b334a45a8ff	52	* Polling mode IO operation *
bogdanm	0:9b334a45a8ff	53	=================================
bogdanm	0:9b334a45a8ff	54	[..]
bogdanm	0:9b334a45a8ff	55	(+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
bogdanm	0:9b334a45a8ff	56	(+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
bogdanm	0:9b334a45a8ff	57
bogdanm	0:9b334a45a8ff	58	* Interrupt mode IO operation *
bogdanm	0:9b334a45a8ff	59	===================================
bogdanm	0:9b334a45a8ff	60	[..]
bogdanm	0:9b334a45a8ff	61	(+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
bogdanm	0:9b334a45a8ff	62	(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	63	add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm	0:9b334a45a8ff	64	(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	65	add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm	0:9b334a45a8ff	66	(+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
bogdanm	0:9b334a45a8ff	67	(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	68	add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm	0:9b334a45a8ff	69	(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	70	add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm	0:9b334a45a8ff	71	(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	72	add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm	0:9b334a45a8ff	73
bogdanm	0:9b334a45a8ff	74	* DMA mode IO operation *
bogdanm	0:9b334a45a8ff	75	==============================
bogdanm	0:9b334a45a8ff	76	[..]
bogdanm	0:9b334a45a8ff	77	(+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
bogdanm	0:9b334a45a8ff	78	(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	79	add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
bogdanm	0:9b334a45a8ff	80	(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	81	add his own code by customization of function pointer HAL_I2S_TxCpltCallback
bogdanm	0:9b334a45a8ff	82	(+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
bogdanm	0:9b334a45a8ff	83	(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	84	add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
bogdanm	0:9b334a45a8ff	85	(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
bogdanm	0:9b334a45a8ff	86	add his own code by customization of function pointer HAL_I2S_RxCpltCallback
bogdanm	0:9b334a45a8ff	87	(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	88	add his own code by customization of function pointer HAL_I2S_ErrorCallback
bogdanm	0:9b334a45a8ff	89	(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
bogdanm	0:9b334a45a8ff	90	(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
bogdanm	0:9b334a45a8ff	91	(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	* I2S HAL driver macros list *
bogdanm	0:9b334a45a8ff	94	===================================
bogdanm	0:9b334a45a8ff	95	[..]
bogdanm	0:9b334a45a8ff	96	Below the list of most used macros in USART HAL driver.
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	(+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
bogdanm	0:9b334a45a8ff	99	(+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
bogdanm	0:9b334a45a8ff	100	(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
bogdanm	0:9b334a45a8ff	101	(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
bogdanm	0:9b334a45a8ff	102	(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	[..]
bogdanm	0:9b334a45a8ff	105	(@) You can refer to the I2S HAL driver header file for more useful macros
bogdanm	0:9b334a45a8ff	106
bogdanm	0:9b334a45a8ff	107	@endverbatim
bogdanm	0:9b334a45a8ff	108	******************************************************************************
bogdanm	0:9b334a45a8ff	109	* @attention
bogdanm	0:9b334a45a8ff	110	*
mbed_official	113:b3775bf36a83	111	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	112	*
bogdanm	0:9b334a45a8ff	113	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	114	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	115	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	116	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	117	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	118	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	119	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	120	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	121	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	122	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	123	*
bogdanm	0:9b334a45a8ff	124	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	125	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	126	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	127	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	128	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	129	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	130	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	131	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	132	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	133	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	134	*
bogdanm	0:9b334a45a8ff	135	******************************************************************************
bogdanm	0:9b334a45a8ff	136	*/
bogdanm	0:9b334a45a8ff	137
mbed_official	113:b3775bf36a83	138	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
bogdanm	0:9b334a45a8ff	139	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	140	#include "stm32l0xx_hal.h"
bogdanm	0:9b334a45a8ff	141
bogdanm	0:9b334a45a8ff	142	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	143	* @{
bogdanm	0:9b334a45a8ff	144	*/
bogdanm	0:9b334a45a8ff	145
mbed_official	113:b3775bf36a83	146	#ifdef HAL_I2S_MODULE_ENABLED
mbed_official	113:b3775bf36a83	147
mbed_official	113:b3775bf36a83	148	/** @addtogroup I2S I2S
bogdanm	0:9b334a45a8ff	149	* @brief I2S HAL module driver
bogdanm	0:9b334a45a8ff	150	* @{
bogdanm	0:9b334a45a8ff	151	*/
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	156	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	157	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	158	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	159	/* Private function prototypes -----------------------------------------------*/
mbed_official	113:b3775bf36a83	160	/** @addtogroup I2S_Private
bogdanm	0:9b334a45a8ff	161	* @{
bogdanm	0:9b334a45a8ff	162	*/
bogdanm	0:9b334a45a8ff	163	static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	164	static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	165	static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	166	static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	167	static void I2S_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	168	static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
bogdanm	0:9b334a45a8ff	169	static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
bogdanm	0:9b334a45a8ff	170	static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	171	/**
bogdanm	0:9b334a45a8ff	172	* @}
bogdanm	0:9b334a45a8ff	173	*/
bogdanm	0:9b334a45a8ff	174
bogdanm	0:9b334a45a8ff	175	/* Exported functions ---------------------------------------------------------*/
mbed_official	113:b3775bf36a83	176	/** @addtogroup I2S_Exported_Functions I2S Exported Functions
bogdanm	0:9b334a45a8ff	177	* @{
bogdanm	0:9b334a45a8ff	178	*/
bogdanm	0:9b334a45a8ff	179
mbed_official	113:b3775bf36a83	180	/** @addtogroup I2S_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	181	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	182	*
bogdanm	0:9b334a45a8ff	183	@verbatim
bogdanm	0:9b334a45a8ff	184	===============================================================================
bogdanm	0:9b334a45a8ff	185	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	186	===============================================================================
bogdanm	0:9b334a45a8ff	187	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	188	de-initialiaze the I2Sx peripheral in simplex mode:
bogdanm	0:9b334a45a8ff	189
bogdanm	0:9b334a45a8ff	190	(+) User must Implement HAL_I2S_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	191	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	(+) Call the function HAL_I2S_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	194	the selected configuration:
bogdanm	0:9b334a45a8ff	195	(++) Mode
bogdanm	0:9b334a45a8ff	196	(++) Standard
bogdanm	0:9b334a45a8ff	197	(++) Data Format
bogdanm	0:9b334a45a8ff	198	(++) MCLK Output
bogdanm	0:9b334a45a8ff	199	(++) Audio frequency
bogdanm	0:9b334a45a8ff	200	(++) Polarity
bogdanm	0:9b334a45a8ff	201
bogdanm	0:9b334a45a8ff	202	(+) Call the function HAL_I2S_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	203	of the selected I2Sx periperal.
bogdanm	0:9b334a45a8ff	204	@endverbatim
bogdanm	0:9b334a45a8ff	205	* @{
bogdanm	0:9b334a45a8ff	206	*/
bogdanm	0:9b334a45a8ff	207
bogdanm	0:9b334a45a8ff	208	/**
bogdanm	0:9b334a45a8ff	209	* @brief Initializes the I2S according to the specified parameters
bogdanm	0:9b334a45a8ff	210	* in the I2S_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	211	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	212	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	213	* @retval HAL status
bogdanm	0:9b334a45a8ff	214	*/
bogdanm	0:9b334a45a8ff	215	HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	216	{
bogdanm	0:9b334a45a8ff	217	uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1;
bogdanm	0:9b334a45a8ff	218	uint32_t tmp = 0, i2sclk = 0, tmpreg = 0;
bogdanm	0:9b334a45a8ff	219
bogdanm	0:9b334a45a8ff	220	/* Check the I2S handle allocation */
bogdanm	0:9b334a45a8ff	221	if(hi2s == NULL)
bogdanm	0:9b334a45a8ff	222	{
bogdanm	0:9b334a45a8ff	223	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	224	}
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	/* Check the I2S parameters */
bogdanm	0:9b334a45a8ff	227	assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
bogdanm	0:9b334a45a8ff	228	assert_param(IS_I2S_MODE(hi2s->Init.Mode));
bogdanm	0:9b334a45a8ff	229	assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
bogdanm	0:9b334a45a8ff	230	assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
bogdanm	0:9b334a45a8ff	231	assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
bogdanm	0:9b334a45a8ff	232	assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
bogdanm	0:9b334a45a8ff	233	assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	if(hi2s->State == HAL_I2S_STATE_RESET)
bogdanm	0:9b334a45a8ff	236	{
mbed_official	113:b3775bf36a83	237	/* Allocate lock resource and initialize it */
mbed_official	113:b3775bf36a83	238	hi2s->Lock = HAL_UNLOCKED;
mbed_official	113:b3775bf36a83	239
bogdanm	0:9b334a45a8ff	240	/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
bogdanm	0:9b334a45a8ff	241	HAL_I2S_MspInit(hi2s);
bogdanm	0:9b334a45a8ff	242	}
bogdanm	0:9b334a45a8ff	243
bogdanm	0:9b334a45a8ff	244	hi2s->State = HAL_I2S_STATE_BUSY;
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
bogdanm	0:9b334a45a8ff	247	if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
bogdanm	0:9b334a45a8ff	248	{
bogdanm	0:9b334a45a8ff	249	i2sodd = (uint32_t)0;
bogdanm	0:9b334a45a8ff	250	i2sdiv = (uint32_t)2;
bogdanm	0:9b334a45a8ff	251	}
bogdanm	0:9b334a45a8ff	252	/* If the requested audio frequency is not the default, compute the prescaler */
bogdanm	0:9b334a45a8ff	253	else
bogdanm	0:9b334a45a8ff	254	{
bogdanm	0:9b334a45a8ff	255	/* Check the frame length (For the Prescaler computing) *******************/
bogdanm	0:9b334a45a8ff	256	if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
bogdanm	0:9b334a45a8ff	257	{
bogdanm	0:9b334a45a8ff	258	/* Packet length is 16 bits */
bogdanm	0:9b334a45a8ff	259	packetlength = 1;
bogdanm	0:9b334a45a8ff	260	}
bogdanm	0:9b334a45a8ff	261	else
bogdanm	0:9b334a45a8ff	262	{
bogdanm	0:9b334a45a8ff	263	/* Packet length is 32 bits */
bogdanm	0:9b334a45a8ff	264	packetlength = 2;
bogdanm	0:9b334a45a8ff	265	}
bogdanm	0:9b334a45a8ff	266
bogdanm	0:9b334a45a8ff	267	/* Get the source clock value: based on System Clock value */
bogdanm	0:9b334a45a8ff	268	i2sclk = HAL_RCC_GetSysClockFreq();
bogdanm	0:9b334a45a8ff	269
bogdanm	0:9b334a45a8ff	270	/* Compute the Real divider depending on the MCLK output state, with a floating point */
bogdanm	0:9b334a45a8ff	271	if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
bogdanm	0:9b334a45a8ff	272	{
bogdanm	0:9b334a45a8ff	273	/* MCLK output is enabled */
bogdanm	0:9b334a45a8ff	274	tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
bogdanm	0:9b334a45a8ff	275	}
bogdanm	0:9b334a45a8ff	276	else
bogdanm	0:9b334a45a8ff	277	{
bogdanm	0:9b334a45a8ff	278	/* MCLK output is disabled */
bogdanm	0:9b334a45a8ff	279	tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
bogdanm	0:9b334a45a8ff	280	}
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282	/* Remove the flatting point */
bogdanm	0:9b334a45a8ff	283	tmp = tmp / 10;
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	/* Check the parity of the divider */
bogdanm	0:9b334a45a8ff	286	i2sodd = (uint32_t)(tmp & (uint32_t)1);
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	/* Compute the i2sdiv prescaler */
bogdanm	0:9b334a45a8ff	289	i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
bogdanm	0:9b334a45a8ff	290
bogdanm	0:9b334a45a8ff	291	/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
bogdanm	0:9b334a45a8ff	292	i2sodd = (uint32_t) (i2sodd << 8);
bogdanm	0:9b334a45a8ff	293	}
bogdanm	0:9b334a45a8ff	294
bogdanm	0:9b334a45a8ff	295	/* Test if the divider is 1 or 0 or greater than 0xFF */
bogdanm	0:9b334a45a8ff	296	if((i2sdiv < 2) \|\| (i2sdiv > 0xFF))
bogdanm	0:9b334a45a8ff	297	{
bogdanm	0:9b334a45a8ff	298	/* Set the default values */
bogdanm	0:9b334a45a8ff	299	i2sdiv = 2;
bogdanm	0:9b334a45a8ff	300	i2sodd = 0;
bogdanm	0:9b334a45a8ff	301	}
bogdanm	0:9b334a45a8ff	302
bogdanm	0:9b334a45a8ff	303	/----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------/
bogdanm	0:9b334a45a8ff	304
bogdanm	0:9b334a45a8ff	305	/* Write to SPIx I2SPR register the computed value */
bogdanm	0:9b334a45a8ff	306	hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv \| (uint32_t)(i2sodd \| (uint32_t)hi2s->Init.MCLKOutput));
bogdanm	0:9b334a45a8ff	307
bogdanm	0:9b334a45a8ff	308	/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
bogdanm	0:9b334a45a8ff	309	/* And configure the I2S with the I2S_InitStruct values */
bogdanm	0:9b334a45a8ff	310	MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN \|\
bogdanm	0:9b334a45a8ff	311	SPI_I2SCFGR_CKPOL \| SPI_I2SCFGR_I2SSTD \|\
bogdanm	0:9b334a45a8ff	312	SPI_I2SCFGR_PCMSYNC \| SPI_I2SCFGR_I2SCFG \|\
bogdanm	0:9b334a45a8ff	313	SPI_I2SCFGR_I2SE \| SPI_I2SCFGR_I2SMOD),\
bogdanm	0:9b334a45a8ff	314	(SPI_I2SCFGR_I2SMOD \| hi2s->Init.Mode \|\
bogdanm	0:9b334a45a8ff	315	hi2s->Init.Standard \| hi2s->Init.DataFormat \|\
bogdanm	0:9b334a45a8ff	316	hi2s->Init.CPOL));
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	/* Get the I2SCFGR register value */
bogdanm	0:9b334a45a8ff	319	tmpreg = hi2s->Instance->I2SCFGR;
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	#if defined(SPI_I2SCFGR_ASTRTEN)
bogdanm	0:9b334a45a8ff	322	if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
bogdanm	0:9b334a45a8ff	323	{
bogdanm	0:9b334a45a8ff	324	/* Write to SPIx I2SCFGR */
bogdanm	0:9b334a45a8ff	325	hi2s->Instance->I2SCFGR = tmpreg \| SPI_I2SCFGR_ASTRTEN;
bogdanm	0:9b334a45a8ff	326	}
bogdanm	0:9b334a45a8ff	327	else
bogdanm	0:9b334a45a8ff	328	{
bogdanm	0:9b334a45a8ff	329	/* Write to SPIx I2SCFGR */
bogdanm	0:9b334a45a8ff	330	hi2s->Instance->I2SCFGR = tmpreg;
bogdanm	0:9b334a45a8ff	331	}
bogdanm	0:9b334a45a8ff	332	#else
bogdanm	0:9b334a45a8ff	333	/* Write to SPIx I2SCFGR */
bogdanm	0:9b334a45a8ff	334	hi2s->Instance->I2SCFGR = tmpreg;
bogdanm	0:9b334a45a8ff	335	#endif
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	338	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	return HAL_OK;
bogdanm	0:9b334a45a8ff	341	}
bogdanm	0:9b334a45a8ff	342
bogdanm	0:9b334a45a8ff	343	/**
bogdanm	0:9b334a45a8ff	344	* @brief DeInitializes the I2S peripheral
bogdanm	0:9b334a45a8ff	345	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	346	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	347	* @retval HAL status
bogdanm	0:9b334a45a8ff	348	*/
bogdanm	0:9b334a45a8ff	349	HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	350	{
bogdanm	0:9b334a45a8ff	351	/* Check the I2S handle allocation */
bogdanm	0:9b334a45a8ff	352	if(hi2s == NULL)
bogdanm	0:9b334a45a8ff	353	{
bogdanm	0:9b334a45a8ff	354	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	355	}
bogdanm	0:9b334a45a8ff	356
bogdanm	0:9b334a45a8ff	357	hi2s->State = HAL_I2S_STATE_BUSY;
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	/* Disable the I2S Peripheral Clock */
bogdanm	0:9b334a45a8ff	360	__HAL_I2S_DISABLE(hi2s);
bogdanm	0:9b334a45a8ff	361
bogdanm	0:9b334a45a8ff	362	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	363	HAL_I2S_MspDeInit(hi2s);
bogdanm	0:9b334a45a8ff	364
bogdanm	0:9b334a45a8ff	365	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	366	hi2s->State = HAL_I2S_STATE_RESET;
bogdanm	0:9b334a45a8ff	367
bogdanm	0:9b334a45a8ff	368	/* Release Lock */
bogdanm	0:9b334a45a8ff	369	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	return HAL_OK;
bogdanm	0:9b334a45a8ff	372	}
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/**
bogdanm	0:9b334a45a8ff	375	* @brief I2S MSP Init
bogdanm	0:9b334a45a8ff	376	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	377	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	378	* @retval None
bogdanm	0:9b334a45a8ff	379	*/
bogdanm	0:9b334a45a8ff	380	__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	381	{
mbed_official	113:b3775bf36a83	382	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	383	UNUSED(hi2s);
mbed_official	113:b3775bf36a83	384
bogdanm	0:9b334a45a8ff	385	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	386	the HAL_I2S_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	387	*/
bogdanm	0:9b334a45a8ff	388	}
bogdanm	0:9b334a45a8ff	389
bogdanm	0:9b334a45a8ff	390	/**
bogdanm	0:9b334a45a8ff	391	* @brief I2S MSP DeInit
bogdanm	0:9b334a45a8ff	392	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	393	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	394	* @retval None
bogdanm	0:9b334a45a8ff	395	*/
bogdanm	0:9b334a45a8ff	396	__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	397	{
mbed_official	113:b3775bf36a83	398	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	399	UNUSED(hi2s);
mbed_official	113:b3775bf36a83	400
bogdanm	0:9b334a45a8ff	401	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	402	the HAL_I2S_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	403	*/
bogdanm	0:9b334a45a8ff	404	}
bogdanm	0:9b334a45a8ff	405
bogdanm	0:9b334a45a8ff	406	/**
bogdanm	0:9b334a45a8ff	407	* @}
bogdanm	0:9b334a45a8ff	408	*/
bogdanm	0:9b334a45a8ff	409
mbed_official	113:b3775bf36a83	410	/** @addtogroup I2S_Exported_Functions_Group2
bogdanm	0:9b334a45a8ff	411	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	412	*
bogdanm	0:9b334a45a8ff	413	@verbatim
bogdanm	0:9b334a45a8ff	414	===============================================================================
bogdanm	0:9b334a45a8ff	415	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	416	===============================================================================
bogdanm	0:9b334a45a8ff	417	[..]
bogdanm	0:9b334a45a8ff	418	This subsection provides a set of functions allowing to manage the I2S data
bogdanm	0:9b334a45a8ff	419	transfers.
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	(#) There are two modes of transfer:
bogdanm	0:9b334a45a8ff	422	(++) Blocking mode : The communication is performed in the polling mode.
bogdanm	0:9b334a45a8ff	423	The status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	424	after finishing transfer.
bogdanm	0:9b334a45a8ff	425	(++) No-Blocking mode : The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	426	or DMA. These functions return the status of the transfer startup.
bogdanm	0:9b334a45a8ff	427	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	428	dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	429	using DMA mode.
bogdanm	0:9b334a45a8ff	430
bogdanm	0:9b334a45a8ff	431	(#) Blocking mode functions are :
bogdanm	0:9b334a45a8ff	432	(++) HAL_I2S_Transmit()
bogdanm	0:9b334a45a8ff	433	(++) HAL_I2S_Receive()
bogdanm	0:9b334a45a8ff	434
bogdanm	0:9b334a45a8ff	435	(#) No-Blocking mode functions with Interrupt are :
bogdanm	0:9b334a45a8ff	436	(++) HAL_I2S_Transmit_IT()
bogdanm	0:9b334a45a8ff	437	(++) HAL_I2S_Receive_IT()
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	(#) No-Blocking mode functions with DMA are :
bogdanm	0:9b334a45a8ff	440	(++) HAL_I2S_Transmit_DMA()
bogdanm	0:9b334a45a8ff	441	(++) HAL_I2S_Receive_DMA()
bogdanm	0:9b334a45a8ff	442
bogdanm	0:9b334a45a8ff	443	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
bogdanm	0:9b334a45a8ff	444	(++) HAL_I2S_TxCpltCallback()
bogdanm	0:9b334a45a8ff	445	(++) HAL_I2S_RxCpltCallback()
bogdanm	0:9b334a45a8ff	446	(++) HAL_I2S_ErrorCallback()
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448	@endverbatim
bogdanm	0:9b334a45a8ff	449	* @{
bogdanm	0:9b334a45a8ff	450	*/
bogdanm	0:9b334a45a8ff	451
bogdanm	0:9b334a45a8ff	452	/**
bogdanm	0:9b334a45a8ff	453	* @brief Transmit an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	454	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	455	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	456	* @param pData: a 16-bit pointer to data buffer.
bogdanm	0:9b334a45a8ff	457	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	458	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	459	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	460	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	461	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	462	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	463	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	464	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	465	* @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
bogdanm	0:9b334a45a8ff	466	* @retval HAL status
bogdanm	0:9b334a45a8ff	467	*/
bogdanm	0:9b334a45a8ff	468	HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	469	{
bogdanm	0:9b334a45a8ff	470	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	471	{
bogdanm	0:9b334a45a8ff	472	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	473	}
bogdanm	0:9b334a45a8ff	474
bogdanm	0:9b334a45a8ff	475	/* Process Locked */
bogdanm	0:9b334a45a8ff	476	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	479	{
bogdanm	0:9b334a45a8ff	480	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	481	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	482	{
bogdanm	0:9b334a45a8ff	483	hi2s->TxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	484	hi2s->TxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	485	}
bogdanm	0:9b334a45a8ff	486	else
bogdanm	0:9b334a45a8ff	487	{
bogdanm	0:9b334a45a8ff	488	hi2s->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	489	hi2s->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	490	}
bogdanm	0:9b334a45a8ff	491
bogdanm	0:9b334a45a8ff	492	/* Set state and reset error code */
bogdanm	0:9b334a45a8ff	493	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	494	hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	495	hi2s->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	496
bogdanm	0:9b334a45a8ff	497	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	498	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	499	{
bogdanm	0:9b334a45a8ff	500	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	501	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	502	}
bogdanm	0:9b334a45a8ff	503
bogdanm	0:9b334a45a8ff	504	while(hi2s->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	505	{
bogdanm	0:9b334a45a8ff	506	/* Wait until TXE flag is set */
bogdanm	0:9b334a45a8ff	507	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	508	{
bogdanm	0:9b334a45a8ff	509	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	510	}
bogdanm	0:9b334a45a8ff	511	hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	512	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	513	}
bogdanm	0:9b334a45a8ff	514
bogdanm	0:9b334a45a8ff	515	/* Wait until TXE flag is set, to confirm the end of the transaction */
bogdanm	0:9b334a45a8ff	516	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	517	{
bogdanm	0:9b334a45a8ff	518	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	519	}
mbed_official	113:b3775bf36a83	520
mbed_official	113:b3775bf36a83	521	/* Check if Slave mode is selected */
mbed_official	113:b3775bf36a83	522	if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) \|\| ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
mbed_official	113:b3775bf36a83	523	{
mbed_official	113:b3775bf36a83	524	/* Wait until Busy flag is reset */
mbed_official	113:b3775bf36a83	525	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	113:b3775bf36a83	526	{
mbed_official	113:b3775bf36a83	527	return HAL_TIMEOUT;
mbed_official	113:b3775bf36a83	528	}
bogdanm	0:9b334a45a8ff	529	}
bogdanm	0:9b334a45a8ff	530	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	533	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	534
bogdanm	0:9b334a45a8ff	535	return HAL_OK;
bogdanm	0:9b334a45a8ff	536	}
bogdanm	0:9b334a45a8ff	537	else
bogdanm	0:9b334a45a8ff	538	{
bogdanm	0:9b334a45a8ff	539	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	540	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	541	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	542	}
bogdanm	0:9b334a45a8ff	543	}
bogdanm	0:9b334a45a8ff	544
bogdanm	0:9b334a45a8ff	545	/**
bogdanm	0:9b334a45a8ff	546	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	547	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	548	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	549	* @param pData: a 16-bit pointer to data buffer.
bogdanm	0:9b334a45a8ff	550	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	551	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	552	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	553	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	554	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	555	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	556	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	557	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	558	* @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
bogdanm	0:9b334a45a8ff	559	* in continouse way and as the I2S is not disabled at the end of the I2S transaction.
bogdanm	0:9b334a45a8ff	560	* @note This function can use an Audio Frequency up to 44KHz when I2S Clock Source is 32MHz
bogdanm	0:9b334a45a8ff	561	* @retval HAL status
bogdanm	0:9b334a45a8ff	562	*/
bogdanm	0:9b334a45a8ff	563	HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	564	{
bogdanm	0:9b334a45a8ff	565	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	566	{
bogdanm	0:9b334a45a8ff	567	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	568	}
bogdanm	0:9b334a45a8ff	569
bogdanm	0:9b334a45a8ff	570	/* Process Locked */
bogdanm	0:9b334a45a8ff	571	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	572
bogdanm	0:9b334a45a8ff	573	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	574	{
bogdanm	0:9b334a45a8ff	575	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	576	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	577	{
bogdanm	0:9b334a45a8ff	578	hi2s->RxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	579	hi2s->RxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	580	}
bogdanm	0:9b334a45a8ff	581	else
bogdanm	0:9b334a45a8ff	582	{
bogdanm	0:9b334a45a8ff	583	hi2s->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	584	hi2s->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	585	}
bogdanm	0:9b334a45a8ff	586
bogdanm	0:9b334a45a8ff	587	/* Set state and reset error code */
bogdanm	0:9b334a45a8ff	588	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	589	hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	590	hi2s->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	591
bogdanm	0:9b334a45a8ff	592	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	593	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	594	{
bogdanm	0:9b334a45a8ff	595	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	596	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	597	}
bogdanm	0:9b334a45a8ff	598
bogdanm	0:9b334a45a8ff	599	/* Check if Master Receiver mode is selected */
bogdanm	0:9b334a45a8ff	600	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm	0:9b334a45a8ff	601	{
bogdanm	0:9b334a45a8ff	602	/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
bogdanm	0:9b334a45a8ff	603	access to the SPI_SR register. */
bogdanm	0:9b334a45a8ff	604	__HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm	0:9b334a45a8ff	605	}
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	/* Receive data */
bogdanm	0:9b334a45a8ff	608	while(hi2s->RxXferCount > 0)
bogdanm	0:9b334a45a8ff	609	{
bogdanm	0:9b334a45a8ff	610	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	611	if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	612	{
bogdanm	0:9b334a45a8ff	613	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	614	}
bogdanm	0:9b334a45a8ff	615
bogdanm	0:9b334a45a8ff	616	(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
bogdanm	0:9b334a45a8ff	617	hi2s->RxXferCount--;
bogdanm	0:9b334a45a8ff	618	}
bogdanm	0:9b334a45a8ff	619
bogdanm	0:9b334a45a8ff	620	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	621
bogdanm	0:9b334a45a8ff	622	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	623	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625	return HAL_OK;
bogdanm	0:9b334a45a8ff	626	}
bogdanm	0:9b334a45a8ff	627	else
bogdanm	0:9b334a45a8ff	628	{
bogdanm	0:9b334a45a8ff	629	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	630	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	631	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	632	}
bogdanm	0:9b334a45a8ff	633	}
bogdanm	0:9b334a45a8ff	634
bogdanm	0:9b334a45a8ff	635	/**
bogdanm	0:9b334a45a8ff	636	* @brief Transmit an amount of data in non-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	637	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	638	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	639	* @param pData: a 16-bit pointer to data buffer.
bogdanm	0:9b334a45a8ff	640	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	641	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	642	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	643	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	644	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	645	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	646	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	647	* @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
bogdanm	0:9b334a45a8ff	648	* @retval HAL status
bogdanm	0:9b334a45a8ff	649	*/
bogdanm	0:9b334a45a8ff	650	HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	651	{
bogdanm	0:9b334a45a8ff	652	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	653	{
bogdanm	0:9b334a45a8ff	654	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	655	}
bogdanm	0:9b334a45a8ff	656
bogdanm	0:9b334a45a8ff	657	/* Process Locked */
bogdanm	0:9b334a45a8ff	658	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	659
bogdanm	0:9b334a45a8ff	660	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	661	{
bogdanm	0:9b334a45a8ff	662	hi2s->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	663	hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	664	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	665
bogdanm	0:9b334a45a8ff	666	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	667	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	668	{
bogdanm	0:9b334a45a8ff	669	hi2s->TxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	670	hi2s->TxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	671	}
bogdanm	0:9b334a45a8ff	672	else
bogdanm	0:9b334a45a8ff	673	{
bogdanm	0:9b334a45a8ff	674	hi2s->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	675	hi2s->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	676	}
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	679	__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	680
bogdanm	0:9b334a45a8ff	681	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	682	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	683	{
bogdanm	0:9b334a45a8ff	684	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	685	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	686	}
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	689	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	690
bogdanm	0:9b334a45a8ff	691	return HAL_OK;
bogdanm	0:9b334a45a8ff	692	}
bogdanm	0:9b334a45a8ff	693	else
bogdanm	0:9b334a45a8ff	694	{
bogdanm	0:9b334a45a8ff	695	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	696	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	697	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	698	}
bogdanm	0:9b334a45a8ff	699	}
bogdanm	0:9b334a45a8ff	700
bogdanm	0:9b334a45a8ff	701	/**
bogdanm	0:9b334a45a8ff	702	* @brief Receive an amount of data in non-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	703	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	704	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	705	* @param pData: a 16-bit pointer to the Receive data buffer.
bogdanm	0:9b334a45a8ff	706	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	707	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	708	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	709	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	710	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	711	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	712	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	713	* @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
bogdanm	0:9b334a45a8ff	714	* between Master and Slave otherwise the I2S interrupt should be optimized.
bogdanm	0:9b334a45a8ff	715	* @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz
bogdanm	0:9b334a45a8ff	716	* @retval HAL status
bogdanm	0:9b334a45a8ff	717	*/
bogdanm	0:9b334a45a8ff	718	HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	719	{
bogdanm	0:9b334a45a8ff	720	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	721	{
bogdanm	0:9b334a45a8ff	722	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	723	}
bogdanm	0:9b334a45a8ff	724
bogdanm	0:9b334a45a8ff	725	/* Process Locked */
bogdanm	0:9b334a45a8ff	726	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	727
bogdanm	0:9b334a45a8ff	728	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	729	{
bogdanm	0:9b334a45a8ff	730	hi2s->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	731	hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	732	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	733
bogdanm	0:9b334a45a8ff	734	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	735	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	736	{
bogdanm	0:9b334a45a8ff	737	hi2s->RxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	738	hi2s->RxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	739	}
bogdanm	0:9b334a45a8ff	740	else
bogdanm	0:9b334a45a8ff	741	{
bogdanm	0:9b334a45a8ff	742	hi2s->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	743	hi2s->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	744	}
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	/* Enable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	747	__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	748
bogdanm	0:9b334a45a8ff	749	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	750	if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
bogdanm	0:9b334a45a8ff	751	{
bogdanm	0:9b334a45a8ff	752	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	753	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	754	}
bogdanm	0:9b334a45a8ff	755
bogdanm	0:9b334a45a8ff	756	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	757	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	758
bogdanm	0:9b334a45a8ff	759	return HAL_OK;
bogdanm	0:9b334a45a8ff	760	}
bogdanm	0:9b334a45a8ff	761	else
bogdanm	0:9b334a45a8ff	762	{
bogdanm	0:9b334a45a8ff	763	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	764	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	765	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	766	}
bogdanm	0:9b334a45a8ff	767	}
bogdanm	0:9b334a45a8ff	768
bogdanm	0:9b334a45a8ff	769	/**
bogdanm	0:9b334a45a8ff	770	* @brief Transmit an amount of data in non-blocking mode with DMA
bogdanm	0:9b334a45a8ff	771	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	772	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	773	* @param pData: a 16-bit pointer to the Transmit data buffer.
bogdanm	0:9b334a45a8ff	774	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	775	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	776	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	777	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	778	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	779	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	780	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	781	* @retval HAL status
bogdanm	0:9b334a45a8ff	782	*/
bogdanm	0:9b334a45a8ff	783	HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	784	{
bogdanm	0:9b334a45a8ff	785	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	786	{
bogdanm	0:9b334a45a8ff	787	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	788	}
bogdanm	0:9b334a45a8ff	789
bogdanm	0:9b334a45a8ff	790	/* Process Locked */
bogdanm	0:9b334a45a8ff	791	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	792
bogdanm	0:9b334a45a8ff	793	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	794	{
bogdanm	0:9b334a45a8ff	795	hi2s->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	796	hi2s->State = HAL_I2S_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	797	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	798
bogdanm	0:9b334a45a8ff	799	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	800	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	801	{
bogdanm	0:9b334a45a8ff	802	hi2s->TxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	803	hi2s->TxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	804	}
bogdanm	0:9b334a45a8ff	805	else
bogdanm	0:9b334a45a8ff	806	{
bogdanm	0:9b334a45a8ff	807	hi2s->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	808	hi2s->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	809	}
bogdanm	0:9b334a45a8ff	810
bogdanm	0:9b334a45a8ff	811	/* Set the I2S Tx DMA Half transfert complete callback */
bogdanm	0:9b334a45a8ff	812	hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
bogdanm	0:9b334a45a8ff	813
bogdanm	0:9b334a45a8ff	814	/* Set the I2S Tx DMA transfert complete callback */
bogdanm	0:9b334a45a8ff	815	hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	818	hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
bogdanm	0:9b334a45a8ff	819
bogdanm	0:9b334a45a8ff	820	/* Enable the Tx DMA Channel */
bogdanm	0:9b334a45a8ff	821	HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	824	if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
bogdanm	0:9b334a45a8ff	825	{
bogdanm	0:9b334a45a8ff	826	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	827	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	828	}
bogdanm	0:9b334a45a8ff	829
bogdanm	0:9b334a45a8ff	830	/* Check if the I2S Tx request is already enabled */
bogdanm	0:9b334a45a8ff	831	if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
bogdanm	0:9b334a45a8ff	832	{
bogdanm	0:9b334a45a8ff	833	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	834	SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	835	}
bogdanm	0:9b334a45a8ff	836
bogdanm	0:9b334a45a8ff	837	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	838	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	839
bogdanm	0:9b334a45a8ff	840	return HAL_OK;
bogdanm	0:9b334a45a8ff	841	}
bogdanm	0:9b334a45a8ff	842	else
bogdanm	0:9b334a45a8ff	843	{
bogdanm	0:9b334a45a8ff	844	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	845	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	846	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	847	}
bogdanm	0:9b334a45a8ff	848	}
bogdanm	0:9b334a45a8ff	849
bogdanm	0:9b334a45a8ff	850	/**
bogdanm	0:9b334a45a8ff	851	* @brief Receive an amount of data in non-blocking mode with DMA
bogdanm	0:9b334a45a8ff	852	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	853	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	854	* @param pData: a 16-bit pointer to the Receive data buffer.
bogdanm	0:9b334a45a8ff	855	* @param Size: number of data sample to be sent:
bogdanm	0:9b334a45a8ff	856	* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
bogdanm	0:9b334a45a8ff	857	* configuration phase, the Size parameter means the number of 16-bit data length
bogdanm	0:9b334a45a8ff	858	* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
bogdanm	0:9b334a45a8ff	859	* the Size parameter means the number of 16-bit data length.
bogdanm	0:9b334a45a8ff	860	* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
bogdanm	0:9b334a45a8ff	861	* between Master and Slave(example: audio streaming).
bogdanm	0:9b334a45a8ff	862	* @retval HAL status
bogdanm	0:9b334a45a8ff	863	*/
bogdanm	0:9b334a45a8ff	864	HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef hi2s, uint16_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	865	{
bogdanm	0:9b334a45a8ff	866	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	867	{
bogdanm	0:9b334a45a8ff	868	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	869	}
bogdanm	0:9b334a45a8ff	870
bogdanm	0:9b334a45a8ff	871	/* Process Locked */
bogdanm	0:9b334a45a8ff	872	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	873
bogdanm	0:9b334a45a8ff	874	if(hi2s->State == HAL_I2S_STATE_READY)
bogdanm	0:9b334a45a8ff	875	{
bogdanm	0:9b334a45a8ff	876	hi2s->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	877	hi2s->State = HAL_I2S_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	878	hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
bogdanm	0:9b334a45a8ff	879
bogdanm	0:9b334a45a8ff	880	if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)\|\|\
bogdanm	0:9b334a45a8ff	881	((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
bogdanm	0:9b334a45a8ff	882	{
bogdanm	0:9b334a45a8ff	883	hi2s->RxXferSize = (Size << 1);
bogdanm	0:9b334a45a8ff	884	hi2s->RxXferCount = (Size << 1);
bogdanm	0:9b334a45a8ff	885	}
bogdanm	0:9b334a45a8ff	886	else
bogdanm	0:9b334a45a8ff	887	{
bogdanm	0:9b334a45a8ff	888	hi2s->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	889	hi2s->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	890	}
bogdanm	0:9b334a45a8ff	891
bogdanm	0:9b334a45a8ff	892
bogdanm	0:9b334a45a8ff	893	/* Set the I2S Rx DMA Half transfert complete callback */
bogdanm	0:9b334a45a8ff	894	hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
bogdanm	0:9b334a45a8ff	895
bogdanm	0:9b334a45a8ff	896	/* Set the I2S Rx DMA transfert complete callback */
bogdanm	0:9b334a45a8ff	897	hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
bogdanm	0:9b334a45a8ff	898
bogdanm	0:9b334a45a8ff	899	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	900	hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
bogdanm	0:9b334a45a8ff	901
bogdanm	0:9b334a45a8ff	902	/* Check if Master Receiver mode is selected */
bogdanm	0:9b334a45a8ff	903	if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
bogdanm	0:9b334a45a8ff	904	{
bogdanm	0:9b334a45a8ff	905	/* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
bogdanm	0:9b334a45a8ff	906	access to the SPI_SR register. */
bogdanm	0:9b334a45a8ff	907	__HAL_I2S_CLEAR_OVRFLAG(hi2s);
bogdanm	0:9b334a45a8ff	908	}
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	/* Enable the Rx DMA Channel */
bogdanm	0:9b334a45a8ff	911	HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
bogdanm	0:9b334a45a8ff	912
bogdanm	0:9b334a45a8ff	913	/* Check if the I2S is already enabled */
bogdanm	0:9b334a45a8ff	914	if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
bogdanm	0:9b334a45a8ff	915	{
bogdanm	0:9b334a45a8ff	916	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	917	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	918	}
bogdanm	0:9b334a45a8ff	919
bogdanm	0:9b334a45a8ff	920	/* Check if the I2S Rx request is already enabled */
bogdanm	0:9b334a45a8ff	921	if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
bogdanm	0:9b334a45a8ff	922	{
bogdanm	0:9b334a45a8ff	923	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	924	SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	925	}
bogdanm	0:9b334a45a8ff	926
bogdanm	0:9b334a45a8ff	927	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	928	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	929
bogdanm	0:9b334a45a8ff	930	return HAL_OK;
bogdanm	0:9b334a45a8ff	931	}
bogdanm	0:9b334a45a8ff	932	else
bogdanm	0:9b334a45a8ff	933	{
bogdanm	0:9b334a45a8ff	934	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	935	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	936	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	937	}
bogdanm	0:9b334a45a8ff	938	}
bogdanm	0:9b334a45a8ff	939
bogdanm	0:9b334a45a8ff	940	/**
bogdanm	0:9b334a45a8ff	941	* @brief Pauses the audio stream playing from the Media.
bogdanm	0:9b334a45a8ff	942	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	943	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	944	* @retval HAL status
bogdanm	0:9b334a45a8ff	945	*/
bogdanm	0:9b334a45a8ff	946	HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	947	{
bogdanm	0:9b334a45a8ff	948	/* Process Locked */
bogdanm	0:9b334a45a8ff	949	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	950
bogdanm	0:9b334a45a8ff	951	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	952	{
bogdanm	0:9b334a45a8ff	953	/* Disable the I2S DMA Tx request */
bogdanm	0:9b334a45a8ff	954	CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	955	}
bogdanm	0:9b334a45a8ff	956	else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	957	{
bogdanm	0:9b334a45a8ff	958	/* Disable the I2S DMA Rx request */
bogdanm	0:9b334a45a8ff	959	CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	960	}
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	963	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	964
bogdanm	0:9b334a45a8ff	965	return HAL_OK;
bogdanm	0:9b334a45a8ff	966	}
bogdanm	0:9b334a45a8ff	967
bogdanm	0:9b334a45a8ff	968	/**
bogdanm	0:9b334a45a8ff	969	* @brief Resumes the audio stream playing from the Media.
bogdanm	0:9b334a45a8ff	970	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	971	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	972	* @retval HAL status
bogdanm	0:9b334a45a8ff	973	*/
bogdanm	0:9b334a45a8ff	974	HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	975	{
bogdanm	0:9b334a45a8ff	976	/* Process Locked */
bogdanm	0:9b334a45a8ff	977	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	978
bogdanm	0:9b334a45a8ff	979	if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	980	{
bogdanm	0:9b334a45a8ff	981	/* Enable the I2S DMA Tx request */
bogdanm	0:9b334a45a8ff	982	SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	983	}
bogdanm	0:9b334a45a8ff	984	else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	985	{
bogdanm	0:9b334a45a8ff	986	/* Enable the I2S DMA Rx request */
bogdanm	0:9b334a45a8ff	987	SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	988	}
bogdanm	0:9b334a45a8ff	989
bogdanm	0:9b334a45a8ff	990	/* If the I2S peripheral is still not enabled, enable it */
bogdanm	0:9b334a45a8ff	991	if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
bogdanm	0:9b334a45a8ff	992	{
bogdanm	0:9b334a45a8ff	993	/* Enable I2S peripheral */
bogdanm	0:9b334a45a8ff	994	__HAL_I2S_ENABLE(hi2s);
bogdanm	0:9b334a45a8ff	995	}
bogdanm	0:9b334a45a8ff	996
bogdanm	0:9b334a45a8ff	997	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	998	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	999
bogdanm	0:9b334a45a8ff	1000	return HAL_OK;
bogdanm	0:9b334a45a8ff	1001	}
bogdanm	0:9b334a45a8ff	1002
bogdanm	0:9b334a45a8ff	1003	/**
bogdanm	0:9b334a45a8ff	1004	* @brief Stops the audio stream playing from the Media.
bogdanm	0:9b334a45a8ff	1005	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1006	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1007	* @retval HAL status
bogdanm	0:9b334a45a8ff	1008	*/
bogdanm	0:9b334a45a8ff	1009	HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1010	{
bogdanm	0:9b334a45a8ff	1011	/* Process Locked */
bogdanm	0:9b334a45a8ff	1012	__HAL_LOCK(hi2s);
bogdanm	0:9b334a45a8ff	1013
bogdanm	0:9b334a45a8ff	1014	/* Disable the I2S Tx/Rx DMA requests */
bogdanm	0:9b334a45a8ff	1015	CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1016	CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	/* Abort the I2S DMA Channel tx */
bogdanm	0:9b334a45a8ff	1019	if(hi2s->hdmatx != NULL)
bogdanm	0:9b334a45a8ff	1020	{
bogdanm	0:9b334a45a8ff	1021	/* Disable the I2S DMA channel */
bogdanm	0:9b334a45a8ff	1022	__HAL_DMA_DISABLE(hi2s->hdmatx);
bogdanm	0:9b334a45a8ff	1023	HAL_DMA_Abort(hi2s->hdmatx);
bogdanm	0:9b334a45a8ff	1024	}
bogdanm	0:9b334a45a8ff	1025	/* Abort the I2S DMA Channel rx */
bogdanm	0:9b334a45a8ff	1026	if(hi2s->hdmarx != NULL)
bogdanm	0:9b334a45a8ff	1027	{
bogdanm	0:9b334a45a8ff	1028	/* Disable the I2S DMA channel */
bogdanm	0:9b334a45a8ff	1029	__HAL_DMA_DISABLE(hi2s->hdmarx);
bogdanm	0:9b334a45a8ff	1030	HAL_DMA_Abort(hi2s->hdmarx);
bogdanm	0:9b334a45a8ff	1031	}
bogdanm	0:9b334a45a8ff	1032
bogdanm	0:9b334a45a8ff	1033	/* Disable I2S peripheral */
bogdanm	0:9b334a45a8ff	1034	__HAL_I2S_DISABLE(hi2s);
bogdanm	0:9b334a45a8ff	1035
bogdanm	0:9b334a45a8ff	1036	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1037
bogdanm	0:9b334a45a8ff	1038	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1039	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1040
bogdanm	0:9b334a45a8ff	1041	return HAL_OK;
bogdanm	0:9b334a45a8ff	1042	}
bogdanm	0:9b334a45a8ff	1043
bogdanm	0:9b334a45a8ff	1044	/**
bogdanm	0:9b334a45a8ff	1045	* @brief This function handles I2S interrupt request.
bogdanm	0:9b334a45a8ff	1046	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1047	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1048	* @retval None
bogdanm	0:9b334a45a8ff	1049	*/
bogdanm	0:9b334a45a8ff	1050	void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1051	{
bogdanm	0:9b334a45a8ff	1052	uint32_t i2ssr = hi2s->Instance->SR;
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	/* I2S in mode Receiver ------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1055	if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
bogdanm	0:9b334a45a8ff	1056	((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
bogdanm	0:9b334a45a8ff	1057	{
bogdanm	0:9b334a45a8ff	1058	I2S_Receive_IT(hi2s);
bogdanm	0:9b334a45a8ff	1059	return;
bogdanm	0:9b334a45a8ff	1060	}
bogdanm	0:9b334a45a8ff	1061
bogdanm	0:9b334a45a8ff	1062	/* I2S in mode Tramitter -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	1063	if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
bogdanm	0:9b334a45a8ff	1064	{
bogdanm	0:9b334a45a8ff	1065	I2S_Transmit_IT(hi2s);
bogdanm	0:9b334a45a8ff	1066	return;
bogdanm	0:9b334a45a8ff	1067	}
bogdanm	0:9b334a45a8ff	1068
bogdanm	0:9b334a45a8ff	1069	/* I2S interrupt error -------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1070	if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)
bogdanm	0:9b334a45a8ff	1071	{
bogdanm	0:9b334a45a8ff	1072	/* I2S Overrun error interrupt occured ---------------------------------*/
bogdanm	0:9b334a45a8ff	1073	if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR)
bogdanm	0:9b334a45a8ff	1074	{
bogdanm	0:9b334a45a8ff	1075	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1076	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1077
bogdanm	0:9b334a45a8ff	1078	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	1079	SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
bogdanm	0:9b334a45a8ff	1080	}
bogdanm	0:9b334a45a8ff	1081
bogdanm	0:9b334a45a8ff	1082	/* I2S Underrun error interrupt occured --------------------------------*/
bogdanm	0:9b334a45a8ff	1083	if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR)
bogdanm	0:9b334a45a8ff	1084	{
bogdanm	0:9b334a45a8ff	1085	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1086	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	1089	SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
bogdanm	0:9b334a45a8ff	1090	}
bogdanm	0:9b334a45a8ff	1091
bogdanm	0:9b334a45a8ff	1092	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	1093	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1094	/* Call the Error Callback */
bogdanm	0:9b334a45a8ff	1095	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	1096	}
bogdanm	0:9b334a45a8ff	1097	}
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	/**
bogdanm	0:9b334a45a8ff	1100	* @brief Tx Transfer Half completed callbacks
bogdanm	0:9b334a45a8ff	1101	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1102	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1103	* @retval None
bogdanm	0:9b334a45a8ff	1104	*/
bogdanm	0:9b334a45a8ff	1105	__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1106	{
mbed_official	113:b3775bf36a83	1107	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1108	UNUSED(hi2s);
mbed_official	113:b3775bf36a83	1109
bogdanm	0:9b334a45a8ff	1110	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1111	the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1112	*/
bogdanm	0:9b334a45a8ff	1113	}
bogdanm	0:9b334a45a8ff	1114
bogdanm	0:9b334a45a8ff	1115	/**
bogdanm	0:9b334a45a8ff	1116	* @brief Tx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1117	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1118	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1119	* @retval None
bogdanm	0:9b334a45a8ff	1120	*/
bogdanm	0:9b334a45a8ff	1121	__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1122	{
mbed_official	113:b3775bf36a83	1123	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1124	UNUSED(hi2s);
mbed_official	113:b3775bf36a83	1125
bogdanm	0:9b334a45a8ff	1126	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1127	the HAL_I2S_TxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1128	*/
bogdanm	0:9b334a45a8ff	1129	}
bogdanm	0:9b334a45a8ff	1130
bogdanm	0:9b334a45a8ff	1131	/**
bogdanm	0:9b334a45a8ff	1132	* @brief Rx Transfer half completed callbacks
bogdanm	0:9b334a45a8ff	1133	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1134	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1135	* @retval None
bogdanm	0:9b334a45a8ff	1136	*/
bogdanm	0:9b334a45a8ff	1137	__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1138	{
mbed_official	113:b3775bf36a83	1139	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1140	UNUSED(hi2s);
mbed_official	113:b3775bf36a83	1141
bogdanm	0:9b334a45a8ff	1142	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1143	the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1144	*/
bogdanm	0:9b334a45a8ff	1145	}
bogdanm	0:9b334a45a8ff	1146
bogdanm	0:9b334a45a8ff	1147	/**
bogdanm	0:9b334a45a8ff	1148	* @brief Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1149	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1150	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1151	* @retval None
bogdanm	0:9b334a45a8ff	1152	*/
bogdanm	0:9b334a45a8ff	1153	__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1154	{
mbed_official	113:b3775bf36a83	1155	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1156	UNUSED(hi2s);
mbed_official	113:b3775bf36a83	1157
bogdanm	0:9b334a45a8ff	1158	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1159	the HAL_I2S_RxCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1160	*/
bogdanm	0:9b334a45a8ff	1161	}
bogdanm	0:9b334a45a8ff	1162
bogdanm	0:9b334a45a8ff	1163	/**
bogdanm	0:9b334a45a8ff	1164	* @brief I2S error callbacks
bogdanm	0:9b334a45a8ff	1165	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1166	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1167	* @retval None
bogdanm	0:9b334a45a8ff	1168	*/
bogdanm	0:9b334a45a8ff	1169	__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1170	{
mbed_official	113:b3775bf36a83	1171	/* Prevent unused argument(s) compilation warning */
mbed_official	113:b3775bf36a83	1172	UNUSED(hi2s);
mbed_official	113:b3775bf36a83	1173
bogdanm	0:9b334a45a8ff	1174	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1175	the HAL_I2S_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1176	*/
bogdanm	0:9b334a45a8ff	1177	}
bogdanm	0:9b334a45a8ff	1178
bogdanm	0:9b334a45a8ff	1179	/**
bogdanm	0:9b334a45a8ff	1180	* @}
bogdanm	0:9b334a45a8ff	1181	*/
bogdanm	0:9b334a45a8ff	1182
mbed_official	113:b3775bf36a83	1183	/** @addtogroup I2S_Exported_Functions_Group3
bogdanm	0:9b334a45a8ff	1184	* @brief Peripheral State functions
bogdanm	0:9b334a45a8ff	1185	*
bogdanm	0:9b334a45a8ff	1186	@verbatim
bogdanm	0:9b334a45a8ff	1187	===============================================================================
bogdanm	0:9b334a45a8ff	1188	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1189	===============================================================================
bogdanm	0:9b334a45a8ff	1190	[..]
bogdanm	0:9b334a45a8ff	1191	This subsection permits to get in run-time the status of the peripheral
bogdanm	0:9b334a45a8ff	1192	and the data flow.
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	@endverbatim
bogdanm	0:9b334a45a8ff	1195	* @{
bogdanm	0:9b334a45a8ff	1196	*/
bogdanm	0:9b334a45a8ff	1197
bogdanm	0:9b334a45a8ff	1198	/**
bogdanm	0:9b334a45a8ff	1199	* @brief Return the I2S state
bogdanm	0:9b334a45a8ff	1200	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1201	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1202	* @retval HAL state
bogdanm	0:9b334a45a8ff	1203	*/
bogdanm	0:9b334a45a8ff	1204	HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1205	{
bogdanm	0:9b334a45a8ff	1206	return hi2s->State;
bogdanm	0:9b334a45a8ff	1207	}
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209	/**
bogdanm	0:9b334a45a8ff	1210	* @brief Return the I2S error code
bogdanm	0:9b334a45a8ff	1211	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1212	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1213	* @retval I2S Error Code
bogdanm	0:9b334a45a8ff	1214	*/
bogdanm	0:9b334a45a8ff	1215	uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1216	{
bogdanm	0:9b334a45a8ff	1217	return hi2s->ErrorCode;
bogdanm	0:9b334a45a8ff	1218	}
bogdanm	0:9b334a45a8ff	1219	/**
bogdanm	0:9b334a45a8ff	1220	* @}
bogdanm	0:9b334a45a8ff	1221	*/
bogdanm	0:9b334a45a8ff	1222
bogdanm	0:9b334a45a8ff	1223	/**
bogdanm	0:9b334a45a8ff	1224	* @}
bogdanm	0:9b334a45a8ff	1225	*/
bogdanm	0:9b334a45a8ff	1226
bogdanm	0:9b334a45a8ff	1227	/* Private functions ---------------------------------------------------------*/
mbed_official	113:b3775bf36a83	1228	/** @addtogroup I2S_Private
bogdanm	0:9b334a45a8ff	1229	* @{
bogdanm	0:9b334a45a8ff	1230	*/
bogdanm	0:9b334a45a8ff	1231	/**
bogdanm	0:9b334a45a8ff	1232	* @brief DMA I2S transmit process complete callback
bogdanm	0:9b334a45a8ff	1233	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1234	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1235	* @retval None
bogdanm	0:9b334a45a8ff	1236	*/
bogdanm	0:9b334a45a8ff	1237	static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1238	{
bogdanm	0:9b334a45a8ff	1239	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1240
bogdanm	0:9b334a45a8ff	1241	if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
bogdanm	0:9b334a45a8ff	1242	{
bogdanm	0:9b334a45a8ff	1243	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1244	CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	hi2s->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1247	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1248	}
bogdanm	0:9b334a45a8ff	1249	HAL_I2S_TxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1250	}
bogdanm	0:9b334a45a8ff	1251
bogdanm	0:9b334a45a8ff	1252	/**
bogdanm	0:9b334a45a8ff	1253	* @brief DMA I2S transmit process half complete callback
bogdanm	0:9b334a45a8ff	1254	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1255	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1256	* @retval None
bogdanm	0:9b334a45a8ff	1257	*/
bogdanm	0:9b334a45a8ff	1258	static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1259	{
bogdanm	0:9b334a45a8ff	1260	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1261
bogdanm	0:9b334a45a8ff	1262	HAL_I2S_TxHalfCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1263	}
bogdanm	0:9b334a45a8ff	1264
bogdanm	0:9b334a45a8ff	1265	/**
bogdanm	0:9b334a45a8ff	1266	* @brief DMA I2S receive process complete callback
bogdanm	0:9b334a45a8ff	1267	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1268	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1269	* @retval None
bogdanm	0:9b334a45a8ff	1270	*/
bogdanm	0:9b334a45a8ff	1271	static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1272	{
bogdanm	0:9b334a45a8ff	1273	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1274
bogdanm	0:9b334a45a8ff	1275	if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
bogdanm	0:9b334a45a8ff	1276	{
bogdanm	0:9b334a45a8ff	1277	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1278	CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1279	hi2s->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1280	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1281	}
bogdanm	0:9b334a45a8ff	1282	HAL_I2S_RxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1283	}
bogdanm	0:9b334a45a8ff	1284
bogdanm	0:9b334a45a8ff	1285	/**
bogdanm	0:9b334a45a8ff	1286	* @brief DMA I2S receive process half complete callback
bogdanm	0:9b334a45a8ff	1287	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1288	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1289	* @retval None
bogdanm	0:9b334a45a8ff	1290	*/
bogdanm	0:9b334a45a8ff	1291	static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1292	{
bogdanm	0:9b334a45a8ff	1293	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	HAL_I2S_RxHalfCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1296	}
bogdanm	0:9b334a45a8ff	1297
bogdanm	0:9b334a45a8ff	1298	/**
bogdanm	0:9b334a45a8ff	1299	* @brief DMA I2S communication error callback
bogdanm	0:9b334a45a8ff	1300	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1301	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1302	* @retval None
bogdanm	0:9b334a45a8ff	1303	*/
bogdanm	0:9b334a45a8ff	1304	static void I2S_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1305	{
bogdanm	0:9b334a45a8ff	1306	I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
bogdanm	0:9b334a45a8ff	1307
bogdanm	0:9b334a45a8ff	1308	/* Disable Rx and Tx DMA Request */
bogdanm	0:9b334a45a8ff	1309	CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN \| SPI_CR2_TXDMAEN));
bogdanm	0:9b334a45a8ff	1310	hi2s->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1311	hi2s->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1312
bogdanm	0:9b334a45a8ff	1313	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	/* Set the error code and execute error callback*/
bogdanm	0:9b334a45a8ff	1316	SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
bogdanm	0:9b334a45a8ff	1317	HAL_I2S_ErrorCallback(hi2s);
bogdanm	0:9b334a45a8ff	1318	}
bogdanm	0:9b334a45a8ff	1319
bogdanm	0:9b334a45a8ff	1320	/**
bogdanm	0:9b334a45a8ff	1321	* @brief Transmit an amount of data in non-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1322	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1323	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1324	* @retval None
bogdanm	0:9b334a45a8ff	1325	*/
bogdanm	0:9b334a45a8ff	1326	static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1327	{
bogdanm	0:9b334a45a8ff	1328	/* Transmit data */
bogdanm	0:9b334a45a8ff	1329	hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	1330	hi2s->TxXferCount--;
bogdanm	0:9b334a45a8ff	1331
bogdanm	0:9b334a45a8ff	1332	if(hi2s->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	1333	{
bogdanm	0:9b334a45a8ff	1334	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1335	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1336
bogdanm	0:9b334a45a8ff	1337	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1338	HAL_I2S_TxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1339	}
bogdanm	0:9b334a45a8ff	1340	}
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	/**
bogdanm	0:9b334a45a8ff	1343	* @brief Receive an amount of data in non-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1344	* @param hi2s: I2S handle
bogdanm	0:9b334a45a8ff	1345	* @retval None
bogdanm	0:9b334a45a8ff	1346	*/
bogdanm	0:9b334a45a8ff	1347	static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
bogdanm	0:9b334a45a8ff	1348	{
bogdanm	0:9b334a45a8ff	1349	/* Receive data */
bogdanm	0:9b334a45a8ff	1350	(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
bogdanm	0:9b334a45a8ff	1351	hi2s->RxXferCount--;
bogdanm	0:9b334a45a8ff	1352
bogdanm	0:9b334a45a8ff	1353	if(hi2s->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	1354	{
bogdanm	0:9b334a45a8ff	1355	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1356	__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE \| I2S_IT_ERR));
bogdanm	0:9b334a45a8ff	1357
bogdanm	0:9b334a45a8ff	1358	hi2s->State = HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1359	HAL_I2S_RxCpltCallback(hi2s);
bogdanm	0:9b334a45a8ff	1360	}
bogdanm	0:9b334a45a8ff	1361	}
bogdanm	0:9b334a45a8ff	1362
bogdanm	0:9b334a45a8ff	1363
bogdanm	0:9b334a45a8ff	1364	/**
bogdanm	0:9b334a45a8ff	1365	* @brief This function handles I2S Communication Timeout.
bogdanm	0:9b334a45a8ff	1366	* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1367	* the configuration information for I2S module
bogdanm	0:9b334a45a8ff	1368	* @param Flag: Flag checked
bogdanm	0:9b334a45a8ff	1369	* @param Status: Value of the flag expected
bogdanm	0:9b334a45a8ff	1370	* @param Timeout: Duration of the timeout
bogdanm	0:9b334a45a8ff	1371	* @retval HAL status
bogdanm	0:9b334a45a8ff	1372	*/
bogdanm	0:9b334a45a8ff	1373	static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	1374	{
bogdanm	0:9b334a45a8ff	1375	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	1376
bogdanm	0:9b334a45a8ff	1377	/* Get tick */
bogdanm	0:9b334a45a8ff	1378	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	1379
bogdanm	0:9b334a45a8ff	1380	/* Wait until flag is set */
bogdanm	0:9b334a45a8ff	1381	if(Status == RESET)
bogdanm	0:9b334a45a8ff	1382	{
bogdanm	0:9b334a45a8ff	1383	while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
bogdanm	0:9b334a45a8ff	1384	{
bogdanm	0:9b334a45a8ff	1385	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1386	{
bogdanm	0:9b334a45a8ff	1387	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	1388	{
bogdanm	0:9b334a45a8ff	1389	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	1390	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1391
bogdanm	0:9b334a45a8ff	1392	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1393	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1394
bogdanm	0:9b334a45a8ff	1395	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1396	}
bogdanm	0:9b334a45a8ff	1397	}
bogdanm	0:9b334a45a8ff	1398	}
bogdanm	0:9b334a45a8ff	1399	}
bogdanm	0:9b334a45a8ff	1400	else
bogdanm	0:9b334a45a8ff	1401	{
bogdanm	0:9b334a45a8ff	1402	while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
bogdanm	0:9b334a45a8ff	1403	{
bogdanm	0:9b334a45a8ff	1404	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	1405	{
bogdanm	0:9b334a45a8ff	1406	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	1407	{
bogdanm	0:9b334a45a8ff	1408	/* Set the I2S State ready */
bogdanm	0:9b334a45a8ff	1409	hi2s->State= HAL_I2S_STATE_READY;
bogdanm	0:9b334a45a8ff	1410
bogdanm	0:9b334a45a8ff	1411	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1412	__HAL_UNLOCK(hi2s);
bogdanm	0:9b334a45a8ff	1413
bogdanm	0:9b334a45a8ff	1414	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	1415	}
bogdanm	0:9b334a45a8ff	1416	}
bogdanm	0:9b334a45a8ff	1417	}
bogdanm	0:9b334a45a8ff	1418	}
bogdanm	0:9b334a45a8ff	1419	return HAL_OK;
bogdanm	0:9b334a45a8ff	1420	}
bogdanm	0:9b334a45a8ff	1421
bogdanm	0:9b334a45a8ff	1422	/**
bogdanm	0:9b334a45a8ff	1423	* @}
bogdanm	0:9b334a45a8ff	1424	*/
bogdanm	0:9b334a45a8ff	1425
bogdanm	0:9b334a45a8ff	1426	/**
bogdanm	0:9b334a45a8ff	1427	* @}
bogdanm	0:9b334a45a8ff	1428	*/
mbed_official	113:b3775bf36a83	1429	#endif /* HAL_I2S_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1430
bogdanm	0:9b334a45a8ff	1431	/**
bogdanm	0:9b334a45a8ff	1432	* @}
bogdanm	0:9b334a45a8ff	1433	*/
bogdanm	0:9b334a45a8ff	1434
mbed_official	113:b3775bf36a83	1435	#endif /* #if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) */
bogdanm	0:9b334a45a8ff	1436
bogdanm	0:9b334a45a8ff	1437	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	1438

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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