en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
83:a036322b8637 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f7xx_hal_dma.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 83:a036322b8637 5 * @version V1.0.4
mbed_official 83:a036322b8637 6 * @date 09-December-2015
bogdanm 0:9b334a45a8ff 7 * @brief Header file of DMA HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32F7xx_HAL_DMA_H
bogdanm 0:9b334a45a8ff 40 #define __STM32F7xx_HAL_DMA_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32f7xx_hal_def.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32F7xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @addtogroup DMA
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Exported types ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /** @defgroup DMA_Exported_Types DMA Exported Types
bogdanm 0:9b334a45a8ff 60 * @brief DMA Exported Types
bogdanm 0:9b334a45a8ff 61 * @{
bogdanm 0:9b334a45a8ff 62 */
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 /**
bogdanm 0:9b334a45a8ff 65 * @brief DMA Configuration Structure definition
bogdanm 0:9b334a45a8ff 66 */
bogdanm 0:9b334a45a8ff 67 typedef struct
bogdanm 0:9b334a45a8ff 68 {
bogdanm 0:9b334a45a8ff 69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
bogdanm 0:9b334a45a8ff 70 This parameter can be a value of @ref DMA_Channel_selection */
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 0:9b334a45a8ff 73 from memory to memory or from peripheral to memory.
bogdanm 0:9b334a45a8ff 74 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 0:9b334a45a8ff 77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 0:9b334a45a8ff 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 0:9b334a45a8ff 81
bogdanm 0:9b334a45a8ff 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 0:9b334a45a8ff 83 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 0:9b334a45a8ff 86 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
bogdanm 0:9b334a45a8ff 89 This parameter can be a value of @ref DMA_mode
bogdanm 0:9b334a45a8ff 90 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 0:9b334a45a8ff 91 data transfer is configured on the selected Stream */
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
bogdanm 0:9b334a45a8ff 94 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
bogdanm 0:9b334a45a8ff 97 This parameter can be a value of @ref DMA_FIFO_direct_mode
bogdanm 0:9b334a45a8ff 98 @note The Direct mode (FIFO mode disabled) cannot be used if the
bogdanm 0:9b334a45a8ff 99 memory-to-memory data transfer is configured on the selected stream */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
bogdanm 0:9b334a45a8ff 102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
bogdanm 0:9b334a45a8ff 105 It specifies the amount of data to be transferred in a single non interruptible
bogdanm 0:9b334a45a8ff 106 transaction.
bogdanm 0:9b334a45a8ff 107 This parameter can be a value of @ref DMA_Memory_burst
bogdanm 0:9b334a45a8ff 108 @note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
bogdanm 0:9b334a45a8ff 111 It specifies the amount of data to be transferred in a single non interruptible
bogdanm 0:9b334a45a8ff 112 transaction.
bogdanm 0:9b334a45a8ff 113 This parameter can be a value of @ref DMA_Peripheral_burst
bogdanm 0:9b334a45a8ff 114 @note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm 0:9b334a45a8ff 115 }DMA_InitTypeDef;
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /**
bogdanm 0:9b334a45a8ff 118 * @brief HAL DMA State structures definition
bogdanm 0:9b334a45a8ff 119 */
bogdanm 0:9b334a45a8ff 120 typedef enum
bogdanm 0:9b334a45a8ff 121 {
bogdanm 0:9b334a45a8ff 122 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
bogdanm 0:9b334a45a8ff 123 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
bogdanm 0:9b334a45a8ff 124 HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
bogdanm 0:9b334a45a8ff 125 HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
bogdanm 0:9b334a45a8ff 126 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
bogdanm 0:9b334a45a8ff 127 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
bogdanm 0:9b334a45a8ff 128 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
bogdanm 0:9b334a45a8ff 129 HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
bogdanm 0:9b334a45a8ff 130 HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
bogdanm 0:9b334a45a8ff 131 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 0:9b334a45a8ff 132 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 0:9b334a45a8ff 133 }HAL_DMA_StateTypeDef;
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /**
bogdanm 0:9b334a45a8ff 136 * @brief HAL DMA Error Code structure definition
bogdanm 0:9b334a45a8ff 137 */
bogdanm 0:9b334a45a8ff 138 typedef enum
bogdanm 0:9b334a45a8ff 139 {
bogdanm 0:9b334a45a8ff 140 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 0:9b334a45a8ff 141 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
bogdanm 0:9b334a45a8ff 142 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 /**
bogdanm 0:9b334a45a8ff 145 * @brief DMA handle Structure definition
bogdanm 0:9b334a45a8ff 146 */
bogdanm 0:9b334a45a8ff 147 typedef struct __DMA_HandleTypeDef
bogdanm 0:9b334a45a8ff 148 {
bogdanm 0:9b334a45a8ff 149 DMA_Stream_TypeDef *Instance; /*!< Register base address */
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 void *Parent; /*!< Parent object state */
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 __IO uint32_t ErrorCode; /*!< DMA Error code */
mbed_official 83:a036322b8637 168
mbed_official 83:a036322b8637 169 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
mbed_official 83:a036322b8637 170
mbed_official 83:a036322b8637 171 uint32_t StreamIndex; /*!< DMA Stream Index */
mbed_official 83:a036322b8637 172
bogdanm 0:9b334a45a8ff 173 }DMA_HandleTypeDef;
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 /**
bogdanm 0:9b334a45a8ff 176 * @}
bogdanm 0:9b334a45a8ff 177 */
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 /** @defgroup DMA_Exported_Constants DMA Exported Constants
bogdanm 0:9b334a45a8ff 183 * @brief DMA Exported constants
bogdanm 0:9b334a45a8ff 184 * @{
bogdanm 0:9b334a45a8ff 185 */
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 /** @defgroup DMA_Error_Code DMA Error Code
bogdanm 0:9b334a45a8ff 188 * @brief DMA Error Code
bogdanm 0:9b334a45a8ff 189 * @{
bogdanm 0:9b334a45a8ff 190 */
bogdanm 0:9b334a45a8ff 191 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 0:9b334a45a8ff 192 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 0:9b334a45a8ff 193 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
bogdanm 0:9b334a45a8ff 194 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
bogdanm 0:9b334a45a8ff 195 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 0:9b334a45a8ff 196 /**
bogdanm 0:9b334a45a8ff 197 * @}
bogdanm 0:9b334a45a8ff 198 */
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 /** @defgroup DMA_Channel_selection DMA Channel selection
bogdanm 0:9b334a45a8ff 201 * @brief DMA channel selection
bogdanm 0:9b334a45a8ff 202 * @{
bogdanm 0:9b334a45a8ff 203 */
bogdanm 0:9b334a45a8ff 204 #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
bogdanm 0:9b334a45a8ff 205 #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
bogdanm 0:9b334a45a8ff 206 #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
bogdanm 0:9b334a45a8ff 207 #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
bogdanm 0:9b334a45a8ff 208 #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
bogdanm 0:9b334a45a8ff 209 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
bogdanm 0:9b334a45a8ff 210 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
bogdanm 0:9b334a45a8ff 211 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
bogdanm 0:9b334a45a8ff 212 /**
bogdanm 0:9b334a45a8ff 213 * @}
bogdanm 0:9b334a45a8ff 214 */
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
bogdanm 0:9b334a45a8ff 217 * @brief DMA data transfer direction
bogdanm 0:9b334a45a8ff 218 * @{
bogdanm 0:9b334a45a8ff 219 */
bogdanm 0:9b334a45a8ff 220 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
bogdanm 0:9b334a45a8ff 221 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
bogdanm 0:9b334a45a8ff 222 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
bogdanm 0:9b334a45a8ff 223 /**
bogdanm 0:9b334a45a8ff 224 * @}
bogdanm 0:9b334a45a8ff 225 */
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
bogdanm 0:9b334a45a8ff 228 * @brief DMA peripheral incremented mode
bogdanm 0:9b334a45a8ff 229 * @{
bogdanm 0:9b334a45a8ff 230 */
bogdanm 0:9b334a45a8ff 231 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
bogdanm 0:9b334a45a8ff 232 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
bogdanm 0:9b334a45a8ff 233 /**
bogdanm 0:9b334a45a8ff 234 * @}
bogdanm 0:9b334a45a8ff 235 */
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
bogdanm 0:9b334a45a8ff 238 * @brief DMA memory incremented mode
bogdanm 0:9b334a45a8ff 239 * @{
bogdanm 0:9b334a45a8ff 240 */
bogdanm 0:9b334a45a8ff 241 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
bogdanm 0:9b334a45a8ff 242 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
bogdanm 0:9b334a45a8ff 243 /**
bogdanm 0:9b334a45a8ff 244 * @}
bogdanm 0:9b334a45a8ff 245 */
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
bogdanm 0:9b334a45a8ff 249 * @brief DMA peripheral data size
bogdanm 0:9b334a45a8ff 250 * @{
bogdanm 0:9b334a45a8ff 251 */
bogdanm 0:9b334a45a8ff 252 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
bogdanm 0:9b334a45a8ff 253 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
bogdanm 0:9b334a45a8ff 254 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
bogdanm 0:9b334a45a8ff 255 /**
bogdanm 0:9b334a45a8ff 256 * @}
bogdanm 0:9b334a45a8ff 257 */
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /** @defgroup DMA_Memory_data_size DMA Memory data size
bogdanm 0:9b334a45a8ff 261 * @brief DMA memory data size
bogdanm 0:9b334a45a8ff 262 * @{
bogdanm 0:9b334a45a8ff 263 */
bogdanm 0:9b334a45a8ff 264 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
bogdanm 0:9b334a45a8ff 265 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
bogdanm 0:9b334a45a8ff 266 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
bogdanm 0:9b334a45a8ff 267 /**
bogdanm 0:9b334a45a8ff 268 * @}
bogdanm 0:9b334a45a8ff 269 */
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /** @defgroup DMA_mode DMA mode
bogdanm 0:9b334a45a8ff 272 * @brief DMA mode
bogdanm 0:9b334a45a8ff 273 * @{
bogdanm 0:9b334a45a8ff 274 */
bogdanm 0:9b334a45a8ff 275 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
bogdanm 0:9b334a45a8ff 276 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
bogdanm 0:9b334a45a8ff 277 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
bogdanm 0:9b334a45a8ff 278 /**
bogdanm 0:9b334a45a8ff 279 * @}
bogdanm 0:9b334a45a8ff 280 */
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 /** @defgroup DMA_Priority_level DMA Priority level
bogdanm 0:9b334a45a8ff 284 * @brief DMA priority levels
bogdanm 0:9b334a45a8ff 285 * @{
bogdanm 0:9b334a45a8ff 286 */
bogdanm 0:9b334a45a8ff 287 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
bogdanm 0:9b334a45a8ff 288 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
bogdanm 0:9b334a45a8ff 289 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
bogdanm 0:9b334a45a8ff 290 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
bogdanm 0:9b334a45a8ff 291 /**
bogdanm 0:9b334a45a8ff 292 * @}
bogdanm 0:9b334a45a8ff 293 */
bogdanm 0:9b334a45a8ff 294
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
bogdanm 0:9b334a45a8ff 297 * @brief DMA FIFO direct mode
bogdanm 0:9b334a45a8ff 298 * @{
bogdanm 0:9b334a45a8ff 299 */
bogdanm 0:9b334a45a8ff 300 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
bogdanm 0:9b334a45a8ff 301 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
bogdanm 0:9b334a45a8ff 302 /**
bogdanm 0:9b334a45a8ff 303 * @}
bogdanm 0:9b334a45a8ff 304 */
bogdanm 0:9b334a45a8ff 305
bogdanm 0:9b334a45a8ff 306 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
bogdanm 0:9b334a45a8ff 307 * @brief DMA FIFO level
bogdanm 0:9b334a45a8ff 308 * @{
bogdanm 0:9b334a45a8ff 309 */
bogdanm 0:9b334a45a8ff 310 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
bogdanm 0:9b334a45a8ff 311 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
bogdanm 0:9b334a45a8ff 312 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
bogdanm 0:9b334a45a8ff 313 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
bogdanm 0:9b334a45a8ff 314 /**
bogdanm 0:9b334a45a8ff 315 * @}
bogdanm 0:9b334a45a8ff 316 */
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 /** @defgroup DMA_Memory_burst DMA Memory burst
bogdanm 0:9b334a45a8ff 319 * @brief DMA memory burst
bogdanm 0:9b334a45a8ff 320 * @{
bogdanm 0:9b334a45a8ff 321 */
bogdanm 0:9b334a45a8ff 322 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 323 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
bogdanm 0:9b334a45a8ff 324 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
bogdanm 0:9b334a45a8ff 325 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
bogdanm 0:9b334a45a8ff 326 /**
bogdanm 0:9b334a45a8ff 327 * @}
bogdanm 0:9b334a45a8ff 328 */
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
bogdanm 0:9b334a45a8ff 332 * @brief DMA peripheral burst
bogdanm 0:9b334a45a8ff 333 * @{
bogdanm 0:9b334a45a8ff 334 */
bogdanm 0:9b334a45a8ff 335 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 336 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
bogdanm 0:9b334a45a8ff 337 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
bogdanm 0:9b334a45a8ff 338 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
bogdanm 0:9b334a45a8ff 339 /**
bogdanm 0:9b334a45a8ff 340 * @}
bogdanm 0:9b334a45a8ff 341 */
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
bogdanm 0:9b334a45a8ff 344 * @brief DMA interrupts definition
bogdanm 0:9b334a45a8ff 345 * @{
bogdanm 0:9b334a45a8ff 346 */
bogdanm 0:9b334a45a8ff 347 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
bogdanm 0:9b334a45a8ff 348 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
bogdanm 0:9b334a45a8ff 349 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
bogdanm 0:9b334a45a8ff 350 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
bogdanm 0:9b334a45a8ff 351 #define DMA_IT_FE ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 352 /**
bogdanm 0:9b334a45a8ff 353 * @}
bogdanm 0:9b334a45a8ff 354 */
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 /** @defgroup DMA_flag_definitions DMA flag definitions
bogdanm 0:9b334a45a8ff 357 * @brief DMA flag definitions
bogdanm 0:9b334a45a8ff 358 * @{
bogdanm 0:9b334a45a8ff 359 */
bogdanm 0:9b334a45a8ff 360 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
bogdanm 0:9b334a45a8ff 361 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
bogdanm 0:9b334a45a8ff 362 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 363 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 364 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 365 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 366 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 367 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 368 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 369 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 370 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 371 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 372 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 373 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 374 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 375 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 376 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 377 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 378 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 379 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 380 /**
bogdanm 0:9b334a45a8ff 381 * @}
bogdanm 0:9b334a45a8ff 382 */
bogdanm 0:9b334a45a8ff 383
bogdanm 0:9b334a45a8ff 384 /**
bogdanm 0:9b334a45a8ff 385 * @}
bogdanm 0:9b334a45a8ff 386 */
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 /* Exported macro ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 /** @brief Reset DMA handle state
bogdanm 0:9b334a45a8ff 391 * @param __HANDLE__: specifies the DMA handle.
bogdanm 0:9b334a45a8ff 392 * @retval None
bogdanm 0:9b334a45a8ff 393 */
bogdanm 0:9b334a45a8ff 394 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 0:9b334a45a8ff 395
bogdanm 0:9b334a45a8ff 396 /**
bogdanm 0:9b334a45a8ff 397 * @brief Return the current DMA Stream FIFO filled level.
bogdanm 0:9b334a45a8ff 398 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 399 * @retval The FIFO filling state.
bogdanm 0:9b334a45a8ff 400 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
bogdanm 0:9b334a45a8ff 401 * and not empty.
bogdanm 0:9b334a45a8ff 402 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
bogdanm 0:9b334a45a8ff 403 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
bogdanm 0:9b334a45a8ff 404 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
bogdanm 0:9b334a45a8ff 405 * - DMA_FIFOStatus_Empty: when FIFO is empty
bogdanm 0:9b334a45a8ff 406 * - DMA_FIFOStatus_Full: when FIFO is full
bogdanm 0:9b334a45a8ff 407 */
bogdanm 0:9b334a45a8ff 408 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /**
bogdanm 0:9b334a45a8ff 411 * @brief Enable the specified DMA Stream.
bogdanm 0:9b334a45a8ff 412 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 413 * @retval None
bogdanm 0:9b334a45a8ff 414 */
bogdanm 0:9b334a45a8ff 415 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /**
bogdanm 0:9b334a45a8ff 418 * @brief Disable the specified DMA Stream.
bogdanm 0:9b334a45a8ff 419 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 420 * @retval None
bogdanm 0:9b334a45a8ff 421 */
bogdanm 0:9b334a45a8ff 422 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /* Interrupt & Flag management */
bogdanm 0:9b334a45a8ff 425
bogdanm 0:9b334a45a8ff 426 /**
bogdanm 0:9b334a45a8ff 427 * @brief Return the current DMA Stream transfer complete flag.
bogdanm 0:9b334a45a8ff 428 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 429 * @retval The specified transfer complete flag index.
bogdanm 0:9b334a45a8ff 430 */
bogdanm 0:9b334a45a8ff 431 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
bogdanm 0:9b334a45a8ff 432 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
bogdanm 0:9b334a45a8ff 433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
bogdanm 0:9b334a45a8ff 434 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
bogdanm 0:9b334a45a8ff 435 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
bogdanm 0:9b334a45a8ff 436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
bogdanm 0:9b334a45a8ff 437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
bogdanm 0:9b334a45a8ff 438 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
bogdanm 0:9b334a45a8ff 439 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
bogdanm 0:9b334a45a8ff 440 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
bogdanm 0:9b334a45a8ff 441 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
bogdanm 0:9b334a45a8ff 442 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
bogdanm 0:9b334a45a8ff 443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
bogdanm 0:9b334a45a8ff 444 DMA_FLAG_TCIF3_7)
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /**
bogdanm 0:9b334a45a8ff 447 * @brief Return the current DMA Stream half transfer complete flag.
bogdanm 0:9b334a45a8ff 448 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 449 * @retval The specified half transfer complete flag index.
bogdanm 0:9b334a45a8ff 450 */
bogdanm 0:9b334a45a8ff 451 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
bogdanm 0:9b334a45a8ff 452 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
bogdanm 0:9b334a45a8ff 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
bogdanm 0:9b334a45a8ff 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
bogdanm 0:9b334a45a8ff 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
bogdanm 0:9b334a45a8ff 456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
bogdanm 0:9b334a45a8ff 457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
bogdanm 0:9b334a45a8ff 458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
bogdanm 0:9b334a45a8ff 459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
bogdanm 0:9b334a45a8ff 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
bogdanm 0:9b334a45a8ff 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
bogdanm 0:9b334a45a8ff 462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
bogdanm 0:9b334a45a8ff 463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
bogdanm 0:9b334a45a8ff 464 DMA_FLAG_HTIF3_7)
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 /**
bogdanm 0:9b334a45a8ff 467 * @brief Return the current DMA Stream transfer error flag.
bogdanm 0:9b334a45a8ff 468 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 469 * @retval The specified transfer error flag index.
bogdanm 0:9b334a45a8ff 470 */
bogdanm 0:9b334a45a8ff 471 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
bogdanm 0:9b334a45a8ff 472 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
bogdanm 0:9b334a45a8ff 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
bogdanm 0:9b334a45a8ff 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
bogdanm 0:9b334a45a8ff 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
bogdanm 0:9b334a45a8ff 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
bogdanm 0:9b334a45a8ff 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
bogdanm 0:9b334a45a8ff 478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
bogdanm 0:9b334a45a8ff 479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
bogdanm 0:9b334a45a8ff 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
bogdanm 0:9b334a45a8ff 481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
bogdanm 0:9b334a45a8ff 482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
bogdanm 0:9b334a45a8ff 483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
bogdanm 0:9b334a45a8ff 484 DMA_FLAG_TEIF3_7)
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 /**
bogdanm 0:9b334a45a8ff 487 * @brief Return the current DMA Stream FIFO error flag.
bogdanm 0:9b334a45a8ff 488 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 489 * @retval The specified FIFO error flag index.
bogdanm 0:9b334a45a8ff 490 */
bogdanm 0:9b334a45a8ff 491 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
bogdanm 0:9b334a45a8ff 492 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
bogdanm 0:9b334a45a8ff 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
bogdanm 0:9b334a45a8ff 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
bogdanm 0:9b334a45a8ff 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
bogdanm 0:9b334a45a8ff 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
bogdanm 0:9b334a45a8ff 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
bogdanm 0:9b334a45a8ff 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
bogdanm 0:9b334a45a8ff 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
bogdanm 0:9b334a45a8ff 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
bogdanm 0:9b334a45a8ff 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
bogdanm 0:9b334a45a8ff 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
bogdanm 0:9b334a45a8ff 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
bogdanm 0:9b334a45a8ff 504 DMA_FLAG_FEIF3_7)
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 /**
bogdanm 0:9b334a45a8ff 507 * @brief Return the current DMA Stream direct mode error flag.
bogdanm 0:9b334a45a8ff 508 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 509 * @retval The specified direct mode error flag index.
bogdanm 0:9b334a45a8ff 510 */
bogdanm 0:9b334a45a8ff 511 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
bogdanm 0:9b334a45a8ff 512 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
bogdanm 0:9b334a45a8ff 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
bogdanm 0:9b334a45a8ff 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
bogdanm 0:9b334a45a8ff 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
bogdanm 0:9b334a45a8ff 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
bogdanm 0:9b334a45a8ff 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
bogdanm 0:9b334a45a8ff 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
bogdanm 0:9b334a45a8ff 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
bogdanm 0:9b334a45a8ff 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
bogdanm 0:9b334a45a8ff 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
bogdanm 0:9b334a45a8ff 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
bogdanm 0:9b334a45a8ff 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
bogdanm 0:9b334a45a8ff 524 DMA_FLAG_DMEIF3_7)
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 /**
bogdanm 0:9b334a45a8ff 527 * @brief Get the DMA Stream pending flags.
bogdanm 0:9b334a45a8ff 528 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 529 * @param __FLAG__: Get the specified flag.
bogdanm 0:9b334a45a8ff 530 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 531 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
bogdanm 0:9b334a45a8ff 532 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
bogdanm 0:9b334a45a8ff 533 * @arg DMA_FLAG_TEIFx: Transfer error flag.
bogdanm 0:9b334a45a8ff 534 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
bogdanm 0:9b334a45a8ff 535 * @arg DMA_FLAG_FEIFx: FIFO error flag.
bogdanm 0:9b334a45a8ff 536 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
bogdanm 0:9b334a45a8ff 537 * @retval The state of FLAG (SET or RESET).
bogdanm 0:9b334a45a8ff 538 */
bogdanm 0:9b334a45a8ff 539 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
bogdanm 0:9b334a45a8ff 540 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
bogdanm 0:9b334a45a8ff 541 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
bogdanm 0:9b334a45a8ff 542 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
bogdanm 0:9b334a45a8ff 543
bogdanm 0:9b334a45a8ff 544 /**
bogdanm 0:9b334a45a8ff 545 * @brief Clear the DMA Stream pending flags.
bogdanm 0:9b334a45a8ff 546 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 547 * @param __FLAG__: specifies the flag to clear.
bogdanm 0:9b334a45a8ff 548 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 549 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
bogdanm 0:9b334a45a8ff 550 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
bogdanm 0:9b334a45a8ff 551 * @arg DMA_FLAG_TEIFx: Transfer error flag.
bogdanm 0:9b334a45a8ff 552 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
bogdanm 0:9b334a45a8ff 553 * @arg DMA_FLAG_FEIFx: FIFO error flag.
bogdanm 0:9b334a45a8ff 554 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
bogdanm 0:9b334a45a8ff 555 * @retval None
bogdanm 0:9b334a45a8ff 556 */
bogdanm 0:9b334a45a8ff 557 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
bogdanm 0:9b334a45a8ff 558 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
bogdanm 0:9b334a45a8ff 559 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
bogdanm 0:9b334a45a8ff 560 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
bogdanm 0:9b334a45a8ff 561
bogdanm 0:9b334a45a8ff 562 /**
bogdanm 0:9b334a45a8ff 563 * @brief Enable the specified DMA Stream interrupts.
bogdanm 0:9b334a45a8ff 564 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 565 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 0:9b334a45a8ff 566 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 567 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 0:9b334a45a8ff 568 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 0:9b334a45a8ff 569 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 0:9b334a45a8ff 570 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 0:9b334a45a8ff 571 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 0:9b334a45a8ff 572 * @retval None
bogdanm 0:9b334a45a8ff 573 */
bogdanm 0:9b334a45a8ff 574 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 0:9b334a45a8ff 575 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 /**
bogdanm 0:9b334a45a8ff 578 * @brief Disable the specified DMA Stream interrupts.
bogdanm 0:9b334a45a8ff 579 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 580 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 0:9b334a45a8ff 581 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 582 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 0:9b334a45a8ff 583 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 0:9b334a45a8ff 584 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 0:9b334a45a8ff 585 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 0:9b334a45a8ff 586 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 0:9b334a45a8ff 587 * @retval None
bogdanm 0:9b334a45a8ff 588 */
bogdanm 0:9b334a45a8ff 589 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 0:9b334a45a8ff 590 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592 /**
bogdanm 0:9b334a45a8ff 593 * @brief Check whether the specified DMA Stream interrupt is enabled or not.
bogdanm 0:9b334a45a8ff 594 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 595 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 0:9b334a45a8ff 596 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 597 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 0:9b334a45a8ff 598 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 0:9b334a45a8ff 599 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 0:9b334a45a8ff 600 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 0:9b334a45a8ff 601 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 0:9b334a45a8ff 602 * @retval The state of DMA_IT.
bogdanm 0:9b334a45a8ff 603 */
bogdanm 0:9b334a45a8ff 604 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 0:9b334a45a8ff 605 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
bogdanm 0:9b334a45a8ff 606 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
bogdanm 0:9b334a45a8ff 607
bogdanm 0:9b334a45a8ff 608 /**
bogdanm 0:9b334a45a8ff 609 * @brief Writes the number of data units to be transferred on the DMA Stream.
bogdanm 0:9b334a45a8ff 610 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 611 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
bogdanm 0:9b334a45a8ff 612 * Number of data items depends only on the Peripheral data format.
bogdanm 0:9b334a45a8ff 613 *
bogdanm 0:9b334a45a8ff 614 * @note If Peripheral data format is Bytes: number of data units is equal
bogdanm 0:9b334a45a8ff 615 * to total number of bytes to be transferred.
bogdanm 0:9b334a45a8ff 616 *
bogdanm 0:9b334a45a8ff 617 * @note If Peripheral data format is Half-Word: number of data units is
bogdanm 0:9b334a45a8ff 618 * equal to total number of bytes to be transferred / 2.
bogdanm 0:9b334a45a8ff 619 *
bogdanm 0:9b334a45a8ff 620 * @note If Peripheral data format is Word: number of data units is equal
bogdanm 0:9b334a45a8ff 621 * to total number of bytes to be transferred / 4.
bogdanm 0:9b334a45a8ff 622 *
bogdanm 0:9b334a45a8ff 623 * @retval The number of remaining data units in the current DMAy Streamx transfer.
bogdanm 0:9b334a45a8ff 624 */
bogdanm 0:9b334a45a8ff 625 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
bogdanm 0:9b334a45a8ff 626
bogdanm 0:9b334a45a8ff 627 /**
bogdanm 0:9b334a45a8ff 628 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
bogdanm 0:9b334a45a8ff 629 * @param __HANDLE__: DMA handle
bogdanm 0:9b334a45a8ff 630 *
bogdanm 0:9b334a45a8ff 631 * @retval The number of remaining data units in the current DMA Stream transfer.
bogdanm 0:9b334a45a8ff 632 */
bogdanm 0:9b334a45a8ff 633 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
bogdanm 0:9b334a45a8ff 634
bogdanm 0:9b334a45a8ff 635
bogdanm 0:9b334a45a8ff 636 /* Include DMA HAL Extension module */
bogdanm 0:9b334a45a8ff 637 #include "stm32f7xx_hal_dma_ex.h"
bogdanm 0:9b334a45a8ff 638
bogdanm 0:9b334a45a8ff 639 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 640
bogdanm 0:9b334a45a8ff 641 /** @defgroup DMA_Exported_Functions DMA Exported Functions
bogdanm 0:9b334a45a8ff 642 * @brief DMA Exported functions
bogdanm 0:9b334a45a8ff 643 * @{
bogdanm 0:9b334a45a8ff 644 */
bogdanm 0:9b334a45a8ff 645
bogdanm 0:9b334a45a8ff 646 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 647 * @brief Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 648 * @{
bogdanm 0:9b334a45a8ff 649 */
bogdanm 0:9b334a45a8ff 650 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 651 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 652 /**
bogdanm 0:9b334a45a8ff 653 * @}
bogdanm 0:9b334a45a8ff 654 */
bogdanm 0:9b334a45a8ff 655
bogdanm 0:9b334a45a8ff 656 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
bogdanm 0:9b334a45a8ff 657 * @brief I/O operation functions
bogdanm 0:9b334a45a8ff 658 * @{
bogdanm 0:9b334a45a8ff 659 */
bogdanm 0:9b334a45a8ff 660 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 0:9b334a45a8ff 661 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 0:9b334a45a8ff 662 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 663 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 664 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 665 /**
bogdanm 0:9b334a45a8ff 666 * @}
bogdanm 0:9b334a45a8ff 667 */
bogdanm 0:9b334a45a8ff 668
bogdanm 0:9b334a45a8ff 669 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
bogdanm 0:9b334a45a8ff 670 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 671 * @{
bogdanm 0:9b334a45a8ff 672 */
bogdanm 0:9b334a45a8ff 673 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 674 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm 0:9b334a45a8ff 675 /**
bogdanm 0:9b334a45a8ff 676 * @}
bogdanm 0:9b334a45a8ff 677 */
bogdanm 0:9b334a45a8ff 678 /**
bogdanm 0:9b334a45a8ff 679 * @}
bogdanm 0:9b334a45a8ff 680 */
bogdanm 0:9b334a45a8ff 681 /* Private Constants -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 682 /** @defgroup DMA_Private_Constants DMA Private Constants
bogdanm 0:9b334a45a8ff 683 * @brief DMA private defines and constants
bogdanm 0:9b334a45a8ff 684 * @{
bogdanm 0:9b334a45a8ff 685 */
bogdanm 0:9b334a45a8ff 686 /**
bogdanm 0:9b334a45a8ff 687 * @}
bogdanm 0:9b334a45a8ff 688 */
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 /* Private macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 691 /** @defgroup DMA_Private_Macros DMA Private Macros
bogdanm 0:9b334a45a8ff 692 * @brief DMA private macros
bogdanm 0:9b334a45a8ff 693 * @{
bogdanm 0:9b334a45a8ff 694 */
bogdanm 0:9b334a45a8ff 695 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
bogdanm 0:9b334a45a8ff 696 ((CHANNEL) == DMA_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 697 ((CHANNEL) == DMA_CHANNEL_2) || \
bogdanm 0:9b334a45a8ff 698 ((CHANNEL) == DMA_CHANNEL_3) || \
bogdanm 0:9b334a45a8ff 699 ((CHANNEL) == DMA_CHANNEL_4) || \
bogdanm 0:9b334a45a8ff 700 ((CHANNEL) == DMA_CHANNEL_5) || \
bogdanm 0:9b334a45a8ff 701 ((CHANNEL) == DMA_CHANNEL_6) || \
bogdanm 0:9b334a45a8ff 702 ((CHANNEL) == DMA_CHANNEL_7))
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
bogdanm 0:9b334a45a8ff 705 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
bogdanm 0:9b334a45a8ff 706 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
bogdanm 0:9b334a45a8ff 707
bogdanm 0:9b334a45a8ff 708 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
bogdanm 0:9b334a45a8ff 709
bogdanm 0:9b334a45a8ff 710 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
bogdanm 0:9b334a45a8ff 711 ((STATE) == DMA_PINC_DISABLE))
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
bogdanm 0:9b334a45a8ff 714 ((STATE) == DMA_MINC_DISABLE))
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
bogdanm 0:9b334a45a8ff 717 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
bogdanm 0:9b334a45a8ff 718 ((SIZE) == DMA_PDATAALIGN_WORD))
bogdanm 0:9b334a45a8ff 719
bogdanm 0:9b334a45a8ff 720 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
bogdanm 0:9b334a45a8ff 721 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
bogdanm 0:9b334a45a8ff 722 ((SIZE) == DMA_MDATAALIGN_WORD ))
bogdanm 0:9b334a45a8ff 723
bogdanm 0:9b334a45a8ff 724 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
bogdanm 0:9b334a45a8ff 725 ((MODE) == DMA_CIRCULAR) || \
bogdanm 0:9b334a45a8ff 726 ((MODE) == DMA_PFCTRL))
bogdanm 0:9b334a45a8ff 727
bogdanm 0:9b334a45a8ff 728 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
bogdanm 0:9b334a45a8ff 729 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
bogdanm 0:9b334a45a8ff 730 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
bogdanm 0:9b334a45a8ff 731 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
bogdanm 0:9b334a45a8ff 732
bogdanm 0:9b334a45a8ff 733 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
bogdanm 0:9b334a45a8ff 734 ((STATE) == DMA_FIFOMODE_ENABLE))
bogdanm 0:9b334a45a8ff 735
bogdanm 0:9b334a45a8ff 736 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
bogdanm 0:9b334a45a8ff 737 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
bogdanm 0:9b334a45a8ff 738 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
bogdanm 0:9b334a45a8ff 739 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
bogdanm 0:9b334a45a8ff 740
bogdanm 0:9b334a45a8ff 741 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
bogdanm 0:9b334a45a8ff 742 ((BURST) == DMA_MBURST_INC4) || \
bogdanm 0:9b334a45a8ff 743 ((BURST) == DMA_MBURST_INC8) || \
bogdanm 0:9b334a45a8ff 744 ((BURST) == DMA_MBURST_INC16))
bogdanm 0:9b334a45a8ff 745
bogdanm 0:9b334a45a8ff 746 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
bogdanm 0:9b334a45a8ff 747 ((BURST) == DMA_PBURST_INC4) || \
bogdanm 0:9b334a45a8ff 748 ((BURST) == DMA_PBURST_INC8) || \
bogdanm 0:9b334a45a8ff 749 ((BURST) == DMA_PBURST_INC16))
bogdanm 0:9b334a45a8ff 750 /**
bogdanm 0:9b334a45a8ff 751 * @}
bogdanm 0:9b334a45a8ff 752 */
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 755 /** @defgroup DMA_Private_Functions DMA Private Functions
bogdanm 0:9b334a45a8ff 756 * @brief DMA private functions
bogdanm 0:9b334a45a8ff 757 * @{
bogdanm 0:9b334a45a8ff 758 */
bogdanm 0:9b334a45a8ff 759 /**
bogdanm 0:9b334a45a8ff 760 * @}
bogdanm 0:9b334a45a8ff 761 */
bogdanm 0:9b334a45a8ff 762
bogdanm 0:9b334a45a8ff 763 /**
bogdanm 0:9b334a45a8ff 764 * @}
bogdanm 0:9b334a45a8ff 765 */
bogdanm 0:9b334a45a8ff 766
bogdanm 0:9b334a45a8ff 767 /**
bogdanm 0:9b334a45a8ff 768 * @}
bogdanm 0:9b334a45a8ff 769 */
bogdanm 0:9b334a45a8ff 770
bogdanm 0:9b334a45a8ff 771 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 772 }
bogdanm 0:9b334a45a8ff 773 #endif
bogdanm 0:9b334a45a8ff 774
bogdanm 0:9b334a45a8ff 775 #endif /* __STM32F7xx_HAL_DMA_H */
bogdanm 0:9b334a45a8ff 776
bogdanm 0:9b334a45a8ff 777 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/