en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fsmc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
19:112740acecfa 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_ll_fsmc.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 19:112740acecfa 5 * @version V1.4.1
mbed_official 19:112740acecfa 6 * @date 09-October-2015
bogdanm 0:9b334a45a8ff 7 * @brief FSMC Low Layer HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
bogdanm 0:9b334a45a8ff 11 * + Initialization/de-initialization functions
bogdanm 0:9b334a45a8ff 12 * + Peripheral Control functions
bogdanm 0:9b334a45a8ff 13 * + Peripheral State functions
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 @verbatim
bogdanm 0:9b334a45a8ff 16 ==============================================================================
bogdanm 0:9b334a45a8ff 17 ##### FSMC peripheral features #####
bogdanm 0:9b334a45a8ff 18 ==============================================================================
bogdanm 0:9b334a45a8ff 19 [..] The Flexible static memory controller (FSMC) includes two memory controllers:
bogdanm 0:9b334a45a8ff 20 (+) The NOR/PSRAM memory controller
bogdanm 0:9b334a45a8ff 21 (+) The NAND/PC Card memory controller
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
bogdanm 0:9b334a45a8ff 24 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
bogdanm 0:9b334a45a8ff 25 (+) to translate AHB transactions into the appropriate external device protocol.
bogdanm 0:9b334a45a8ff 26 (+) to meet the access time requirements of the external memory devices.
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 [..] All external memories share the addresses, data and control signals with the controller.
bogdanm 0:9b334a45a8ff 29 Each external device is accessed by means of a unique Chip Select. The FSMC performs
bogdanm 0:9b334a45a8ff 30 only one access at a time to an external device.
bogdanm 0:9b334a45a8ff 31 The main features of the FSMC controller are the following:
bogdanm 0:9b334a45a8ff 32 (+) Interface with static-memory mapped devices including:
bogdanm 0:9b334a45a8ff 33 (++) Static random access memory (SRAM).
bogdanm 0:9b334a45a8ff 34 (++) Read-only memory (ROM).
bogdanm 0:9b334a45a8ff 35 (++) NOR Flash memory/OneNAND Flash memory.
bogdanm 0:9b334a45a8ff 36 (++) PSRAM (4 memory banks).
bogdanm 0:9b334a45a8ff 37 (++) 16-bit PC Card compatible devices.
bogdanm 0:9b334a45a8ff 38 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
bogdanm 0:9b334a45a8ff 39 data.
bogdanm 0:9b334a45a8ff 40 (+) Independent Chip Select control for each memory bank.
bogdanm 0:9b334a45a8ff 41 (+) Independent configuration for each memory bank.
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 @endverbatim
bogdanm 0:9b334a45a8ff 44 ******************************************************************************
bogdanm 0:9b334a45a8ff 45 * @attention
bogdanm 0:9b334a45a8ff 46 *
bogdanm 0:9b334a45a8ff 47 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 48 *
bogdanm 0:9b334a45a8ff 49 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 50 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 51 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 52 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 54 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 55 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 57 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 58 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 59 *
bogdanm 0:9b334a45a8ff 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 70 *
bogdanm 0:9b334a45a8ff 71 ******************************************************************************
bogdanm 0:9b334a45a8ff 72 */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 75 #include "stm32f4xx_hal.h"
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 78 * @{
bogdanm 0:9b334a45a8ff 79 */
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 /** @defgroup FSMC_LL FSMC Low Layer
bogdanm 0:9b334a45a8ff 82 * @brief FSMC driver modules
bogdanm 0:9b334a45a8ff 83 * @{
bogdanm 0:9b334a45a8ff 84 */
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
mbed_official 19:112740acecfa 87 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
bogdanm 0:9b334a45a8ff 88 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 89 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 90 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 91 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 92 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 93 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 94 /** @addtogroup FSMC_LL_Private_Functions
bogdanm 0:9b334a45a8ff 95 * @{
bogdanm 0:9b334a45a8ff 96 */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 /** @addtogroup FSMC_LL_NORSRAM
bogdanm 0:9b334a45a8ff 99 * @brief NORSRAM Controller functions
bogdanm 0:9b334a45a8ff 100 *
bogdanm 0:9b334a45a8ff 101 @verbatim
bogdanm 0:9b334a45a8ff 102 ==============================================================================
bogdanm 0:9b334a45a8ff 103 ##### How to use NORSRAM device driver #####
bogdanm 0:9b334a45a8ff 104 ==============================================================================
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 [..]
bogdanm 0:9b334a45a8ff 107 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
bogdanm 0:9b334a45a8ff 108 to run the NORSRAM external devices.
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
bogdanm 0:9b334a45a8ff 111 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
bogdanm 0:9b334a45a8ff 112 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
bogdanm 0:9b334a45a8ff 113 (+) FSMC NORSRAM bank extended timing configuration using the function
bogdanm 0:9b334a45a8ff 114 FSMC_NORSRAM_Extended_Timing_Init()
bogdanm 0:9b334a45a8ff 115 (+) FSMC NORSRAM bank enable/disable write operation using the functions
bogdanm 0:9b334a45a8ff 116 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 @endverbatim
bogdanm 0:9b334a45a8ff 119 * @{
bogdanm 0:9b334a45a8ff 120 */
bogdanm 0:9b334a45a8ff 121
bogdanm 0:9b334a45a8ff 122 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
bogdanm 0:9b334a45a8ff 123 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 124 *
bogdanm 0:9b334a45a8ff 125 @verbatim
bogdanm 0:9b334a45a8ff 126 ==============================================================================
bogdanm 0:9b334a45a8ff 127 ##### Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 128 ==============================================================================
bogdanm 0:9b334a45a8ff 129 [..]
bogdanm 0:9b334a45a8ff 130 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 131 (+) Initialize and configure the FSMC NORSRAM interface
bogdanm 0:9b334a45a8ff 132 (+) De-initialize the FSMC NORSRAM interface
bogdanm 0:9b334a45a8ff 133 (+) Configure the FSMC clock and associated GPIOs
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 @endverbatim
bogdanm 0:9b334a45a8ff 136 * @{
bogdanm 0:9b334a45a8ff 137 */
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 /**
bogdanm 0:9b334a45a8ff 140 * @brief Initialize the FSMC_NORSRAM device according to the specified
bogdanm 0:9b334a45a8ff 141 * control parameters in the FSMC_NORSRAM_InitTypeDef
bogdanm 0:9b334a45a8ff 142 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 143 * @param Init: Pointer to NORSRAM Initialization structure
bogdanm 0:9b334a45a8ff 144 * @retval HAL status
bogdanm 0:9b334a45a8ff 145 */
bogdanm 0:9b334a45a8ff 146 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
bogdanm 0:9b334a45a8ff 147 {
bogdanm 0:9b334a45a8ff 148 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 /* Check the parameters */
bogdanm 0:9b334a45a8ff 151 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
bogdanm 0:9b334a45a8ff 152 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
bogdanm 0:9b334a45a8ff 153 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
bogdanm 0:9b334a45a8ff 154 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
bogdanm 0:9b334a45a8ff 155 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
bogdanm 0:9b334a45a8ff 156 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
bogdanm 0:9b334a45a8ff 157 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
bogdanm 0:9b334a45a8ff 158 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
bogdanm 0:9b334a45a8ff 159 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
bogdanm 0:9b334a45a8ff 160 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
bogdanm 0:9b334a45a8ff 161 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
bogdanm 0:9b334a45a8ff 162 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
bogdanm 0:9b334a45a8ff 163 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /* Get the BTCR register value */
bogdanm 0:9b334a45a8ff 166 tmpr = Device->BTCR[Init->NSBank];
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
bogdanm 0:9b334a45a8ff 169 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
bogdanm 0:9b334a45a8ff 170 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
bogdanm 0:9b334a45a8ff 171 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
bogdanm 0:9b334a45a8ff 172 FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
bogdanm 0:9b334a45a8ff 173 FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
bogdanm 0:9b334a45a8ff 174 FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW));
bogdanm 0:9b334a45a8ff 175 /* Set NORSRAM device control parameters */
bogdanm 0:9b334a45a8ff 176 tmpr |= (uint32_t)(Init->DataAddressMux |\
bogdanm 0:9b334a45a8ff 177 Init->MemoryType |\
bogdanm 0:9b334a45a8ff 178 Init->MemoryDataWidth |\
bogdanm 0:9b334a45a8ff 179 Init->BurstAccessMode |\
bogdanm 0:9b334a45a8ff 180 Init->WaitSignalPolarity |\
bogdanm 0:9b334a45a8ff 181 Init->WrapMode |\
bogdanm 0:9b334a45a8ff 182 Init->WaitSignalActive |\
bogdanm 0:9b334a45a8ff 183 Init->WriteOperation |\
bogdanm 0:9b334a45a8ff 184 Init->WaitSignal |\
bogdanm 0:9b334a45a8ff 185 Init->ExtendedMode |\
bogdanm 0:9b334a45a8ff 186 Init->AsynchronousWait |\
bogdanm 0:9b334a45a8ff 187 Init->WriteBurst
bogdanm 0:9b334a45a8ff 188 );
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
bogdanm 0:9b334a45a8ff 191 {
bogdanm 0:9b334a45a8ff 192 tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
bogdanm 0:9b334a45a8ff 193 }
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 Device->BTCR[Init->NSBank] = tmpr;
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 return HAL_OK;
bogdanm 0:9b334a45a8ff 198 }
bogdanm 0:9b334a45a8ff 199
bogdanm 0:9b334a45a8ff 200 /**
bogdanm 0:9b334a45a8ff 201 * @brief DeInitialize the FSMC_NORSRAM peripheral
bogdanm 0:9b334a45a8ff 202 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 203 * @param ExDevice: Pointer to NORSRAM extended mode device instance
bogdanm 0:9b334a45a8ff 204 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 205 * @retval HAL status
bogdanm 0:9b334a45a8ff 206 */
bogdanm 0:9b334a45a8ff 207 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
bogdanm 0:9b334a45a8ff 208 {
bogdanm 0:9b334a45a8ff 209 /* Check the parameters */
bogdanm 0:9b334a45a8ff 210 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
bogdanm 0:9b334a45a8ff 211 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /* Disable the FSMC_NORSRAM device */
bogdanm 0:9b334a45a8ff 214 __FSMC_NORSRAM_DISABLE(Device, Bank);
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 /* De-initialize the FSMC_NORSRAM device */
bogdanm 0:9b334a45a8ff 217 /* FSMC_NORSRAM_BANK1 */
bogdanm 0:9b334a45a8ff 218 if(Bank == FSMC_NORSRAM_BANK1)
bogdanm 0:9b334a45a8ff 219 {
bogdanm 0:9b334a45a8ff 220 Device->BTCR[Bank] = 0x000030DB;
bogdanm 0:9b334a45a8ff 221 }
bogdanm 0:9b334a45a8ff 222 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
bogdanm 0:9b334a45a8ff 223 else
bogdanm 0:9b334a45a8ff 224 {
bogdanm 0:9b334a45a8ff 225 Device->BTCR[Bank] = 0x000030D2;
bogdanm 0:9b334a45a8ff 226 }
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 229 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 return HAL_OK;
bogdanm 0:9b334a45a8ff 232 }
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 /**
bogdanm 0:9b334a45a8ff 236 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
bogdanm 0:9b334a45a8ff 237 * parameters in the FSMC_NORSRAM_TimingTypeDef
bogdanm 0:9b334a45a8ff 238 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 239 * @param Timing: Pointer to NORSRAM Timing structure
bogdanm 0:9b334a45a8ff 240 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 241 * @retval HAL status
bogdanm 0:9b334a45a8ff 242 */
bogdanm 0:9b334a45a8ff 243 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
bogdanm 0:9b334a45a8ff 244 {
bogdanm 0:9b334a45a8ff 245 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 /* Check the parameters */
bogdanm 0:9b334a45a8ff 248 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
bogdanm 0:9b334a45a8ff 249 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
bogdanm 0:9b334a45a8ff 250 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
bogdanm 0:9b334a45a8ff 251 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
bogdanm 0:9b334a45a8ff 252 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
bogdanm 0:9b334a45a8ff 253 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
bogdanm 0:9b334a45a8ff 254 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 /* Get the BTCR register value */
bogdanm 0:9b334a45a8ff 257 tmpr = Device->BTCR[Bank + 1];
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
bogdanm 0:9b334a45a8ff 260 tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
bogdanm 0:9b334a45a8ff 261 FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
bogdanm 0:9b334a45a8ff 262 FSMC_BTR1_ACCMOD));
bogdanm 0:9b334a45a8ff 263
bogdanm 0:9b334a45a8ff 264 /* Set FSMC_NORSRAM device timing parameters */
bogdanm 0:9b334a45a8ff 265 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
bogdanm 0:9b334a45a8ff 266 ((Timing->AddressHoldTime) << 4) |\
bogdanm 0:9b334a45a8ff 267 ((Timing->DataSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 268 ((Timing->BusTurnAroundDuration) << 16) |\
bogdanm 0:9b334a45a8ff 269 (((Timing->CLKDivision)-1) << 20) |\
bogdanm 0:9b334a45a8ff 270 (((Timing->DataLatency)-2) << 24) |\
bogdanm 0:9b334a45a8ff 271 (Timing->AccessMode));
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 Device->BTCR[Bank + 1] = tmpr;
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 return HAL_OK;
bogdanm 0:9b334a45a8ff 276 }
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 /**
bogdanm 0:9b334a45a8ff 279 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
bogdanm 0:9b334a45a8ff 280 * parameters in the FSMC_NORSRAM_TimingTypeDef
bogdanm 0:9b334a45a8ff 281 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 282 * @param Timing: Pointer to NORSRAM Timing structure
bogdanm 0:9b334a45a8ff 283 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 284 * @retval HAL status
bogdanm 0:9b334a45a8ff 285 */
bogdanm 0:9b334a45a8ff 286 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
bogdanm 0:9b334a45a8ff 287 {
bogdanm 0:9b334a45a8ff 288 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
bogdanm 0:9b334a45a8ff 291 if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
bogdanm 0:9b334a45a8ff 292 {
bogdanm 0:9b334a45a8ff 293 /* Check the parameters */
bogdanm 0:9b334a45a8ff 294 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
bogdanm 0:9b334a45a8ff 295 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
bogdanm 0:9b334a45a8ff 296 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
bogdanm 0:9b334a45a8ff 297 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
bogdanm 0:9b334a45a8ff 298 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
bogdanm 0:9b334a45a8ff 299 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
bogdanm 0:9b334a45a8ff 300 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 /* Get the BWTR register value */
bogdanm 0:9b334a45a8ff 303 tmpr = Device->BWTR[Bank];
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
bogdanm 0:9b334a45a8ff 306 tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
bogdanm 0:9b334a45a8ff 307 FSMC_BWTR1_BUSTURN | FSMC_BWTR1_CLKDIV | FSMC_BWTR1_DATLAT | \
bogdanm 0:9b334a45a8ff 308 FSMC_BWTR1_ACCMOD));
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
bogdanm 0:9b334a45a8ff 311 ((Timing->AddressHoldTime) << 4) |\
bogdanm 0:9b334a45a8ff 312 ((Timing->DataSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 313 ((Timing->BusTurnAroundDuration) << 16) |\
bogdanm 0:9b334a45a8ff 314 (((Timing->CLKDivision)-1) << 20) |\
bogdanm 0:9b334a45a8ff 315 (((Timing->DataLatency)-2) << 24) |\
bogdanm 0:9b334a45a8ff 316 (Timing->AccessMode));
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 Device->BWTR[Bank] = tmpr;
bogdanm 0:9b334a45a8ff 319 }
bogdanm 0:9b334a45a8ff 320 else
bogdanm 0:9b334a45a8ff 321 {
bogdanm 0:9b334a45a8ff 322 Device->BWTR[Bank] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 323 }
bogdanm 0:9b334a45a8ff 324
bogdanm 0:9b334a45a8ff 325 return HAL_OK;
bogdanm 0:9b334a45a8ff 326 }
bogdanm 0:9b334a45a8ff 327 /**
bogdanm 0:9b334a45a8ff 328 * @}
bogdanm 0:9b334a45a8ff 329 */
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
bogdanm 0:9b334a45a8ff 332 * @brief management functions
bogdanm 0:9b334a45a8ff 333 *
bogdanm 0:9b334a45a8ff 334 @verbatim
bogdanm 0:9b334a45a8ff 335 ==============================================================================
bogdanm 0:9b334a45a8ff 336 ##### FSMC_NORSRAM Control functions #####
bogdanm 0:9b334a45a8ff 337 ==============================================================================
bogdanm 0:9b334a45a8ff 338 [..]
bogdanm 0:9b334a45a8ff 339 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 340 the FSMC NORSRAM interface.
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 @endverbatim
bogdanm 0:9b334a45a8ff 343 * @{
bogdanm 0:9b334a45a8ff 344 */
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 /**
bogdanm 0:9b334a45a8ff 347 * @brief Enables dynamically FSMC_NORSRAM write operation.
bogdanm 0:9b334a45a8ff 348 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 349 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 350 * @retval HAL status
bogdanm 0:9b334a45a8ff 351 */
bogdanm 0:9b334a45a8ff 352 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
bogdanm 0:9b334a45a8ff 353 {
bogdanm 0:9b334a45a8ff 354 /* Enable write operation */
bogdanm 0:9b334a45a8ff 355 Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 return HAL_OK;
bogdanm 0:9b334a45a8ff 358 }
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360 /**
bogdanm 0:9b334a45a8ff 361 * @brief Disables dynamically FSMC_NORSRAM write operation.
bogdanm 0:9b334a45a8ff 362 * @param Device: Pointer to NORSRAM device instance
bogdanm 0:9b334a45a8ff 363 * @param Bank: NORSRAM bank number
bogdanm 0:9b334a45a8ff 364 * @retval HAL status
bogdanm 0:9b334a45a8ff 365 */
bogdanm 0:9b334a45a8ff 366 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
bogdanm 0:9b334a45a8ff 367 {
bogdanm 0:9b334a45a8ff 368 /* Disable write operation */
bogdanm 0:9b334a45a8ff 369 Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 return HAL_OK;
bogdanm 0:9b334a45a8ff 372 }
bogdanm 0:9b334a45a8ff 373 /**
bogdanm 0:9b334a45a8ff 374 * @}
bogdanm 0:9b334a45a8ff 375 */
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 /**
bogdanm 0:9b334a45a8ff 378 * @}
bogdanm 0:9b334a45a8ff 379 */
mbed_official 19:112740acecfa 380
mbed_official 19:112740acecfa 381 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
bogdanm 0:9b334a45a8ff 382 /** @addtogroup FSMC_LL_NAND
bogdanm 0:9b334a45a8ff 383 * @brief NAND Controller functions
bogdanm 0:9b334a45a8ff 384 *
bogdanm 0:9b334a45a8ff 385 @verbatim
bogdanm 0:9b334a45a8ff 386 ==============================================================================
bogdanm 0:9b334a45a8ff 387 ##### How to use NAND device driver #####
bogdanm 0:9b334a45a8ff 388 ==============================================================================
bogdanm 0:9b334a45a8ff 389 [..]
bogdanm 0:9b334a45a8ff 390 This driver contains a set of APIs to interface with the FSMC NAND banks in order
bogdanm 0:9b334a45a8ff 391 to run the NAND external devices.
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
bogdanm 0:9b334a45a8ff 394 (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
bogdanm 0:9b334a45a8ff 395 (+) FSMC NAND bank common space timing configuration using the function
bogdanm 0:9b334a45a8ff 396 FSMC_NAND_CommonSpace_Timing_Init()
bogdanm 0:9b334a45a8ff 397 (+) FSMC NAND bank attribute space timing configuration using the function
bogdanm 0:9b334a45a8ff 398 FSMC_NAND_AttributeSpace_Timing_Init()
bogdanm 0:9b334a45a8ff 399 (+) FSMC NAND bank enable/disable ECC correction feature using the functions
bogdanm 0:9b334a45a8ff 400 FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
bogdanm 0:9b334a45a8ff 401 (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 @endverbatim
bogdanm 0:9b334a45a8ff 404 * @{
bogdanm 0:9b334a45a8ff 405 */
bogdanm 0:9b334a45a8ff 406
bogdanm 0:9b334a45a8ff 407 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
bogdanm 0:9b334a45a8ff 408 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 409 *
bogdanm 0:9b334a45a8ff 410 @verbatim
bogdanm 0:9b334a45a8ff 411 ==============================================================================
bogdanm 0:9b334a45a8ff 412 ##### Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 413 ==============================================================================
bogdanm 0:9b334a45a8ff 414 [..]
bogdanm 0:9b334a45a8ff 415 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 416 (+) Initialize and configure the FSMC NAND interface
bogdanm 0:9b334a45a8ff 417 (+) De-initialize the FSMC NAND interface
bogdanm 0:9b334a45a8ff 418 (+) Configure the FSMC clock and associated GPIOs
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 @endverbatim
bogdanm 0:9b334a45a8ff 421 * @{
bogdanm 0:9b334a45a8ff 422 */
bogdanm 0:9b334a45a8ff 423
bogdanm 0:9b334a45a8ff 424 /**
bogdanm 0:9b334a45a8ff 425 * @brief Initializes the FSMC_NAND device according to the specified
bogdanm 0:9b334a45a8ff 426 * control parameters in the FSMC_NAND_HandleTypeDef
bogdanm 0:9b334a45a8ff 427 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 428 * @param Init: Pointer to NAND Initialization structure
bogdanm 0:9b334a45a8ff 429 * @retval HAL status
bogdanm 0:9b334a45a8ff 430 */
bogdanm 0:9b334a45a8ff 431 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
bogdanm 0:9b334a45a8ff 432 {
bogdanm 0:9b334a45a8ff 433 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 /* Check the parameters */
bogdanm 0:9b334a45a8ff 436 assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
bogdanm 0:9b334a45a8ff 437 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
bogdanm 0:9b334a45a8ff 438 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
bogdanm 0:9b334a45a8ff 439 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
bogdanm 0:9b334a45a8ff 440 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
bogdanm 0:9b334a45a8ff 441 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
bogdanm 0:9b334a45a8ff 442 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 if(Init->NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 445 {
bogdanm 0:9b334a45a8ff 446 /* Get the NAND bank 2 register value */
bogdanm 0:9b334a45a8ff 447 tmpr = Device->PCR2;
bogdanm 0:9b334a45a8ff 448 }
bogdanm 0:9b334a45a8ff 449 else
bogdanm 0:9b334a45a8ff 450 {
bogdanm 0:9b334a45a8ff 451 /* Get the NAND bank 3 register value */
bogdanm 0:9b334a45a8ff 452 tmpr = Device->PCR3;
bogdanm 0:9b334a45a8ff 453 }
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
bogdanm 0:9b334a45a8ff 456 tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
bogdanm 0:9b334a45a8ff 457 FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
bogdanm 0:9b334a45a8ff 458 FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /* Set NAND device control parameters */
bogdanm 0:9b334a45a8ff 461 tmpr |= (uint32_t)(Init->Waitfeature |\
bogdanm 0:9b334a45a8ff 462 FSMC_PCR_MEMORY_TYPE_NAND |\
bogdanm 0:9b334a45a8ff 463 Init->MemoryDataWidth |\
bogdanm 0:9b334a45a8ff 464 Init->EccComputation |\
bogdanm 0:9b334a45a8ff 465 Init->ECCPageSize |\
bogdanm 0:9b334a45a8ff 466 ((Init->TCLRSetupTime) << 9) |\
bogdanm 0:9b334a45a8ff 467 ((Init->TARSetupTime) << 13));
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 if(Init->NandBank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 470 {
bogdanm 0:9b334a45a8ff 471 /* NAND bank 2 registers configuration */
bogdanm 0:9b334a45a8ff 472 Device->PCR2 = tmpr;
bogdanm 0:9b334a45a8ff 473 }
bogdanm 0:9b334a45a8ff 474 else
bogdanm 0:9b334a45a8ff 475 {
bogdanm 0:9b334a45a8ff 476 /* NAND bank 3 registers configuration */
bogdanm 0:9b334a45a8ff 477 Device->PCR3 = tmpr;
bogdanm 0:9b334a45a8ff 478 }
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 return HAL_OK;
bogdanm 0:9b334a45a8ff 481 }
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /**
bogdanm 0:9b334a45a8ff 484 * @brief Initializes the FSMC_NAND Common space Timing according to the specified
bogdanm 0:9b334a45a8ff 485 * parameters in the FSMC_NAND_PCC_TimingTypeDef
bogdanm 0:9b334a45a8ff 486 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 487 * @param Timing: Pointer to NAND timing structure
bogdanm 0:9b334a45a8ff 488 * @param Bank: NAND bank number
bogdanm 0:9b334a45a8ff 489 * @retval HAL status
bogdanm 0:9b334a45a8ff 490 */
bogdanm 0:9b334a45a8ff 491 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
bogdanm 0:9b334a45a8ff 492 {
bogdanm 0:9b334a45a8ff 493 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 /* Check the parameters */
bogdanm 0:9b334a45a8ff 496 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
bogdanm 0:9b334a45a8ff 497 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm 0:9b334a45a8ff 498 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm 0:9b334a45a8ff 499 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm 0:9b334a45a8ff 500
bogdanm 0:9b334a45a8ff 501 if(Bank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 502 {
bogdanm 0:9b334a45a8ff 503 /* Get the NAND bank 2 register value */
bogdanm 0:9b334a45a8ff 504 tmpr = Device->PMEM2;
bogdanm 0:9b334a45a8ff 505 }
bogdanm 0:9b334a45a8ff 506 else
bogdanm 0:9b334a45a8ff 507 {
bogdanm 0:9b334a45a8ff 508 /* Get the NAND bank 3 register value */
bogdanm 0:9b334a45a8ff 509 tmpr = Device->PMEM3;
bogdanm 0:9b334a45a8ff 510 }
bogdanm 0:9b334a45a8ff 511
bogdanm 0:9b334a45a8ff 512 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
bogdanm 0:9b334a45a8ff 513 tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
bogdanm 0:9b334a45a8ff 514 FSMC_PMEM2_MEMHIZ2));
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 /* Set FSMC_NAND device timing parameters */
bogdanm 0:9b334a45a8ff 517 tmpr |= (uint32_t)(Timing->SetupTime |\
bogdanm 0:9b334a45a8ff 518 ((Timing->WaitSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 519 ((Timing->HoldSetupTime) << 16) |\
bogdanm 0:9b334a45a8ff 520 ((Timing->HiZSetupTime) << 24)
bogdanm 0:9b334a45a8ff 521 );
bogdanm 0:9b334a45a8ff 522
bogdanm 0:9b334a45a8ff 523 if(Bank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 524 {
bogdanm 0:9b334a45a8ff 525 /* NAND bank 2 registers configuration */
bogdanm 0:9b334a45a8ff 526 Device->PMEM2 = tmpr;
bogdanm 0:9b334a45a8ff 527 }
bogdanm 0:9b334a45a8ff 528 else
bogdanm 0:9b334a45a8ff 529 {
bogdanm 0:9b334a45a8ff 530 /* NAND bank 3 registers configuration */
bogdanm 0:9b334a45a8ff 531 Device->PMEM3 = tmpr;
bogdanm 0:9b334a45a8ff 532 }
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 return HAL_OK;
bogdanm 0:9b334a45a8ff 535 }
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 /**
bogdanm 0:9b334a45a8ff 538 * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
bogdanm 0:9b334a45a8ff 539 * parameters in the FSMC_NAND_PCC_TimingTypeDef
bogdanm 0:9b334a45a8ff 540 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 541 * @param Timing: Pointer to NAND timing structure
bogdanm 0:9b334a45a8ff 542 * @param Bank: NAND bank number
bogdanm 0:9b334a45a8ff 543 * @retval HAL status
bogdanm 0:9b334a45a8ff 544 */
bogdanm 0:9b334a45a8ff 545 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
bogdanm 0:9b334a45a8ff 546 {
bogdanm 0:9b334a45a8ff 547 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549 /* Check the parameters */
bogdanm 0:9b334a45a8ff 550 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
bogdanm 0:9b334a45a8ff 551 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm 0:9b334a45a8ff 552 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm 0:9b334a45a8ff 553 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm 0:9b334a45a8ff 554
bogdanm 0:9b334a45a8ff 555 if(Bank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 556 {
bogdanm 0:9b334a45a8ff 557 /* Get the NAND bank 2 register value */
bogdanm 0:9b334a45a8ff 558 tmpr = Device->PATT2;
bogdanm 0:9b334a45a8ff 559 }
bogdanm 0:9b334a45a8ff 560 else
bogdanm 0:9b334a45a8ff 561 {
bogdanm 0:9b334a45a8ff 562 /* Get the NAND bank 3 register value */
bogdanm 0:9b334a45a8ff 563 tmpr = Device->PATT3;
bogdanm 0:9b334a45a8ff 564 }
bogdanm 0:9b334a45a8ff 565
bogdanm 0:9b334a45a8ff 566 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
bogdanm 0:9b334a45a8ff 567 tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
bogdanm 0:9b334a45a8ff 568 FSMC_PATT2_ATTHIZ2));
bogdanm 0:9b334a45a8ff 569
bogdanm 0:9b334a45a8ff 570 /* Set FSMC_NAND device timing parameters */
bogdanm 0:9b334a45a8ff 571 tmpr |= (uint32_t)(Timing->SetupTime |\
bogdanm 0:9b334a45a8ff 572 ((Timing->WaitSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 573 ((Timing->HoldSetupTime) << 16) |\
bogdanm 0:9b334a45a8ff 574 ((Timing->HiZSetupTime) << 24)
bogdanm 0:9b334a45a8ff 575 );
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 if(Bank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 578 {
bogdanm 0:9b334a45a8ff 579 /* NAND bank 2 registers configuration */
bogdanm 0:9b334a45a8ff 580 Device->PATT2 = tmpr;
bogdanm 0:9b334a45a8ff 581 }
bogdanm 0:9b334a45a8ff 582 else
bogdanm 0:9b334a45a8ff 583 {
bogdanm 0:9b334a45a8ff 584 /* NAND bank 3 registers configuration */
bogdanm 0:9b334a45a8ff 585 Device->PATT3 = tmpr;
bogdanm 0:9b334a45a8ff 586 }
bogdanm 0:9b334a45a8ff 587
bogdanm 0:9b334a45a8ff 588 return HAL_OK;
bogdanm 0:9b334a45a8ff 589 }
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 /**
bogdanm 0:9b334a45a8ff 592 * @brief DeInitializes the FSMC_NAND device
bogdanm 0:9b334a45a8ff 593 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 594 * @param Bank: NAND bank number
bogdanm 0:9b334a45a8ff 595 * @retval HAL status
bogdanm 0:9b334a45a8ff 596 */
bogdanm 0:9b334a45a8ff 597 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
bogdanm 0:9b334a45a8ff 598 {
bogdanm 0:9b334a45a8ff 599 /* Disable the NAND Bank */
bogdanm 0:9b334a45a8ff 600 __FSMC_NAND_DISABLE(Device, Bank);
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 /* De-initialize the NAND Bank */
bogdanm 0:9b334a45a8ff 603 if(Bank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 604 {
bogdanm 0:9b334a45a8ff 605 /* Set the FSMC_NAND_BANK2 registers to their reset values */
bogdanm 0:9b334a45a8ff 606 Device->PCR2 = 0x00000018;
bogdanm 0:9b334a45a8ff 607 Device->SR2 = 0x00000040;
bogdanm 0:9b334a45a8ff 608 Device->PMEM2 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 609 Device->PATT2 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 610 }
bogdanm 0:9b334a45a8ff 611 /* FSMC_Bank3_NAND */
bogdanm 0:9b334a45a8ff 612 else
bogdanm 0:9b334a45a8ff 613 {
bogdanm 0:9b334a45a8ff 614 /* Set the FSMC_NAND_BANK3 registers to their reset values */
bogdanm 0:9b334a45a8ff 615 Device->PCR3 = 0x00000018;
bogdanm 0:9b334a45a8ff 616 Device->SR3 = 0x00000040;
bogdanm 0:9b334a45a8ff 617 Device->PMEM3 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 618 Device->PATT3 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 619 }
bogdanm 0:9b334a45a8ff 620
bogdanm 0:9b334a45a8ff 621 return HAL_OK;
bogdanm 0:9b334a45a8ff 622 }
bogdanm 0:9b334a45a8ff 623 /**
bogdanm 0:9b334a45a8ff 624 * @}
bogdanm 0:9b334a45a8ff 625 */
bogdanm 0:9b334a45a8ff 626
bogdanm 0:9b334a45a8ff 627 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
bogdanm 0:9b334a45a8ff 628 * @brief management functions
bogdanm 0:9b334a45a8ff 629 *
bogdanm 0:9b334a45a8ff 630 @verbatim
bogdanm 0:9b334a45a8ff 631 ==============================================================================
bogdanm 0:9b334a45a8ff 632 ##### FSMC_NAND Control functions #####
bogdanm 0:9b334a45a8ff 633 ==============================================================================
bogdanm 0:9b334a45a8ff 634 [..]
bogdanm 0:9b334a45a8ff 635 This subsection provides a set of functions allowing to control dynamically
bogdanm 0:9b334a45a8ff 636 the FSMC NAND interface.
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638 @endverbatim
bogdanm 0:9b334a45a8ff 639 * @{
bogdanm 0:9b334a45a8ff 640 */
bogdanm 0:9b334a45a8ff 641
bogdanm 0:9b334a45a8ff 642 /**
bogdanm 0:9b334a45a8ff 643 * @brief Enables dynamically FSMC_NAND ECC feature.
bogdanm 0:9b334a45a8ff 644 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 645 * @param Bank: NAND bank number
bogdanm 0:9b334a45a8ff 646 * @retval HAL status
bogdanm 0:9b334a45a8ff 647 */
bogdanm 0:9b334a45a8ff 648 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
bogdanm 0:9b334a45a8ff 649 {
bogdanm 0:9b334a45a8ff 650 /* Enable ECC feature */
bogdanm 0:9b334a45a8ff 651 if(Bank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 652 {
bogdanm 0:9b334a45a8ff 653 Device->PCR2 |= FSMC_PCR2_ECCEN;
bogdanm 0:9b334a45a8ff 654 }
bogdanm 0:9b334a45a8ff 655 else
bogdanm 0:9b334a45a8ff 656 {
bogdanm 0:9b334a45a8ff 657 Device->PCR3 |= FSMC_PCR3_ECCEN;
bogdanm 0:9b334a45a8ff 658 }
bogdanm 0:9b334a45a8ff 659
bogdanm 0:9b334a45a8ff 660 return HAL_OK;
bogdanm 0:9b334a45a8ff 661 }
bogdanm 0:9b334a45a8ff 662
bogdanm 0:9b334a45a8ff 663 /**
bogdanm 0:9b334a45a8ff 664 * @brief Disables dynamically FSMC_NAND ECC feature.
bogdanm 0:9b334a45a8ff 665 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 666 * @param Bank: NAND bank number
bogdanm 0:9b334a45a8ff 667 * @retval HAL status
bogdanm 0:9b334a45a8ff 668 */
bogdanm 0:9b334a45a8ff 669 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
bogdanm 0:9b334a45a8ff 670 {
bogdanm 0:9b334a45a8ff 671 /* Disable ECC feature */
bogdanm 0:9b334a45a8ff 672 if(Bank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 Device->PCR2 &= ~FSMC_PCR2_ECCEN;
bogdanm 0:9b334a45a8ff 675 }
bogdanm 0:9b334a45a8ff 676 else
bogdanm 0:9b334a45a8ff 677 {
bogdanm 0:9b334a45a8ff 678 Device->PCR3 &= ~FSMC_PCR3_ECCEN;
bogdanm 0:9b334a45a8ff 679 }
bogdanm 0:9b334a45a8ff 680
bogdanm 0:9b334a45a8ff 681 return HAL_OK;
bogdanm 0:9b334a45a8ff 682 }
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684 /**
bogdanm 0:9b334a45a8ff 685 * @brief Disables dynamically FSMC_NAND ECC feature.
bogdanm 0:9b334a45a8ff 686 * @param Device: Pointer to NAND device instance
bogdanm 0:9b334a45a8ff 687 * @param ECCval: Pointer to ECC value
bogdanm 0:9b334a45a8ff 688 * @param Bank: NAND bank number
bogdanm 0:9b334a45a8ff 689 * @param Timeout: Timeout wait value
bogdanm 0:9b334a45a8ff 690 * @retval HAL status
bogdanm 0:9b334a45a8ff 691 */
bogdanm 0:9b334a45a8ff 692 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
bogdanm 0:9b334a45a8ff 693 {
bogdanm 0:9b334a45a8ff 694 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 695
bogdanm 0:9b334a45a8ff 696 /* Check the parameters */
bogdanm 0:9b334a45a8ff 697 assert_param(IS_FSMC_NAND_DEVICE(Device));
bogdanm 0:9b334a45a8ff 698 assert_param(IS_FSMC_NAND_BANK(Bank));
bogdanm 0:9b334a45a8ff 699
bogdanm 0:9b334a45a8ff 700 /* Get tick */
bogdanm 0:9b334a45a8ff 701 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 702
bogdanm 0:9b334a45a8ff 703 /* Wait until FIFO is empty */
bogdanm 0:9b334a45a8ff 704 while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
bogdanm 0:9b334a45a8ff 705 {
bogdanm 0:9b334a45a8ff 706 /* Check for the Timeout */
bogdanm 0:9b334a45a8ff 707 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 708 {
bogdanm 0:9b334a45a8ff 709 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
bogdanm 0:9b334a45a8ff 710 {
bogdanm 0:9b334a45a8ff 711 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 712 }
bogdanm 0:9b334a45a8ff 713 }
bogdanm 0:9b334a45a8ff 714 }
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 if(Bank == FSMC_NAND_BANK2)
bogdanm 0:9b334a45a8ff 717 {
bogdanm 0:9b334a45a8ff 718 /* Get the ECCR2 register value */
bogdanm 0:9b334a45a8ff 719 *ECCval = (uint32_t)Device->ECCR2;
bogdanm 0:9b334a45a8ff 720 }
bogdanm 0:9b334a45a8ff 721 else
bogdanm 0:9b334a45a8ff 722 {
bogdanm 0:9b334a45a8ff 723 /* Get the ECCR3 register value */
bogdanm 0:9b334a45a8ff 724 *ECCval = (uint32_t)Device->ECCR3;
bogdanm 0:9b334a45a8ff 725 }
bogdanm 0:9b334a45a8ff 726
bogdanm 0:9b334a45a8ff 727 return HAL_OK;
bogdanm 0:9b334a45a8ff 728 }
bogdanm 0:9b334a45a8ff 729
bogdanm 0:9b334a45a8ff 730 /**
bogdanm 0:9b334a45a8ff 731 * @}
bogdanm 0:9b334a45a8ff 732 */
bogdanm 0:9b334a45a8ff 733
bogdanm 0:9b334a45a8ff 734 /**
bogdanm 0:9b334a45a8ff 735 * @}
bogdanm 0:9b334a45a8ff 736 */
bogdanm 0:9b334a45a8ff 737
bogdanm 0:9b334a45a8ff 738 /** @addtogroup FSMC_LL_PCCARD
bogdanm 0:9b334a45a8ff 739 * @brief PCCARD Controller functions
bogdanm 0:9b334a45a8ff 740 *
bogdanm 0:9b334a45a8ff 741 @verbatim
bogdanm 0:9b334a45a8ff 742 ==============================================================================
bogdanm 0:9b334a45a8ff 743 ##### How to use PCCARD device driver #####
bogdanm 0:9b334a45a8ff 744 ==============================================================================
bogdanm 0:9b334a45a8ff 745 [..]
bogdanm 0:9b334a45a8ff 746 This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
bogdanm 0:9b334a45a8ff 747 to run the PCCARD/compact flash external devices.
bogdanm 0:9b334a45a8ff 748
bogdanm 0:9b334a45a8ff 749 (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
bogdanm 0:9b334a45a8ff 750 (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
bogdanm 0:9b334a45a8ff 751 (+) FSMC PCCARD bank common space timing configuration using the function
bogdanm 0:9b334a45a8ff 752 FSMC_PCCARD_CommonSpace_Timing_Init()
bogdanm 0:9b334a45a8ff 753 (+) FSMC PCCARD bank attribute space timing configuration using the function
bogdanm 0:9b334a45a8ff 754 FSMC_PCCARD_AttributeSpace_Timing_Init()
bogdanm 0:9b334a45a8ff 755 (+) FSMC PCCARD bank IO space timing configuration using the function
bogdanm 0:9b334a45a8ff 756 FSMC_PCCARD_IOSpace_Timing_Init()
bogdanm 0:9b334a45a8ff 757
bogdanm 0:9b334a45a8ff 758 @endverbatim
bogdanm 0:9b334a45a8ff 759 * @{
bogdanm 0:9b334a45a8ff 760 */
bogdanm 0:9b334a45a8ff 761
bogdanm 0:9b334a45a8ff 762 /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
bogdanm 0:9b334a45a8ff 763 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 764 *
bogdanm 0:9b334a45a8ff 765 @verbatim
bogdanm 0:9b334a45a8ff 766 ==============================================================================
bogdanm 0:9b334a45a8ff 767 ##### Initialization and de_initialization functions #####
bogdanm 0:9b334a45a8ff 768 ==============================================================================
bogdanm 0:9b334a45a8ff 769 [..]
bogdanm 0:9b334a45a8ff 770 This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 771 (+) Initialize and configure the FSMC PCCARD interface
bogdanm 0:9b334a45a8ff 772 (+) De-initialize the FSMC PCCARD interface
bogdanm 0:9b334a45a8ff 773 (+) Configure the FSMC clock and associated GPIOs
bogdanm 0:9b334a45a8ff 774
bogdanm 0:9b334a45a8ff 775 @endverbatim
bogdanm 0:9b334a45a8ff 776 * @{
bogdanm 0:9b334a45a8ff 777 */
bogdanm 0:9b334a45a8ff 778
bogdanm 0:9b334a45a8ff 779 /**
bogdanm 0:9b334a45a8ff 780 * @brief Initializes the FSMC_PCCARD device according to the specified
bogdanm 0:9b334a45a8ff 781 * control parameters in the FSMC_PCCARD_HandleTypeDef
bogdanm 0:9b334a45a8ff 782 * @param Device: Pointer to PCCARD device instance
bogdanm 0:9b334a45a8ff 783 * @param Init: Pointer to PCCARD Initialization structure
bogdanm 0:9b334a45a8ff 784 * @retval HAL status
bogdanm 0:9b334a45a8ff 785 */
bogdanm 0:9b334a45a8ff 786 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
bogdanm 0:9b334a45a8ff 787 {
bogdanm 0:9b334a45a8ff 788 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 789
bogdanm 0:9b334a45a8ff 790 /* Check the parameters */
bogdanm 0:9b334a45a8ff 791 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
bogdanm 0:9b334a45a8ff 792 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
bogdanm 0:9b334a45a8ff 793 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
bogdanm 0:9b334a45a8ff 794
bogdanm 0:9b334a45a8ff 795 /* Get PCCARD control register value */
bogdanm 0:9b334a45a8ff 796 tmpr = Device->PCR4;
bogdanm 0:9b334a45a8ff 797
bogdanm 0:9b334a45a8ff 798 /* Clear TAR, TCLR, PWAITEN and PWID bits */
bogdanm 0:9b334a45a8ff 799 tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
bogdanm 0:9b334a45a8ff 800 FSMC_PCR4_PWID));
bogdanm 0:9b334a45a8ff 801
bogdanm 0:9b334a45a8ff 802 /* Set FSMC_PCCARD device control parameters */
bogdanm 0:9b334a45a8ff 803 tmpr |= (uint32_t)(Init->Waitfeature |\
bogdanm 0:9b334a45a8ff 804 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
bogdanm 0:9b334a45a8ff 805 (Init->TCLRSetupTime << 9) |\
bogdanm 0:9b334a45a8ff 806 (Init->TARSetupTime << 13));
bogdanm 0:9b334a45a8ff 807
bogdanm 0:9b334a45a8ff 808 Device->PCR4 = tmpr;
bogdanm 0:9b334a45a8ff 809
bogdanm 0:9b334a45a8ff 810 return HAL_OK;
bogdanm 0:9b334a45a8ff 811 }
bogdanm 0:9b334a45a8ff 812
bogdanm 0:9b334a45a8ff 813 /**
bogdanm 0:9b334a45a8ff 814 * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
bogdanm 0:9b334a45a8ff 815 * parameters in the FSMC_NAND_PCC_TimingTypeDef
bogdanm 0:9b334a45a8ff 816 * @param Device: Pointer to PCCARD device instance
bogdanm 0:9b334a45a8ff 817 * @param Timing: Pointer to PCCARD timing structure
bogdanm 0:9b334a45a8ff 818 * @retval HAL status
bogdanm 0:9b334a45a8ff 819 */
bogdanm 0:9b334a45a8ff 820 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
bogdanm 0:9b334a45a8ff 821 {
bogdanm 0:9b334a45a8ff 822 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 823
bogdanm 0:9b334a45a8ff 824 /* Check the parameters */
bogdanm 0:9b334a45a8ff 825 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
bogdanm 0:9b334a45a8ff 826 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm 0:9b334a45a8ff 827 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm 0:9b334a45a8ff 828 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm 0:9b334a45a8ff 829
bogdanm 0:9b334a45a8ff 830 /* Get PCCARD common space timing register value */
bogdanm 0:9b334a45a8ff 831 tmpr = Device->PMEM4;
bogdanm 0:9b334a45a8ff 832
bogdanm 0:9b334a45a8ff 833 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
bogdanm 0:9b334a45a8ff 834 tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
bogdanm 0:9b334a45a8ff 835 FSMC_PMEM4_MEMHIZ4));
bogdanm 0:9b334a45a8ff 836 /* Set PCCARD timing parameters */
bogdanm 0:9b334a45a8ff 837 tmpr |= (uint32_t)((Timing->SetupTime |\
bogdanm 0:9b334a45a8ff 838 ((Timing->WaitSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 839 (Timing->HoldSetupTime) << 16) |\
bogdanm 0:9b334a45a8ff 840 ((Timing->HiZSetupTime) << 24));
bogdanm 0:9b334a45a8ff 841
bogdanm 0:9b334a45a8ff 842 Device->PMEM4 = tmpr;
bogdanm 0:9b334a45a8ff 843
bogdanm 0:9b334a45a8ff 844 return HAL_OK;
bogdanm 0:9b334a45a8ff 845 }
bogdanm 0:9b334a45a8ff 846
bogdanm 0:9b334a45a8ff 847 /**
bogdanm 0:9b334a45a8ff 848 * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
bogdanm 0:9b334a45a8ff 849 * parameters in the FSMC_NAND_PCC_TimingTypeDef
bogdanm 0:9b334a45a8ff 850 * @param Device: Pointer to PCCARD device instance
bogdanm 0:9b334a45a8ff 851 * @param Timing: Pointer to PCCARD timing structure
bogdanm 0:9b334a45a8ff 852 * @retval HAL status
bogdanm 0:9b334a45a8ff 853 */
bogdanm 0:9b334a45a8ff 854 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
bogdanm 0:9b334a45a8ff 855 {
bogdanm 0:9b334a45a8ff 856 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 857
bogdanm 0:9b334a45a8ff 858 /* Check the parameters */
bogdanm 0:9b334a45a8ff 859 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
bogdanm 0:9b334a45a8ff 860 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm 0:9b334a45a8ff 861 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm 0:9b334a45a8ff 862 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm 0:9b334a45a8ff 863
bogdanm 0:9b334a45a8ff 864 /* Get PCCARD timing parameters */
bogdanm 0:9b334a45a8ff 865 tmpr = Device->PATT4;
bogdanm 0:9b334a45a8ff 866
bogdanm 0:9b334a45a8ff 867 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
bogdanm 0:9b334a45a8ff 868 tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
bogdanm 0:9b334a45a8ff 869 FSMC_PATT4_ATTHIZ4));
bogdanm 0:9b334a45a8ff 870
bogdanm 0:9b334a45a8ff 871 /* Set PCCARD timing parameters */
bogdanm 0:9b334a45a8ff 872 tmpr |= (uint32_t)(Timing->SetupTime |\
bogdanm 0:9b334a45a8ff 873 ((Timing->WaitSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 874 ((Timing->HoldSetupTime) << 16) |\
bogdanm 0:9b334a45a8ff 875 ((Timing->HiZSetupTime) << 24));
bogdanm 0:9b334a45a8ff 876 Device->PATT4 = tmpr;
bogdanm 0:9b334a45a8ff 877
bogdanm 0:9b334a45a8ff 878 return HAL_OK;
bogdanm 0:9b334a45a8ff 879 }
bogdanm 0:9b334a45a8ff 880
bogdanm 0:9b334a45a8ff 881 /**
bogdanm 0:9b334a45a8ff 882 * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
bogdanm 0:9b334a45a8ff 883 * parameters in the FSMC_NAND_PCC_TimingTypeDef
bogdanm 0:9b334a45a8ff 884 * @param Device: Pointer to PCCARD device instance
bogdanm 0:9b334a45a8ff 885 * @param Timing: Pointer to PCCARD timing structure
bogdanm 0:9b334a45a8ff 886 * @retval HAL status
bogdanm 0:9b334a45a8ff 887 */
bogdanm 0:9b334a45a8ff 888 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
bogdanm 0:9b334a45a8ff 889 {
bogdanm 0:9b334a45a8ff 890 uint32_t tmpr = 0;
bogdanm 0:9b334a45a8ff 891
bogdanm 0:9b334a45a8ff 892 /* Check the parameters */
bogdanm 0:9b334a45a8ff 893 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
bogdanm 0:9b334a45a8ff 894 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
bogdanm 0:9b334a45a8ff 895 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
bogdanm 0:9b334a45a8ff 896 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
bogdanm 0:9b334a45a8ff 897
bogdanm 0:9b334a45a8ff 898 /* Get FSMC_PCCARD device timing parameters */
bogdanm 0:9b334a45a8ff 899 tmpr = Device->PIO4;
bogdanm 0:9b334a45a8ff 900
bogdanm 0:9b334a45a8ff 901 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
bogdanm 0:9b334a45a8ff 902 tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
bogdanm 0:9b334a45a8ff 903 FSMC_PIO4_IOHIZ4));
bogdanm 0:9b334a45a8ff 904
bogdanm 0:9b334a45a8ff 905 /* Set FSMC_PCCARD device timing parameters */
bogdanm 0:9b334a45a8ff 906 tmpr |= (uint32_t)(Timing->SetupTime |\
bogdanm 0:9b334a45a8ff 907 ((Timing->WaitSetupTime) << 8) |\
bogdanm 0:9b334a45a8ff 908 ((Timing->HoldSetupTime) << 16) |\
bogdanm 0:9b334a45a8ff 909 ((Timing->HiZSetupTime) << 24));
bogdanm 0:9b334a45a8ff 910
bogdanm 0:9b334a45a8ff 911 Device->PIO4 = tmpr;
bogdanm 0:9b334a45a8ff 912
bogdanm 0:9b334a45a8ff 913 return HAL_OK;
bogdanm 0:9b334a45a8ff 914 }
bogdanm 0:9b334a45a8ff 915
bogdanm 0:9b334a45a8ff 916 /**
bogdanm 0:9b334a45a8ff 917 * @brief DeInitializes the FSMC_PCCARD device
bogdanm 0:9b334a45a8ff 918 * @param Device: Pointer to PCCARD device instance
bogdanm 0:9b334a45a8ff 919 * @retval HAL status
bogdanm 0:9b334a45a8ff 920 */
bogdanm 0:9b334a45a8ff 921 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
bogdanm 0:9b334a45a8ff 922 {
bogdanm 0:9b334a45a8ff 923 /* Disable the FSMC_PCCARD device */
bogdanm 0:9b334a45a8ff 924 __FSMC_PCCARD_DISABLE(Device);
bogdanm 0:9b334a45a8ff 925
bogdanm 0:9b334a45a8ff 926 /* De-initialize the FSMC_PCCARD device */
bogdanm 0:9b334a45a8ff 927 Device->PCR4 = 0x00000018;
bogdanm 0:9b334a45a8ff 928 Device->SR4 = 0x00000000;
bogdanm 0:9b334a45a8ff 929 Device->PMEM4 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 930 Device->PATT4 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 931 Device->PIO4 = 0xFCFCFCFC;
bogdanm 0:9b334a45a8ff 932
bogdanm 0:9b334a45a8ff 933 return HAL_OK;
bogdanm 0:9b334a45a8ff 934 }
bogdanm 0:9b334a45a8ff 935 /**
bogdanm 0:9b334a45a8ff 936 * @}
bogdanm 0:9b334a45a8ff 937 */
bogdanm 0:9b334a45a8ff 938
bogdanm 0:9b334a45a8ff 939 /**
bogdanm 0:9b334a45a8ff 940 * @}
bogdanm 0:9b334a45a8ff 941 */
mbed_official 19:112740acecfa 942 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 0:9b334a45a8ff 943
bogdanm 0:9b334a45a8ff 944 /**
bogdanm 0:9b334a45a8ff 945 * @}
bogdanm 0:9b334a45a8ff 946 */
mbed_official 19:112740acecfa 947 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 0:9b334a45a8ff 948 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 949
bogdanm 0:9b334a45a8ff 950 /**
bogdanm 0:9b334a45a8ff 951 * @}
bogdanm 0:9b334a45a8ff 952 */
bogdanm 0:9b334a45a8ff 953
bogdanm 0:9b334a45a8ff 954 /**
bogdanm 0:9b334a45a8ff 955 * @}
bogdanm 0:9b334a45a8ff 956 */
bogdanm 0:9b334a45a8ff 957 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/