mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 19:112740acecfa

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f4xx_ll_fmc.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	19:112740acecfa	5	* @version V1.4.1
mbed_official	19:112740acecfa	6	* @date 09-October-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of FMC HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F4xx_LL_FMC_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F4xx_LL_FMC_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32f4xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup FMC_LL
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
mbed_official	19:112740acecfa	56	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
mbed_official	19:112740acecfa	57	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	0:9b334a45a8ff	58	/* Private types -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	59	/** @defgroup FMC_LL_Private_Types FMC Private Types
bogdanm	0:9b334a45a8ff	60	* @{
bogdanm	0:9b334a45a8ff	61	*/
bogdanm	0:9b334a45a8ff	62
bogdanm	0:9b334a45a8ff	63	/**
bogdanm	0:9b334a45a8ff	64	* @brief FMC NORSRAM Configuration Structure definition
bogdanm	0:9b334a45a8ff	65	*/
bogdanm	0:9b334a45a8ff	66	typedef struct
bogdanm	0:9b334a45a8ff	67	{
bogdanm	0:9b334a45a8ff	68	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm	0:9b334a45a8ff	69	This parameter can be a value of @ref FMC_NORSRAM_Bank */
bogdanm	0:9b334a45a8ff	70
bogdanm	0:9b334a45a8ff	71	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm	0:9b334a45a8ff	72	multiplexed on the data bus or not.
bogdanm	0:9b334a45a8ff	73	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
bogdanm	0:9b334a45a8ff	74
bogdanm	0:9b334a45a8ff	75	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm	0:9b334a45a8ff	76	the corresponding memory device.
bogdanm	0:9b334a45a8ff	77	This parameter can be a value of @ref FMC_Memory_Type */
bogdanm	0:9b334a45a8ff	78
bogdanm	0:9b334a45a8ff	79	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm	0:9b334a45a8ff	80	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
bogdanm	0:9b334a45a8ff	81
bogdanm	0:9b334a45a8ff	82	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm	0:9b334a45a8ff	83	valid only with synchronous burst Flash memories.
bogdanm	0:9b334a45a8ff	84	This parameter can be a value of @ref FMC_Burst_Access_Mode */
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm	0:9b334a45a8ff	87	the Flash memory in burst mode.
bogdanm	0:9b334a45a8ff	88	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
bogdanm	0:9b334a45a8ff	89
bogdanm	0:9b334a45a8ff	90	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm	0:9b334a45a8ff	91	memory, valid only when accessing Flash memories in burst mode.
bogdanm	0:9b334a45a8ff	92	This parameter can be a value of @ref FMC_Wrap_Mode
mbed_official	19:112740acecfa	93	This mode is not available for the STM32F446/467/479xx devices */
bogdanm	0:9b334a45a8ff	94
bogdanm	0:9b334a45a8ff	95	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm	0:9b334a45a8ff	96	clock cycle before the wait state or during the wait state,
bogdanm	0:9b334a45a8ff	97	valid only when accessing memories in burst mode.
bogdanm	0:9b334a45a8ff	98	This parameter can be a value of @ref FMC_Wait_Timing */
bogdanm	0:9b334a45a8ff	99
bogdanm	0:9b334a45a8ff	100	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
bogdanm	0:9b334a45a8ff	101	This parameter can be a value of @ref FMC_Write_Operation */
bogdanm	0:9b334a45a8ff	102
bogdanm	0:9b334a45a8ff	103	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
bogdanm	0:9b334a45a8ff	104	signal, valid for Flash memory access in burst mode.
bogdanm	0:9b334a45a8ff	105	This parameter can be a value of @ref FMC_Wait_Signal */
bogdanm	0:9b334a45a8ff	106
bogdanm	0:9b334a45a8ff	107	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm	0:9b334a45a8ff	108	This parameter can be a value of @ref FMC_Extended_Mode */
bogdanm	0:9b334a45a8ff	109
bogdanm	0:9b334a45a8ff	110	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm	0:9b334a45a8ff	111	valid only with asynchronous Flash memories.
bogdanm	0:9b334a45a8ff	112	This parameter can be a value of @ref FMC_AsynchronousWait */
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm	0:9b334a45a8ff	115	This parameter can be a value of @ref FMC_Write_Burst */
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
bogdanm	0:9b334a45a8ff	118	This parameter is only enabled through the FMC_BCR1 register, and don't care
bogdanm	0:9b334a45a8ff	119	through FMC_BCR2..4 registers.
bogdanm	0:9b334a45a8ff	120	This parameter can be a value of @ref FMC_Continous_Clock */
bogdanm	0:9b334a45a8ff	121
bogdanm	0:9b334a45a8ff	122	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
bogdanm	0:9b334a45a8ff	123	This parameter is only enabled through the FMC_BCR1 register, and don't care
bogdanm	0:9b334a45a8ff	124	through FMC_BCR2..4 registers.
bogdanm	0:9b334a45a8ff	125	This parameter can be a value of @ref FMC_Write_FIFO
mbed_official	19:112740acecfa	126	This mode is available only for the STM32F446/469/479xx devices */
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	uint32_t PageSize; /*!< Specifies the memory page size.
bogdanm	0:9b334a45a8ff	129	This parameter can be a value of @ref FMC_Page_Size
bogdanm	0:9b334a45a8ff	130	This mode is available only for the STM32F446xx devices */
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132	}FMC_NORSRAM_InitTypeDef;
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	/**
bogdanm	0:9b334a45a8ff	135	* @brief FMC NORSRAM Timing parameters structure definition
bogdanm	0:9b334a45a8ff	136	*/
bogdanm	0:9b334a45a8ff	137	typedef struct
bogdanm	0:9b334a45a8ff	138	{
bogdanm	0:9b334a45a8ff	139	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	0:9b334a45a8ff	140	the duration of the address setup time.
bogdanm	0:9b334a45a8ff	141	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	142	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	0:9b334a45a8ff	143
bogdanm	0:9b334a45a8ff	144	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	0:9b334a45a8ff	145	the duration of the address hold time.
bogdanm	0:9b334a45a8ff	146	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	147	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	0:9b334a45a8ff	148
bogdanm	0:9b334a45a8ff	149	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	0:9b334a45a8ff	150	the duration of the data setup time.
bogdanm	0:9b334a45a8ff	151	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
bogdanm	0:9b334a45a8ff	152	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm	0:9b334a45a8ff	153	NOR Flash memories. */
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm	0:9b334a45a8ff	156	the duration of the bus turnaround.
bogdanm	0:9b334a45a8ff	157	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm	0:9b334a45a8ff	158	@note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm	0:9b334a45a8ff	159
bogdanm	0:9b334a45a8ff	160	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm	0:9b334a45a8ff	161	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
bogdanm	0:9b334a45a8ff	162	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm	0:9b334a45a8ff	163	accesses. */
bogdanm	0:9b334a45a8ff	164
bogdanm	0:9b334a45a8ff	165	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm	0:9b334a45a8ff	166	to the memory before getting the first data.
bogdanm	0:9b334a45a8ff	167	The parameter value depends on the memory type as shown below:
bogdanm	0:9b334a45a8ff	168	- It must be set to 0 in case of a CRAM
bogdanm	0:9b334a45a8ff	169	- It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm	0:9b334a45a8ff	170	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm	0:9b334a45a8ff	171	with synchronous burst mode enable */
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm	0:9b334a45a8ff	174	This parameter can be a value of @ref FMC_Access_Mode */
bogdanm	0:9b334a45a8ff	175	}FMC_NORSRAM_TimingTypeDef;
bogdanm	0:9b334a45a8ff	176
bogdanm	0:9b334a45a8ff	177	/**
bogdanm	0:9b334a45a8ff	178	* @brief FMC NAND Configuration Structure definition
bogdanm	0:9b334a45a8ff	179	*/
bogdanm	0:9b334a45a8ff	180	typedef struct
bogdanm	0:9b334a45a8ff	181	{
bogdanm	0:9b334a45a8ff	182	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm	0:9b334a45a8ff	183	This parameter can be a value of @ref FMC_NAND_Bank */
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
bogdanm	0:9b334a45a8ff	186	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	0:9b334a45a8ff	187
bogdanm	0:9b334a45a8ff	188	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm	0:9b334a45a8ff	189	This parameter can be any value of @ref FMC_NAND_Data_Width */
bogdanm	0:9b334a45a8ff	190
bogdanm	0:9b334a45a8ff	191	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
bogdanm	0:9b334a45a8ff	192	This parameter can be any value of @ref FMC_ECC */
bogdanm	0:9b334a45a8ff	193
bogdanm	0:9b334a45a8ff	194	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm	0:9b334a45a8ff	195	This parameter can be any value of @ref FMC_ECC_Page_Size */
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	0:9b334a45a8ff	198	delay between CLE low and RE low.
bogdanm	0:9b334a45a8ff	199	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	0:9b334a45a8ff	202	delay between ALE low and RE low.
bogdanm	0:9b334a45a8ff	203	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	0:9b334a45a8ff	204	}FMC_NAND_InitTypeDef;
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	/**
bogdanm	0:9b334a45a8ff	207	* @brief FMC NAND/PCCARD Timing parameters structure definition
bogdanm	0:9b334a45a8ff	208	*/
bogdanm	0:9b334a45a8ff	209	typedef struct
bogdanm	0:9b334a45a8ff	210	{
bogdanm	0:9b334a45a8ff	211	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm	0:9b334a45a8ff	212	the command assertion for NAND-Flash read or write access
bogdanm	0:9b334a45a8ff	213	to common/Attribute or I/O memory space (depending on
bogdanm	0:9b334a45a8ff	214	the memory space timing to be configured).
bogdanm	0:9b334a45a8ff	215	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	0:9b334a45a8ff	216
bogdanm	0:9b334a45a8ff	217	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm	0:9b334a45a8ff	218	command for NAND-Flash read or write access to
bogdanm	0:9b334a45a8ff	219	common/Attribute or I/O memory space (depending on the
bogdanm	0:9b334a45a8ff	220	memory space timing to be configured).
bogdanm	0:9b334a45a8ff	221	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm	0:9b334a45a8ff	224	(and data for write access) after the command de-assertion
bogdanm	0:9b334a45a8ff	225	for NAND-Flash read or write access to common/Attribute
bogdanm	0:9b334a45a8ff	226	or I/O memory space (depending on the memory space timing
bogdanm	0:9b334a45a8ff	227	to be configured).
bogdanm	0:9b334a45a8ff	228	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	0:9b334a45a8ff	229
bogdanm	0:9b334a45a8ff	230	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm	0:9b334a45a8ff	231	data bus is kept in HiZ after the start of a NAND-Flash
bogdanm	0:9b334a45a8ff	232	write access to common/Attribute or I/O memory space (depending
bogdanm	0:9b334a45a8ff	233	on the memory space timing to be configured).
bogdanm	0:9b334a45a8ff	234	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	0:9b334a45a8ff	235	}FMC_NAND_PCC_TimingTypeDef;
bogdanm	0:9b334a45a8ff	236
bogdanm	0:9b334a45a8ff	237	/**
bogdanm	0:9b334a45a8ff	238	* @brief FMC NAND Configuration Structure definition
bogdanm	0:9b334a45a8ff	239	*/
bogdanm	0:9b334a45a8ff	240	typedef struct
bogdanm	0:9b334a45a8ff	241	{
bogdanm	0:9b334a45a8ff	242	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
bogdanm	0:9b334a45a8ff	243	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	0:9b334a45a8ff	246	delay between CLE low and RE low.
bogdanm	0:9b334a45a8ff	247	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	0:9b334a45a8ff	248
bogdanm	0:9b334a45a8ff	249	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	0:9b334a45a8ff	250	delay between ALE low and RE low.
bogdanm	0:9b334a45a8ff	251	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	0:9b334a45a8ff	252	}FMC_PCCARD_InitTypeDef;
bogdanm	0:9b334a45a8ff	253
bogdanm	0:9b334a45a8ff	254	/**
bogdanm	0:9b334a45a8ff	255	* @brief FMC SDRAM Configuration Structure definition
bogdanm	0:9b334a45a8ff	256	*/
bogdanm	0:9b334a45a8ff	257	typedef struct
bogdanm	0:9b334a45a8ff	258	{
bogdanm	0:9b334a45a8ff	259	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
bogdanm	0:9b334a45a8ff	260	This parameter can be a value of @ref FMC_SDRAM_Bank */
bogdanm	0:9b334a45a8ff	261
bogdanm	0:9b334a45a8ff	262	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
bogdanm	0:9b334a45a8ff	263	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
bogdanm	0:9b334a45a8ff	264
bogdanm	0:9b334a45a8ff	265	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
bogdanm	0:9b334a45a8ff	266	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
bogdanm	0:9b334a45a8ff	269	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
bogdanm	0:9b334a45a8ff	270
bogdanm	0:9b334a45a8ff	271	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
bogdanm	0:9b334a45a8ff	272	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
bogdanm	0:9b334a45a8ff	273
bogdanm	0:9b334a45a8ff	274	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
bogdanm	0:9b334a45a8ff	275	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
bogdanm	0:9b334a45a8ff	276
bogdanm	0:9b334a45a8ff	277	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
bogdanm	0:9b334a45a8ff	278	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
bogdanm	0:9b334a45a8ff	279
bogdanm	0:9b334a45a8ff	280	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
bogdanm	0:9b334a45a8ff	281	to disable the clock before changing frequency.
bogdanm	0:9b334a45a8ff	282	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
bogdanm	0:9b334a45a8ff	285	commands during the CAS latency and stores data in the Read FIFO.
bogdanm	0:9b334a45a8ff	286	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
bogdanm	0:9b334a45a8ff	289	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
bogdanm	0:9b334a45a8ff	290	}FMC_SDRAM_InitTypeDef;
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/**
bogdanm	0:9b334a45a8ff	293	* @brief FMC SDRAM Timing parameters structure definition
bogdanm	0:9b334a45a8ff	294	*/
bogdanm	0:9b334a45a8ff	295	typedef struct
bogdanm	0:9b334a45a8ff	296	{
bogdanm	0:9b334a45a8ff	297	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
bogdanm	0:9b334a45a8ff	298	an active or Refresh command in number of memory clock cycles.
bogdanm	0:9b334a45a8ff	299	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	0:9b334a45a8ff	300
bogdanm	0:9b334a45a8ff	301	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
bogdanm	0:9b334a45a8ff	302	issuing the Activate command in number of memory clock cycles.
bogdanm	0:9b334a45a8ff	303	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	0:9b334a45a8ff	304
bogdanm	0:9b334a45a8ff	305	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
bogdanm	0:9b334a45a8ff	306	cycles.
bogdanm	0:9b334a45a8ff	307	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	0:9b334a45a8ff	308
bogdanm	0:9b334a45a8ff	309	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
bogdanm	0:9b334a45a8ff	310	and the delay between two consecutive Refresh commands in number of
bogdanm	0:9b334a45a8ff	311	memory clock cycles.
bogdanm	0:9b334a45a8ff	312	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	0:9b334a45a8ff	313
bogdanm	0:9b334a45a8ff	314	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
bogdanm	0:9b334a45a8ff	315	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	0:9b334a45a8ff	316
bogdanm	0:9b334a45a8ff	317	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
bogdanm	0:9b334a45a8ff	318	in number of memory clock cycles.
bogdanm	0:9b334a45a8ff	319	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
bogdanm	0:9b334a45a8ff	322	command in number of memory clock cycles.
bogdanm	0:9b334a45a8ff	323	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	0:9b334a45a8ff	324	}FMC_SDRAM_TimingTypeDef;
bogdanm	0:9b334a45a8ff	325
bogdanm	0:9b334a45a8ff	326	/**
bogdanm	0:9b334a45a8ff	327	* @brief SDRAM command parameters structure definition
bogdanm	0:9b334a45a8ff	328	*/
bogdanm	0:9b334a45a8ff	329	typedef struct
bogdanm	0:9b334a45a8ff	330	{
bogdanm	0:9b334a45a8ff	331	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
bogdanm	0:9b334a45a8ff	332	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
bogdanm	0:9b334a45a8ff	333
bogdanm	0:9b334a45a8ff	334	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
bogdanm	0:9b334a45a8ff	335	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
bogdanm	0:9b334a45a8ff	338	in auto refresh mode.
bogdanm	0:9b334a45a8ff	339	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	0:9b334a45a8ff	340	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
bogdanm	0:9b334a45a8ff	341	}FMC_SDRAM_CommandTypeDef;
bogdanm	0:9b334a45a8ff	342	/**
bogdanm	0:9b334a45a8ff	343	* @}
bogdanm	0:9b334a45a8ff	344	*/
bogdanm	0:9b334a45a8ff	345
bogdanm	0:9b334a45a8ff	346	/* Private constants ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	347	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
bogdanm	0:9b334a45a8ff	348	* @{
bogdanm	0:9b334a45a8ff	349	*/
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
bogdanm	0:9b334a45a8ff	352	* @{
bogdanm	0:9b334a45a8ff	353	*/
bogdanm	0:9b334a45a8ff	354	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
bogdanm	0:9b334a45a8ff	355	* @{
bogdanm	0:9b334a45a8ff	356	*/
bogdanm	0:9b334a45a8ff	357	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	358	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	359	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	360	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
bogdanm	0:9b334a45a8ff	361	/**
bogdanm	0:9b334a45a8ff	362	* @}
bogdanm	0:9b334a45a8ff	363	*/
bogdanm	0:9b334a45a8ff	364
bogdanm	0:9b334a45a8ff	365	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
bogdanm	0:9b334a45a8ff	366	* @{
bogdanm	0:9b334a45a8ff	367	*/
bogdanm	0:9b334a45a8ff	368	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	369	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	370	/**
bogdanm	0:9b334a45a8ff	371	* @}
bogdanm	0:9b334a45a8ff	372	*/
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/** @defgroup FMC_Memory_Type FMC Memory Type
bogdanm	0:9b334a45a8ff	375	* @{
bogdanm	0:9b334a45a8ff	376	*/
bogdanm	0:9b334a45a8ff	377	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	378	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	379	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	380	/**
bogdanm	0:9b334a45a8ff	381	* @}
bogdanm	0:9b334a45a8ff	382	*/
bogdanm	0:9b334a45a8ff	383
bogdanm	0:9b334a45a8ff	384	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
bogdanm	0:9b334a45a8ff	385	* @{
bogdanm	0:9b334a45a8ff	386	*/
bogdanm	0:9b334a45a8ff	387	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	388	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	389	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	390	/**
bogdanm	0:9b334a45a8ff	391	* @}
bogdanm	0:9b334a45a8ff	392	*/
bogdanm	0:9b334a45a8ff	393
bogdanm	0:9b334a45a8ff	394	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
bogdanm	0:9b334a45a8ff	395	* @{
bogdanm	0:9b334a45a8ff	396	*/
bogdanm	0:9b334a45a8ff	397	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	398	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	399	/**
bogdanm	0:9b334a45a8ff	400	* @}
bogdanm	0:9b334a45a8ff	401	*/
bogdanm	0:9b334a45a8ff	402
bogdanm	0:9b334a45a8ff	403	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
bogdanm	0:9b334a45a8ff	404	* @{
bogdanm	0:9b334a45a8ff	405	*/
bogdanm	0:9b334a45a8ff	406	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	407	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	408	/**
bogdanm	0:9b334a45a8ff	409	* @}
bogdanm	0:9b334a45a8ff	410	*/
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
bogdanm	0:9b334a45a8ff	413	* @{
bogdanm	0:9b334a45a8ff	414	*/
bogdanm	0:9b334a45a8ff	415	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	416	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	417	/**
bogdanm	0:9b334a45a8ff	418	* @}
bogdanm	0:9b334a45a8ff	419	*/
bogdanm	0:9b334a45a8ff	420
bogdanm	0:9b334a45a8ff	421	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
bogdanm	0:9b334a45a8ff	422	* @{
bogdanm	0:9b334a45a8ff	423	*/
mbed_official	19:112740acecfa	424	/** @note This mode is not available for the STM32F446/469/479xx devices
bogdanm	0:9b334a45a8ff	425	*/
bogdanm	0:9b334a45a8ff	426	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	427	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	428	/**
bogdanm	0:9b334a45a8ff	429	* @}
bogdanm	0:9b334a45a8ff	430	*/
bogdanm	0:9b334a45a8ff	431
bogdanm	0:9b334a45a8ff	432	/** @defgroup FMC_Wait_Timing FMC Wait Timing
bogdanm	0:9b334a45a8ff	433	* @{
bogdanm	0:9b334a45a8ff	434	*/
bogdanm	0:9b334a45a8ff	435	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	436	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	437	/**
bogdanm	0:9b334a45a8ff	438	* @}
bogdanm	0:9b334a45a8ff	439	*/
bogdanm	0:9b334a45a8ff	440
bogdanm	0:9b334a45a8ff	441	/** @defgroup FMC_Write_Operation FMC Write Operation
bogdanm	0:9b334a45a8ff	442	* @{
bogdanm	0:9b334a45a8ff	443	*/
bogdanm	0:9b334a45a8ff	444	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	445	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	446	/**
bogdanm	0:9b334a45a8ff	447	* @}
bogdanm	0:9b334a45a8ff	448	*/
bogdanm	0:9b334a45a8ff	449
bogdanm	0:9b334a45a8ff	450	/** @defgroup FMC_Wait_Signal FMC Wait Signal
bogdanm	0:9b334a45a8ff	451	* @{
bogdanm	0:9b334a45a8ff	452	*/
bogdanm	0:9b334a45a8ff	453	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	454	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	455	/**
bogdanm	0:9b334a45a8ff	456	* @}
bogdanm	0:9b334a45a8ff	457	*/
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	/** @defgroup FMC_Extended_Mode FMC Extended Mode
bogdanm	0:9b334a45a8ff	460	* @{
bogdanm	0:9b334a45a8ff	461	*/
bogdanm	0:9b334a45a8ff	462	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	463	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	464	/**
bogdanm	0:9b334a45a8ff	465	* @}
bogdanm	0:9b334a45a8ff	466	*/
bogdanm	0:9b334a45a8ff	467
bogdanm	0:9b334a45a8ff	468	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
bogdanm	0:9b334a45a8ff	469	* @{
bogdanm	0:9b334a45a8ff	470	*/
bogdanm	0:9b334a45a8ff	471	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	472	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
bogdanm	0:9b334a45a8ff	473	/**
bogdanm	0:9b334a45a8ff	474	* @}
bogdanm	0:9b334a45a8ff	475	*/
bogdanm	0:9b334a45a8ff	476
bogdanm	0:9b334a45a8ff	477	/** @defgroup FMC_Page_Size FMC Page Size
mbed_official	19:112740acecfa	478	* @note These values are available only for the STM32F446/469/479xx devices.
bogdanm	0:9b334a45a8ff	479	* @{
bogdanm	0:9b334a45a8ff	480	*/
bogdanm	0:9b334a45a8ff	481	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	482	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
bogdanm	0:9b334a45a8ff	483	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
bogdanm	0:9b334a45a8ff	484	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
bogdanm	0:9b334a45a8ff	485	/**
bogdanm	0:9b334a45a8ff	486	* @}
bogdanm	0:9b334a45a8ff	487	*/
bogdanm	0:9b334a45a8ff	488
bogdanm	0:9b334a45a8ff	489	/** @defgroup FMC_Write_FIFO FMC Write FIFO
mbed_official	19:112740acecfa	490	* @note These values are available only for the STM32F446/469/479xx devices.
bogdanm	0:9b334a45a8ff	491	* @{
bogdanm	0:9b334a45a8ff	492	*/
bogdanm	0:9b334a45a8ff	493	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	494	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
bogdanm	0:9b334a45a8ff	495	/**
bogdanm	0:9b334a45a8ff	496	* @}
bogdanm	0:9b334a45a8ff	497	*/
bogdanm	0:9b334a45a8ff	498
bogdanm	0:9b334a45a8ff	499	/** @defgroup FMC_Write_Burst FMC Write Burst
bogdanm	0:9b334a45a8ff	500	* @{
bogdanm	0:9b334a45a8ff	501	*/
bogdanm	0:9b334a45a8ff	502	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	503	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	504	/**
bogdanm	0:9b334a45a8ff	505	* @}
bogdanm	0:9b334a45a8ff	506	*/
bogdanm	0:9b334a45a8ff	507
bogdanm	0:9b334a45a8ff	508	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
bogdanm	0:9b334a45a8ff	509	* @{
bogdanm	0:9b334a45a8ff	510	*/
bogdanm	0:9b334a45a8ff	511	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	512	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
bogdanm	0:9b334a45a8ff	513	/**
bogdanm	0:9b334a45a8ff	514	* @}
bogdanm	0:9b334a45a8ff	515	*/
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	/** @defgroup FMC_Access_Mode FMC Access Mode
bogdanm	0:9b334a45a8ff	518	* @{
bogdanm	0:9b334a45a8ff	519	*/
bogdanm	0:9b334a45a8ff	520	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	521	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	522	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	523	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	524	/**
bogdanm	0:9b334a45a8ff	525	* @}
bogdanm	0:9b334a45a8ff	526	*/
bogdanm	0:9b334a45a8ff	527
bogdanm	0:9b334a45a8ff	528	/**
bogdanm	0:9b334a45a8ff	529	* @}
bogdanm	0:9b334a45a8ff	530	*/
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
bogdanm	0:9b334a45a8ff	533	* @{
bogdanm	0:9b334a45a8ff	534	*/
bogdanm	0:9b334a45a8ff	535	/** @defgroup FMC_NAND_Bank FMC NAND Bank
bogdanm	0:9b334a45a8ff	536	* @{
bogdanm	0:9b334a45a8ff	537	*/
bogdanm	0:9b334a45a8ff	538	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	539	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	540	/**
bogdanm	0:9b334a45a8ff	541	* @}
bogdanm	0:9b334a45a8ff	542	*/
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	/** @defgroup FMC_Wait_feature FMC Wait feature
bogdanm	0:9b334a45a8ff	545	* @{
bogdanm	0:9b334a45a8ff	546	*/
bogdanm	0:9b334a45a8ff	547	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	548	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	549	/**
bogdanm	0:9b334a45a8ff	550	* @}
bogdanm	0:9b334a45a8ff	551	*/
bogdanm	0:9b334a45a8ff	552
bogdanm	0:9b334a45a8ff	553	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
bogdanm	0:9b334a45a8ff	554	* @{
bogdanm	0:9b334a45a8ff	555	*/
bogdanm	0:9b334a45a8ff	556	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	557	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	558	/**
bogdanm	0:9b334a45a8ff	559	* @}
bogdanm	0:9b334a45a8ff	560	*/
bogdanm	0:9b334a45a8ff	561
bogdanm	0:9b334a45a8ff	562	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
bogdanm	0:9b334a45a8ff	563	* @{
bogdanm	0:9b334a45a8ff	564	*/
bogdanm	0:9b334a45a8ff	565	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	566	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	567	/**
bogdanm	0:9b334a45a8ff	568	* @}
bogdanm	0:9b334a45a8ff	569	*/
bogdanm	0:9b334a45a8ff	570
bogdanm	0:9b334a45a8ff	571	/** @defgroup FMC_ECC FMC ECC
bogdanm	0:9b334a45a8ff	572	* @{
bogdanm	0:9b334a45a8ff	573	*/
bogdanm	0:9b334a45a8ff	574	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	575	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	576	/**
bogdanm	0:9b334a45a8ff	577	* @}
bogdanm	0:9b334a45a8ff	578	*/
bogdanm	0:9b334a45a8ff	579
bogdanm	0:9b334a45a8ff	580	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
bogdanm	0:9b334a45a8ff	581	* @{
bogdanm	0:9b334a45a8ff	582	*/
bogdanm	0:9b334a45a8ff	583	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	584	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	585	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	586	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
bogdanm	0:9b334a45a8ff	587	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
bogdanm	0:9b334a45a8ff	588	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
bogdanm	0:9b334a45a8ff	589	/**
bogdanm	0:9b334a45a8ff	590	* @}
bogdanm	0:9b334a45a8ff	591	*/
bogdanm	0:9b334a45a8ff	592
bogdanm	0:9b334a45a8ff	593	/**
bogdanm	0:9b334a45a8ff	594	* @}
bogdanm	0:9b334a45a8ff	595	*/
bogdanm	0:9b334a45a8ff	596
bogdanm	0:9b334a45a8ff	597	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
bogdanm	0:9b334a45a8ff	598	* @{
bogdanm	0:9b334a45a8ff	599	*/
bogdanm	0:9b334a45a8ff	600	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
bogdanm	0:9b334a45a8ff	601	* @{
bogdanm	0:9b334a45a8ff	602	*/
bogdanm	0:9b334a45a8ff	603	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	604	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	605	/**
bogdanm	0:9b334a45a8ff	606	* @}
bogdanm	0:9b334a45a8ff	607	*/
bogdanm	0:9b334a45a8ff	608
bogdanm	0:9b334a45a8ff	609	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
bogdanm	0:9b334a45a8ff	610	* @{
bogdanm	0:9b334a45a8ff	611	*/
bogdanm	0:9b334a45a8ff	612	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	613	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	614	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	615	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	616	/**
bogdanm	0:9b334a45a8ff	617	* @}
bogdanm	0:9b334a45a8ff	618	*/
bogdanm	0:9b334a45a8ff	619
bogdanm	0:9b334a45a8ff	620	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
bogdanm	0:9b334a45a8ff	621	* @{
bogdanm	0:9b334a45a8ff	622	*/
bogdanm	0:9b334a45a8ff	623	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	624	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	625	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	626	/**
bogdanm	0:9b334a45a8ff	627	* @}
bogdanm	0:9b334a45a8ff	628	*/
bogdanm	0:9b334a45a8ff	629
bogdanm	0:9b334a45a8ff	630	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
bogdanm	0:9b334a45a8ff	631	* @{
bogdanm	0:9b334a45a8ff	632	*/
bogdanm	0:9b334a45a8ff	633	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	634	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	635	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	636	/**
bogdanm	0:9b334a45a8ff	637	* @}
bogdanm	0:9b334a45a8ff	638	*/
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
bogdanm	0:9b334a45a8ff	641	* @{
bogdanm	0:9b334a45a8ff	642	*/
bogdanm	0:9b334a45a8ff	643	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	644	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	645	/**
bogdanm	0:9b334a45a8ff	646	* @}
bogdanm	0:9b334a45a8ff	647	*/
bogdanm	0:9b334a45a8ff	648
bogdanm	0:9b334a45a8ff	649	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
bogdanm	0:9b334a45a8ff	650	* @{
bogdanm	0:9b334a45a8ff	651	*/
bogdanm	0:9b334a45a8ff	652	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	653	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	654	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
bogdanm	0:9b334a45a8ff	655	/**
bogdanm	0:9b334a45a8ff	656	* @}
bogdanm	0:9b334a45a8ff	657	*/
bogdanm	0:9b334a45a8ff	658
bogdanm	0:9b334a45a8ff	659	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
bogdanm	0:9b334a45a8ff	660	* @{
bogdanm	0:9b334a45a8ff	661	*/
bogdanm	0:9b334a45a8ff	662	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	663	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
bogdanm	0:9b334a45a8ff	664
bogdanm	0:9b334a45a8ff	665	/**
bogdanm	0:9b334a45a8ff	666	* @}
bogdanm	0:9b334a45a8ff	667	*/
bogdanm	0:9b334a45a8ff	668
bogdanm	0:9b334a45a8ff	669	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
bogdanm	0:9b334a45a8ff	670	* @{
bogdanm	0:9b334a45a8ff	671	*/
bogdanm	0:9b334a45a8ff	672	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	673	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	674	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
bogdanm	0:9b334a45a8ff	675	/**
bogdanm	0:9b334a45a8ff	676	* @}
bogdanm	0:9b334a45a8ff	677	*/
bogdanm	0:9b334a45a8ff	678
bogdanm	0:9b334a45a8ff	679	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
bogdanm	0:9b334a45a8ff	680	* @{
bogdanm	0:9b334a45a8ff	681	*/
bogdanm	0:9b334a45a8ff	682	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	683	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
bogdanm	0:9b334a45a8ff	684	/**
bogdanm	0:9b334a45a8ff	685	* @}
bogdanm	0:9b334a45a8ff	686	*/
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
bogdanm	0:9b334a45a8ff	689	* @{
bogdanm	0:9b334a45a8ff	690	*/
bogdanm	0:9b334a45a8ff	691	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	692	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
bogdanm	0:9b334a45a8ff	693	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	694	/**
bogdanm	0:9b334a45a8ff	695	* @}
bogdanm	0:9b334a45a8ff	696	*/
bogdanm	0:9b334a45a8ff	697
bogdanm	0:9b334a45a8ff	698	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
bogdanm	0:9b334a45a8ff	699	* @{
bogdanm	0:9b334a45a8ff	700	*/
bogdanm	0:9b334a45a8ff	701	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	702	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	703	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	704	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
bogdanm	0:9b334a45a8ff	705	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	706	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
bogdanm	0:9b334a45a8ff	707	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
bogdanm	0:9b334a45a8ff	708	/**
bogdanm	0:9b334a45a8ff	709	* @}
bogdanm	0:9b334a45a8ff	710	*/
bogdanm	0:9b334a45a8ff	711
bogdanm	0:9b334a45a8ff	712	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
bogdanm	0:9b334a45a8ff	713	* @{
bogdanm	0:9b334a45a8ff	714	*/
bogdanm	0:9b334a45a8ff	715	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
bogdanm	0:9b334a45a8ff	716	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
bogdanm	0:9b334a45a8ff	717	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
bogdanm	0:9b334a45a8ff	718	/**
bogdanm	0:9b334a45a8ff	719	* @}
bogdanm	0:9b334a45a8ff	720	*/
bogdanm	0:9b334a45a8ff	721
bogdanm	0:9b334a45a8ff	722	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
bogdanm	0:9b334a45a8ff	723	* @{
bogdanm	0:9b334a45a8ff	724	*/
bogdanm	0:9b334a45a8ff	725	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	726	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
bogdanm	0:9b334a45a8ff	727	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
bogdanm	0:9b334a45a8ff	728	/**
bogdanm	0:9b334a45a8ff	729	* @}
bogdanm	0:9b334a45a8ff	730	*/
bogdanm	0:9b334a45a8ff	731
bogdanm	0:9b334a45a8ff	732	/**
bogdanm	0:9b334a45a8ff	733	* @}
bogdanm	0:9b334a45a8ff	734	*/
bogdanm	0:9b334a45a8ff	735
bogdanm	0:9b334a45a8ff	736	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
bogdanm	0:9b334a45a8ff	737	* @{
bogdanm	0:9b334a45a8ff	738	*/
bogdanm	0:9b334a45a8ff	739	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	740	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	741	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	742	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
bogdanm	0:9b334a45a8ff	743	/**
bogdanm	0:9b334a45a8ff	744	* @}
bogdanm	0:9b334a45a8ff	745	*/
bogdanm	0:9b334a45a8ff	746
bogdanm	0:9b334a45a8ff	747	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
bogdanm	0:9b334a45a8ff	748	* @{
bogdanm	0:9b334a45a8ff	749	*/
bogdanm	0:9b334a45a8ff	750	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	751	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	752	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	753	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	754	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
bogdanm	0:9b334a45a8ff	755	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
bogdanm	0:9b334a45a8ff	756	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
bogdanm	0:9b334a45a8ff	757	/**
bogdanm	0:9b334a45a8ff	758	* @}
bogdanm	0:9b334a45a8ff	759	*/
bogdanm	0:9b334a45a8ff	760
bogdanm	0:9b334a45a8ff	761	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
bogdanm	0:9b334a45a8ff	762	* @{
bogdanm	0:9b334a45a8ff	763	*/
mbed_official	19:112740acecfa	764	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	0:9b334a45a8ff	765	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
bogdanm	0:9b334a45a8ff	766	#else
bogdanm	0:9b334a45a8ff	767	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
bogdanm	0:9b334a45a8ff	768	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
mbed_official	19:112740acecfa	769	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	0:9b334a45a8ff	770	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
bogdanm	0:9b334a45a8ff	771	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
bogdanm	0:9b334a45a8ff	772	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
bogdanm	0:9b334a45a8ff	773
bogdanm	0:9b334a45a8ff	774
mbed_official	19:112740acecfa	775	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	0:9b334a45a8ff	776	#define FMC_NAND_DEVICE FMC_Bank3
bogdanm	0:9b334a45a8ff	777	#else
bogdanm	0:9b334a45a8ff	778	#define FMC_NAND_DEVICE FMC_Bank2_3
bogdanm	0:9b334a45a8ff	779	#define FMC_PCCARD_DEVICE FMC_Bank4
mbed_official	19:112740acecfa	780	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	0:9b334a45a8ff	781	#define FMC_NORSRAM_DEVICE FMC_Bank1
bogdanm	0:9b334a45a8ff	782	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
bogdanm	0:9b334a45a8ff	783	#define FMC_SDRAM_DEVICE FMC_Bank5_6
bogdanm	0:9b334a45a8ff	784	/**
bogdanm	0:9b334a45a8ff	785	* @}
bogdanm	0:9b334a45a8ff	786	*/
bogdanm	0:9b334a45a8ff	787
bogdanm	0:9b334a45a8ff	788	/**
bogdanm	0:9b334a45a8ff	789	* @}
bogdanm	0:9b334a45a8ff	790	*/
bogdanm	0:9b334a45a8ff	791
bogdanm	0:9b334a45a8ff	792	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	793	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
bogdanm	0:9b334a45a8ff	794	* @{
bogdanm	0:9b334a45a8ff	795	*/
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
bogdanm	0:9b334a45a8ff	798	* @brief macros to handle NOR device enable/disable and read/write operations
bogdanm	0:9b334a45a8ff	799	* @{
bogdanm	0:9b334a45a8ff	800	*/
bogdanm	0:9b334a45a8ff	801	/**
bogdanm	0:9b334a45a8ff	802	* @brief Enable the NORSRAM device access.
bogdanm	0:9b334a45a8ff	803	* @param __INSTANCE__: FMC_NORSRAM Instance
bogdanm	0:9b334a45a8ff	804	* @param __BANK__: FMC_NORSRAM Bank
bogdanm	0:9b334a45a8ff	805	* @retval None
bogdanm	0:9b334a45a8ff	806	*/
bogdanm	0:9b334a45a8ff	807	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
bogdanm	0:9b334a45a8ff	808
bogdanm	0:9b334a45a8ff	809	/**
bogdanm	0:9b334a45a8ff	810	* @brief Disable the NORSRAM device access.
bogdanm	0:9b334a45a8ff	811	* @param __INSTANCE__: FMC_NORSRAM Instance
bogdanm	0:9b334a45a8ff	812	* @param __BANK__: FMC_NORSRAM Bank
bogdanm	0:9b334a45a8ff	813	* @retval None
bogdanm	0:9b334a45a8ff	814	*/
bogdanm	0:9b334a45a8ff	815	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
bogdanm	0:9b334a45a8ff	816	/**
bogdanm	0:9b334a45a8ff	817	* @}
bogdanm	0:9b334a45a8ff	818	*/
bogdanm	0:9b334a45a8ff	819
bogdanm	0:9b334a45a8ff	820	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
bogdanm	0:9b334a45a8ff	821	* @brief macros to handle NAND device enable/disable
bogdanm	0:9b334a45a8ff	822	* @{
bogdanm	0:9b334a45a8ff	823	*/
mbed_official	19:112740acecfa	824	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	0:9b334a45a8ff	825	/**
bogdanm	0:9b334a45a8ff	826	* @brief Enable the NAND device access.
bogdanm	0:9b334a45a8ff	827	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	0:9b334a45a8ff	828	* @param __BANK__: FMC_NAND Bank
bogdanm	0:9b334a45a8ff	829	* @retval None
bogdanm	0:9b334a45a8ff	830	*/
bogdanm	0:9b334a45a8ff	831	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
bogdanm	0:9b334a45a8ff	832
bogdanm	0:9b334a45a8ff	833	/**
bogdanm	0:9b334a45a8ff	834	* @brief Disable the NAND device access.
bogdanm	0:9b334a45a8ff	835	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	0:9b334a45a8ff	836	* @param __BANK__: FMC_NAND Bank
bogdanm	0:9b334a45a8ff	837	* @retval None
bogdanm	0:9b334a45a8ff	838	*/
bogdanm	0:9b334a45a8ff	839	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
bogdanm	0:9b334a45a8ff	840	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
bogdanm	0:9b334a45a8ff	841	/**
bogdanm	0:9b334a45a8ff	842	* @brief Enable the NAND device access.
bogdanm	0:9b334a45a8ff	843	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	0:9b334a45a8ff	844	* @param __BANK__: FMC_NAND Bank
bogdanm	0:9b334a45a8ff	845	* @retval None
bogdanm	0:9b334a45a8ff	846	*/
bogdanm	0:9b334a45a8ff	847	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
bogdanm	0:9b334a45a8ff	848	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
bogdanm	0:9b334a45a8ff	849
bogdanm	0:9b334a45a8ff	850	/**
bogdanm	0:9b334a45a8ff	851	* @brief Disable the NAND device access.
bogdanm	0:9b334a45a8ff	852	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	0:9b334a45a8ff	853	* @param __BANK__: FMC_NAND Bank
bogdanm	0:9b334a45a8ff	854	* @retval None
bogdanm	0:9b334a45a8ff	855	*/
bogdanm	0:9b334a45a8ff	856	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
bogdanm	0:9b334a45a8ff	857	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
bogdanm	0:9b334a45a8ff	858
mbed_official	19:112740acecfa	859	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
bogdanm	0:9b334a45a8ff	860	/**
bogdanm	0:9b334a45a8ff	861	* @}
bogdanm	0:9b334a45a8ff	862	*/
bogdanm	0:9b334a45a8ff	863	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	864	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
bogdanm	0:9b334a45a8ff	865	* @brief macros to handle SRAM read/write operations
bogdanm	0:9b334a45a8ff	866	* @{
bogdanm	0:9b334a45a8ff	867	*/
bogdanm	0:9b334a45a8ff	868	/**
bogdanm	0:9b334a45a8ff	869	* @brief Enable the PCCARD device access.
bogdanm	0:9b334a45a8ff	870	* @param __INSTANCE__: FMC_PCCARD Instance
bogdanm	0:9b334a45a8ff	871	* @retval None
bogdanm	0:9b334a45a8ff	872	*/
bogdanm	0:9b334a45a8ff	873	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
bogdanm	0:9b334a45a8ff	874
bogdanm	0:9b334a45a8ff	875	/**
bogdanm	0:9b334a45a8ff	876	* @brief Disable the PCCARD device access.
bogdanm	0:9b334a45a8ff	877	* @param __INSTANCE__: FMC_PCCARD Instance
bogdanm	0:9b334a45a8ff	878	* @retval None
bogdanm	0:9b334a45a8ff	879	*/
bogdanm	0:9b334a45a8ff	880	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
bogdanm	0:9b334a45a8ff	881	/**
bogdanm	0:9b334a45a8ff	882	* @}
bogdanm	0:9b334a45a8ff	883	*/
bogdanm	0:9b334a45a8ff	884	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
bogdanm	0:9b334a45a8ff	885
bogdanm	0:9b334a45a8ff	886	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
bogdanm	0:9b334a45a8ff	887	* @brief macros to handle FMC flags and interrupts
bogdanm	0:9b334a45a8ff	888	* @{
bogdanm	0:9b334a45a8ff	889	*/
mbed_official	19:112740acecfa	890	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	0:9b334a45a8ff	891	/**
bogdanm	0:9b334a45a8ff	892	* @brief Enable the NAND device interrupt.
bogdanm	0:9b334a45a8ff	893	* @param __INSTANCE__: FMC_NAND instance
bogdanm	0:9b334a45a8ff	894	* @param __BANK__: FMC_NAND Bank
bogdanm	0:9b334a45a8ff	895	* @param __INTERRUPT__: FMC_NAND interrupt
bogdanm	0:9b334a45a8ff	896	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	897	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	0:9b334a45a8ff	898	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	0:9b334a45a8ff	899	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	0:9b334a45a8ff	900	* @retval None
bogdanm	0:9b334a45a8ff	901	*/
bogdanm	0:9b334a45a8ff	902	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	/**
bogdanm	0:9b334a45a8ff	905	* @brief Disable the NAND device interrupt.
bogdanm	0:9b334a45a8ff	906	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	0:9b334a45a8ff	907	* @param __BANK__: FMC_NAND Bank
bogdanm	0:9b334a45a8ff	908	* @param __INTERRUPT__: FMC_NAND interrupt
bogdanm	0:9b334a45a8ff	909	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	910	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	0:9b334a45a8ff	911	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	0:9b334a45a8ff	912	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	0:9b334a45a8ff	913	* @retval None
bogdanm	0:9b334a45a8ff	914	*/
bogdanm	0:9b334a45a8ff	915	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	/**
bogdanm	0:9b334a45a8ff	918	* @brief Get flag status of the NAND device.
bogdanm	0:9b334a45a8ff	919	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	0:9b334a45a8ff	920	* @param __BANK__: FMC_NAND Bank
bogdanm	0:9b334a45a8ff	921	* @param __FLAG__: FMC_NAND flag
bogdanm	0:9b334a45a8ff	922	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	923	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	0:9b334a45a8ff	924	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	0:9b334a45a8ff	925	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	0:9b334a45a8ff	926	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	0:9b334a45a8ff	927	* @retval The state of FLAG (SET or RESET).
bogdanm	0:9b334a45a8ff	928	*/
bogdanm	0:9b334a45a8ff	929	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	930	/**
bogdanm	0:9b334a45a8ff	931	* @brief Clear flag status of the NAND device.
bogdanm	0:9b334a45a8ff	932	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	0:9b334a45a8ff	933	* @param __BANK__: FMC_NAND Bank
bogdanm	0:9b334a45a8ff	934	* @param __FLAG__: FMC_NAND flag
bogdanm	0:9b334a45a8ff	935	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	936	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	0:9b334a45a8ff	937	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	0:9b334a45a8ff	938	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	0:9b334a45a8ff	939	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	0:9b334a45a8ff	940	* @retval None
bogdanm	0:9b334a45a8ff	941	*/
bogdanm	0:9b334a45a8ff	942	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
bogdanm	0:9b334a45a8ff	943	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
bogdanm	0:9b334a45a8ff	944	/**
bogdanm	0:9b334a45a8ff	945	* @brief Enable the NAND device interrupt.
bogdanm	0:9b334a45a8ff	946	* @param __INSTANCE__: FMC_NAND instance
bogdanm	0:9b334a45a8ff	947	* @param __BANK__: FMC_NAND Bank
bogdanm	0:9b334a45a8ff	948	* @param __INTERRUPT__: FMC_NAND interrupt
bogdanm	0:9b334a45a8ff	949	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	950	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	0:9b334a45a8ff	951	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	0:9b334a45a8ff	952	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	0:9b334a45a8ff	953	* @retval None
bogdanm	0:9b334a45a8ff	954	*/
bogdanm	0:9b334a45a8ff	955	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
bogdanm	0:9b334a45a8ff	956	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958	/**
bogdanm	0:9b334a45a8ff	959	* @brief Disable the NAND device interrupt.
bogdanm	0:9b334a45a8ff	960	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	0:9b334a45a8ff	961	* @param __BANK__: FMC_NAND Bank
bogdanm	0:9b334a45a8ff	962	* @param __INTERRUPT__: FMC_NAND interrupt
bogdanm	0:9b334a45a8ff	963	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	964	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	0:9b334a45a8ff	965	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	0:9b334a45a8ff	966	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	0:9b334a45a8ff	967	* @retval None
bogdanm	0:9b334a45a8ff	968	*/
bogdanm	0:9b334a45a8ff	969	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
bogdanm	0:9b334a45a8ff	970	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/**
bogdanm	0:9b334a45a8ff	973	* @brief Get flag status of the NAND device.
bogdanm	0:9b334a45a8ff	974	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	0:9b334a45a8ff	975	* @param __BANK__: FMC_NAND Bank
bogdanm	0:9b334a45a8ff	976	* @param __FLAG__: FMC_NAND flag
bogdanm	0:9b334a45a8ff	977	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	978	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	0:9b334a45a8ff	979	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	0:9b334a45a8ff	980	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	0:9b334a45a8ff	981	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	0:9b334a45a8ff	982	* @retval The state of FLAG (SET or RESET).
bogdanm	0:9b334a45a8ff	983	*/
bogdanm	0:9b334a45a8ff	984	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
bogdanm	0:9b334a45a8ff	985	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
bogdanm	0:9b334a45a8ff	986	/**
bogdanm	0:9b334a45a8ff	987	* @brief Clear flag status of the NAND device.
bogdanm	0:9b334a45a8ff	988	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	0:9b334a45a8ff	989	* @param __BANK__: FMC_NAND Bank
bogdanm	0:9b334a45a8ff	990	* @param __FLAG__: FMC_NAND flag
bogdanm	0:9b334a45a8ff	991	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	992	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	0:9b334a45a8ff	993	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	0:9b334a45a8ff	994	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	0:9b334a45a8ff	995	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	0:9b334a45a8ff	996	* @retval None
bogdanm	0:9b334a45a8ff	997	*/
bogdanm	0:9b334a45a8ff	998	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
bogdanm	0:9b334a45a8ff	999	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
mbed_official	19:112740acecfa	1000	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
bogdanm	0:9b334a45a8ff	1001
bogdanm	0:9b334a45a8ff	1002	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	1003	/**
bogdanm	0:9b334a45a8ff	1004	* @brief Enable the PCCARD device interrupt.
bogdanm	0:9b334a45a8ff	1005	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	0:9b334a45a8ff	1006	* @param __INTERRUPT__: FMC_PCCARD interrupt
bogdanm	0:9b334a45a8ff	1007	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1008	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	0:9b334a45a8ff	1009	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	0:9b334a45a8ff	1010	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	0:9b334a45a8ff	1011	* @retval None
bogdanm	0:9b334a45a8ff	1012	*/
bogdanm	0:9b334a45a8ff	1013	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1014
bogdanm	0:9b334a45a8ff	1015	/**
bogdanm	0:9b334a45a8ff	1016	* @brief Disable the PCCARD device interrupt.
bogdanm	0:9b334a45a8ff	1017	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	0:9b334a45a8ff	1018	* @param __INTERRUPT__: FMC_PCCARD interrupt
bogdanm	0:9b334a45a8ff	1019	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1020	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	0:9b334a45a8ff	1021	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	0:9b334a45a8ff	1022	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	0:9b334a45a8ff	1023	* @retval None
bogdanm	0:9b334a45a8ff	1024	*/
bogdanm	0:9b334a45a8ff	1025	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1026
bogdanm	0:9b334a45a8ff	1027	/**
bogdanm	0:9b334a45a8ff	1028	* @brief Get flag status of the PCCARD device.
bogdanm	0:9b334a45a8ff	1029	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	0:9b334a45a8ff	1030	* @param __FLAG__: FMC_PCCARD flag
bogdanm	0:9b334a45a8ff	1031	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1032	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	0:9b334a45a8ff	1033	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	0:9b334a45a8ff	1034	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	0:9b334a45a8ff	1035	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	0:9b334a45a8ff	1036	* @retval The state of FLAG (SET or RESET).
bogdanm	0:9b334a45a8ff	1037	*/
bogdanm	0:9b334a45a8ff	1038	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	1039
bogdanm	0:9b334a45a8ff	1040	/**
bogdanm	0:9b334a45a8ff	1041	* @brief Clear flag status of the PCCARD device.
bogdanm	0:9b334a45a8ff	1042	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	0:9b334a45a8ff	1043	* @param __FLAG__: FMC_PCCARD flag
bogdanm	0:9b334a45a8ff	1044	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1045	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	0:9b334a45a8ff	1046	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	0:9b334a45a8ff	1047	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	0:9b334a45a8ff	1048	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	0:9b334a45a8ff	1049	* @retval None
bogdanm	0:9b334a45a8ff	1050	*/
bogdanm	0:9b334a45a8ff	1051	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
bogdanm	0:9b334a45a8ff	1052	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	/**
bogdanm	0:9b334a45a8ff	1055	* @brief Enable the SDRAM device interrupt.
bogdanm	0:9b334a45a8ff	1056	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	0:9b334a45a8ff	1057	* @param __INTERRUPT__: FMC_SDRAM interrupt
bogdanm	0:9b334a45a8ff	1058	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1059	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
bogdanm	0:9b334a45a8ff	1060	* @retval None
bogdanm	0:9b334a45a8ff	1061	*/
bogdanm	0:9b334a45a8ff	1062	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	/**
bogdanm	0:9b334a45a8ff	1065	* @brief Disable the SDRAM device interrupt.
bogdanm	0:9b334a45a8ff	1066	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	0:9b334a45a8ff	1067	* @param __INTERRUPT__: FMC_SDRAM interrupt
bogdanm	0:9b334a45a8ff	1068	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1069	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
bogdanm	0:9b334a45a8ff	1070	* @retval None
bogdanm	0:9b334a45a8ff	1071	*/
bogdanm	0:9b334a45a8ff	1072	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1073
bogdanm	0:9b334a45a8ff	1074	/**
bogdanm	0:9b334a45a8ff	1075	* @brief Get flag status of the SDRAM device.
bogdanm	0:9b334a45a8ff	1076	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	0:9b334a45a8ff	1077	* @param __FLAG__: FMC_SDRAM flag
bogdanm	0:9b334a45a8ff	1078	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1079	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
bogdanm	0:9b334a45a8ff	1080	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
bogdanm	0:9b334a45a8ff	1081	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
bogdanm	0:9b334a45a8ff	1082	* @retval The state of FLAG (SET or RESET).
bogdanm	0:9b334a45a8ff	1083	*/
bogdanm	0:9b334a45a8ff	1084	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	1085
bogdanm	0:9b334a45a8ff	1086	/**
bogdanm	0:9b334a45a8ff	1087	* @brief Clear flag status of the SDRAM device.
bogdanm	0:9b334a45a8ff	1088	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	0:9b334a45a8ff	1089	* @param __FLAG__: FMC_SDRAM flag
bogdanm	0:9b334a45a8ff	1090	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1091	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
bogdanm	0:9b334a45a8ff	1092	* @retval None
bogdanm	0:9b334a45a8ff	1093	*/
bogdanm	0:9b334a45a8ff	1094	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
bogdanm	0:9b334a45a8ff	1095	/**
bogdanm	0:9b334a45a8ff	1096	* @}
bogdanm	0:9b334a45a8ff	1097	*/
bogdanm	0:9b334a45a8ff	1098
bogdanm	0:9b334a45a8ff	1099	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
bogdanm	0:9b334a45a8ff	1100	* @{
bogdanm	0:9b334a45a8ff	1101	*/
bogdanm	0:9b334a45a8ff	1102	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
bogdanm	0:9b334a45a8ff	1103	((BANK) == FMC_NORSRAM_BANK2) \|\| \
bogdanm	0:9b334a45a8ff	1104	((BANK) == FMC_NORSRAM_BANK3) \|\| \
bogdanm	0:9b334a45a8ff	1105	((BANK) == FMC_NORSRAM_BANK4))
bogdanm	0:9b334a45a8ff	1106
bogdanm	0:9b334a45a8ff	1107	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1108	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
bogdanm	0:9b334a45a8ff	1109
bogdanm	0:9b334a45a8ff	1110	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
bogdanm	0:9b334a45a8ff	1111	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
bogdanm	0:9b334a45a8ff	1112	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
bogdanm	0:9b334a45a8ff	1113
bogdanm	0:9b334a45a8ff	1114	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
bogdanm	0:9b334a45a8ff	1115	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
bogdanm	0:9b334a45a8ff	1116	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
bogdanm	0:9b334a45a8ff	1117
bogdanm	0:9b334a45a8ff	1118	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
bogdanm	0:9b334a45a8ff	1119	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
bogdanm	0:9b334a45a8ff	1120	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
bogdanm	0:9b334a45a8ff	1121	((__MODE__) == FMC_ACCESS_MODE_D))
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
bogdanm	0:9b334a45a8ff	1124	((BANK) == FMC_NAND_BANK3))
bogdanm	0:9b334a45a8ff	1125
bogdanm	0:9b334a45a8ff	1126	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1127	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
bogdanm	0:9b334a45a8ff	1128
bogdanm	0:9b334a45a8ff	1129	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
bogdanm	0:9b334a45a8ff	1130	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
bogdanm	0:9b334a45a8ff	1131
bogdanm	0:9b334a45a8ff	1132	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1133	((STATE) == FMC_NAND_ECC_ENABLE))
bogdanm	0:9b334a45a8ff	1134
bogdanm	0:9b334a45a8ff	1135	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
bogdanm	0:9b334a45a8ff	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
bogdanm	0:9b334a45a8ff	1137	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
bogdanm	0:9b334a45a8ff	1138	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
bogdanm	0:9b334a45a8ff	1139	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
bogdanm	0:9b334a45a8ff	1140	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
bogdanm	0:9b334a45a8ff	1141
bogdanm	0:9b334a45a8ff	1142	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
bogdanm	0:9b334a45a8ff	1143
bogdanm	0:9b334a45a8ff	1144	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
bogdanm	0:9b334a45a8ff	1147
bogdanm	0:9b334a45a8ff	1148	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
bogdanm	0:9b334a45a8ff	1149
bogdanm	0:9b334a45a8ff	1150	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
bogdanm	0:9b334a45a8ff	1151
bogdanm	0:9b334a45a8ff	1152	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
bogdanm	0:9b334a45a8ff	1153
bogdanm	0:9b334a45a8ff	1154	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
bogdanm	0:9b334a45a8ff	1155
bogdanm	0:9b334a45a8ff	1156	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
bogdanm	0:9b334a45a8ff	1157
bogdanm	0:9b334a45a8ff	1158	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
bogdanm	0:9b334a45a8ff	1159
bogdanm	0:9b334a45a8ff	1160	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
bogdanm	0:9b334a45a8ff	1161
bogdanm	0:9b334a45a8ff	1162	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1163	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
bogdanm	0:9b334a45a8ff	1166	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
bogdanm	0:9b334a45a8ff	1167
mbed_official	19:112740acecfa	1168	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	1169	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
mbed_official	19:112740acecfa	1170	((__MODE__) == FMC_WRAP_MODE_ENABLE))
mbed_official	19:112740acecfa	1171	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	1172
bogdanm	0:9b334a45a8ff	1173	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
bogdanm	0:9b334a45a8ff	1174	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1177	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
bogdanm	0:9b334a45a8ff	1178
bogdanm	0:9b334a45a8ff	1179	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1180	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
bogdanm	0:9b334a45a8ff	1181
bogdanm	0:9b334a45a8ff	1182	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1183	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1186	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
bogdanm	0:9b334a45a8ff	1187
bogdanm	0:9b334a45a8ff	1188	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1189	((__BURST__) == FMC_WRITE_BURST_ENABLE))
bogdanm	0:9b334a45a8ff	1190
bogdanm	0:9b334a45a8ff	1191	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
bogdanm	0:9b334a45a8ff	1192	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
bogdanm	0:9b334a45a8ff	1193
bogdanm	0:9b334a45a8ff	1194	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
bogdanm	0:9b334a45a8ff	1197
bogdanm	0:9b334a45a8ff	1198	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
bogdanm	0:9b334a45a8ff	1199
bogdanm	0:9b334a45a8ff	1200	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
bogdanm	0:9b334a45a8ff	1201
bogdanm	0:9b334a45a8ff	1202	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
bogdanm	0:9b334a45a8ff	1203
bogdanm	0:9b334a45a8ff	1204	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
bogdanm	0:9b334a45a8ff	1205
bogdanm	0:9b334a45a8ff	1206	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
bogdanm	0:9b334a45a8ff	1207	((BANK) == FMC_SDRAM_BANK2))
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
bogdanm	0:9b334a45a8ff	1210	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
bogdanm	0:9b334a45a8ff	1211	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
bogdanm	0:9b334a45a8ff	1212	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
bogdanm	0:9b334a45a8ff	1213
bogdanm	0:9b334a45a8ff	1214	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
bogdanm	0:9b334a45a8ff	1215	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
bogdanm	0:9b334a45a8ff	1216	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
bogdanm	0:9b334a45a8ff	1217
bogdanm	0:9b334a45a8ff	1218	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
bogdanm	0:9b334a45a8ff	1219	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
bogdanm	0:9b334a45a8ff	1220	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
bogdanm	0:9b334a45a8ff	1223	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
bogdanm	0:9b334a45a8ff	1224
bogdanm	0:9b334a45a8ff	1225
bogdanm	0:9b334a45a8ff	1226	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
bogdanm	0:9b334a45a8ff	1227	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
bogdanm	0:9b334a45a8ff	1228	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
bogdanm	0:9b334a45a8ff	1229
bogdanm	0:9b334a45a8ff	1230	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1231	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
bogdanm	0:9b334a45a8ff	1232	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
bogdanm	0:9b334a45a8ff	1233
bogdanm	0:9b334a45a8ff	1234	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1235	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237
bogdanm	0:9b334a45a8ff	1238	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
bogdanm	0:9b334a45a8ff	1239	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
bogdanm	0:9b334a45a8ff	1240	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
bogdanm	0:9b334a45a8ff	1241
bogdanm	0:9b334a45a8ff	1242	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	0:9b334a45a8ff	1243
bogdanm	0:9b334a45a8ff	1244	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	0:9b334a45a8ff	1245
bogdanm	0:9b334a45a8ff	1246	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
bogdanm	0:9b334a45a8ff	1247
bogdanm	0:9b334a45a8ff	1248	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	0:9b334a45a8ff	1249
bogdanm	0:9b334a45a8ff	1250	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
bogdanm	0:9b334a45a8ff	1251
bogdanm	0:9b334a45a8ff	1252	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	0:9b334a45a8ff	1253
bogdanm	0:9b334a45a8ff	1254	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	0:9b334a45a8ff	1255
bogdanm	0:9b334a45a8ff	1256	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
bogdanm	0:9b334a45a8ff	1257	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1258	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
bogdanm	0:9b334a45a8ff	1259	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
bogdanm	0:9b334a45a8ff	1260	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
bogdanm	0:9b334a45a8ff	1261	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
bogdanm	0:9b334a45a8ff	1262	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
bogdanm	0:9b334a45a8ff	1263
bogdanm	0:9b334a45a8ff	1264	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
bogdanm	0:9b334a45a8ff	1265	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
bogdanm	0:9b334a45a8ff	1266	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
bogdanm	0:9b334a45a8ff	1267
bogdanm	0:9b334a45a8ff	1268	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
bogdanm	0:9b334a45a8ff	1269
bogdanm	0:9b334a45a8ff	1270	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
bogdanm	0:9b334a45a8ff	1271
bogdanm	0:9b334a45a8ff	1272	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1277	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
bogdanm	0:9b334a45a8ff	1278
mbed_official	19:112740acecfa	1279	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
bogdanm	0:9b334a45a8ff	1280	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1281	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
bogdanm	0:9b334a45a8ff	1282	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
bogdanm	0:9b334a45a8ff	1283	((SIZE) == FMC_PAGE_SIZE_1024))
bogdanm	0:9b334a45a8ff	1284
bogdanm	0:9b334a45a8ff	1285	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
bogdanm	0:9b334a45a8ff	1286	((FIFO) == FMC_WRITE_FIFO_ENABLE))
mbed_official	19:112740acecfa	1287	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	0:9b334a45a8ff	1288
bogdanm	0:9b334a45a8ff	1289	/**
bogdanm	0:9b334a45a8ff	1290	* @}
bogdanm	0:9b334a45a8ff	1291	*/
bogdanm	0:9b334a45a8ff	1292
bogdanm	0:9b334a45a8ff	1293	/**
bogdanm	0:9b334a45a8ff	1294	* @}
bogdanm	0:9b334a45a8ff	1295	*/
bogdanm	0:9b334a45a8ff	1296
bogdanm	0:9b334a45a8ff	1297	/* Private functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1298	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
bogdanm	0:9b334a45a8ff	1299	* @{
bogdanm	0:9b334a45a8ff	1300	*/
bogdanm	0:9b334a45a8ff	1301
bogdanm	0:9b334a45a8ff	1302	/** @defgroup FMC_LL_NORSRAM NOR SRAM
bogdanm	0:9b334a45a8ff	1303	* @{
bogdanm	0:9b334a45a8ff	1304	*/
bogdanm	0:9b334a45a8ff	1305	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	1306	* @{
bogdanm	0:9b334a45a8ff	1307	*/
bogdanm	0:9b334a45a8ff	1308	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
bogdanm	0:9b334a45a8ff	1309	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1310	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
bogdanm	0:9b334a45a8ff	1311	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1312	/**
bogdanm	0:9b334a45a8ff	1313	* @}
bogdanm	0:9b334a45a8ff	1314	*/
bogdanm	0:9b334a45a8ff	1315
bogdanm	0:9b334a45a8ff	1316	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
bogdanm	0:9b334a45a8ff	1317	* @{
bogdanm	0:9b334a45a8ff	1318	*/
bogdanm	0:9b334a45a8ff	1319	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1320	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1321	/**
bogdanm	0:9b334a45a8ff	1322	* @}
bogdanm	0:9b334a45a8ff	1323	*/
bogdanm	0:9b334a45a8ff	1324	/**
bogdanm	0:9b334a45a8ff	1325	* @}
bogdanm	0:9b334a45a8ff	1326	*/
bogdanm	0:9b334a45a8ff	1327
bogdanm	0:9b334a45a8ff	1328	/** @defgroup FMC_LL_NAND NAND
bogdanm	0:9b334a45a8ff	1329	* @{
bogdanm	0:9b334a45a8ff	1330	*/
bogdanm	0:9b334a45a8ff	1331	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	1332	* @{
bogdanm	0:9b334a45a8ff	1333	*/
bogdanm	0:9b334a45a8ff	1334	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
bogdanm	0:9b334a45a8ff	1335	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1336	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1337	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1338	/**
bogdanm	0:9b334a45a8ff	1339	* @}
bogdanm	0:9b334a45a8ff	1340	*/
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
bogdanm	0:9b334a45a8ff	1343	* @{
bogdanm	0:9b334a45a8ff	1344	*/
bogdanm	0:9b334a45a8ff	1345	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1346	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1347	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	1348
bogdanm	0:9b334a45a8ff	1349	/**
bogdanm	0:9b334a45a8ff	1350	* @}
bogdanm	0:9b334a45a8ff	1351	*/
bogdanm	0:9b334a45a8ff	1352	/**
bogdanm	0:9b334a45a8ff	1353	* @}
bogdanm	0:9b334a45a8ff	1354	*/
bogdanm	0:9b334a45a8ff	1355	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	0:9b334a45a8ff	1356	/** @defgroup FMC_LL_PCCARD PCCARD
bogdanm	0:9b334a45a8ff	1357	* @{
bogdanm	0:9b334a45a8ff	1358	*/
bogdanm	0:9b334a45a8ff	1359	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	1360	* @{
bogdanm	0:9b334a45a8ff	1361	*/
bogdanm	0:9b334a45a8ff	1362	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
bogdanm	0:9b334a45a8ff	1363	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	0:9b334a45a8ff	1364	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	0:9b334a45a8ff	1365	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	0:9b334a45a8ff	1366	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
bogdanm	0:9b334a45a8ff	1367	/**
bogdanm	0:9b334a45a8ff	1368	* @}
bogdanm	0:9b334a45a8ff	1369	*/
bogdanm	0:9b334a45a8ff	1370	/**
bogdanm	0:9b334a45a8ff	1371	* @}
bogdanm	0:9b334a45a8ff	1372	*/
bogdanm	0:9b334a45a8ff	1373	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	0:9b334a45a8ff	1374
bogdanm	0:9b334a45a8ff	1375	/** @defgroup FMC_LL_SDRAM SDRAM
bogdanm	0:9b334a45a8ff	1376	* @{
bogdanm	0:9b334a45a8ff	1377	*/
bogdanm	0:9b334a45a8ff	1378	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
bogdanm	0:9b334a45a8ff	1379	* @{
bogdanm	0:9b334a45a8ff	1380	*/
bogdanm	0:9b334a45a8ff	1381	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
bogdanm	0:9b334a45a8ff	1382	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1383	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1384	/**
bogdanm	0:9b334a45a8ff	1385	* @}
bogdanm	0:9b334a45a8ff	1386	*/
bogdanm	0:9b334a45a8ff	1387
bogdanm	0:9b334a45a8ff	1388	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
bogdanm	0:9b334a45a8ff	1389	* @{
bogdanm	0:9b334a45a8ff	1390	*/
bogdanm	0:9b334a45a8ff	1391	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1392	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1393	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	1394	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
bogdanm	0:9b334a45a8ff	1395	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
bogdanm	0:9b334a45a8ff	1396	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	0:9b334a45a8ff	1397	/**
bogdanm	0:9b334a45a8ff	1398	* @}
bogdanm	0:9b334a45a8ff	1399	*/
bogdanm	0:9b334a45a8ff	1400	/**
bogdanm	0:9b334a45a8ff	1401	* @}
bogdanm	0:9b334a45a8ff	1402	*/
bogdanm	0:9b334a45a8ff	1403
bogdanm	0:9b334a45a8ff	1404	/**
bogdanm	0:9b334a45a8ff	1405	* @}
bogdanm	0:9b334a45a8ff	1406	*/
bogdanm	0:9b334a45a8ff	1407
mbed_official	19:112740acecfa	1408	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
bogdanm	0:9b334a45a8ff	1409	/**
bogdanm	0:9b334a45a8ff	1410	* @}
bogdanm	0:9b334a45a8ff	1411	*/
bogdanm	0:9b334a45a8ff	1412
bogdanm	0:9b334a45a8ff	1413	/**
bogdanm	0:9b334a45a8ff	1414	* @}
bogdanm	0:9b334a45a8ff	1415	*/
bogdanm	0:9b334a45a8ff	1416	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1417	}
bogdanm	0:9b334a45a8ff	1418	#endif
bogdanm	0:9b334a45a8ff	1419
bogdanm	0:9b334a45a8ff	1420	#endif /* __STM32F4xx_LL_FMC_H */
bogdanm	0:9b334a45a8ff	1421
bogdanm	0:9b334a45a8ff	1422	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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