en 129
fix LPC812 PWM
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by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_pwr_ex.c@129:2e517c56bcfb, 2016-05-16 (annotated)
- Committer:
- nameless129
- Date:
- Mon May 16 16:50:30 2016 +0000
- Revision:
- 129:2e517c56bcfb
- Parent:
- 19:112740acecfa
PWM Fix:Duty 0%??H???????????????
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f4xx_hal_pwr_ex.c |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| mbed_official | 19:112740acecfa | 5 | * @version V1.4.1 |
| mbed_official | 19:112740acecfa | 6 | * @date 09-October-2015 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief Extended PWR HAL module driver. |
| bogdanm | 0:9b334a45a8ff | 8 | * This file provides firmware functions to manage the following |
| bogdanm | 0:9b334a45a8ff | 9 | * functionalities of PWR extension peripheral: |
| bogdanm | 0:9b334a45a8ff | 10 | * + Peripheral Extended features functions |
| bogdanm | 0:9b334a45a8ff | 11 | * |
| bogdanm | 0:9b334a45a8ff | 12 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 13 | * @attention |
| bogdanm | 0:9b334a45a8ff | 14 | * |
| bogdanm | 0:9b334a45a8ff | 15 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 16 | * |
| bogdanm | 0:9b334a45a8ff | 17 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 18 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 19 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 20 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 22 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 23 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 25 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 26 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 27 | * |
| bogdanm | 0:9b334a45a8ff | 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 38 | * |
| bogdanm | 0:9b334a45a8ff | 39 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 40 | */ |
| bogdanm | 0:9b334a45a8ff | 41 | |
| bogdanm | 0:9b334a45a8ff | 42 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 43 | #include "stm32f4xx_hal.h" |
| bogdanm | 0:9b334a45a8ff | 44 | |
| bogdanm | 0:9b334a45a8ff | 45 | /** @addtogroup STM32F4xx_HAL_Driver |
| bogdanm | 0:9b334a45a8ff | 46 | * @{ |
| bogdanm | 0:9b334a45a8ff | 47 | */ |
| bogdanm | 0:9b334a45a8ff | 48 | |
| bogdanm | 0:9b334a45a8ff | 49 | /** @defgroup PWREx PWREx |
| bogdanm | 0:9b334a45a8ff | 50 | * @brief PWR HAL module driver |
| bogdanm | 0:9b334a45a8ff | 51 | * @{ |
| bogdanm | 0:9b334a45a8ff | 52 | */ |
| bogdanm | 0:9b334a45a8ff | 53 | |
| bogdanm | 0:9b334a45a8ff | 54 | #ifdef HAL_PWR_MODULE_ENABLED |
| bogdanm | 0:9b334a45a8ff | 55 | |
| bogdanm | 0:9b334a45a8ff | 56 | /* Private typedef -----------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 57 | /* Private define ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 58 | /** @addtogroup PWREx_Private_Constants |
| bogdanm | 0:9b334a45a8ff | 59 | * @{ |
| bogdanm | 0:9b334a45a8ff | 60 | */ |
| bogdanm | 0:9b334a45a8ff | 61 | #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000 |
| bogdanm | 0:9b334a45a8ff | 62 | #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000 |
| bogdanm | 0:9b334a45a8ff | 63 | #define PWR_BKPREG_TIMEOUT_VALUE 1000 |
| bogdanm | 0:9b334a45a8ff | 64 | #define PWR_VOSRDY_TIMEOUT_VALUE 1000 |
| bogdanm | 0:9b334a45a8ff | 65 | /** |
| bogdanm | 0:9b334a45a8ff | 66 | * @} |
| bogdanm | 0:9b334a45a8ff | 67 | */ |
| bogdanm | 0:9b334a45a8ff | 68 | |
| bogdanm | 0:9b334a45a8ff | 69 | |
| bogdanm | 0:9b334a45a8ff | 70 | /* Private macro -------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 71 | /* Private variables ---------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 72 | /* Private function prototypes -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 73 | /* Private functions ---------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 74 | /** @defgroup PWREx_Exported_Functions PWREx Exported Functions |
| bogdanm | 0:9b334a45a8ff | 75 | * @{ |
| bogdanm | 0:9b334a45a8ff | 76 | */ |
| bogdanm | 0:9b334a45a8ff | 77 | |
| bogdanm | 0:9b334a45a8ff | 78 | /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions |
| bogdanm | 0:9b334a45a8ff | 79 | * @brief Peripheral Extended features functions |
| bogdanm | 0:9b334a45a8ff | 80 | * |
| bogdanm | 0:9b334a45a8ff | 81 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 82 | |
| bogdanm | 0:9b334a45a8ff | 83 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 84 | ##### Peripheral extended features functions ##### |
| bogdanm | 0:9b334a45a8ff | 85 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 86 | |
| bogdanm | 0:9b334a45a8ff | 87 | *** Main and Backup Regulators configuration *** |
| bogdanm | 0:9b334a45a8ff | 88 | ================================================ |
| bogdanm | 0:9b334a45a8ff | 89 | [..] |
| bogdanm | 0:9b334a45a8ff | 90 | (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from |
| bogdanm | 0:9b334a45a8ff | 91 | the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is |
| bogdanm | 0:9b334a45a8ff | 92 | retained even in Standby or VBAT mode when the low power backup regulator |
| bogdanm | 0:9b334a45a8ff | 93 | is enabled. It can be considered as an internal EEPROM when VBAT is |
| bogdanm | 0:9b334a45a8ff | 94 | always present. You can use the HAL_PWREx_EnableBkUpReg() function to |
| bogdanm | 0:9b334a45a8ff | 95 | enable the low power backup regulator. |
| bogdanm | 0:9b334a45a8ff | 96 | |
| bogdanm | 0:9b334a45a8ff | 97 | (+) When the backup domain is supplied by VDD (analog switch connected to VDD) |
| bogdanm | 0:9b334a45a8ff | 98 | the backup SRAM is powered from VDD which replaces the VBAT power supply to |
| bogdanm | 0:9b334a45a8ff | 99 | save battery life. |
| bogdanm | 0:9b334a45a8ff | 100 | |
| bogdanm | 0:9b334a45a8ff | 101 | (+) The backup SRAM is not mass erased by a tamper event. It is read |
| bogdanm | 0:9b334a45a8ff | 102 | protected to prevent confidential data, such as cryptographic private |
| bogdanm | 0:9b334a45a8ff | 103 | key, from being accessed. The backup SRAM can be erased only through |
| bogdanm | 0:9b334a45a8ff | 104 | the Flash interface when a protection level change from level 1 to |
| bogdanm | 0:9b334a45a8ff | 105 | level 0 is requested. |
| bogdanm | 0:9b334a45a8ff | 106 | -@- Refer to the description of Read protection (RDP) in the Flash |
| bogdanm | 0:9b334a45a8ff | 107 | programming manual. |
| bogdanm | 0:9b334a45a8ff | 108 | |
| bogdanm | 0:9b334a45a8ff | 109 | (+) The main internal regulator can be configured to have a tradeoff between |
| bogdanm | 0:9b334a45a8ff | 110 | performance and power consumption when the device does not operate at |
| bogdanm | 0:9b334a45a8ff | 111 | the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() |
| bogdanm | 0:9b334a45a8ff | 112 | macro which configure VOS bit in PWR_CR register |
| bogdanm | 0:9b334a45a8ff | 113 | |
| bogdanm | 0:9b334a45a8ff | 114 | Refer to the product datasheets for more details. |
| bogdanm | 0:9b334a45a8ff | 115 | |
| bogdanm | 0:9b334a45a8ff | 116 | *** FLASH Power Down configuration **** |
| bogdanm | 0:9b334a45a8ff | 117 | ======================================= |
| bogdanm | 0:9b334a45a8ff | 118 | [..] |
| bogdanm | 0:9b334a45a8ff | 119 | (+) By setting the FPDS bit in the PWR_CR register by using the |
| bogdanm | 0:9b334a45a8ff | 120 | HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power |
| bogdanm | 0:9b334a45a8ff | 121 | down mode when the device enters Stop mode. When the Flash memory |
| bogdanm | 0:9b334a45a8ff | 122 | is in power down mode, an additional startup delay is incurred when |
| bogdanm | 0:9b334a45a8ff | 123 | waking up from Stop mode. |
| bogdanm | 0:9b334a45a8ff | 124 | |
| mbed_official | 19:112740acecfa | 125 | (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL |
| bogdanm | 0:9b334a45a8ff | 126 | is OFF and the HSI or HSE clock source is selected as system clock. |
| bogdanm | 0:9b334a45a8ff | 127 | The new value programmed is active only when the PLL is ON. |
| bogdanm | 0:9b334a45a8ff | 128 | When the PLL is OFF, the voltage scale 3 is automatically selected. |
| bogdanm | 0:9b334a45a8ff | 129 | Refer to the datasheets for more details. |
| bogdanm | 0:9b334a45a8ff | 130 | |
| bogdanm | 0:9b334a45a8ff | 131 | *** Over-Drive and Under-Drive configuration **** |
| bogdanm | 0:9b334a45a8ff | 132 | ================================================= |
| bogdanm | 0:9b334a45a8ff | 133 | [..] |
| mbed_official | 19:112740acecfa | 134 | (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has |
| bogdanm | 0:9b334a45a8ff | 135 | 2 operating modes available: |
| bogdanm | 0:9b334a45a8ff | 136 | (++) Normal mode: The CPU and core logic operate at maximum frequency at a given |
| bogdanm | 0:9b334a45a8ff | 137 | voltage scaling (scale 1, scale 2 or scale 3) |
| bogdanm | 0:9b334a45a8ff | 138 | (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a |
| bogdanm | 0:9b334a45a8ff | 139 | higher frequency than the normal mode for a given voltage scaling (scale 1, |
| bogdanm | 0:9b334a45a8ff | 140 | scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and |
| bogdanm | 0:9b334a45a8ff | 141 | disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow |
| bogdanm | 0:9b334a45a8ff | 142 | the sequence described in Reference manual. |
| bogdanm | 0:9b334a45a8ff | 143 | |
| mbed_official | 19:112740acecfa | 144 | (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator |
| bogdanm | 0:9b334a45a8ff | 145 | supplies a low power voltage to the 1.2V domain, thus preserving the content of registers |
| bogdanm | 0:9b334a45a8ff | 146 | and internal SRAM. 2 operating modes are available: |
| bogdanm | 0:9b334a45a8ff | 147 | (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only |
| bogdanm | 0:9b334a45a8ff | 148 | available when the main regulator or the low power regulator is used in Scale 3 or |
| bogdanm | 0:9b334a45a8ff | 149 | low voltage mode. |
| bogdanm | 0:9b334a45a8ff | 150 | (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only |
| bogdanm | 0:9b334a45a8ff | 151 | available when the main regulator or the low power regulator is in low voltage mode. |
| bogdanm | 0:9b334a45a8ff | 152 | |
| bogdanm | 0:9b334a45a8ff | 153 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 154 | * @{ |
| bogdanm | 0:9b334a45a8ff | 155 | */ |
| bogdanm | 0:9b334a45a8ff | 156 | |
| bogdanm | 0:9b334a45a8ff | 157 | /** |
| bogdanm | 0:9b334a45a8ff | 158 | * @brief Enables the Backup Regulator. |
| bogdanm | 0:9b334a45a8ff | 159 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 160 | */ |
| bogdanm | 0:9b334a45a8ff | 161 | HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) |
| bogdanm | 0:9b334a45a8ff | 162 | { |
| bogdanm | 0:9b334a45a8ff | 163 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 164 | |
| bogdanm | 0:9b334a45a8ff | 165 | *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE; |
| bogdanm | 0:9b334a45a8ff | 166 | |
| bogdanm | 0:9b334a45a8ff | 167 | /* Get tick */ |
| bogdanm | 0:9b334a45a8ff | 168 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 169 | |
| bogdanm | 0:9b334a45a8ff | 170 | /* Wait till Backup regulator ready flag is set */ |
| bogdanm | 0:9b334a45a8ff | 171 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) |
| bogdanm | 0:9b334a45a8ff | 172 | { |
| bogdanm | 0:9b334a45a8ff | 173 | if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 174 | { |
| bogdanm | 0:9b334a45a8ff | 175 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 176 | } |
| bogdanm | 0:9b334a45a8ff | 177 | } |
| bogdanm | 0:9b334a45a8ff | 178 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 179 | } |
| bogdanm | 0:9b334a45a8ff | 180 | |
| bogdanm | 0:9b334a45a8ff | 181 | /** |
| bogdanm | 0:9b334a45a8ff | 182 | * @brief Disables the Backup Regulator. |
| bogdanm | 0:9b334a45a8ff | 183 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 184 | */ |
| bogdanm | 0:9b334a45a8ff | 185 | HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) |
| bogdanm | 0:9b334a45a8ff | 186 | { |
| bogdanm | 0:9b334a45a8ff | 187 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 188 | |
| bogdanm | 0:9b334a45a8ff | 189 | *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE; |
| bogdanm | 0:9b334a45a8ff | 190 | |
| bogdanm | 0:9b334a45a8ff | 191 | /* Get tick */ |
| bogdanm | 0:9b334a45a8ff | 192 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 193 | |
| bogdanm | 0:9b334a45a8ff | 194 | /* Wait till Backup regulator ready flag is set */ |
| bogdanm | 0:9b334a45a8ff | 195 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) |
| bogdanm | 0:9b334a45a8ff | 196 | { |
| bogdanm | 0:9b334a45a8ff | 197 | if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 198 | { |
| bogdanm | 0:9b334a45a8ff | 199 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 200 | } |
| bogdanm | 0:9b334a45a8ff | 201 | } |
| bogdanm | 0:9b334a45a8ff | 202 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 203 | } |
| bogdanm | 0:9b334a45a8ff | 204 | |
| bogdanm | 0:9b334a45a8ff | 205 | /** |
| bogdanm | 0:9b334a45a8ff | 206 | * @brief Enables the Flash Power Down in Stop mode. |
| bogdanm | 0:9b334a45a8ff | 207 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 208 | */ |
| bogdanm | 0:9b334a45a8ff | 209 | void HAL_PWREx_EnableFlashPowerDown(void) |
| bogdanm | 0:9b334a45a8ff | 210 | { |
| bogdanm | 0:9b334a45a8ff | 211 | *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE; |
| bogdanm | 0:9b334a45a8ff | 212 | } |
| bogdanm | 0:9b334a45a8ff | 213 | |
| bogdanm | 0:9b334a45a8ff | 214 | /** |
| bogdanm | 0:9b334a45a8ff | 215 | * @brief Disables the Flash Power Down in Stop mode. |
| bogdanm | 0:9b334a45a8ff | 216 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 217 | */ |
| bogdanm | 0:9b334a45a8ff | 218 | void HAL_PWREx_DisableFlashPowerDown(void) |
| bogdanm | 0:9b334a45a8ff | 219 | { |
| bogdanm | 0:9b334a45a8ff | 220 | *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE; |
| bogdanm | 0:9b334a45a8ff | 221 | } |
| bogdanm | 0:9b334a45a8ff | 222 | |
| bogdanm | 0:9b334a45a8ff | 223 | /** |
| bogdanm | 0:9b334a45a8ff | 224 | * @brief Return Voltage Scaling Range. |
| bogdanm | 0:9b334a45a8ff | 225 | * @retval The configured scale for the regulator voltage(VOS bit field). |
| bogdanm | 0:9b334a45a8ff | 226 | * The returned value can be one of the following: |
| bogdanm | 0:9b334a45a8ff | 227 | * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode |
| bogdanm | 0:9b334a45a8ff | 228 | * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode |
| bogdanm | 0:9b334a45a8ff | 229 | * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode |
| bogdanm | 0:9b334a45a8ff | 230 | */ |
| bogdanm | 0:9b334a45a8ff | 231 | uint32_t HAL_PWREx_GetVoltageRange(void) |
| bogdanm | 0:9b334a45a8ff | 232 | { |
| bogdanm | 0:9b334a45a8ff | 233 | return (PWR->CR & PWR_CR_VOS); |
| bogdanm | 0:9b334a45a8ff | 234 | } |
| bogdanm | 0:9b334a45a8ff | 235 | |
| bogdanm | 0:9b334a45a8ff | 236 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| bogdanm | 0:9b334a45a8ff | 237 | /** |
| bogdanm | 0:9b334a45a8ff | 238 | * @brief Configures the main internal regulator output voltage. |
| bogdanm | 0:9b334a45a8ff | 239 | * @param VoltageScaling: specifies the regulator output voltage to achieve |
| bogdanm | 0:9b334a45a8ff | 240 | * a tradeoff between performance and power consumption. |
| bogdanm | 0:9b334a45a8ff | 241 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 242 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, |
| bogdanm | 0:9b334a45a8ff | 243 | * the maximum value of fHCLK = 168 MHz. |
| bogdanm | 0:9b334a45a8ff | 244 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, |
| bogdanm | 0:9b334a45a8ff | 245 | * the maximum value of fHCLK = 144 MHz. |
| bogdanm | 0:9b334a45a8ff | 246 | * @note When moving from Range 1 to Range 2, the system frequency must be decreased to |
| bogdanm | 0:9b334a45a8ff | 247 | * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API. |
| bogdanm | 0:9b334a45a8ff | 248 | * When moving from Range 2 to Range 1, the system frequency can be increased to |
| bogdanm | 0:9b334a45a8ff | 249 | * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API. |
| bogdanm | 0:9b334a45a8ff | 250 | * @retval HAL Status |
| bogdanm | 0:9b334a45a8ff | 251 | */ |
| bogdanm | 0:9b334a45a8ff | 252 | HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) |
| bogdanm | 0:9b334a45a8ff | 253 | { |
| bogdanm | 0:9b334a45a8ff | 254 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 255 | |
| bogdanm | 0:9b334a45a8ff | 256 | assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); |
| bogdanm | 0:9b334a45a8ff | 257 | |
| bogdanm | 0:9b334a45a8ff | 258 | /* Enable PWR RCC Clock Peripheral */ |
| bogdanm | 0:9b334a45a8ff | 259 | __HAL_RCC_PWR_CLK_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 260 | |
| bogdanm | 0:9b334a45a8ff | 261 | /* Set Range */ |
| bogdanm | 0:9b334a45a8ff | 262 | __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); |
| bogdanm | 0:9b334a45a8ff | 263 | |
| bogdanm | 0:9b334a45a8ff | 264 | /* Get Start Tick*/ |
| bogdanm | 0:9b334a45a8ff | 265 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 266 | while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) |
| bogdanm | 0:9b334a45a8ff | 267 | { |
| bogdanm | 0:9b334a45a8ff | 268 | if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 269 | { |
| bogdanm | 0:9b334a45a8ff | 270 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 271 | } |
| bogdanm | 0:9b334a45a8ff | 272 | } |
| bogdanm | 0:9b334a45a8ff | 273 | |
| bogdanm | 0:9b334a45a8ff | 274 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 275 | } |
| bogdanm | 0:9b334a45a8ff | 276 | |
| bogdanm | 0:9b334a45a8ff | 277 | #elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ |
| mbed_official | 19:112740acecfa | 278 | defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ |
| mbed_official | 19:112740acecfa | 279 | defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \ |
| mbed_official | 19:112740acecfa | 280 | defined(STM32F479xx) |
| bogdanm | 0:9b334a45a8ff | 281 | /** |
| bogdanm | 0:9b334a45a8ff | 282 | * @brief Configures the main internal regulator output voltage. |
| bogdanm | 0:9b334a45a8ff | 283 | * @param VoltageScaling: specifies the regulator output voltage to achieve |
| bogdanm | 0:9b334a45a8ff | 284 | * a tradeoff between performance and power consumption. |
| bogdanm | 0:9b334a45a8ff | 285 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 286 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, |
| bogdanm | 0:9b334a45a8ff | 287 | * the maximum value of fHCLK is 168 MHz. It can be extended to |
| bogdanm | 0:9b334a45a8ff | 288 | * 180 MHz by activating the over-drive mode. |
| bogdanm | 0:9b334a45a8ff | 289 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, |
| bogdanm | 0:9b334a45a8ff | 290 | * the maximum value of fHCLK is 144 MHz. It can be extended to, |
| bogdanm | 0:9b334a45a8ff | 291 | * 168 MHz by activating the over-drive mode. |
| bogdanm | 0:9b334a45a8ff | 292 | * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode, |
| bogdanm | 0:9b334a45a8ff | 293 | * the maximum value of fHCLK is 120 MHz. |
| bogdanm | 0:9b334a45a8ff | 294 | * @note To update the system clock frequency(SYSCLK): |
| bogdanm | 0:9b334a45a8ff | 295 | * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). |
| bogdanm | 0:9b334a45a8ff | 296 | * - Call the HAL_RCC_OscConfig() to configure the PLL. |
| bogdanm | 0:9b334a45a8ff | 297 | * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. |
| bogdanm | 0:9b334a45a8ff | 298 | * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). |
| bogdanm | 0:9b334a45a8ff | 299 | * @note The scale can be modified only when the HSI or HSE clock source is selected |
| bogdanm | 0:9b334a45a8ff | 300 | * as system clock source, otherwise the API returns HAL_ERROR. |
| bogdanm | 0:9b334a45a8ff | 301 | * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits |
| bogdanm | 0:9b334a45a8ff | 302 | * value in the PWR_CR1 register are not taken in account. |
| bogdanm | 0:9b334a45a8ff | 303 | * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. |
| bogdanm | 0:9b334a45a8ff | 304 | * @note The new voltage scale is active only when the PLL is ON. |
| bogdanm | 0:9b334a45a8ff | 305 | * @retval HAL Status |
| bogdanm | 0:9b334a45a8ff | 306 | */ |
| bogdanm | 0:9b334a45a8ff | 307 | HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) |
| bogdanm | 0:9b334a45a8ff | 308 | { |
| bogdanm | 0:9b334a45a8ff | 309 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 310 | |
| bogdanm | 0:9b334a45a8ff | 311 | assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); |
| bogdanm | 0:9b334a45a8ff | 312 | |
| bogdanm | 0:9b334a45a8ff | 313 | /* Enable PWR RCC Clock Peripheral */ |
| bogdanm | 0:9b334a45a8ff | 314 | __HAL_RCC_PWR_CLK_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 315 | |
| bogdanm | 0:9b334a45a8ff | 316 | /* Check if the PLL is used as system clock or not */ |
| bogdanm | 0:9b334a45a8ff | 317 | if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) |
| bogdanm | 0:9b334a45a8ff | 318 | { |
| bogdanm | 0:9b334a45a8ff | 319 | /* Disable the main PLL */ |
| bogdanm | 0:9b334a45a8ff | 320 | __HAL_RCC_PLL_DISABLE(); |
| bogdanm | 0:9b334a45a8ff | 321 | |
| bogdanm | 0:9b334a45a8ff | 322 | /* Get Start Tick */ |
| bogdanm | 0:9b334a45a8ff | 323 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 324 | /* Wait till PLL is disabled */ |
| bogdanm | 0:9b334a45a8ff | 325 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) |
| bogdanm | 0:9b334a45a8ff | 326 | { |
| bogdanm | 0:9b334a45a8ff | 327 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 328 | { |
| bogdanm | 0:9b334a45a8ff | 329 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 330 | } |
| bogdanm | 0:9b334a45a8ff | 331 | } |
| bogdanm | 0:9b334a45a8ff | 332 | |
| bogdanm | 0:9b334a45a8ff | 333 | /* Set Range */ |
| bogdanm | 0:9b334a45a8ff | 334 | __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); |
| bogdanm | 0:9b334a45a8ff | 335 | |
| bogdanm | 0:9b334a45a8ff | 336 | /* Enable the main PLL */ |
| bogdanm | 0:9b334a45a8ff | 337 | __HAL_RCC_PLL_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 338 | |
| bogdanm | 0:9b334a45a8ff | 339 | /* Get Start Tick */ |
| bogdanm | 0:9b334a45a8ff | 340 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 341 | /* Wait till PLL is ready */ |
| bogdanm | 0:9b334a45a8ff | 342 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
| bogdanm | 0:9b334a45a8ff | 343 | { |
| bogdanm | 0:9b334a45a8ff | 344 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 345 | { |
| bogdanm | 0:9b334a45a8ff | 346 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 347 | } |
| bogdanm | 0:9b334a45a8ff | 348 | } |
| bogdanm | 0:9b334a45a8ff | 349 | |
| bogdanm | 0:9b334a45a8ff | 350 | /* Get Start Tick */ |
| bogdanm | 0:9b334a45a8ff | 351 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 352 | while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) |
| bogdanm | 0:9b334a45a8ff | 353 | { |
| bogdanm | 0:9b334a45a8ff | 354 | if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 355 | { |
| bogdanm | 0:9b334a45a8ff | 356 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 357 | } |
| bogdanm | 0:9b334a45a8ff | 358 | } |
| bogdanm | 0:9b334a45a8ff | 359 | } |
| bogdanm | 0:9b334a45a8ff | 360 | else |
| bogdanm | 0:9b334a45a8ff | 361 | { |
| bogdanm | 0:9b334a45a8ff | 362 | return HAL_ERROR; |
| bogdanm | 0:9b334a45a8ff | 363 | } |
| bogdanm | 0:9b334a45a8ff | 364 | |
| bogdanm | 0:9b334a45a8ff | 365 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 366 | } |
| bogdanm | 0:9b334a45a8ff | 367 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| bogdanm | 0:9b334a45a8ff | 368 | |
| mbed_official | 19:112740acecfa | 369 | #if defined(STM32F469xx) || defined(STM32F479xx) |
| mbed_official | 19:112740acecfa | 370 | /** |
| mbed_official | 19:112740acecfa | 371 | * @brief Enables Wakeup Pin Detection on high level (rising edge). |
| mbed_official | 19:112740acecfa | 372 | * @retval None |
| mbed_official | 19:112740acecfa | 373 | */ |
| mbed_official | 19:112740acecfa | 374 | void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void) |
| mbed_official | 19:112740acecfa | 375 | { |
| mbed_official | 19:112740acecfa | 376 | *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE; |
| mbed_official | 19:112740acecfa | 377 | } |
| mbed_official | 19:112740acecfa | 378 | |
| mbed_official | 19:112740acecfa | 379 | /** |
| mbed_official | 19:112740acecfa | 380 | * @brief Enables Wakeup Pin Detection on low level (falling edge). |
| mbed_official | 19:112740acecfa | 381 | * @retval None |
| mbed_official | 19:112740acecfa | 382 | */ |
| mbed_official | 19:112740acecfa | 383 | void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void) |
| mbed_official | 19:112740acecfa | 384 | { |
| mbed_official | 19:112740acecfa | 385 | *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE; |
| mbed_official | 19:112740acecfa | 386 | } |
| mbed_official | 19:112740acecfa | 387 | #endif /* STM32F469xx || STM32F479xx */ |
| mbed_official | 19:112740acecfa | 388 | |
| mbed_official | 19:112740acecfa | 389 | #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ |
| mbed_official | 19:112740acecfa | 390 | defined(STM32F411xE) |
| bogdanm | 0:9b334a45a8ff | 391 | /** |
| bogdanm | 0:9b334a45a8ff | 392 | * @brief Enables Main Regulator low voltage mode. |
| mbed_official | 19:112740acecfa | 393 | * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices. |
| bogdanm | 0:9b334a45a8ff | 394 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 395 | */ |
| bogdanm | 0:9b334a45a8ff | 396 | void HAL_PWREx_EnableMainRegulatorLowVoltage(void) |
| bogdanm | 0:9b334a45a8ff | 397 | { |
| bogdanm | 0:9b334a45a8ff | 398 | *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; |
| bogdanm | 0:9b334a45a8ff | 399 | } |
| bogdanm | 0:9b334a45a8ff | 400 | |
| bogdanm | 0:9b334a45a8ff | 401 | /** |
| bogdanm | 0:9b334a45a8ff | 402 | * @brief Disables Main Regulator low voltage mode. |
| mbed_official | 19:112740acecfa | 403 | * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices. |
| bogdanm | 0:9b334a45a8ff | 404 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 405 | */ |
| bogdanm | 0:9b334a45a8ff | 406 | void HAL_PWREx_DisableMainRegulatorLowVoltage(void) |
| bogdanm | 0:9b334a45a8ff | 407 | { |
| bogdanm | 0:9b334a45a8ff | 408 | *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE; |
| bogdanm | 0:9b334a45a8ff | 409 | } |
| bogdanm | 0:9b334a45a8ff | 410 | |
| bogdanm | 0:9b334a45a8ff | 411 | /** |
| bogdanm | 0:9b334a45a8ff | 412 | * @brief Enables Low Power Regulator low voltage mode. |
| mbed_official | 19:112740acecfa | 413 | * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices. |
| bogdanm | 0:9b334a45a8ff | 414 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 415 | */ |
| bogdanm | 0:9b334a45a8ff | 416 | void HAL_PWREx_EnableLowRegulatorLowVoltage(void) |
| bogdanm | 0:9b334a45a8ff | 417 | { |
| bogdanm | 0:9b334a45a8ff | 418 | *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; |
| bogdanm | 0:9b334a45a8ff | 419 | } |
| bogdanm | 0:9b334a45a8ff | 420 | |
| bogdanm | 0:9b334a45a8ff | 421 | /** |
| bogdanm | 0:9b334a45a8ff | 422 | * @brief Disables Low Power Regulator low voltage mode. |
| mbed_official | 19:112740acecfa | 423 | * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx devices. |
| bogdanm | 0:9b334a45a8ff | 424 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 425 | */ |
| bogdanm | 0:9b334a45a8ff | 426 | void HAL_PWREx_DisableLowRegulatorLowVoltage(void) |
| bogdanm | 0:9b334a45a8ff | 427 | { |
| bogdanm | 0:9b334a45a8ff | 428 | *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; |
| bogdanm | 0:9b334a45a8ff | 429 | } |
| bogdanm | 0:9b334a45a8ff | 430 | |
| mbed_official | 19:112740acecfa | 431 | #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE */ |
| bogdanm | 0:9b334a45a8ff | 432 | |
| mbed_official | 19:112740acecfa | 433 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
| mbed_official | 19:112740acecfa | 434 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| bogdanm | 0:9b334a45a8ff | 435 | /** |
| bogdanm | 0:9b334a45a8ff | 436 | * @brief Activates the Over-Drive mode. |
| mbed_official | 19:112740acecfa | 437 | * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. |
| bogdanm | 0:9b334a45a8ff | 438 | * This mode allows the CPU and the core logic to operate at a higher frequency |
| bogdanm | 0:9b334a45a8ff | 439 | * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). |
| bogdanm | 0:9b334a45a8ff | 440 | * @note It is recommended to enter or exit Over-drive mode when the application is not running |
| bogdanm | 0:9b334a45a8ff | 441 | * critical tasks and when the system clock source is either HSI or HSE. |
| bogdanm | 0:9b334a45a8ff | 442 | * During the Over-drive switch activation, no peripheral clocks should be enabled. |
| bogdanm | 0:9b334a45a8ff | 443 | * The peripheral clocks must be enabled once the Over-drive mode is activated. |
| bogdanm | 0:9b334a45a8ff | 444 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 445 | */ |
| bogdanm | 0:9b334a45a8ff | 446 | HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) |
| bogdanm | 0:9b334a45a8ff | 447 | { |
| bogdanm | 0:9b334a45a8ff | 448 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 449 | |
| bogdanm | 0:9b334a45a8ff | 450 | __HAL_RCC_PWR_CLK_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 451 | |
| bogdanm | 0:9b334a45a8ff | 452 | /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ |
| bogdanm | 0:9b334a45a8ff | 453 | __HAL_PWR_OVERDRIVE_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 454 | |
| bogdanm | 0:9b334a45a8ff | 455 | /* Get tick */ |
| bogdanm | 0:9b334a45a8ff | 456 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 457 | |
| bogdanm | 0:9b334a45a8ff | 458 | while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) |
| bogdanm | 0:9b334a45a8ff | 459 | { |
| bogdanm | 0:9b334a45a8ff | 460 | if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 461 | { |
| bogdanm | 0:9b334a45a8ff | 462 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 463 | } |
| bogdanm | 0:9b334a45a8ff | 464 | } |
| bogdanm | 0:9b334a45a8ff | 465 | |
| bogdanm | 0:9b334a45a8ff | 466 | /* Enable the Over-drive switch */ |
| bogdanm | 0:9b334a45a8ff | 467 | __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 468 | |
| bogdanm | 0:9b334a45a8ff | 469 | /* Get tick */ |
| bogdanm | 0:9b334a45a8ff | 470 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 471 | |
| bogdanm | 0:9b334a45a8ff | 472 | while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) |
| bogdanm | 0:9b334a45a8ff | 473 | { |
| bogdanm | 0:9b334a45a8ff | 474 | if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 475 | { |
| bogdanm | 0:9b334a45a8ff | 476 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 477 | } |
| bogdanm | 0:9b334a45a8ff | 478 | } |
| bogdanm | 0:9b334a45a8ff | 479 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 480 | } |
| bogdanm | 0:9b334a45a8ff | 481 | |
| bogdanm | 0:9b334a45a8ff | 482 | /** |
| bogdanm | 0:9b334a45a8ff | 483 | * @brief Deactivates the Over-Drive mode. |
| mbed_official | 19:112740acecfa | 484 | * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. |
| bogdanm | 0:9b334a45a8ff | 485 | * This mode allows the CPU and the core logic to operate at a higher frequency |
| bogdanm | 0:9b334a45a8ff | 486 | * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). |
| bogdanm | 0:9b334a45a8ff | 487 | * @note It is recommended to enter or exit Over-drive mode when the application is not running |
| bogdanm | 0:9b334a45a8ff | 488 | * critical tasks and when the system clock source is either HSI or HSE. |
| bogdanm | 0:9b334a45a8ff | 489 | * During the Over-drive switch activation, no peripheral clocks should be enabled. |
| bogdanm | 0:9b334a45a8ff | 490 | * The peripheral clocks must be enabled once the Over-drive mode is activated. |
| bogdanm | 0:9b334a45a8ff | 491 | * @retval HAL status |
| bogdanm | 0:9b334a45a8ff | 492 | */ |
| bogdanm | 0:9b334a45a8ff | 493 | HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) |
| bogdanm | 0:9b334a45a8ff | 494 | { |
| bogdanm | 0:9b334a45a8ff | 495 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 496 | |
| bogdanm | 0:9b334a45a8ff | 497 | __HAL_RCC_PWR_CLK_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 498 | |
| bogdanm | 0:9b334a45a8ff | 499 | /* Disable the Over-drive switch */ |
| bogdanm | 0:9b334a45a8ff | 500 | __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); |
| bogdanm | 0:9b334a45a8ff | 501 | |
| bogdanm | 0:9b334a45a8ff | 502 | /* Get tick */ |
| bogdanm | 0:9b334a45a8ff | 503 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 504 | |
| bogdanm | 0:9b334a45a8ff | 505 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) |
| bogdanm | 0:9b334a45a8ff | 506 | { |
| bogdanm | 0:9b334a45a8ff | 507 | if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 508 | { |
| bogdanm | 0:9b334a45a8ff | 509 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 510 | } |
| bogdanm | 0:9b334a45a8ff | 511 | } |
| bogdanm | 0:9b334a45a8ff | 512 | |
| bogdanm | 0:9b334a45a8ff | 513 | /* Disable the Over-drive */ |
| bogdanm | 0:9b334a45a8ff | 514 | __HAL_PWR_OVERDRIVE_DISABLE(); |
| bogdanm | 0:9b334a45a8ff | 515 | |
| bogdanm | 0:9b334a45a8ff | 516 | /* Get tick */ |
| bogdanm | 0:9b334a45a8ff | 517 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 518 | |
| bogdanm | 0:9b334a45a8ff | 519 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) |
| bogdanm | 0:9b334a45a8ff | 520 | { |
| bogdanm | 0:9b334a45a8ff | 521 | if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 522 | { |
| bogdanm | 0:9b334a45a8ff | 523 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 524 | } |
| bogdanm | 0:9b334a45a8ff | 525 | } |
| bogdanm | 0:9b334a45a8ff | 526 | |
| bogdanm | 0:9b334a45a8ff | 527 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 528 | } |
| bogdanm | 0:9b334a45a8ff | 529 | |
| bogdanm | 0:9b334a45a8ff | 530 | /** |
| bogdanm | 0:9b334a45a8ff | 531 | * @brief Enters in Under-Drive STOP mode. |
| bogdanm | 0:9b334a45a8ff | 532 | * |
| mbed_official | 19:112740acecfa | 533 | * @note This mode is only available for STM32F42xxx/STM324F3xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. |
| bogdanm | 0:9b334a45a8ff | 534 | * |
| bogdanm | 0:9b334a45a8ff | 535 | * @note This mode can be selected only when the Under-Drive is already active |
| bogdanm | 0:9b334a45a8ff | 536 | * |
| bogdanm | 0:9b334a45a8ff | 537 | * @note This mode is enabled only with STOP low power mode. |
| bogdanm | 0:9b334a45a8ff | 538 | * In this mode, the 1.2V domain is preserved in reduced leakage mode. This |
| bogdanm | 0:9b334a45a8ff | 539 | * mode is only available when the main regulator or the low power regulator |
| bogdanm | 0:9b334a45a8ff | 540 | * is in low voltage mode |
| bogdanm | 0:9b334a45a8ff | 541 | * |
| bogdanm | 0:9b334a45a8ff | 542 | * @note If the Under-drive mode was enabled, it is automatically disabled after |
| bogdanm | 0:9b334a45a8ff | 543 | * exiting Stop mode. |
| bogdanm | 0:9b334a45a8ff | 544 | * When the voltage regulator operates in Under-drive mode, an additional |
| bogdanm | 0:9b334a45a8ff | 545 | * startup delay is induced when waking up from Stop mode. |
| bogdanm | 0:9b334a45a8ff | 546 | * |
| bogdanm | 0:9b334a45a8ff | 547 | * @note In Stop mode, all I/O pins keep the same state as in Run mode. |
| bogdanm | 0:9b334a45a8ff | 548 | * |
| bogdanm | 0:9b334a45a8ff | 549 | * @note When exiting Stop mode by issuing an interrupt or a wake-up event, |
| bogdanm | 0:9b334a45a8ff | 550 | * the HSI RC oscillator is selected as system clock. |
| bogdanm | 0:9b334a45a8ff | 551 | * |
| bogdanm | 0:9b334a45a8ff | 552 | * @note When the voltage regulator operates in low power mode, an additional |
| bogdanm | 0:9b334a45a8ff | 553 | * startup delay is incurred when waking up from Stop mode. |
| bogdanm | 0:9b334a45a8ff | 554 | * By keeping the internal regulator ON during Stop mode, the consumption |
| bogdanm | 0:9b334a45a8ff | 555 | * is higher although the startup time is reduced. |
| bogdanm | 0:9b334a45a8ff | 556 | * |
| bogdanm | 0:9b334a45a8ff | 557 | * @param Regulator: specifies the regulator state in STOP mode. |
| bogdanm | 0:9b334a45a8ff | 558 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 559 | * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode |
| bogdanm | 0:9b334a45a8ff | 560 | * and Flash memory in power-down when the device is in Stop under-drive mode |
| bogdanm | 0:9b334a45a8ff | 561 | * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode |
| bogdanm | 0:9b334a45a8ff | 562 | * and Flash memory in power-down when the device is in Stop under-drive mode |
| bogdanm | 0:9b334a45a8ff | 563 | * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. |
| bogdanm | 0:9b334a45a8ff | 564 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 565 | * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction |
| bogdanm | 0:9b334a45a8ff | 566 | * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction |
| bogdanm | 0:9b334a45a8ff | 567 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 568 | */ |
| bogdanm | 0:9b334a45a8ff | 569 | HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) |
| bogdanm | 0:9b334a45a8ff | 570 | { |
| bogdanm | 0:9b334a45a8ff | 571 | uint32_t tmpreg1 = 0; |
| bogdanm | 0:9b334a45a8ff | 572 | uint32_t tickstart = 0; |
| bogdanm | 0:9b334a45a8ff | 573 | |
| bogdanm | 0:9b334a45a8ff | 574 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 575 | assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); |
| bogdanm | 0:9b334a45a8ff | 576 | assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
| bogdanm | 0:9b334a45a8ff | 577 | |
| bogdanm | 0:9b334a45a8ff | 578 | /* Enable Power ctrl clock */ |
| bogdanm | 0:9b334a45a8ff | 579 | __HAL_RCC_PWR_CLK_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 580 | /* Enable the Under-drive Mode ---------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 581 | /* Clear Under-drive flag */ |
| bogdanm | 0:9b334a45a8ff | 582 | __HAL_PWR_CLEAR_ODRUDR_FLAG(); |
| bogdanm | 0:9b334a45a8ff | 583 | |
| bogdanm | 0:9b334a45a8ff | 584 | /* Enable the Under-drive */ |
| bogdanm | 0:9b334a45a8ff | 585 | __HAL_PWR_UNDERDRIVE_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 586 | |
| bogdanm | 0:9b334a45a8ff | 587 | /* Get tick */ |
| bogdanm | 0:9b334a45a8ff | 588 | tickstart = HAL_GetTick(); |
| bogdanm | 0:9b334a45a8ff | 589 | |
| bogdanm | 0:9b334a45a8ff | 590 | /* Wait for UnderDrive mode is ready */ |
| bogdanm | 0:9b334a45a8ff | 591 | while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY)) |
| bogdanm | 0:9b334a45a8ff | 592 | { |
| bogdanm | 0:9b334a45a8ff | 593 | if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE) |
| bogdanm | 0:9b334a45a8ff | 594 | { |
| bogdanm | 0:9b334a45a8ff | 595 | return HAL_TIMEOUT; |
| bogdanm | 0:9b334a45a8ff | 596 | } |
| bogdanm | 0:9b334a45a8ff | 597 | } |
| bogdanm | 0:9b334a45a8ff | 598 | |
| bogdanm | 0:9b334a45a8ff | 599 | /* Select the regulator state in STOP mode ---------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 600 | tmpreg1 = PWR->CR; |
| bogdanm | 0:9b334a45a8ff | 601 | /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ |
| bogdanm | 0:9b334a45a8ff | 602 | tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS); |
| bogdanm | 0:9b334a45a8ff | 603 | |
| bogdanm | 0:9b334a45a8ff | 604 | /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ |
| bogdanm | 0:9b334a45a8ff | 605 | tmpreg1 |= Regulator; |
| bogdanm | 0:9b334a45a8ff | 606 | |
| bogdanm | 0:9b334a45a8ff | 607 | /* Store the new value */ |
| bogdanm | 0:9b334a45a8ff | 608 | PWR->CR = tmpreg1; |
| bogdanm | 0:9b334a45a8ff | 609 | |
| bogdanm | 0:9b334a45a8ff | 610 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
| bogdanm | 0:9b334a45a8ff | 611 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
| bogdanm | 0:9b334a45a8ff | 612 | |
| bogdanm | 0:9b334a45a8ff | 613 | /* Select STOP mode entry --------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 614 | if(STOPEntry == PWR_SLEEPENTRY_WFI) |
| bogdanm | 0:9b334a45a8ff | 615 | { |
| bogdanm | 0:9b334a45a8ff | 616 | /* Request Wait For Interrupt */ |
| bogdanm | 0:9b334a45a8ff | 617 | __WFI(); |
| bogdanm | 0:9b334a45a8ff | 618 | } |
| bogdanm | 0:9b334a45a8ff | 619 | else |
| bogdanm | 0:9b334a45a8ff | 620 | { |
| bogdanm | 0:9b334a45a8ff | 621 | /* Request Wait For Event */ |
| bogdanm | 0:9b334a45a8ff | 622 | __WFE(); |
| bogdanm | 0:9b334a45a8ff | 623 | } |
| bogdanm | 0:9b334a45a8ff | 624 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ |
| bogdanm | 0:9b334a45a8ff | 625 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); |
| bogdanm | 0:9b334a45a8ff | 626 | |
| bogdanm | 0:9b334a45a8ff | 627 | return HAL_OK; |
| bogdanm | 0:9b334a45a8ff | 628 | } |
| bogdanm | 0:9b334a45a8ff | 629 | |
| mbed_official | 19:112740acecfa | 630 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
| bogdanm | 0:9b334a45a8ff | 631 | /** |
| bogdanm | 0:9b334a45a8ff | 632 | * @} |
| bogdanm | 0:9b334a45a8ff | 633 | */ |
| bogdanm | 0:9b334a45a8ff | 634 | |
| bogdanm | 0:9b334a45a8ff | 635 | /** |
| bogdanm | 0:9b334a45a8ff | 636 | * @} |
| bogdanm | 0:9b334a45a8ff | 637 | */ |
| bogdanm | 0:9b334a45a8ff | 638 | |
| bogdanm | 0:9b334a45a8ff | 639 | #endif /* HAL_PWR_MODULE_ENABLED */ |
| bogdanm | 0:9b334a45a8ff | 640 | /** |
| bogdanm | 0:9b334a45a8ff | 641 | * @} |
| bogdanm | 0:9b334a45a8ff | 642 | */ |
| bogdanm | 0:9b334a45a8ff | 643 | |
| bogdanm | 0:9b334a45a8ff | 644 | /** |
| bogdanm | 0:9b334a45a8ff | 645 | * @} |
| bogdanm | 0:9b334a45a8ff | 646 | */ |
| bogdanm | 0:9b334a45a8ff | 647 | |
| bogdanm | 0:9b334a45a8ff | 648 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |