fix LPC812 PWM
Fork of mbed-dev by
targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.c@129:2e517c56bcfb, 2016-05-16 (annotated)
- Committer:
- nameless129
- Date:
- Mon May 16 16:50:30 2016 +0000
- Revision:
- 129:2e517c56bcfb
- Parent:
- 19:112740acecfa
PWM Fix:Duty 0%??H???????????????
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /** |
bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f4xx_hal_nand.c |
bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
mbed_official | 19:112740acecfa | 5 | * @version V1.4.1 |
mbed_official | 19:112740acecfa | 6 | * @date 09-October-2015 |
bogdanm | 0:9b334a45a8ff | 7 | * @brief NAND HAL module driver. |
bogdanm | 0:9b334a45a8ff | 8 | * This file provides a generic firmware to drive NAND memories mounted |
bogdanm | 0:9b334a45a8ff | 9 | * as external device. |
bogdanm | 0:9b334a45a8ff | 10 | * |
bogdanm | 0:9b334a45a8ff | 11 | @verbatim |
bogdanm | 0:9b334a45a8ff | 12 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 13 | ##### How to use this driver ##### |
bogdanm | 0:9b334a45a8ff | 14 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 15 | [..] |
bogdanm | 0:9b334a45a8ff | 16 | This driver is a generic layered driver which contains a set of APIs used to |
bogdanm | 0:9b334a45a8ff | 17 | control NAND flash memories. It uses the FMC/FSMC layer functions to interface |
bogdanm | 0:9b334a45a8ff | 18 | with NAND devices. This driver is used as follows: |
bogdanm | 0:9b334a45a8ff | 19 | |
bogdanm | 0:9b334a45a8ff | 20 | (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() |
bogdanm | 0:9b334a45a8ff | 21 | with control and timing parameters for both common and attribute spaces. |
bogdanm | 0:9b334a45a8ff | 22 | |
bogdanm | 0:9b334a45a8ff | 23 | (+) Read NAND flash memory maker and device IDs using the function |
bogdanm | 0:9b334a45a8ff | 24 | HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef |
bogdanm | 0:9b334a45a8ff | 25 | structure declared by the function caller. |
bogdanm | 0:9b334a45a8ff | 26 | |
bogdanm | 0:9b334a45a8ff | 27 | (+) Access NAND flash memory by read/write operations using the functions |
bogdanm | 0:9b334a45a8ff | 28 | HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea() |
bogdanm | 0:9b334a45a8ff | 29 | to read/write page(s)/spare area(s). These functions use specific device |
bogdanm | 0:9b334a45a8ff | 30 | information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef |
bogdanm | 0:9b334a45a8ff | 31 | structure. The read/write address information is contained by the Nand_Address_Typedef |
bogdanm | 0:9b334a45a8ff | 32 | structure passed as parameter. |
bogdanm | 0:9b334a45a8ff | 33 | |
bogdanm | 0:9b334a45a8ff | 34 | (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset(). |
bogdanm | 0:9b334a45a8ff | 35 | |
bogdanm | 0:9b334a45a8ff | 36 | (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block(). |
bogdanm | 0:9b334a45a8ff | 37 | The erase block address information is contained in the Nand_Address_Typedef |
bogdanm | 0:9b334a45a8ff | 38 | structure passed as parameter. |
bogdanm | 0:9b334a45a8ff | 39 | |
bogdanm | 0:9b334a45a8ff | 40 | (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status(). |
bogdanm | 0:9b334a45a8ff | 41 | |
bogdanm | 0:9b334a45a8ff | 42 | (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/ |
bogdanm | 0:9b334a45a8ff | 43 | HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction |
bogdanm | 0:9b334a45a8ff | 44 | feature or the function HAL_NAND_GetECC() to get the ECC correction code. |
bogdanm | 0:9b334a45a8ff | 45 | |
bogdanm | 0:9b334a45a8ff | 46 | (+) You can monitor the NAND device HAL state by calling the function |
bogdanm | 0:9b334a45a8ff | 47 | HAL_NAND_GetState() |
bogdanm | 0:9b334a45a8ff | 48 | |
bogdanm | 0:9b334a45a8ff | 49 | [..] |
bogdanm | 0:9b334a45a8ff | 50 | (@) This driver is a set of generic APIs which handle standard NAND flash operations. |
bogdanm | 0:9b334a45a8ff | 51 | If a NAND flash device contains different operations and/or implementations, |
bogdanm | 0:9b334a45a8ff | 52 | it should be implemented separately. |
bogdanm | 0:9b334a45a8ff | 53 | |
bogdanm | 0:9b334a45a8ff | 54 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 55 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 56 | * @attention |
bogdanm | 0:9b334a45a8ff | 57 | * |
bogdanm | 0:9b334a45a8ff | 58 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
bogdanm | 0:9b334a45a8ff | 59 | * |
bogdanm | 0:9b334a45a8ff | 60 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 0:9b334a45a8ff | 61 | * are permitted provided that the following conditions are met: |
bogdanm | 0:9b334a45a8ff | 62 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 63 | * this list of conditions and the following disclaimer. |
bogdanm | 0:9b334a45a8ff | 64 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 65 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 0:9b334a45a8ff | 66 | * and/or other materials provided with the distribution. |
bogdanm | 0:9b334a45a8ff | 67 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 0:9b334a45a8ff | 68 | * may be used to endorse or promote products derived from this software |
bogdanm | 0:9b334a45a8ff | 69 | * without specific prior written permission. |
bogdanm | 0:9b334a45a8ff | 70 | * |
bogdanm | 0:9b334a45a8ff | 71 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 0:9b334a45a8ff | 72 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 0:9b334a45a8ff | 73 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 0:9b334a45a8ff | 74 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 0:9b334a45a8ff | 75 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 0:9b334a45a8ff | 76 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 0:9b334a45a8ff | 77 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 0:9b334a45a8ff | 78 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 0:9b334a45a8ff | 79 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 0:9b334a45a8ff | 80 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 0:9b334a45a8ff | 81 | * |
bogdanm | 0:9b334a45a8ff | 82 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 83 | */ |
bogdanm | 0:9b334a45a8ff | 84 | |
bogdanm | 0:9b334a45a8ff | 85 | /* Includes ------------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 86 | #include "stm32f4xx_hal.h" |
bogdanm | 0:9b334a45a8ff | 87 | |
bogdanm | 0:9b334a45a8ff | 88 | /** @addtogroup STM32F4xx_HAL_Driver |
bogdanm | 0:9b334a45a8ff | 89 | * @{ |
bogdanm | 0:9b334a45a8ff | 90 | */ |
bogdanm | 0:9b334a45a8ff | 91 | |
bogdanm | 0:9b334a45a8ff | 92 | |
bogdanm | 0:9b334a45a8ff | 93 | #ifdef HAL_NAND_MODULE_ENABLED |
bogdanm | 0:9b334a45a8ff | 94 | |
bogdanm | 0:9b334a45a8ff | 95 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ |
bogdanm | 0:9b334a45a8ff | 96 | defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
mbed_official | 19:112740acecfa | 97 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
bogdanm | 0:9b334a45a8ff | 98 | |
bogdanm | 0:9b334a45a8ff | 99 | /** @defgroup NAND NAND |
bogdanm | 0:9b334a45a8ff | 100 | * @brief NAND HAL module driver |
bogdanm | 0:9b334a45a8ff | 101 | * @{ |
bogdanm | 0:9b334a45a8ff | 102 | */ |
bogdanm | 0:9b334a45a8ff | 103 | |
bogdanm | 0:9b334a45a8ff | 104 | /* Private typedef -----------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 105 | /* Private define ------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 106 | /** @defgroup NAND_Private_Constants NAND Private Constants |
bogdanm | 0:9b334a45a8ff | 107 | * @{ |
bogdanm | 0:9b334a45a8ff | 108 | */ |
bogdanm | 0:9b334a45a8ff | 109 | |
bogdanm | 0:9b334a45a8ff | 110 | /** |
bogdanm | 0:9b334a45a8ff | 111 | * @} |
bogdanm | 0:9b334a45a8ff | 112 | */ |
bogdanm | 0:9b334a45a8ff | 113 | |
bogdanm | 0:9b334a45a8ff | 114 | /* Private macro -------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 115 | /** @defgroup NAND_Private_Macros NAND Private Macros |
bogdanm | 0:9b334a45a8ff | 116 | * @{ |
bogdanm | 0:9b334a45a8ff | 117 | */ |
bogdanm | 0:9b334a45a8ff | 118 | |
bogdanm | 0:9b334a45a8ff | 119 | /** |
bogdanm | 0:9b334a45a8ff | 120 | * @} |
bogdanm | 0:9b334a45a8ff | 121 | */ |
bogdanm | 0:9b334a45a8ff | 122 | /* Private variables ---------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 123 | /* Private function prototypes -----------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 124 | /* Exported functions --------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 125 | /** @defgroup NAND_Exported_Functions NAND Exported Functions |
bogdanm | 0:9b334a45a8ff | 126 | * @{ |
bogdanm | 0:9b334a45a8ff | 127 | */ |
bogdanm | 0:9b334a45a8ff | 128 | |
bogdanm | 0:9b334a45a8ff | 129 | /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
bogdanm | 0:9b334a45a8ff | 130 | * @brief Initialization and Configuration functions |
bogdanm | 0:9b334a45a8ff | 131 | * |
bogdanm | 0:9b334a45a8ff | 132 | @verbatim |
bogdanm | 0:9b334a45a8ff | 133 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 134 | ##### NAND Initialization and de-initialization functions ##### |
bogdanm | 0:9b334a45a8ff | 135 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 136 | [..] |
bogdanm | 0:9b334a45a8ff | 137 | This section provides functions allowing to initialize/de-initialize |
bogdanm | 0:9b334a45a8ff | 138 | the NAND memory |
bogdanm | 0:9b334a45a8ff | 139 | |
bogdanm | 0:9b334a45a8ff | 140 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 141 | * @{ |
bogdanm | 0:9b334a45a8ff | 142 | */ |
bogdanm | 0:9b334a45a8ff | 143 | |
bogdanm | 0:9b334a45a8ff | 144 | /** |
bogdanm | 0:9b334a45a8ff | 145 | * @brief Perform NAND memory Initialization sequence |
bogdanm | 0:9b334a45a8ff | 146 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 147 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 148 | * @param ComSpace_Timing: pointer to Common space timing structure |
bogdanm | 0:9b334a45a8ff | 149 | * @param AttSpace_Timing: pointer to Attribute space timing structure |
bogdanm | 0:9b334a45a8ff | 150 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 151 | */ |
bogdanm | 0:9b334a45a8ff | 152 | HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) |
bogdanm | 0:9b334a45a8ff | 153 | { |
bogdanm | 0:9b334a45a8ff | 154 | /* Check the NAND handle state */ |
bogdanm | 0:9b334a45a8ff | 155 | if(hnand == NULL) |
bogdanm | 0:9b334a45a8ff | 156 | { |
bogdanm | 0:9b334a45a8ff | 157 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 158 | } |
bogdanm | 0:9b334a45a8ff | 159 | |
bogdanm | 0:9b334a45a8ff | 160 | if(hnand->State == HAL_NAND_STATE_RESET) |
bogdanm | 0:9b334a45a8ff | 161 | { |
bogdanm | 0:9b334a45a8ff | 162 | /* Allocate lock resource and initialize it */ |
bogdanm | 0:9b334a45a8ff | 163 | hnand->Lock = HAL_UNLOCKED; |
bogdanm | 0:9b334a45a8ff | 164 | /* Initialize the low level hardware (MSP) */ |
bogdanm | 0:9b334a45a8ff | 165 | HAL_NAND_MspInit(hnand); |
bogdanm | 0:9b334a45a8ff | 166 | } |
bogdanm | 0:9b334a45a8ff | 167 | |
bogdanm | 0:9b334a45a8ff | 168 | /* Initialize NAND control Interface */ |
bogdanm | 0:9b334a45a8ff | 169 | FMC_NAND_Init(hnand->Instance, &(hnand->Init)); |
bogdanm | 0:9b334a45a8ff | 170 | |
bogdanm | 0:9b334a45a8ff | 171 | /* Initialize NAND common space timing Interface */ |
bogdanm | 0:9b334a45a8ff | 172 | FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank); |
bogdanm | 0:9b334a45a8ff | 173 | |
bogdanm | 0:9b334a45a8ff | 174 | /* Initialize NAND attribute space timing Interface */ |
bogdanm | 0:9b334a45a8ff | 175 | FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank); |
bogdanm | 0:9b334a45a8ff | 176 | |
bogdanm | 0:9b334a45a8ff | 177 | /* Enable the NAND device */ |
bogdanm | 0:9b334a45a8ff | 178 | __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank); |
bogdanm | 0:9b334a45a8ff | 179 | |
bogdanm | 0:9b334a45a8ff | 180 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 181 | hnand->State = HAL_NAND_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 182 | |
bogdanm | 0:9b334a45a8ff | 183 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 184 | } |
bogdanm | 0:9b334a45a8ff | 185 | |
bogdanm | 0:9b334a45a8ff | 186 | /** |
bogdanm | 0:9b334a45a8ff | 187 | * @brief Perform NAND memory De-Initialization sequence |
bogdanm | 0:9b334a45a8ff | 188 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 189 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 190 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 191 | */ |
bogdanm | 0:9b334a45a8ff | 192 | HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) |
bogdanm | 0:9b334a45a8ff | 193 | { |
bogdanm | 0:9b334a45a8ff | 194 | /* Initialize the low level hardware (MSP) */ |
bogdanm | 0:9b334a45a8ff | 195 | HAL_NAND_MspDeInit(hnand); |
bogdanm | 0:9b334a45a8ff | 196 | |
bogdanm | 0:9b334a45a8ff | 197 | /* Configure the NAND registers with their reset values */ |
bogdanm | 0:9b334a45a8ff | 198 | FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); |
bogdanm | 0:9b334a45a8ff | 199 | |
bogdanm | 0:9b334a45a8ff | 200 | /* Reset the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 201 | hnand->State = HAL_NAND_STATE_RESET; |
bogdanm | 0:9b334a45a8ff | 202 | |
bogdanm | 0:9b334a45a8ff | 203 | /* Release Lock */ |
bogdanm | 0:9b334a45a8ff | 204 | __HAL_UNLOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 205 | |
bogdanm | 0:9b334a45a8ff | 206 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 207 | } |
bogdanm | 0:9b334a45a8ff | 208 | |
bogdanm | 0:9b334a45a8ff | 209 | /** |
bogdanm | 0:9b334a45a8ff | 210 | * @brief NAND MSP Init |
bogdanm | 0:9b334a45a8ff | 211 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 212 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 213 | * @retval None |
bogdanm | 0:9b334a45a8ff | 214 | */ |
bogdanm | 0:9b334a45a8ff | 215 | __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) |
bogdanm | 0:9b334a45a8ff | 216 | { |
bogdanm | 0:9b334a45a8ff | 217 | /* NOTE : This function Should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 218 | the HAL_NAND_MspInit could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 219 | */ |
bogdanm | 0:9b334a45a8ff | 220 | } |
bogdanm | 0:9b334a45a8ff | 221 | |
bogdanm | 0:9b334a45a8ff | 222 | /** |
bogdanm | 0:9b334a45a8ff | 223 | * @brief NAND MSP DeInit |
bogdanm | 0:9b334a45a8ff | 224 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 225 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 226 | * @retval None |
bogdanm | 0:9b334a45a8ff | 227 | */ |
bogdanm | 0:9b334a45a8ff | 228 | __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) |
bogdanm | 0:9b334a45a8ff | 229 | { |
bogdanm | 0:9b334a45a8ff | 230 | /* NOTE : This function Should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 231 | the HAL_NAND_MspDeInit could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 232 | */ |
bogdanm | 0:9b334a45a8ff | 233 | } |
bogdanm | 0:9b334a45a8ff | 234 | |
bogdanm | 0:9b334a45a8ff | 235 | |
bogdanm | 0:9b334a45a8ff | 236 | /** |
bogdanm | 0:9b334a45a8ff | 237 | * @brief This function handles NAND device interrupt request. |
bogdanm | 0:9b334a45a8ff | 238 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 239 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 240 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 241 | */ |
bogdanm | 0:9b334a45a8ff | 242 | void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) |
bogdanm | 0:9b334a45a8ff | 243 | { |
bogdanm | 0:9b334a45a8ff | 244 | /* Check NAND interrupt Rising edge flag */ |
bogdanm | 0:9b334a45a8ff | 245 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE)) |
bogdanm | 0:9b334a45a8ff | 246 | { |
bogdanm | 0:9b334a45a8ff | 247 | /* NAND interrupt callback*/ |
bogdanm | 0:9b334a45a8ff | 248 | HAL_NAND_ITCallback(hnand); |
bogdanm | 0:9b334a45a8ff | 249 | |
bogdanm | 0:9b334a45a8ff | 250 | /* Clear NAND interrupt Rising edge pending bit */ |
bogdanm | 0:9b334a45a8ff | 251 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE); |
bogdanm | 0:9b334a45a8ff | 252 | } |
bogdanm | 0:9b334a45a8ff | 253 | |
bogdanm | 0:9b334a45a8ff | 254 | /* Check NAND interrupt Level flag */ |
bogdanm | 0:9b334a45a8ff | 255 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL)) |
bogdanm | 0:9b334a45a8ff | 256 | { |
bogdanm | 0:9b334a45a8ff | 257 | /* NAND interrupt callback*/ |
bogdanm | 0:9b334a45a8ff | 258 | HAL_NAND_ITCallback(hnand); |
bogdanm | 0:9b334a45a8ff | 259 | |
bogdanm | 0:9b334a45a8ff | 260 | /* Clear NAND interrupt Level pending bit */ |
bogdanm | 0:9b334a45a8ff | 261 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL); |
bogdanm | 0:9b334a45a8ff | 262 | } |
bogdanm | 0:9b334a45a8ff | 263 | |
bogdanm | 0:9b334a45a8ff | 264 | /* Check NAND interrupt Falling edge flag */ |
bogdanm | 0:9b334a45a8ff | 265 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE)) |
bogdanm | 0:9b334a45a8ff | 266 | { |
bogdanm | 0:9b334a45a8ff | 267 | /* NAND interrupt callback*/ |
bogdanm | 0:9b334a45a8ff | 268 | HAL_NAND_ITCallback(hnand); |
bogdanm | 0:9b334a45a8ff | 269 | |
bogdanm | 0:9b334a45a8ff | 270 | /* Clear NAND interrupt Falling edge pending bit */ |
bogdanm | 0:9b334a45a8ff | 271 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE); |
bogdanm | 0:9b334a45a8ff | 272 | } |
bogdanm | 0:9b334a45a8ff | 273 | |
bogdanm | 0:9b334a45a8ff | 274 | /* Check NAND interrupt FIFO empty flag */ |
bogdanm | 0:9b334a45a8ff | 275 | if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT)) |
bogdanm | 0:9b334a45a8ff | 276 | { |
bogdanm | 0:9b334a45a8ff | 277 | /* NAND interrupt callback*/ |
bogdanm | 0:9b334a45a8ff | 278 | HAL_NAND_ITCallback(hnand); |
bogdanm | 0:9b334a45a8ff | 279 | |
bogdanm | 0:9b334a45a8ff | 280 | /* Clear NAND interrupt FIFO empty pending bit */ |
bogdanm | 0:9b334a45a8ff | 281 | __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT); |
bogdanm | 0:9b334a45a8ff | 282 | } |
bogdanm | 0:9b334a45a8ff | 283 | |
bogdanm | 0:9b334a45a8ff | 284 | } |
bogdanm | 0:9b334a45a8ff | 285 | |
bogdanm | 0:9b334a45a8ff | 286 | /** |
bogdanm | 0:9b334a45a8ff | 287 | * @brief NAND interrupt feature callback |
bogdanm | 0:9b334a45a8ff | 288 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 289 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 290 | * @retval None |
bogdanm | 0:9b334a45a8ff | 291 | */ |
bogdanm | 0:9b334a45a8ff | 292 | __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) |
bogdanm | 0:9b334a45a8ff | 293 | { |
bogdanm | 0:9b334a45a8ff | 294 | /* NOTE : This function Should not be modified, when the callback is needed, |
bogdanm | 0:9b334a45a8ff | 295 | the HAL_NAND_ITCallback could be implemented in the user file |
bogdanm | 0:9b334a45a8ff | 296 | */ |
bogdanm | 0:9b334a45a8ff | 297 | } |
bogdanm | 0:9b334a45a8ff | 298 | |
bogdanm | 0:9b334a45a8ff | 299 | /** |
bogdanm | 0:9b334a45a8ff | 300 | * @} |
bogdanm | 0:9b334a45a8ff | 301 | */ |
bogdanm | 0:9b334a45a8ff | 302 | |
bogdanm | 0:9b334a45a8ff | 303 | /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions |
bogdanm | 0:9b334a45a8ff | 304 | * @brief Input Output and memory control functions |
bogdanm | 0:9b334a45a8ff | 305 | * |
bogdanm | 0:9b334a45a8ff | 306 | @verbatim |
bogdanm | 0:9b334a45a8ff | 307 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 308 | ##### NAND Input and Output functions ##### |
bogdanm | 0:9b334a45a8ff | 309 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 310 | [..] |
bogdanm | 0:9b334a45a8ff | 311 | This section provides functions allowing to use and control the NAND |
bogdanm | 0:9b334a45a8ff | 312 | memory |
bogdanm | 0:9b334a45a8ff | 313 | |
bogdanm | 0:9b334a45a8ff | 314 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 315 | * @{ |
bogdanm | 0:9b334a45a8ff | 316 | */ |
bogdanm | 0:9b334a45a8ff | 317 | |
bogdanm | 0:9b334a45a8ff | 318 | /** |
bogdanm | 0:9b334a45a8ff | 319 | * @brief Read the NAND memory electronic signature |
bogdanm | 0:9b334a45a8ff | 320 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 321 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 322 | * @param pNAND_ID: NAND ID structure |
bogdanm | 0:9b334a45a8ff | 323 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 324 | */ |
bogdanm | 0:9b334a45a8ff | 325 | HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) |
bogdanm | 0:9b334a45a8ff | 326 | { |
bogdanm | 0:9b334a45a8ff | 327 | __IO uint32_t data = 0; |
bogdanm | 0:9b334a45a8ff | 328 | uint32_t deviceaddress = 0; |
bogdanm | 0:9b334a45a8ff | 329 | |
bogdanm | 0:9b334a45a8ff | 330 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 331 | __HAL_LOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 332 | |
bogdanm | 0:9b334a45a8ff | 333 | /* Check the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 334 | if(hnand->State == HAL_NAND_STATE_BUSY) |
bogdanm | 0:9b334a45a8ff | 335 | { |
bogdanm | 0:9b334a45a8ff | 336 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 337 | } |
bogdanm | 0:9b334a45a8ff | 338 | |
bogdanm | 0:9b334a45a8ff | 339 | /* Identify the device address */ |
bogdanm | 0:9b334a45a8ff | 340 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
bogdanm | 0:9b334a45a8ff | 341 | { |
bogdanm | 0:9b334a45a8ff | 342 | deviceaddress = NAND_DEVICE1; |
bogdanm | 0:9b334a45a8ff | 343 | } |
bogdanm | 0:9b334a45a8ff | 344 | else |
bogdanm | 0:9b334a45a8ff | 345 | { |
bogdanm | 0:9b334a45a8ff | 346 | deviceaddress = NAND_DEVICE2; |
bogdanm | 0:9b334a45a8ff | 347 | } |
bogdanm | 0:9b334a45a8ff | 348 | |
bogdanm | 0:9b334a45a8ff | 349 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 350 | hnand->State = HAL_NAND_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 351 | |
bogdanm | 0:9b334a45a8ff | 352 | /* Send Read ID command sequence */ |
bogdanm | 0:9b334a45a8ff | 353 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; |
bogdanm | 0:9b334a45a8ff | 354 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; |
bogdanm | 0:9b334a45a8ff | 355 | |
bogdanm | 0:9b334a45a8ff | 356 | /* Read the electronic signature from NAND flash */ |
bogdanm | 0:9b334a45a8ff | 357 | data = *(__IO uint32_t *)deviceaddress; |
bogdanm | 0:9b334a45a8ff | 358 | |
bogdanm | 0:9b334a45a8ff | 359 | /* Return the data read */ |
bogdanm | 0:9b334a45a8ff | 360 | pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); |
bogdanm | 0:9b334a45a8ff | 361 | pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); |
bogdanm | 0:9b334a45a8ff | 362 | pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); |
bogdanm | 0:9b334a45a8ff | 363 | pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); |
bogdanm | 0:9b334a45a8ff | 364 | |
bogdanm | 0:9b334a45a8ff | 365 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 366 | hnand->State = HAL_NAND_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 367 | |
bogdanm | 0:9b334a45a8ff | 368 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 369 | __HAL_UNLOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 370 | |
bogdanm | 0:9b334a45a8ff | 371 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 372 | } |
bogdanm | 0:9b334a45a8ff | 373 | |
bogdanm | 0:9b334a45a8ff | 374 | /** |
bogdanm | 0:9b334a45a8ff | 375 | * @brief NAND memory reset |
bogdanm | 0:9b334a45a8ff | 376 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 377 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 378 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 379 | */ |
bogdanm | 0:9b334a45a8ff | 380 | HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) |
bogdanm | 0:9b334a45a8ff | 381 | { |
bogdanm | 0:9b334a45a8ff | 382 | uint32_t deviceaddress = 0; |
bogdanm | 0:9b334a45a8ff | 383 | |
bogdanm | 0:9b334a45a8ff | 384 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 385 | __HAL_LOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 386 | |
bogdanm | 0:9b334a45a8ff | 387 | /* Check the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 388 | if(hnand->State == HAL_NAND_STATE_BUSY) |
bogdanm | 0:9b334a45a8ff | 389 | { |
bogdanm | 0:9b334a45a8ff | 390 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 391 | } |
bogdanm | 0:9b334a45a8ff | 392 | |
bogdanm | 0:9b334a45a8ff | 393 | /* Identify the device address */ |
bogdanm | 0:9b334a45a8ff | 394 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
bogdanm | 0:9b334a45a8ff | 395 | { |
bogdanm | 0:9b334a45a8ff | 396 | deviceaddress = NAND_DEVICE1; |
bogdanm | 0:9b334a45a8ff | 397 | } |
bogdanm | 0:9b334a45a8ff | 398 | else |
bogdanm | 0:9b334a45a8ff | 399 | { |
bogdanm | 0:9b334a45a8ff | 400 | deviceaddress = NAND_DEVICE2; |
bogdanm | 0:9b334a45a8ff | 401 | } |
bogdanm | 0:9b334a45a8ff | 402 | |
bogdanm | 0:9b334a45a8ff | 403 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 404 | hnand->State = HAL_NAND_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 405 | |
bogdanm | 0:9b334a45a8ff | 406 | /* Send NAND reset command */ |
bogdanm | 0:9b334a45a8ff | 407 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; |
bogdanm | 0:9b334a45a8ff | 408 | |
bogdanm | 0:9b334a45a8ff | 409 | |
bogdanm | 0:9b334a45a8ff | 410 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 411 | hnand->State = HAL_NAND_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 412 | |
bogdanm | 0:9b334a45a8ff | 413 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 414 | __HAL_UNLOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 415 | |
bogdanm | 0:9b334a45a8ff | 416 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 417 | |
bogdanm | 0:9b334a45a8ff | 418 | } |
bogdanm | 0:9b334a45a8ff | 419 | |
bogdanm | 0:9b334a45a8ff | 420 | /** |
bogdanm | 0:9b334a45a8ff | 421 | * @brief Read Page(s) from NAND memory block |
bogdanm | 0:9b334a45a8ff | 422 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 423 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 424 | * @param pAddress : pointer to NAND address structure |
bogdanm | 0:9b334a45a8ff | 425 | * @param pBuffer : pointer to destination read buffer |
bogdanm | 0:9b334a45a8ff | 426 | * @param NumPageToRead : number of pages to read from block |
bogdanm | 0:9b334a45a8ff | 427 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 428 | */ |
bogdanm | 0:9b334a45a8ff | 429 | HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) |
bogdanm | 0:9b334a45a8ff | 430 | { |
bogdanm | 0:9b334a45a8ff | 431 | __IO uint32_t index = 0; |
bogdanm | 0:9b334a45a8ff | 432 | uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS; |
bogdanm | 0:9b334a45a8ff | 433 | NAND_AddressTypeDef nandaddress; |
bogdanm | 0:9b334a45a8ff | 434 | uint32_t addressoffset = 0; |
bogdanm | 0:9b334a45a8ff | 435 | |
bogdanm | 0:9b334a45a8ff | 436 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 437 | __HAL_LOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 438 | |
bogdanm | 0:9b334a45a8ff | 439 | /* Check the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 440 | if(hnand->State == HAL_NAND_STATE_BUSY) |
bogdanm | 0:9b334a45a8ff | 441 | { |
bogdanm | 0:9b334a45a8ff | 442 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 443 | } |
bogdanm | 0:9b334a45a8ff | 444 | |
bogdanm | 0:9b334a45a8ff | 445 | /* Identify the device address */ |
bogdanm | 0:9b334a45a8ff | 446 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
bogdanm | 0:9b334a45a8ff | 447 | { |
bogdanm | 0:9b334a45a8ff | 448 | deviceaddress = NAND_DEVICE1; |
bogdanm | 0:9b334a45a8ff | 449 | } |
bogdanm | 0:9b334a45a8ff | 450 | else |
bogdanm | 0:9b334a45a8ff | 451 | { |
bogdanm | 0:9b334a45a8ff | 452 | deviceaddress = NAND_DEVICE2; |
bogdanm | 0:9b334a45a8ff | 453 | } |
bogdanm | 0:9b334a45a8ff | 454 | |
bogdanm | 0:9b334a45a8ff | 455 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 456 | hnand->State = HAL_NAND_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 457 | |
bogdanm | 0:9b334a45a8ff | 458 | /* Save the content of pAddress as it will be modified */ |
bogdanm | 0:9b334a45a8ff | 459 | nandaddress.Block = pAddress->Block; |
bogdanm | 0:9b334a45a8ff | 460 | nandaddress.Page = pAddress->Page; |
bogdanm | 0:9b334a45a8ff | 461 | nandaddress.Zone = pAddress->Zone; |
bogdanm | 0:9b334a45a8ff | 462 | |
bogdanm | 0:9b334a45a8ff | 463 | /* Page(s) read loop */ |
bogdanm | 0:9b334a45a8ff | 464 | while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) |
bogdanm | 0:9b334a45a8ff | 465 | { |
bogdanm | 0:9b334a45a8ff | 466 | /* update the buffer size */ |
bogdanm | 0:9b334a45a8ff | 467 | size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread); |
bogdanm | 0:9b334a45a8ff | 468 | |
bogdanm | 0:9b334a45a8ff | 469 | /* Get the address offset */ |
bogdanm | 0:9b334a45a8ff | 470 | addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); |
bogdanm | 0:9b334a45a8ff | 471 | |
bogdanm | 0:9b334a45a8ff | 472 | /* Send read page command sequence */ |
bogdanm | 0:9b334a45a8ff | 473 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; |
bogdanm | 0:9b334a45a8ff | 474 | |
bogdanm | 0:9b334a45a8ff | 475 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; |
bogdanm | 0:9b334a45a8ff | 476 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 477 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 478 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 479 | |
bogdanm | 0:9b334a45a8ff | 480 | /* for 512 and 1 GB devices, 4th cycle is required */ |
bogdanm | 0:9b334a45a8ff | 481 | if(hnand->Info.BlockNbr >= 1024) |
bogdanm | 0:9b334a45a8ff | 482 | { |
bogdanm | 0:9b334a45a8ff | 483 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 484 | } |
bogdanm | 0:9b334a45a8ff | 485 | |
bogdanm | 0:9b334a45a8ff | 486 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; |
bogdanm | 0:9b334a45a8ff | 487 | |
bogdanm | 0:9b334a45a8ff | 488 | /* Get Data into Buffer */ |
bogdanm | 0:9b334a45a8ff | 489 | for(index = size; index != 0; index--) |
bogdanm | 0:9b334a45a8ff | 490 | { |
bogdanm | 0:9b334a45a8ff | 491 | *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; |
bogdanm | 0:9b334a45a8ff | 492 | } |
bogdanm | 0:9b334a45a8ff | 493 | |
bogdanm | 0:9b334a45a8ff | 494 | /* Increment read pages number */ |
bogdanm | 0:9b334a45a8ff | 495 | numpagesread++; |
bogdanm | 0:9b334a45a8ff | 496 | |
bogdanm | 0:9b334a45a8ff | 497 | /* Decrement pages to read */ |
bogdanm | 0:9b334a45a8ff | 498 | NumPageToRead--; |
bogdanm | 0:9b334a45a8ff | 499 | |
bogdanm | 0:9b334a45a8ff | 500 | /* Increment the NAND address */ |
bogdanm | 0:9b334a45a8ff | 501 | addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress); |
bogdanm | 0:9b334a45a8ff | 502 | } |
bogdanm | 0:9b334a45a8ff | 503 | |
bogdanm | 0:9b334a45a8ff | 504 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 505 | hnand->State = HAL_NAND_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 506 | |
bogdanm | 0:9b334a45a8ff | 507 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 508 | __HAL_UNLOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 509 | |
bogdanm | 0:9b334a45a8ff | 510 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 511 | |
bogdanm | 0:9b334a45a8ff | 512 | } |
bogdanm | 0:9b334a45a8ff | 513 | |
bogdanm | 0:9b334a45a8ff | 514 | /** |
bogdanm | 0:9b334a45a8ff | 515 | * @brief Write Page(s) to NAND memory block |
bogdanm | 0:9b334a45a8ff | 516 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 517 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 518 | * @param pAddress : pointer to NAND address structure |
bogdanm | 0:9b334a45a8ff | 519 | * @param pBuffer : pointer to source buffer to write |
bogdanm | 0:9b334a45a8ff | 520 | * @param NumPageToWrite : number of pages to write to block |
bogdanm | 0:9b334a45a8ff | 521 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 522 | */ |
bogdanm | 0:9b334a45a8ff | 523 | HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) |
bogdanm | 0:9b334a45a8ff | 524 | { |
bogdanm | 0:9b334a45a8ff | 525 | __IO uint32_t index = 0; |
bogdanm | 0:9b334a45a8ff | 526 | uint32_t tickstart = 0; |
bogdanm | 0:9b334a45a8ff | 527 | uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS; |
bogdanm | 0:9b334a45a8ff | 528 | NAND_AddressTypeDef nandaddress; |
bogdanm | 0:9b334a45a8ff | 529 | uint32_t addressoffset = 0; |
bogdanm | 0:9b334a45a8ff | 530 | |
bogdanm | 0:9b334a45a8ff | 531 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 532 | __HAL_LOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 533 | |
bogdanm | 0:9b334a45a8ff | 534 | /* Check the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 535 | if(hnand->State == HAL_NAND_STATE_BUSY) |
bogdanm | 0:9b334a45a8ff | 536 | { |
bogdanm | 0:9b334a45a8ff | 537 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 538 | } |
bogdanm | 0:9b334a45a8ff | 539 | |
bogdanm | 0:9b334a45a8ff | 540 | /* Identify the device address */ |
bogdanm | 0:9b334a45a8ff | 541 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
bogdanm | 0:9b334a45a8ff | 542 | { |
bogdanm | 0:9b334a45a8ff | 543 | deviceaddress = NAND_DEVICE1; |
bogdanm | 0:9b334a45a8ff | 544 | } |
bogdanm | 0:9b334a45a8ff | 545 | else |
bogdanm | 0:9b334a45a8ff | 546 | { |
bogdanm | 0:9b334a45a8ff | 547 | deviceaddress = NAND_DEVICE2; |
bogdanm | 0:9b334a45a8ff | 548 | } |
bogdanm | 0:9b334a45a8ff | 549 | |
bogdanm | 0:9b334a45a8ff | 550 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 551 | hnand->State = HAL_NAND_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 552 | |
bogdanm | 0:9b334a45a8ff | 553 | /* Save the content of pAddress as it will be modified */ |
bogdanm | 0:9b334a45a8ff | 554 | nandaddress.Block = pAddress->Block; |
bogdanm | 0:9b334a45a8ff | 555 | nandaddress.Page = pAddress->Page; |
bogdanm | 0:9b334a45a8ff | 556 | nandaddress.Zone = pAddress->Zone; |
bogdanm | 0:9b334a45a8ff | 557 | |
bogdanm | 0:9b334a45a8ff | 558 | /* Page(s) write loop */ |
bogdanm | 0:9b334a45a8ff | 559 | while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) |
bogdanm | 0:9b334a45a8ff | 560 | { |
bogdanm | 0:9b334a45a8ff | 561 | /* update the buffer size */ |
bogdanm | 0:9b334a45a8ff | 562 | size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten); |
bogdanm | 0:9b334a45a8ff | 563 | |
bogdanm | 0:9b334a45a8ff | 564 | /* Get the address offset */ |
bogdanm | 0:9b334a45a8ff | 565 | addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); |
bogdanm | 0:9b334a45a8ff | 566 | |
bogdanm | 0:9b334a45a8ff | 567 | /* Send write page command sequence */ |
bogdanm | 0:9b334a45a8ff | 568 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; |
bogdanm | 0:9b334a45a8ff | 569 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; |
bogdanm | 0:9b334a45a8ff | 570 | |
bogdanm | 0:9b334a45a8ff | 571 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; |
bogdanm | 0:9b334a45a8ff | 572 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 573 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 574 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 575 | |
bogdanm | 0:9b334a45a8ff | 576 | /* for 512 and 1 GB devices, 4th cycle is required */ |
bogdanm | 0:9b334a45a8ff | 577 | if(hnand->Info.BlockNbr >= 1024) |
bogdanm | 0:9b334a45a8ff | 578 | { |
bogdanm | 0:9b334a45a8ff | 579 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 580 | } |
bogdanm | 0:9b334a45a8ff | 581 | |
bogdanm | 0:9b334a45a8ff | 582 | /* Write data to memory */ |
bogdanm | 0:9b334a45a8ff | 583 | for(index = size; index != 0; index--) |
bogdanm | 0:9b334a45a8ff | 584 | { |
bogdanm | 0:9b334a45a8ff | 585 | *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; |
bogdanm | 0:9b334a45a8ff | 586 | } |
bogdanm | 0:9b334a45a8ff | 587 | |
bogdanm | 0:9b334a45a8ff | 588 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; |
bogdanm | 0:9b334a45a8ff | 589 | |
bogdanm | 0:9b334a45a8ff | 590 | /* Get tick */ |
bogdanm | 0:9b334a45a8ff | 591 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 592 | |
bogdanm | 0:9b334a45a8ff | 593 | /* Read status until NAND is ready */ |
bogdanm | 0:9b334a45a8ff | 594 | while(HAL_NAND_Read_Status(hnand) != NAND_READY) |
bogdanm | 0:9b334a45a8ff | 595 | { |
bogdanm | 0:9b334a45a8ff | 596 | if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 597 | { |
bogdanm | 0:9b334a45a8ff | 598 | return HAL_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 599 | } |
bogdanm | 0:9b334a45a8ff | 600 | } |
bogdanm | 0:9b334a45a8ff | 601 | |
bogdanm | 0:9b334a45a8ff | 602 | /* Increment written pages number */ |
bogdanm | 0:9b334a45a8ff | 603 | numpageswritten++; |
bogdanm | 0:9b334a45a8ff | 604 | |
bogdanm | 0:9b334a45a8ff | 605 | /* Decrement pages to write */ |
bogdanm | 0:9b334a45a8ff | 606 | NumPageToWrite--; |
bogdanm | 0:9b334a45a8ff | 607 | |
bogdanm | 0:9b334a45a8ff | 608 | /* Increment the NAND address */ |
bogdanm | 0:9b334a45a8ff | 609 | addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress); |
bogdanm | 0:9b334a45a8ff | 610 | } |
bogdanm | 0:9b334a45a8ff | 611 | |
bogdanm | 0:9b334a45a8ff | 612 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 613 | hnand->State = HAL_NAND_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 614 | |
bogdanm | 0:9b334a45a8ff | 615 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 616 | __HAL_UNLOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 617 | |
bogdanm | 0:9b334a45a8ff | 618 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 619 | } |
bogdanm | 0:9b334a45a8ff | 620 | |
bogdanm | 0:9b334a45a8ff | 621 | /** |
bogdanm | 0:9b334a45a8ff | 622 | * @brief Read Spare area(s) from NAND memory |
bogdanm | 0:9b334a45a8ff | 623 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 624 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 625 | * @param pAddress : pointer to NAND address structure |
bogdanm | 0:9b334a45a8ff | 626 | * @param pBuffer: pointer to source buffer to write |
bogdanm | 0:9b334a45a8ff | 627 | * @param NumSpareAreaToRead: Number of spare area to read |
bogdanm | 0:9b334a45a8ff | 628 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 629 | */ |
bogdanm | 0:9b334a45a8ff | 630 | HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) |
bogdanm | 0:9b334a45a8ff | 631 | { |
bogdanm | 0:9b334a45a8ff | 632 | __IO uint32_t index = 0; |
bogdanm | 0:9b334a45a8ff | 633 | uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS; |
bogdanm | 0:9b334a45a8ff | 634 | NAND_AddressTypeDef nandaddress; |
bogdanm | 0:9b334a45a8ff | 635 | uint32_t addressoffset = 0; |
bogdanm | 0:9b334a45a8ff | 636 | |
bogdanm | 0:9b334a45a8ff | 637 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 638 | __HAL_LOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 639 | |
bogdanm | 0:9b334a45a8ff | 640 | /* Check the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 641 | if(hnand->State == HAL_NAND_STATE_BUSY) |
bogdanm | 0:9b334a45a8ff | 642 | { |
bogdanm | 0:9b334a45a8ff | 643 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 644 | } |
bogdanm | 0:9b334a45a8ff | 645 | |
bogdanm | 0:9b334a45a8ff | 646 | /* Identify the device address */ |
bogdanm | 0:9b334a45a8ff | 647 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
bogdanm | 0:9b334a45a8ff | 648 | { |
bogdanm | 0:9b334a45a8ff | 649 | deviceaddress = NAND_DEVICE1; |
bogdanm | 0:9b334a45a8ff | 650 | } |
bogdanm | 0:9b334a45a8ff | 651 | else |
bogdanm | 0:9b334a45a8ff | 652 | { |
bogdanm | 0:9b334a45a8ff | 653 | deviceaddress = NAND_DEVICE2; |
bogdanm | 0:9b334a45a8ff | 654 | } |
bogdanm | 0:9b334a45a8ff | 655 | |
bogdanm | 0:9b334a45a8ff | 656 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 657 | hnand->State = HAL_NAND_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 658 | |
bogdanm | 0:9b334a45a8ff | 659 | /* Save the content of pAddress as it will be modified */ |
bogdanm | 0:9b334a45a8ff | 660 | nandaddress.Block = pAddress->Block; |
bogdanm | 0:9b334a45a8ff | 661 | nandaddress.Page = pAddress->Page; |
bogdanm | 0:9b334a45a8ff | 662 | nandaddress.Zone = pAddress->Zone; |
bogdanm | 0:9b334a45a8ff | 663 | |
bogdanm | 0:9b334a45a8ff | 664 | /* Spare area(s) read loop */ |
bogdanm | 0:9b334a45a8ff | 665 | while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) |
bogdanm | 0:9b334a45a8ff | 666 | { |
bogdanm | 0:9b334a45a8ff | 667 | /* update the buffer size */ |
bogdanm | 0:9b334a45a8ff | 668 | size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read); |
bogdanm | 0:9b334a45a8ff | 669 | |
bogdanm | 0:9b334a45a8ff | 670 | /* Get the address offset */ |
bogdanm | 0:9b334a45a8ff | 671 | addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); |
bogdanm | 0:9b334a45a8ff | 672 | |
bogdanm | 0:9b334a45a8ff | 673 | /* Send read spare area command sequence */ |
bogdanm | 0:9b334a45a8ff | 674 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; |
bogdanm | 0:9b334a45a8ff | 675 | |
bogdanm | 0:9b334a45a8ff | 676 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; |
bogdanm | 0:9b334a45a8ff | 677 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 678 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 679 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 680 | |
bogdanm | 0:9b334a45a8ff | 681 | /* for 512 and 1 GB devices, 4th cycle is required */ |
bogdanm | 0:9b334a45a8ff | 682 | if(hnand->Info.BlockNbr >= 1024) |
bogdanm | 0:9b334a45a8ff | 683 | { |
bogdanm | 0:9b334a45a8ff | 684 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 685 | } |
bogdanm | 0:9b334a45a8ff | 686 | |
bogdanm | 0:9b334a45a8ff | 687 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; |
bogdanm | 0:9b334a45a8ff | 688 | |
bogdanm | 0:9b334a45a8ff | 689 | /* Get Data into Buffer */ |
bogdanm | 0:9b334a45a8ff | 690 | for (index = size ;index != 0; index--) |
bogdanm | 0:9b334a45a8ff | 691 | { |
bogdanm | 0:9b334a45a8ff | 692 | *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; |
bogdanm | 0:9b334a45a8ff | 693 | } |
bogdanm | 0:9b334a45a8ff | 694 | |
bogdanm | 0:9b334a45a8ff | 695 | /* Increment read spare areas number */ |
bogdanm | 0:9b334a45a8ff | 696 | num_spare_area_read++; |
bogdanm | 0:9b334a45a8ff | 697 | |
bogdanm | 0:9b334a45a8ff | 698 | /* Decrement spare areas to read */ |
bogdanm | 0:9b334a45a8ff | 699 | NumSpareAreaToRead--; |
bogdanm | 0:9b334a45a8ff | 700 | |
bogdanm | 0:9b334a45a8ff | 701 | /* Increment the NAND address */ |
bogdanm | 0:9b334a45a8ff | 702 | addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress); |
bogdanm | 0:9b334a45a8ff | 703 | } |
bogdanm | 0:9b334a45a8ff | 704 | |
bogdanm | 0:9b334a45a8ff | 705 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 706 | hnand->State = HAL_NAND_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 707 | |
bogdanm | 0:9b334a45a8ff | 708 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 709 | __HAL_UNLOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 710 | |
bogdanm | 0:9b334a45a8ff | 711 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 712 | } |
bogdanm | 0:9b334a45a8ff | 713 | |
bogdanm | 0:9b334a45a8ff | 714 | /** |
bogdanm | 0:9b334a45a8ff | 715 | * @brief Write Spare area(s) to NAND memory |
bogdanm | 0:9b334a45a8ff | 716 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 717 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 718 | * @param pAddress : pointer to NAND address structure |
bogdanm | 0:9b334a45a8ff | 719 | * @param pBuffer : pointer to source buffer to write |
bogdanm | 0:9b334a45a8ff | 720 | * @param NumSpareAreaTowrite : number of spare areas to write to block |
bogdanm | 0:9b334a45a8ff | 721 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 722 | */ |
bogdanm | 0:9b334a45a8ff | 723 | HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) |
bogdanm | 0:9b334a45a8ff | 724 | { |
bogdanm | 0:9b334a45a8ff | 725 | __IO uint32_t index = 0; |
bogdanm | 0:9b334a45a8ff | 726 | uint32_t tickstart = 0; |
bogdanm | 0:9b334a45a8ff | 727 | uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS; |
bogdanm | 0:9b334a45a8ff | 728 | NAND_AddressTypeDef nandaddress; |
bogdanm | 0:9b334a45a8ff | 729 | uint32_t addressoffset = 0; |
bogdanm | 0:9b334a45a8ff | 730 | |
bogdanm | 0:9b334a45a8ff | 731 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 732 | __HAL_LOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 733 | |
bogdanm | 0:9b334a45a8ff | 734 | /* Check the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 735 | if(hnand->State == HAL_NAND_STATE_BUSY) |
bogdanm | 0:9b334a45a8ff | 736 | { |
bogdanm | 0:9b334a45a8ff | 737 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 738 | } |
bogdanm | 0:9b334a45a8ff | 739 | |
bogdanm | 0:9b334a45a8ff | 740 | /* Identify the device address */ |
bogdanm | 0:9b334a45a8ff | 741 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
bogdanm | 0:9b334a45a8ff | 742 | { |
bogdanm | 0:9b334a45a8ff | 743 | deviceaddress = NAND_DEVICE1; |
bogdanm | 0:9b334a45a8ff | 744 | } |
bogdanm | 0:9b334a45a8ff | 745 | else |
bogdanm | 0:9b334a45a8ff | 746 | { |
bogdanm | 0:9b334a45a8ff | 747 | deviceaddress = NAND_DEVICE2; |
bogdanm | 0:9b334a45a8ff | 748 | } |
bogdanm | 0:9b334a45a8ff | 749 | |
bogdanm | 0:9b334a45a8ff | 750 | /* Update the FMC_NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 751 | hnand->State = HAL_NAND_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 752 | |
bogdanm | 0:9b334a45a8ff | 753 | /* Save the content of pAddress as it will be modified */ |
bogdanm | 0:9b334a45a8ff | 754 | nandaddress.Block = pAddress->Block; |
bogdanm | 0:9b334a45a8ff | 755 | nandaddress.Page = pAddress->Page; |
bogdanm | 0:9b334a45a8ff | 756 | nandaddress.Zone = pAddress->Zone; |
bogdanm | 0:9b334a45a8ff | 757 | |
bogdanm | 0:9b334a45a8ff | 758 | /* Spare area(s) write loop */ |
bogdanm | 0:9b334a45a8ff | 759 | while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) |
bogdanm | 0:9b334a45a8ff | 760 | { |
bogdanm | 0:9b334a45a8ff | 761 | /* update the buffer size */ |
bogdanm | 0:9b334a45a8ff | 762 | size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written); |
bogdanm | 0:9b334a45a8ff | 763 | |
bogdanm | 0:9b334a45a8ff | 764 | /* Get the address offset */ |
bogdanm | 0:9b334a45a8ff | 765 | addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); |
bogdanm | 0:9b334a45a8ff | 766 | |
bogdanm | 0:9b334a45a8ff | 767 | /* Send write Spare area command sequence */ |
bogdanm | 0:9b334a45a8ff | 768 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; |
bogdanm | 0:9b334a45a8ff | 769 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; |
bogdanm | 0:9b334a45a8ff | 770 | |
bogdanm | 0:9b334a45a8ff | 771 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; |
bogdanm | 0:9b334a45a8ff | 772 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 773 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 774 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 775 | |
bogdanm | 0:9b334a45a8ff | 776 | /* for 512 and 1 GB devices, 4th cycle is required */ |
bogdanm | 0:9b334a45a8ff | 777 | if(hnand->Info.BlockNbr >= 1024) |
bogdanm | 0:9b334a45a8ff | 778 | { |
bogdanm | 0:9b334a45a8ff | 779 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); |
bogdanm | 0:9b334a45a8ff | 780 | } |
bogdanm | 0:9b334a45a8ff | 781 | |
bogdanm | 0:9b334a45a8ff | 782 | /* Write data to memory */ |
bogdanm | 0:9b334a45a8ff | 783 | for(; index < size; index++) |
bogdanm | 0:9b334a45a8ff | 784 | { |
bogdanm | 0:9b334a45a8ff | 785 | *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; |
bogdanm | 0:9b334a45a8ff | 786 | } |
bogdanm | 0:9b334a45a8ff | 787 | |
bogdanm | 0:9b334a45a8ff | 788 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; |
bogdanm | 0:9b334a45a8ff | 789 | |
bogdanm | 0:9b334a45a8ff | 790 | /* Get tick */ |
bogdanm | 0:9b334a45a8ff | 791 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 792 | |
bogdanm | 0:9b334a45a8ff | 793 | /* Read status until NAND is ready */ |
bogdanm | 0:9b334a45a8ff | 794 | while(HAL_NAND_Read_Status(hnand) != NAND_READY) |
bogdanm | 0:9b334a45a8ff | 795 | { |
bogdanm | 0:9b334a45a8ff | 796 | if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 797 | { |
bogdanm | 0:9b334a45a8ff | 798 | return HAL_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 799 | } |
bogdanm | 0:9b334a45a8ff | 800 | } |
bogdanm | 0:9b334a45a8ff | 801 | |
bogdanm | 0:9b334a45a8ff | 802 | /* Increment written spare areas number */ |
bogdanm | 0:9b334a45a8ff | 803 | num_spare_area_written++; |
bogdanm | 0:9b334a45a8ff | 804 | |
bogdanm | 0:9b334a45a8ff | 805 | /* Decrement spare areas to write */ |
bogdanm | 0:9b334a45a8ff | 806 | NumSpareAreaTowrite--; |
bogdanm | 0:9b334a45a8ff | 807 | |
bogdanm | 0:9b334a45a8ff | 808 | /* Increment the NAND address */ |
bogdanm | 0:9b334a45a8ff | 809 | addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress); |
bogdanm | 0:9b334a45a8ff | 810 | } |
bogdanm | 0:9b334a45a8ff | 811 | |
bogdanm | 0:9b334a45a8ff | 812 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 813 | hnand->State = HAL_NAND_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 814 | |
bogdanm | 0:9b334a45a8ff | 815 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 816 | __HAL_UNLOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 817 | |
bogdanm | 0:9b334a45a8ff | 818 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 819 | } |
bogdanm | 0:9b334a45a8ff | 820 | |
bogdanm | 0:9b334a45a8ff | 821 | /** |
bogdanm | 0:9b334a45a8ff | 822 | * @brief NAND memory Block erase |
bogdanm | 0:9b334a45a8ff | 823 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 824 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 825 | * @param pAddress : pointer to NAND address structure |
bogdanm | 0:9b334a45a8ff | 826 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 827 | */ |
bogdanm | 0:9b334a45a8ff | 828 | HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) |
bogdanm | 0:9b334a45a8ff | 829 | { |
bogdanm | 0:9b334a45a8ff | 830 | uint32_t deviceaddress = 0; |
bogdanm | 0:9b334a45a8ff | 831 | uint32_t tickstart = 0; |
bogdanm | 0:9b334a45a8ff | 832 | |
bogdanm | 0:9b334a45a8ff | 833 | /* Process Locked */ |
bogdanm | 0:9b334a45a8ff | 834 | __HAL_LOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 835 | |
bogdanm | 0:9b334a45a8ff | 836 | /* Check the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 837 | if(hnand->State == HAL_NAND_STATE_BUSY) |
bogdanm | 0:9b334a45a8ff | 838 | { |
bogdanm | 0:9b334a45a8ff | 839 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 840 | } |
bogdanm | 0:9b334a45a8ff | 841 | |
bogdanm | 0:9b334a45a8ff | 842 | /* Identify the device address */ |
bogdanm | 0:9b334a45a8ff | 843 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
bogdanm | 0:9b334a45a8ff | 844 | { |
bogdanm | 0:9b334a45a8ff | 845 | deviceaddress = NAND_DEVICE1; |
bogdanm | 0:9b334a45a8ff | 846 | } |
bogdanm | 0:9b334a45a8ff | 847 | else |
bogdanm | 0:9b334a45a8ff | 848 | { |
bogdanm | 0:9b334a45a8ff | 849 | deviceaddress = NAND_DEVICE2; |
bogdanm | 0:9b334a45a8ff | 850 | } |
bogdanm | 0:9b334a45a8ff | 851 | |
bogdanm | 0:9b334a45a8ff | 852 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 853 | hnand->State = HAL_NAND_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 854 | |
bogdanm | 0:9b334a45a8ff | 855 | /* Send Erase block command sequence */ |
bogdanm | 0:9b334a45a8ff | 856 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; |
bogdanm | 0:9b334a45a8ff | 857 | |
bogdanm | 0:9b334a45a8ff | 858 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); |
bogdanm | 0:9b334a45a8ff | 859 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); |
bogdanm | 0:9b334a45a8ff | 860 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); |
bogdanm | 0:9b334a45a8ff | 861 | |
bogdanm | 0:9b334a45a8ff | 862 | /* for 512 and 1 GB devices, 4th cycle is required */ |
bogdanm | 0:9b334a45a8ff | 863 | if(hnand->Info.BlockNbr >= 1024) |
bogdanm | 0:9b334a45a8ff | 864 | { |
bogdanm | 0:9b334a45a8ff | 865 | *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); |
bogdanm | 0:9b334a45a8ff | 866 | } |
bogdanm | 0:9b334a45a8ff | 867 | |
bogdanm | 0:9b334a45a8ff | 868 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; |
bogdanm | 0:9b334a45a8ff | 869 | |
bogdanm | 0:9b334a45a8ff | 870 | /* Update the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 871 | hnand->State = HAL_NAND_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 872 | |
bogdanm | 0:9b334a45a8ff | 873 | /* Get tick */ |
bogdanm | 0:9b334a45a8ff | 874 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 875 | |
bogdanm | 0:9b334a45a8ff | 876 | /* Read status until NAND is ready */ |
bogdanm | 0:9b334a45a8ff | 877 | while(HAL_NAND_Read_Status(hnand) != NAND_READY) |
bogdanm | 0:9b334a45a8ff | 878 | { |
bogdanm | 0:9b334a45a8ff | 879 | if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 880 | { |
bogdanm | 0:9b334a45a8ff | 881 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 882 | __HAL_UNLOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 883 | |
bogdanm | 0:9b334a45a8ff | 884 | return HAL_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 885 | } |
bogdanm | 0:9b334a45a8ff | 886 | } |
bogdanm | 0:9b334a45a8ff | 887 | |
bogdanm | 0:9b334a45a8ff | 888 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 889 | __HAL_UNLOCK(hnand); |
bogdanm | 0:9b334a45a8ff | 890 | |
bogdanm | 0:9b334a45a8ff | 891 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 892 | } |
bogdanm | 0:9b334a45a8ff | 893 | |
bogdanm | 0:9b334a45a8ff | 894 | /** |
bogdanm | 0:9b334a45a8ff | 895 | * @brief NAND memory read status |
bogdanm | 0:9b334a45a8ff | 896 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 897 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 898 | * @retval NAND status |
bogdanm | 0:9b334a45a8ff | 899 | */ |
bogdanm | 0:9b334a45a8ff | 900 | uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) |
bogdanm | 0:9b334a45a8ff | 901 | { |
bogdanm | 0:9b334a45a8ff | 902 | uint32_t data = 0; |
bogdanm | 0:9b334a45a8ff | 903 | uint32_t deviceaddress = 0; |
bogdanm | 0:9b334a45a8ff | 904 | |
bogdanm | 0:9b334a45a8ff | 905 | /* Identify the device address */ |
bogdanm | 0:9b334a45a8ff | 906 | if(hnand->Init.NandBank == FMC_NAND_BANK2) |
bogdanm | 0:9b334a45a8ff | 907 | { |
bogdanm | 0:9b334a45a8ff | 908 | deviceaddress = NAND_DEVICE1; |
bogdanm | 0:9b334a45a8ff | 909 | } |
bogdanm | 0:9b334a45a8ff | 910 | else |
bogdanm | 0:9b334a45a8ff | 911 | { |
bogdanm | 0:9b334a45a8ff | 912 | deviceaddress = NAND_DEVICE2; |
bogdanm | 0:9b334a45a8ff | 913 | } |
bogdanm | 0:9b334a45a8ff | 914 | |
bogdanm | 0:9b334a45a8ff | 915 | /* Send Read status operation command */ |
bogdanm | 0:9b334a45a8ff | 916 | *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; |
bogdanm | 0:9b334a45a8ff | 917 | |
bogdanm | 0:9b334a45a8ff | 918 | /* Read status register data */ |
bogdanm | 0:9b334a45a8ff | 919 | data = *(__IO uint8_t *)deviceaddress; |
bogdanm | 0:9b334a45a8ff | 920 | |
bogdanm | 0:9b334a45a8ff | 921 | /* Return the status */ |
bogdanm | 0:9b334a45a8ff | 922 | if((data & NAND_ERROR) == NAND_ERROR) |
bogdanm | 0:9b334a45a8ff | 923 | { |
bogdanm | 0:9b334a45a8ff | 924 | return NAND_ERROR; |
bogdanm | 0:9b334a45a8ff | 925 | } |
bogdanm | 0:9b334a45a8ff | 926 | else if((data & NAND_READY) == NAND_READY) |
bogdanm | 0:9b334a45a8ff | 927 | { |
bogdanm | 0:9b334a45a8ff | 928 | return NAND_READY; |
bogdanm | 0:9b334a45a8ff | 929 | } |
bogdanm | 0:9b334a45a8ff | 930 | |
bogdanm | 0:9b334a45a8ff | 931 | return NAND_BUSY; |
bogdanm | 0:9b334a45a8ff | 932 | } |
bogdanm | 0:9b334a45a8ff | 933 | |
bogdanm | 0:9b334a45a8ff | 934 | /** |
bogdanm | 0:9b334a45a8ff | 935 | * @brief Increment the NAND memory address |
bogdanm | 0:9b334a45a8ff | 936 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 937 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 938 | * @param pAddress: pointer to NAND address structure |
bogdanm | 0:9b334a45a8ff | 939 | * @retval The new status of the increment address operation. It can be: |
bogdanm | 0:9b334a45a8ff | 940 | * - NAND_VALID_ADDRESS: When the new address is valid address |
bogdanm | 0:9b334a45a8ff | 941 | * - NAND_INVALID_ADDRESS: When the new address is invalid address |
bogdanm | 0:9b334a45a8ff | 942 | */ |
bogdanm | 0:9b334a45a8ff | 943 | uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) |
bogdanm | 0:9b334a45a8ff | 944 | { |
bogdanm | 0:9b334a45a8ff | 945 | uint32_t status = NAND_VALID_ADDRESS; |
bogdanm | 0:9b334a45a8ff | 946 | |
bogdanm | 0:9b334a45a8ff | 947 | /* Increment page address */ |
bogdanm | 0:9b334a45a8ff | 948 | pAddress->Page++; |
bogdanm | 0:9b334a45a8ff | 949 | |
bogdanm | 0:9b334a45a8ff | 950 | /* Check NAND address is valid */ |
bogdanm | 0:9b334a45a8ff | 951 | if(pAddress->Page == hnand->Info.BlockSize) |
bogdanm | 0:9b334a45a8ff | 952 | { |
bogdanm | 0:9b334a45a8ff | 953 | pAddress->Page = 0; |
bogdanm | 0:9b334a45a8ff | 954 | pAddress->Block++; |
bogdanm | 0:9b334a45a8ff | 955 | |
bogdanm | 0:9b334a45a8ff | 956 | if(pAddress->Block == hnand->Info.ZoneSize) |
bogdanm | 0:9b334a45a8ff | 957 | { |
bogdanm | 0:9b334a45a8ff | 958 | pAddress->Block = 0; |
bogdanm | 0:9b334a45a8ff | 959 | pAddress->Zone++; |
bogdanm | 0:9b334a45a8ff | 960 | |
bogdanm | 0:9b334a45a8ff | 961 | if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr)) |
bogdanm | 0:9b334a45a8ff | 962 | { |
bogdanm | 0:9b334a45a8ff | 963 | status = NAND_INVALID_ADDRESS; |
bogdanm | 0:9b334a45a8ff | 964 | } |
bogdanm | 0:9b334a45a8ff | 965 | } |
bogdanm | 0:9b334a45a8ff | 966 | } |
bogdanm | 0:9b334a45a8ff | 967 | |
bogdanm | 0:9b334a45a8ff | 968 | return (status); |
bogdanm | 0:9b334a45a8ff | 969 | } |
bogdanm | 0:9b334a45a8ff | 970 | /** |
bogdanm | 0:9b334a45a8ff | 971 | * @} |
bogdanm | 0:9b334a45a8ff | 972 | */ |
bogdanm | 0:9b334a45a8ff | 973 | |
bogdanm | 0:9b334a45a8ff | 974 | /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions |
bogdanm | 0:9b334a45a8ff | 975 | * @brief management functions |
bogdanm | 0:9b334a45a8ff | 976 | * |
bogdanm | 0:9b334a45a8ff | 977 | @verbatim |
bogdanm | 0:9b334a45a8ff | 978 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 979 | ##### NAND Control functions ##### |
bogdanm | 0:9b334a45a8ff | 980 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 981 | [..] |
bogdanm | 0:9b334a45a8ff | 982 | This subsection provides a set of functions allowing to control dynamically |
bogdanm | 0:9b334a45a8ff | 983 | the NAND interface. |
bogdanm | 0:9b334a45a8ff | 984 | |
bogdanm | 0:9b334a45a8ff | 985 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 986 | * @{ |
bogdanm | 0:9b334a45a8ff | 987 | */ |
bogdanm | 0:9b334a45a8ff | 988 | |
bogdanm | 0:9b334a45a8ff | 989 | |
bogdanm | 0:9b334a45a8ff | 990 | /** |
bogdanm | 0:9b334a45a8ff | 991 | * @brief Enables dynamically NAND ECC feature. |
bogdanm | 0:9b334a45a8ff | 992 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 993 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 994 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 995 | */ |
bogdanm | 0:9b334a45a8ff | 996 | HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) |
bogdanm | 0:9b334a45a8ff | 997 | { |
bogdanm | 0:9b334a45a8ff | 998 | /* Check the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 999 | if(hnand->State == HAL_NAND_STATE_BUSY) |
bogdanm | 0:9b334a45a8ff | 1000 | { |
bogdanm | 0:9b334a45a8ff | 1001 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 1002 | } |
bogdanm | 0:9b334a45a8ff | 1003 | |
bogdanm | 0:9b334a45a8ff | 1004 | /* Update the NAND state */ |
bogdanm | 0:9b334a45a8ff | 1005 | hnand->State = HAL_NAND_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 1006 | |
bogdanm | 0:9b334a45a8ff | 1007 | /* Enable ECC feature */ |
bogdanm | 0:9b334a45a8ff | 1008 | FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank); |
bogdanm | 0:9b334a45a8ff | 1009 | |
bogdanm | 0:9b334a45a8ff | 1010 | /* Update the NAND state */ |
bogdanm | 0:9b334a45a8ff | 1011 | hnand->State = HAL_NAND_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1012 | |
bogdanm | 0:9b334a45a8ff | 1013 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1014 | } |
bogdanm | 0:9b334a45a8ff | 1015 | |
bogdanm | 0:9b334a45a8ff | 1016 | /** |
bogdanm | 0:9b334a45a8ff | 1017 | * @brief Disables dynamically FMC_NAND ECC feature. |
bogdanm | 0:9b334a45a8ff | 1018 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1019 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 1020 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1021 | */ |
bogdanm | 0:9b334a45a8ff | 1022 | HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) |
bogdanm | 0:9b334a45a8ff | 1023 | { |
bogdanm | 0:9b334a45a8ff | 1024 | /* Check the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 1025 | if(hnand->State == HAL_NAND_STATE_BUSY) |
bogdanm | 0:9b334a45a8ff | 1026 | { |
bogdanm | 0:9b334a45a8ff | 1027 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 1028 | } |
bogdanm | 0:9b334a45a8ff | 1029 | |
bogdanm | 0:9b334a45a8ff | 1030 | /* Update the NAND state */ |
bogdanm | 0:9b334a45a8ff | 1031 | hnand->State = HAL_NAND_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 1032 | |
bogdanm | 0:9b334a45a8ff | 1033 | /* Disable ECC feature */ |
bogdanm | 0:9b334a45a8ff | 1034 | FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank); |
bogdanm | 0:9b334a45a8ff | 1035 | |
bogdanm | 0:9b334a45a8ff | 1036 | /* Update the NAND state */ |
bogdanm | 0:9b334a45a8ff | 1037 | hnand->State = HAL_NAND_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1038 | |
bogdanm | 0:9b334a45a8ff | 1039 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1040 | } |
bogdanm | 0:9b334a45a8ff | 1041 | |
bogdanm | 0:9b334a45a8ff | 1042 | /** |
bogdanm | 0:9b334a45a8ff | 1043 | * @brief Disables dynamically NAND ECC feature. |
bogdanm | 0:9b334a45a8ff | 1044 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1045 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 1046 | * @param ECCval: pointer to ECC value |
bogdanm | 0:9b334a45a8ff | 1047 | * @param Timeout: maximum timeout to wait |
bogdanm | 0:9b334a45a8ff | 1048 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1049 | */ |
bogdanm | 0:9b334a45a8ff | 1050 | HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout) |
bogdanm | 0:9b334a45a8ff | 1051 | { |
bogdanm | 0:9b334a45a8ff | 1052 | HAL_StatusTypeDef status = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1053 | |
bogdanm | 0:9b334a45a8ff | 1054 | /* Check the NAND controller state */ |
bogdanm | 0:9b334a45a8ff | 1055 | if(hnand->State == HAL_NAND_STATE_BUSY) |
bogdanm | 0:9b334a45a8ff | 1056 | { |
bogdanm | 0:9b334a45a8ff | 1057 | return HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 1058 | } |
bogdanm | 0:9b334a45a8ff | 1059 | |
bogdanm | 0:9b334a45a8ff | 1060 | /* Update the NAND state */ |
bogdanm | 0:9b334a45a8ff | 1061 | hnand->State = HAL_NAND_STATE_BUSY; |
bogdanm | 0:9b334a45a8ff | 1062 | |
bogdanm | 0:9b334a45a8ff | 1063 | /* Get NAND ECC value */ |
bogdanm | 0:9b334a45a8ff | 1064 | status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout); |
bogdanm | 0:9b334a45a8ff | 1065 | |
bogdanm | 0:9b334a45a8ff | 1066 | /* Update the NAND state */ |
bogdanm | 0:9b334a45a8ff | 1067 | hnand->State = HAL_NAND_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 1068 | |
bogdanm | 0:9b334a45a8ff | 1069 | return status; |
bogdanm | 0:9b334a45a8ff | 1070 | } |
bogdanm | 0:9b334a45a8ff | 1071 | |
bogdanm | 0:9b334a45a8ff | 1072 | /** |
bogdanm | 0:9b334a45a8ff | 1073 | * @} |
bogdanm | 0:9b334a45a8ff | 1074 | */ |
bogdanm | 0:9b334a45a8ff | 1075 | |
bogdanm | 0:9b334a45a8ff | 1076 | |
bogdanm | 0:9b334a45a8ff | 1077 | /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions |
bogdanm | 0:9b334a45a8ff | 1078 | * @brief Peripheral State functions |
bogdanm | 0:9b334a45a8ff | 1079 | * |
bogdanm | 0:9b334a45a8ff | 1080 | @verbatim |
bogdanm | 0:9b334a45a8ff | 1081 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 1082 | ##### NAND State functions ##### |
bogdanm | 0:9b334a45a8ff | 1083 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 1084 | [..] |
bogdanm | 0:9b334a45a8ff | 1085 | This subsection permits to get in run-time the status of the NAND controller |
bogdanm | 0:9b334a45a8ff | 1086 | and the data flow. |
bogdanm | 0:9b334a45a8ff | 1087 | |
bogdanm | 0:9b334a45a8ff | 1088 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 1089 | * @{ |
bogdanm | 0:9b334a45a8ff | 1090 | */ |
bogdanm | 0:9b334a45a8ff | 1091 | |
bogdanm | 0:9b334a45a8ff | 1092 | /** |
bogdanm | 0:9b334a45a8ff | 1093 | * @brief return the NAND state |
bogdanm | 0:9b334a45a8ff | 1094 | * @param hnand: pointer to a NAND_HandleTypeDef structure that contains |
bogdanm | 0:9b334a45a8ff | 1095 | * the configuration information for NAND module. |
bogdanm | 0:9b334a45a8ff | 1096 | * @retval HAL state |
bogdanm | 0:9b334a45a8ff | 1097 | */ |
bogdanm | 0:9b334a45a8ff | 1098 | HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) |
bogdanm | 0:9b334a45a8ff | 1099 | { |
bogdanm | 0:9b334a45a8ff | 1100 | return hnand->State; |
bogdanm | 0:9b334a45a8ff | 1101 | } |
bogdanm | 0:9b334a45a8ff | 1102 | |
bogdanm | 0:9b334a45a8ff | 1103 | /** |
bogdanm | 0:9b334a45a8ff | 1104 | * @} |
bogdanm | 0:9b334a45a8ff | 1105 | */ |
bogdanm | 0:9b334a45a8ff | 1106 | |
bogdanm | 0:9b334a45a8ff | 1107 | /** |
bogdanm | 0:9b334a45a8ff | 1108 | * @} |
bogdanm | 0:9b334a45a8ff | 1109 | */ |
bogdanm | 0:9b334a45a8ff | 1110 | |
bogdanm | 0:9b334a45a8ff | 1111 | /** |
bogdanm | 0:9b334a45a8ff | 1112 | * @} |
bogdanm | 0:9b334a45a8ff | 1113 | */ |
bogdanm | 0:9b334a45a8ff | 1114 | |
bogdanm | 0:9b334a45a8ff | 1115 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ |
bogdanm | 0:9b334a45a8ff | 1116 | STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ |
mbed_official | 19:112740acecfa | 1117 | STM32F446xx || STM32F469xx || STM32F479xx */ |
bogdanm | 0:9b334a45a8ff | 1118 | #endif /* HAL_NAND_MODULE_ENABLED */ |
bogdanm | 0:9b334a45a8ff | 1119 | |
bogdanm | 0:9b334a45a8ff | 1120 | /** |
bogdanm | 0:9b334a45a8ff | 1121 | * @} |
bogdanm | 0:9b334a45a8ff | 1122 | */ |
bogdanm | 0:9b334a45a8ff | 1123 | |
bogdanm | 0:9b334a45a8ff | 1124 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |