mbed-dev - fix LPC812 PWM

Users » nameless129 » Code » mbed-dev

fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 19:112740acecfa

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f4xx_hal_adc.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	19:112740acecfa	5	* @version V1.4.1
mbed_official	19:112740acecfa	6	* @date 09-October-2015
bogdanm	0:9b334a45a8ff	7	* @brief This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	8	* functionalities of the Analog to Digital Convertor (ADC) peripheral:
bogdanm	0:9b334a45a8ff	9	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	10	* + IO operation functions
bogdanm	0:9b334a45a8ff	11	* + State and errors functions
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	@verbatim
bogdanm	0:9b334a45a8ff	14	==============================================================================
bogdanm	0:9b334a45a8ff	15	##### ADC Peripheral features #####
bogdanm	0:9b334a45a8ff	16	==============================================================================
bogdanm	0:9b334a45a8ff	17	[..]
bogdanm	0:9b334a45a8ff	18	(#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
bogdanm	0:9b334a45a8ff	19	(#) Interrupt generation at the end of conversion, end of injected conversion,
bogdanm	0:9b334a45a8ff	20	and in case of analog watchdog or overrun events
bogdanm	0:9b334a45a8ff	21	(#) Single and continuous conversion modes.
bogdanm	0:9b334a45a8ff	22	(#) Scan mode for automatic conversion of channel 0 to channel x.
bogdanm	0:9b334a45a8ff	23	(#) Data alignment with in-built data coherency.
bogdanm	0:9b334a45a8ff	24	(#) Channel-wise programmable sampling time.
bogdanm	0:9b334a45a8ff	25	(#) External trigger option with configurable polarity for both regular and
bogdanm	0:9b334a45a8ff	26	injected conversion.
bogdanm	0:9b334a45a8ff	27	(#) Dual/Triple mode (on devices with 2 ADCs or more).
bogdanm	0:9b334a45a8ff	28	(#) Configurable DMA data storage in Dual/Triple ADC mode.
bogdanm	0:9b334a45a8ff	29	(#) Configurable delay between conversions in Dual/Triple interleaved mode.
bogdanm	0:9b334a45a8ff	30	(#) ADC conversion type (refer to the datasheets).
bogdanm	0:9b334a45a8ff	31	(#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
bogdanm	0:9b334a45a8ff	32	slower speed.
bogdanm	0:9b334a45a8ff	33	(#) ADC input range: VREF(minus) = VIN = VREF(plus).
bogdanm	0:9b334a45a8ff	34	(#) DMA request generation during regular channel conversion.
bogdanm	0:9b334a45a8ff	35
bogdanm	0:9b334a45a8ff	36
bogdanm	0:9b334a45a8ff	37	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	38	==============================================================================
bogdanm	0:9b334a45a8ff	39	[..]
bogdanm	0:9b334a45a8ff	40	(#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():
bogdanm	0:9b334a45a8ff	41	(##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()
bogdanm	0:9b334a45a8ff	42	(##) ADC pins configuration
bogdanm	0:9b334a45a8ff	43	(+++) Enable the clock for the ADC GPIOs using the following function:
bogdanm	0:9b334a45a8ff	44	__HAL_RCC_GPIOx_CLK_ENABLE()
bogdanm	0:9b334a45a8ff	45	(+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()
bogdanm	0:9b334a45a8ff	46	(##) In case of using interrupts (e.g. HAL_ADC_Start_IT())
bogdanm	0:9b334a45a8ff	47	(+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()
bogdanm	0:9b334a45a8ff	48	(+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()
bogdanm	0:9b334a45a8ff	49	(+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()
bogdanm	0:9b334a45a8ff	50	(##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())
bogdanm	0:9b334a45a8ff	51	(+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()
bogdanm	0:9b334a45a8ff	52	(+++) Configure and enable two DMA streams stream for managing data
bogdanm	0:9b334a45a8ff	53	transfer from peripheral to memory (output stream)
bogdanm	0:9b334a45a8ff	54	(+++) Associate the initialized DMA handle to the CRYP DMA handle
bogdanm	0:9b334a45a8ff	55	using __HAL_LINKDMA()
bogdanm	0:9b334a45a8ff	56	(+++) Configure the priority and enable the NVIC for the transfer complete
bogdanm	0:9b334a45a8ff	57	interrupt on the two DMA Streams. The output stream should have higher
bogdanm	0:9b334a45a8ff	58	priority than the input stream.
bogdanm	0:9b334a45a8ff	59
bogdanm	0:9b334a45a8ff	60	* Configuration of ADC, groups regular/injected, channels parameters *
bogdanm	0:9b334a45a8ff	61	==============================================================================
bogdanm	0:9b334a45a8ff	62	[..]
bogdanm	0:9b334a45a8ff	63	(#) Configure the ADC parameters (resolution, data alignment, ...)
bogdanm	0:9b334a45a8ff	64	and regular group parameters (conversion trigger, sequencer, ...)
bogdanm	0:9b334a45a8ff	65	using function HAL_ADC_Init().
bogdanm	0:9b334a45a8ff	66
bogdanm	0:9b334a45a8ff	67	(#) Configure the channels for regular group parameters (channel number,
bogdanm	0:9b334a45a8ff	68	channel rank into sequencer, ..., into regular group)
bogdanm	0:9b334a45a8ff	69	using function HAL_ADC_ConfigChannel().
bogdanm	0:9b334a45a8ff	70
bogdanm	0:9b334a45a8ff	71	(#) Optionally, configure the injected group parameters (conversion trigger,
bogdanm	0:9b334a45a8ff	72	sequencer, ..., of injected group)
bogdanm	0:9b334a45a8ff	73	and the channels for injected group parameters (channel number,
bogdanm	0:9b334a45a8ff	74	channel rank into sequencer, ..., into injected group)
bogdanm	0:9b334a45a8ff	75	using function HAL_ADCEx_InjectedConfigChannel().
bogdanm	0:9b334a45a8ff	76
bogdanm	0:9b334a45a8ff	77	(#) Optionally, configure the analog watchdog parameters (channels
bogdanm	0:9b334a45a8ff	78	monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().
bogdanm	0:9b334a45a8ff	79
bogdanm	0:9b334a45a8ff	80	(#) Optionally, for devices with several ADC instances: configure the
bogdanm	0:9b334a45a8ff	81	multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().
bogdanm	0:9b334a45a8ff	82
bogdanm	0:9b334a45a8ff	83	* Execution of ADC conversions *
bogdanm	0:9b334a45a8ff	84	==============================================================================
bogdanm	0:9b334a45a8ff	85	[..]
bogdanm	0:9b334a45a8ff	86	(#) ADC driver can be used among three modes: polling, interruption,
bogdanm	0:9b334a45a8ff	87	transfer by DMA.
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	* Polling mode IO operation *
bogdanm	0:9b334a45a8ff	90	=================================
bogdanm	0:9b334a45a8ff	91	[..]
bogdanm	0:9b334a45a8ff	92	(+) Start the ADC peripheral using HAL_ADC_Start()
bogdanm	0:9b334a45a8ff	93	(+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage
bogdanm	0:9b334a45a8ff	94	user can specify the value of timeout according to his end application
bogdanm	0:9b334a45a8ff	95	(+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
bogdanm	0:9b334a45a8ff	96	(+) Stop the ADC peripheral using HAL_ADC_Stop()
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	* Interrupt mode IO operation *
bogdanm	0:9b334a45a8ff	99	===================================
bogdanm	0:9b334a45a8ff	100	[..]
bogdanm	0:9b334a45a8ff	101	(+) Start the ADC peripheral using HAL_ADC_Start_IT()
bogdanm	0:9b334a45a8ff	102	(+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine
bogdanm	0:9b334a45a8ff	103	(+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	104	add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
bogdanm	0:9b334a45a8ff	105	(+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	106	add his own code by customization of function pointer HAL_ADC_ErrorCallback
bogdanm	0:9b334a45a8ff	107	(+) Stop the ADC peripheral using HAL_ADC_Stop_IT()
bogdanm	0:9b334a45a8ff	108
bogdanm	0:9b334a45a8ff	109	* DMA mode IO operation *
bogdanm	0:9b334a45a8ff	110	==============================
bogdanm	0:9b334a45a8ff	111	[..]
bogdanm	0:9b334a45a8ff	112	(+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length
bogdanm	0:9b334a45a8ff	113	of data to be transferred at each end of conversion
bogdanm	0:9b334a45a8ff	114	(+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	115	add his own code by customization of function pointer HAL_ADC_ConvCpltCallback
bogdanm	0:9b334a45a8ff	116	(+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can
bogdanm	0:9b334a45a8ff	117	add his own code by customization of function pointer HAL_ADC_ErrorCallback
bogdanm	0:9b334a45a8ff	118	(+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()
bogdanm	0:9b334a45a8ff	119
bogdanm	0:9b334a45a8ff	120	* ADC HAL driver macros list *
bogdanm	0:9b334a45a8ff	121	=============================================
bogdanm	0:9b334a45a8ff	122	[..]
bogdanm	0:9b334a45a8ff	123	Below the list of most used macros in ADC HAL driver.
bogdanm	0:9b334a45a8ff	124
bogdanm	0:9b334a45a8ff	125	(+) __HAL_ADC_ENABLE : Enable the ADC peripheral
bogdanm	0:9b334a45a8ff	126	(+) __HAL_ADC_DISABLE : Disable the ADC peripheral
bogdanm	0:9b334a45a8ff	127	(+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt
bogdanm	0:9b334a45a8ff	128	(+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt
bogdanm	0:9b334a45a8ff	129	(+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled
bogdanm	0:9b334a45a8ff	130	(+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags
bogdanm	0:9b334a45a8ff	131	(+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status
bogdanm	0:9b334a45a8ff	132	(+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register
bogdanm	0:9b334a45a8ff	133
bogdanm	0:9b334a45a8ff	134	[..]
bogdanm	0:9b334a45a8ff	135	(@) You can refer to the ADC HAL driver header file for more useful macros
bogdanm	0:9b334a45a8ff	136
bogdanm	0:9b334a45a8ff	137	* Deinitialization of ADC *
bogdanm	0:9b334a45a8ff	138	==============================================================================
bogdanm	0:9b334a45a8ff	139	[..]
bogdanm	0:9b334a45a8ff	140	(#) Disable the ADC interface
bogdanm	0:9b334a45a8ff	141	(++) ADC clock can be hard reset and disabled at RCC top level.
bogdanm	0:9b334a45a8ff	142	(++) Hard reset of ADC peripherals
bogdanm	0:9b334a45a8ff	143	using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().
bogdanm	0:9b334a45a8ff	144	(++) ADC clock disable using the equivalent macro/functions as configuration step.
bogdanm	0:9b334a45a8ff	145	(+++) Example:
bogdanm	0:9b334a45a8ff	146	Into HAL_ADC_MspDeInit() (recommended code location) or with
bogdanm	0:9b334a45a8ff	147	other device clock parameters configuration:
bogdanm	0:9b334a45a8ff	148	(+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
bogdanm	0:9b334a45a8ff	149	(+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
bogdanm	0:9b334a45a8ff	150	(+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)
bogdanm	0:9b334a45a8ff	151	(+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
bogdanm	0:9b334a45a8ff	152
bogdanm	0:9b334a45a8ff	153	(#) ADC pins configuration
bogdanm	0:9b334a45a8ff	154	(++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	(#) Optionally, in case of usage of ADC with interruptions:
bogdanm	0:9b334a45a8ff	157	(++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
bogdanm	0:9b334a45a8ff	158
bogdanm	0:9b334a45a8ff	159	(#) Optionally, in case of usage of DMA:
bogdanm	0:9b334a45a8ff	160	(++) Deinitialize the DMA using function HAL_DMA_DeInit().
bogdanm	0:9b334a45a8ff	161	(++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
bogdanm	0:9b334a45a8ff	162
bogdanm	0:9b334a45a8ff	163	@endverbatim
bogdanm	0:9b334a45a8ff	164	******************************************************************************
bogdanm	0:9b334a45a8ff	165	* @attention
bogdanm	0:9b334a45a8ff	166	*
bogdanm	0:9b334a45a8ff	167	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	168	*
bogdanm	0:9b334a45a8ff	169	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	170	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	171	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	172	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	173	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	174	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	175	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	176	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	177	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	178	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	179	*
bogdanm	0:9b334a45a8ff	180	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	181	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	182	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	183	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	184	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	185	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	186	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	187	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	188	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	189	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	190	*
bogdanm	0:9b334a45a8ff	191	******************************************************************************
bogdanm	0:9b334a45a8ff	192	*/
bogdanm	0:9b334a45a8ff	193
bogdanm	0:9b334a45a8ff	194	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	195	#include "stm32f4xx_hal.h"
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	0:9b334a45a8ff	198	* @{
bogdanm	0:9b334a45a8ff	199	*/
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	/** @defgroup ADC ADC
bogdanm	0:9b334a45a8ff	202	* @brief ADC driver modules
bogdanm	0:9b334a45a8ff	203	* @{
bogdanm	0:9b334a45a8ff	204	*/
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	#ifdef HAL_ADC_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	207
bogdanm	0:9b334a45a8ff	208	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	209	/* Private define ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	210	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	211	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	212	/** @addtogroup ADC_Private_Functions
bogdanm	0:9b334a45a8ff	213	* @{
bogdanm	0:9b334a45a8ff	214	*/
bogdanm	0:9b334a45a8ff	215	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	216	static void ADC_Init(ADC_HandleTypeDef* hadc);
bogdanm	0:9b334a45a8ff	217	static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	218	static void ADC_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	219	static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	220	/**
bogdanm	0:9b334a45a8ff	221	* @}
bogdanm	0:9b334a45a8ff	222	*/
bogdanm	0:9b334a45a8ff	223	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	224	/** @defgroup ADC_Exported_Functions ADC Exported Functions
bogdanm	0:9b334a45a8ff	225	* @{
bogdanm	0:9b334a45a8ff	226	*/
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	229	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	230	*
bogdanm	0:9b334a45a8ff	231	@verbatim
bogdanm	0:9b334a45a8ff	232	===============================================================================
bogdanm	0:9b334a45a8ff	233	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	234	===============================================================================
bogdanm	0:9b334a45a8ff	235	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	236	(+) Initialize and configure the ADC.
bogdanm	0:9b334a45a8ff	237	(+) De-initialize the ADC.
bogdanm	0:9b334a45a8ff	238
bogdanm	0:9b334a45a8ff	239	@endverbatim
bogdanm	0:9b334a45a8ff	240	* @{
bogdanm	0:9b334a45a8ff	241	*/
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	/**
bogdanm	0:9b334a45a8ff	244	* @brief Initializes the ADCx peripheral according to the specified parameters
bogdanm	0:9b334a45a8ff	245	* in the ADC_InitStruct and initializes the ADC MSP.
bogdanm	0:9b334a45a8ff	246	*
bogdanm	0:9b334a45a8ff	247	* @note This function is used to configure the global features of the ADC (
bogdanm	0:9b334a45a8ff	248	* ClockPrescaler, Resolution, Data Alignment and number of conversion), however,
bogdanm	0:9b334a45a8ff	249	* the rest of the configuration parameters are specific to the regular
bogdanm	0:9b334a45a8ff	250	* channels group (scan mode activation, continuous mode activation,
bogdanm	0:9b334a45a8ff	251	* External trigger source and edge, DMA continuous request after the
bogdanm	0:9b334a45a8ff	252	* last transfer and End of conversion selection).
bogdanm	0:9b334a45a8ff	253	*
bogdanm	0:9b334a45a8ff	254	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	255	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	256	* @retval HAL status
bogdanm	0:9b334a45a8ff	257	*/
bogdanm	0:9b334a45a8ff	258	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	259	{
bogdanm	0:9b334a45a8ff	260	/* Check ADC handle */
bogdanm	0:9b334a45a8ff	261	if(hadc == NULL)
bogdanm	0:9b334a45a8ff	262	{
bogdanm	0:9b334a45a8ff	263	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	264	}
bogdanm	0:9b334a45a8ff	265
bogdanm	0:9b334a45a8ff	266	/* Check the parameters */
bogdanm	0:9b334a45a8ff	267	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	268	assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
bogdanm	0:9b334a45a8ff	269	assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
bogdanm	0:9b334a45a8ff	270	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));
bogdanm	0:9b334a45a8ff	271	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	272	assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));
bogdanm	0:9b334a45a8ff	273	assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
bogdanm	0:9b334a45a8ff	274	assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
bogdanm	0:9b334a45a8ff	275	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
bogdanm	0:9b334a45a8ff	276	assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
bogdanm	0:9b334a45a8ff	277	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
bogdanm	0:9b334a45a8ff	278
bogdanm	0:9b334a45a8ff	279	if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
bogdanm	0:9b334a45a8ff	280	{
bogdanm	0:9b334a45a8ff	281	assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
bogdanm	0:9b334a45a8ff	282	}
bogdanm	0:9b334a45a8ff	283
bogdanm	0:9b334a45a8ff	284	if(hadc->State == HAL_ADC_STATE_RESET)
bogdanm	0:9b334a45a8ff	285	{
bogdanm	0:9b334a45a8ff	286	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	287	hadc->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	288	/* Init the low level hardware */
bogdanm	0:9b334a45a8ff	289	HAL_ADC_MspInit(hadc);
bogdanm	0:9b334a45a8ff	290	}
bogdanm	0:9b334a45a8ff	291
bogdanm	0:9b334a45a8ff	292	/* Initialize the ADC state */
bogdanm	0:9b334a45a8ff	293	hadc->State = HAL_ADC_STATE_BUSY;
bogdanm	0:9b334a45a8ff	294
bogdanm	0:9b334a45a8ff	295	/* Set ADC parameters */
bogdanm	0:9b334a45a8ff	296	ADC_Init(hadc);
bogdanm	0:9b334a45a8ff	297
bogdanm	0:9b334a45a8ff	298	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	299	hadc->ErrorCode = HAL_ADC_ERROR_NONE;
bogdanm	0:9b334a45a8ff	300
bogdanm	0:9b334a45a8ff	301	/* Initialize the ADC state */
bogdanm	0:9b334a45a8ff	302	hadc->State = HAL_ADC_STATE_READY;
bogdanm	0:9b334a45a8ff	303
bogdanm	0:9b334a45a8ff	304	/* Release Lock */
bogdanm	0:9b334a45a8ff	305	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	306
bogdanm	0:9b334a45a8ff	307	/* Return function status */
bogdanm	0:9b334a45a8ff	308	return HAL_OK;
bogdanm	0:9b334a45a8ff	309	}
bogdanm	0:9b334a45a8ff	310
bogdanm	0:9b334a45a8ff	311	/**
bogdanm	0:9b334a45a8ff	312	* @brief Deinitializes the ADCx peripheral registers to their default reset values.
bogdanm	0:9b334a45a8ff	313	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	314	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	315	* @retval HAL status
bogdanm	0:9b334a45a8ff	316	*/
bogdanm	0:9b334a45a8ff	317	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	318	{
bogdanm	0:9b334a45a8ff	319	/* Check ADC handle */
bogdanm	0:9b334a45a8ff	320	if(hadc == NULL)
bogdanm	0:9b334a45a8ff	321	{
bogdanm	0:9b334a45a8ff	322	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	323	}
bogdanm	0:9b334a45a8ff	324
bogdanm	0:9b334a45a8ff	325	/* Check the parameters */
bogdanm	0:9b334a45a8ff	326	assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
bogdanm	0:9b334a45a8ff	327
bogdanm	0:9b334a45a8ff	328	/* Change ADC state */
bogdanm	0:9b334a45a8ff	329	hadc->State = HAL_ADC_STATE_BUSY;
bogdanm	0:9b334a45a8ff	330
bogdanm	0:9b334a45a8ff	331	/* DeInit the low level hardware */
bogdanm	0:9b334a45a8ff	332	HAL_ADC_MspDeInit(hadc);
bogdanm	0:9b334a45a8ff	333
bogdanm	0:9b334a45a8ff	334	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	335	hadc->ErrorCode = HAL_ADC_ERROR_NONE;
bogdanm	0:9b334a45a8ff	336
bogdanm	0:9b334a45a8ff	337	/* Change ADC state */
bogdanm	0:9b334a45a8ff	338	hadc->State = HAL_ADC_STATE_RESET;
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	/* Return function status */
bogdanm	0:9b334a45a8ff	341	return HAL_OK;
bogdanm	0:9b334a45a8ff	342	}
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	/**
bogdanm	0:9b334a45a8ff	345	* @brief Initializes the ADC MSP.
bogdanm	0:9b334a45a8ff	346	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	347	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	348	* @retval None
bogdanm	0:9b334a45a8ff	349	*/
bogdanm	0:9b334a45a8ff	350	__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	351	{
bogdanm	0:9b334a45a8ff	352	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	353	the HAL_ADC_MspInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	354	*/
bogdanm	0:9b334a45a8ff	355	}
bogdanm	0:9b334a45a8ff	356
bogdanm	0:9b334a45a8ff	357	/**
bogdanm	0:9b334a45a8ff	358	* @brief DeInitializes the ADC MSP.
bogdanm	0:9b334a45a8ff	359	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	360	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	361	* @retval None
bogdanm	0:9b334a45a8ff	362	*/
bogdanm	0:9b334a45a8ff	363	__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	364	{
bogdanm	0:9b334a45a8ff	365	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	366	the HAL_ADC_MspDeInit could be implemented in the user file
bogdanm	0:9b334a45a8ff	367	*/
bogdanm	0:9b334a45a8ff	368	}
bogdanm	0:9b334a45a8ff	369
bogdanm	0:9b334a45a8ff	370	/**
bogdanm	0:9b334a45a8ff	371	* @}
bogdanm	0:9b334a45a8ff	372	*/
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374	/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	375	* @brief IO operation functions
bogdanm	0:9b334a45a8ff	376	*
bogdanm	0:9b334a45a8ff	377	@verbatim
bogdanm	0:9b334a45a8ff	378	===============================================================================
bogdanm	0:9b334a45a8ff	379	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	380	===============================================================================
bogdanm	0:9b334a45a8ff	381	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	382	(+) Start conversion of regular channel.
bogdanm	0:9b334a45a8ff	383	(+) Stop conversion of regular channel.
bogdanm	0:9b334a45a8ff	384	(+) Start conversion of regular channel and enable interrupt.
bogdanm	0:9b334a45a8ff	385	(+) Stop conversion of regular channel and disable interrupt.
bogdanm	0:9b334a45a8ff	386	(+) Start conversion of regular channel and enable DMA transfer.
bogdanm	0:9b334a45a8ff	387	(+) Stop conversion of regular channel and disable DMA transfer.
bogdanm	0:9b334a45a8ff	388	(+) Handle ADC interrupt request.
bogdanm	0:9b334a45a8ff	389
bogdanm	0:9b334a45a8ff	390	@endverbatim
bogdanm	0:9b334a45a8ff	391	* @{
bogdanm	0:9b334a45a8ff	392	*/
bogdanm	0:9b334a45a8ff	393
bogdanm	0:9b334a45a8ff	394	/**
bogdanm	0:9b334a45a8ff	395	* @brief Enables ADC and starts conversion of the regular channels.
bogdanm	0:9b334a45a8ff	396	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	397	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	398	* @retval HAL status
bogdanm	0:9b334a45a8ff	399	*/
bogdanm	0:9b334a45a8ff	400	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	401	{
bogdanm	0:9b334a45a8ff	402	__IO uint32_t counter = 0;
bogdanm	0:9b334a45a8ff	403
bogdanm	0:9b334a45a8ff	404	/* Check the parameters */
bogdanm	0:9b334a45a8ff	405	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	406	assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
bogdanm	0:9b334a45a8ff	407
bogdanm	0:9b334a45a8ff	408	/* Process locked */
bogdanm	0:9b334a45a8ff	409	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	410
bogdanm	0:9b334a45a8ff	411	/* Check if an injected conversion is ongoing */
bogdanm	0:9b334a45a8ff	412	if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
bogdanm	0:9b334a45a8ff	413	{
bogdanm	0:9b334a45a8ff	414	/* Change ADC state */
bogdanm	0:9b334a45a8ff	415	hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
bogdanm	0:9b334a45a8ff	416	}
bogdanm	0:9b334a45a8ff	417	else
bogdanm	0:9b334a45a8ff	418	{
bogdanm	0:9b334a45a8ff	419	/* Change ADC state */
bogdanm	0:9b334a45a8ff	420	hadc->State = HAL_ADC_STATE_BUSY_REG;
bogdanm	0:9b334a45a8ff	421	}
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	/* Check if ADC peripheral is disabled in order to enable it and wait during
bogdanm	0:9b334a45a8ff	424	Tstab time the ADC's stabilization */
bogdanm	0:9b334a45a8ff	425	if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
bogdanm	0:9b334a45a8ff	426	{
bogdanm	0:9b334a45a8ff	427	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	428	__HAL_ADC_ENABLE(hadc);
bogdanm	0:9b334a45a8ff	429
bogdanm	0:9b334a45a8ff	430	/* Delay for ADC stabilization time */
bogdanm	0:9b334a45a8ff	431	/* Compute number of CPU cycles to wait for */
bogdanm	0:9b334a45a8ff	432	counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
bogdanm	0:9b334a45a8ff	433	while(counter != 0)
bogdanm	0:9b334a45a8ff	434	{
bogdanm	0:9b334a45a8ff	435	counter--;
bogdanm	0:9b334a45a8ff	436	}
bogdanm	0:9b334a45a8ff	437	}
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	/* Process unlocked */
bogdanm	0:9b334a45a8ff	440	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	441
bogdanm	0:9b334a45a8ff	442	/* Check if Multimode enabled */
bogdanm	0:9b334a45a8ff	443	if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
bogdanm	0:9b334a45a8ff	444	{
bogdanm	0:9b334a45a8ff	445	/* if no external trigger present enable software conversion of regular channels */
bogdanm	0:9b334a45a8ff	446	if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
bogdanm	0:9b334a45a8ff	447	{
bogdanm	0:9b334a45a8ff	448	/* Enable the selected ADC software conversion for regular group */
bogdanm	0:9b334a45a8ff	449	hadc->Instance->CR2 \|= (uint32_t)ADC_CR2_SWSTART;
bogdanm	0:9b334a45a8ff	450	}
bogdanm	0:9b334a45a8ff	451	}
bogdanm	0:9b334a45a8ff	452	else
bogdanm	0:9b334a45a8ff	453	{
bogdanm	0:9b334a45a8ff	454	/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
bogdanm	0:9b334a45a8ff	455	if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
bogdanm	0:9b334a45a8ff	456	{
bogdanm	0:9b334a45a8ff	457	/* Enable the selected ADC software conversion for regular group */
bogdanm	0:9b334a45a8ff	458	hadc->Instance->CR2 \|= (uint32_t)ADC_CR2_SWSTART;
bogdanm	0:9b334a45a8ff	459	}
bogdanm	0:9b334a45a8ff	460	}
bogdanm	0:9b334a45a8ff	461
bogdanm	0:9b334a45a8ff	462	/* Return function status */
bogdanm	0:9b334a45a8ff	463	return HAL_OK;
bogdanm	0:9b334a45a8ff	464	}
bogdanm	0:9b334a45a8ff	465
bogdanm	0:9b334a45a8ff	466	/**
bogdanm	0:9b334a45a8ff	467	* @brief Disables ADC and stop conversion of regular channels.
bogdanm	0:9b334a45a8ff	468	*
bogdanm	0:9b334a45a8ff	469	* @note Caution: This function will stop also injected channels.
bogdanm	0:9b334a45a8ff	470	*
bogdanm	0:9b334a45a8ff	471	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	472	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	473	*
bogdanm	0:9b334a45a8ff	474	* @retval HAL status.
bogdanm	0:9b334a45a8ff	475	*/
bogdanm	0:9b334a45a8ff	476	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	477	{
bogdanm	0:9b334a45a8ff	478	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	479	__HAL_ADC_DISABLE(hadc);
bogdanm	0:9b334a45a8ff	480
bogdanm	0:9b334a45a8ff	481	/* Change ADC state */
bogdanm	0:9b334a45a8ff	482	hadc->State = HAL_ADC_STATE_READY;
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	/* Return function status */
bogdanm	0:9b334a45a8ff	485	return HAL_OK;
bogdanm	0:9b334a45a8ff	486	}
bogdanm	0:9b334a45a8ff	487
bogdanm	0:9b334a45a8ff	488	/**
bogdanm	0:9b334a45a8ff	489	* @brief Poll for regular conversion complete
bogdanm	0:9b334a45a8ff	490	* @note ADC conversion flags EOS (end of sequence) and EOC (end of
bogdanm	0:9b334a45a8ff	491	* conversion) are cleared by this function.
bogdanm	0:9b334a45a8ff	492	* @note This function cannot be used in a particular setup: ADC configured
bogdanm	0:9b334a45a8ff	493	* in DMA mode and polling for end of each conversion (ADC init
bogdanm	0:9b334a45a8ff	494	* parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
bogdanm	0:9b334a45a8ff	495	* In this case, DMA resets the flag EOC and polling cannot be
bogdanm	0:9b334a45a8ff	496	* performed on each conversion. Nevertheless, polling can still
bogdanm	0:9b334a45a8ff	497	* be performed on the complete sequence.
bogdanm	0:9b334a45a8ff	498	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	499	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	500	* @param Timeout: Timeout value in millisecond.
bogdanm	0:9b334a45a8ff	501	* @retval HAL status
bogdanm	0:9b334a45a8ff	502	*/
bogdanm	0:9b334a45a8ff	503	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	504	{
bogdanm	0:9b334a45a8ff	505	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	506
bogdanm	0:9b334a45a8ff	507	/* Verification that ADC configuration is compliant with polling for */
bogdanm	0:9b334a45a8ff	508	/* each conversion: */
bogdanm	0:9b334a45a8ff	509	/* Particular case is ADC configured in DMA mode and ADC sequencer with */
bogdanm	0:9b334a45a8ff	510	/* several ranks and polling for end of each conversion. */
bogdanm	0:9b334a45a8ff	511	/* For code simplicity sake, this particular case is generalized to */
bogdanm	0:9b334a45a8ff	512	/* ADC configured in DMA mode and polling for end of each conversion. */
bogdanm	0:9b334a45a8ff	513	if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
bogdanm	0:9b334a45a8ff	514	HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
bogdanm	0:9b334a45a8ff	515	{
bogdanm	0:9b334a45a8ff	516	/* Update ADC state machine to error */
bogdanm	0:9b334a45a8ff	517	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	518
bogdanm	0:9b334a45a8ff	519	/* Process unlocked */
bogdanm	0:9b334a45a8ff	520	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	521
bogdanm	0:9b334a45a8ff	522	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	523	}
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525	/* Get tick */
bogdanm	0:9b334a45a8ff	526	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	527
bogdanm	0:9b334a45a8ff	528	/* Check End of conversion flag */
bogdanm	0:9b334a45a8ff	529	while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
bogdanm	0:9b334a45a8ff	530	{
bogdanm	0:9b334a45a8ff	531	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	532	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	533	{
bogdanm	0:9b334a45a8ff	534	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	535	{
bogdanm	0:9b334a45a8ff	536	hadc->State= HAL_ADC_STATE_TIMEOUT;
bogdanm	0:9b334a45a8ff	537	/* Process unlocked */
bogdanm	0:9b334a45a8ff	538	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	539	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	540	}
bogdanm	0:9b334a45a8ff	541	}
bogdanm	0:9b334a45a8ff	542	}
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	/* Check if an injected conversion is ready */
bogdanm	0:9b334a45a8ff	545	if(hadc->State == HAL_ADC_STATE_EOC_INJ)
bogdanm	0:9b334a45a8ff	546	{
bogdanm	0:9b334a45a8ff	547	/* Change ADC state */
bogdanm	0:9b334a45a8ff	548	hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm	0:9b334a45a8ff	549	}
bogdanm	0:9b334a45a8ff	550	else
bogdanm	0:9b334a45a8ff	551	{
bogdanm	0:9b334a45a8ff	552	/* Change ADC state */
bogdanm	0:9b334a45a8ff	553	hadc->State = HAL_ADC_STATE_EOC_REG;
bogdanm	0:9b334a45a8ff	554	}
bogdanm	0:9b334a45a8ff	555
bogdanm	0:9b334a45a8ff	556	/* Return ADC state */
bogdanm	0:9b334a45a8ff	557	return HAL_OK;
bogdanm	0:9b334a45a8ff	558	}
bogdanm	0:9b334a45a8ff	559
bogdanm	0:9b334a45a8ff	560	/**
bogdanm	0:9b334a45a8ff	561	* @brief Poll for conversion event
bogdanm	0:9b334a45a8ff	562	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	563	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	564	* @param EventType: the ADC event type.
bogdanm	0:9b334a45a8ff	565	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	566	* @arg ADC_AWD_EVENT: ADC Analog watch Dog event.
bogdanm	0:9b334a45a8ff	567	* @arg ADC_OVR_EVENT: ADC Overrun event.
bogdanm	0:9b334a45a8ff	568	* @param Timeout: Timeout value in millisecond.
bogdanm	0:9b334a45a8ff	569	* @retval HAL status
bogdanm	0:9b334a45a8ff	570	*/
bogdanm	0:9b334a45a8ff	571	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	572	{
bogdanm	0:9b334a45a8ff	573	uint32_t tickstart = 0;
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	/* Check the parameters */
bogdanm	0:9b334a45a8ff	576	assert_param(IS_ADC_EVENT_TYPE(EventType));
bogdanm	0:9b334a45a8ff	577
bogdanm	0:9b334a45a8ff	578	/* Get tick */
bogdanm	0:9b334a45a8ff	579	tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	/* Check selected event flag */
bogdanm	0:9b334a45a8ff	582	while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
bogdanm	0:9b334a45a8ff	583	{
bogdanm	0:9b334a45a8ff	584	/* Check for the Timeout */
bogdanm	0:9b334a45a8ff	585	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	586	{
bogdanm	0:9b334a45a8ff	587	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
bogdanm	0:9b334a45a8ff	588	{
bogdanm	0:9b334a45a8ff	589	hadc->State= HAL_ADC_STATE_TIMEOUT;
bogdanm	0:9b334a45a8ff	590	/* Process unlocked */
bogdanm	0:9b334a45a8ff	591	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	592	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	593	}
bogdanm	0:9b334a45a8ff	594	}
bogdanm	0:9b334a45a8ff	595	}
bogdanm	0:9b334a45a8ff	596
bogdanm	0:9b334a45a8ff	597	/* Check analog watchdog flag */
bogdanm	0:9b334a45a8ff	598	if(EventType == ADC_AWD_EVENT)
bogdanm	0:9b334a45a8ff	599	{
bogdanm	0:9b334a45a8ff	600	/* Change ADC state */
bogdanm	0:9b334a45a8ff	601	hadc->State = HAL_ADC_STATE_AWD;
bogdanm	0:9b334a45a8ff	602
bogdanm	0:9b334a45a8ff	603	/* Clear the ADCx's analog watchdog flag */
bogdanm	0:9b334a45a8ff	604	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
bogdanm	0:9b334a45a8ff	605	}
bogdanm	0:9b334a45a8ff	606	else
bogdanm	0:9b334a45a8ff	607	{
bogdanm	0:9b334a45a8ff	608	/* Change ADC state */
bogdanm	0:9b334a45a8ff	609	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	610
bogdanm	0:9b334a45a8ff	611	/* Clear the ADCx's Overrun flag */
bogdanm	0:9b334a45a8ff	612	__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
bogdanm	0:9b334a45a8ff	613	}
bogdanm	0:9b334a45a8ff	614
bogdanm	0:9b334a45a8ff	615	/* Return ADC state */
bogdanm	0:9b334a45a8ff	616	return HAL_OK;
bogdanm	0:9b334a45a8ff	617	}
bogdanm	0:9b334a45a8ff	618
bogdanm	0:9b334a45a8ff	619
bogdanm	0:9b334a45a8ff	620	/**
bogdanm	0:9b334a45a8ff	621	* @brief Enables the interrupt and starts ADC conversion of regular channels.
bogdanm	0:9b334a45a8ff	622	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	623	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	624	* @retval HAL status.
bogdanm	0:9b334a45a8ff	625	*/
bogdanm	0:9b334a45a8ff	626	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	627	{
bogdanm	0:9b334a45a8ff	628	__IO uint32_t counter = 0;
bogdanm	0:9b334a45a8ff	629
bogdanm	0:9b334a45a8ff	630	/* Check the parameters */
bogdanm	0:9b334a45a8ff	631	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	632	assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
bogdanm	0:9b334a45a8ff	633
bogdanm	0:9b334a45a8ff	634	/* Process locked */
bogdanm	0:9b334a45a8ff	635	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	636
bogdanm	0:9b334a45a8ff	637	/* Check if an injected conversion is ongoing */
bogdanm	0:9b334a45a8ff	638	if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
bogdanm	0:9b334a45a8ff	639	{
bogdanm	0:9b334a45a8ff	640	/* Change ADC state */
bogdanm	0:9b334a45a8ff	641	hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
bogdanm	0:9b334a45a8ff	642	}
bogdanm	0:9b334a45a8ff	643	else
bogdanm	0:9b334a45a8ff	644	{
bogdanm	0:9b334a45a8ff	645	/* Change ADC state */
bogdanm	0:9b334a45a8ff	646	hadc->State = HAL_ADC_STATE_BUSY_REG;
bogdanm	0:9b334a45a8ff	647	}
bogdanm	0:9b334a45a8ff	648
bogdanm	0:9b334a45a8ff	649	/* Set ADC error code to none */
bogdanm	0:9b334a45a8ff	650	hadc->ErrorCode = HAL_ADC_ERROR_NONE;
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/* Check if ADC peripheral is disabled in order to enable it and wait during
bogdanm	0:9b334a45a8ff	653	Tstab time the ADC's stabilization */
bogdanm	0:9b334a45a8ff	654	if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
bogdanm	0:9b334a45a8ff	655	{
bogdanm	0:9b334a45a8ff	656	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	657	__HAL_ADC_ENABLE(hadc);
bogdanm	0:9b334a45a8ff	658
bogdanm	0:9b334a45a8ff	659	/* Delay for ADC stabilization time */
bogdanm	0:9b334a45a8ff	660	/* Compute number of CPU cycles to wait for */
bogdanm	0:9b334a45a8ff	661	counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
bogdanm	0:9b334a45a8ff	662	while(counter != 0)
bogdanm	0:9b334a45a8ff	663	{
bogdanm	0:9b334a45a8ff	664	counter--;
bogdanm	0:9b334a45a8ff	665	}
bogdanm	0:9b334a45a8ff	666	}
bogdanm	0:9b334a45a8ff	667
bogdanm	0:9b334a45a8ff	668	/* Enable the ADC overrun interrupt */
bogdanm	0:9b334a45a8ff	669	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	670
bogdanm	0:9b334a45a8ff	671	/* Enable the ADC end of conversion interrupt for regular group */
bogdanm	0:9b334a45a8ff	672	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	673
bogdanm	0:9b334a45a8ff	674	/* Process unlocked */
bogdanm	0:9b334a45a8ff	675	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	676
bogdanm	0:9b334a45a8ff	677	/* Check if Multimode enabled */
bogdanm	0:9b334a45a8ff	678	if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
bogdanm	0:9b334a45a8ff	679	{
bogdanm	0:9b334a45a8ff	680	/* if no external trigger present enable software conversion of regular channels */
bogdanm	0:9b334a45a8ff	681	if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
bogdanm	0:9b334a45a8ff	682	{
bogdanm	0:9b334a45a8ff	683	/* Enable the selected ADC software conversion for regular group */
bogdanm	0:9b334a45a8ff	684	hadc->Instance->CR2 \|= (uint32_t)ADC_CR2_SWSTART;
bogdanm	0:9b334a45a8ff	685	}
bogdanm	0:9b334a45a8ff	686	}
bogdanm	0:9b334a45a8ff	687	else
bogdanm	0:9b334a45a8ff	688	{
bogdanm	0:9b334a45a8ff	689	/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
bogdanm	0:9b334a45a8ff	690	if((hadc->Instance == (ADC_TypeDef*)0x40012000) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
bogdanm	0:9b334a45a8ff	691	{
bogdanm	0:9b334a45a8ff	692	/* Enable the selected ADC software conversion for regular group */
bogdanm	0:9b334a45a8ff	693	hadc->Instance->CR2 \|= (uint32_t)ADC_CR2_SWSTART;
bogdanm	0:9b334a45a8ff	694	}
bogdanm	0:9b334a45a8ff	695	}
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697	/* Return function status */
bogdanm	0:9b334a45a8ff	698	return HAL_OK;
bogdanm	0:9b334a45a8ff	699	}
bogdanm	0:9b334a45a8ff	700
bogdanm	0:9b334a45a8ff	701	/**
bogdanm	0:9b334a45a8ff	702	* @brief Disables the interrupt and stop ADC conversion of regular channels.
bogdanm	0:9b334a45a8ff	703	*
bogdanm	0:9b334a45a8ff	704	* @note Caution: This function will stop also injected channels.
bogdanm	0:9b334a45a8ff	705	*
bogdanm	0:9b334a45a8ff	706	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	707	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	708	* @retval HAL status.
bogdanm	0:9b334a45a8ff	709	*/
bogdanm	0:9b334a45a8ff	710	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	711	{
bogdanm	0:9b334a45a8ff	712	/* Disable the ADC end of conversion interrupt for regular group */
bogdanm	0:9b334a45a8ff	713	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	714
bogdanm	0:9b334a45a8ff	715	/* Disable the ADC end of conversion interrupt for injected group */
bogdanm	0:9b334a45a8ff	716	__HAL_ADC_DISABLE_IT(hadc, ADC_CR1_JEOCIE);
bogdanm	0:9b334a45a8ff	717
bogdanm	0:9b334a45a8ff	718	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	719	__HAL_ADC_DISABLE(hadc);
bogdanm	0:9b334a45a8ff	720
bogdanm	0:9b334a45a8ff	721	/* Change ADC state */
bogdanm	0:9b334a45a8ff	722	hadc->State = HAL_ADC_STATE_READY;
bogdanm	0:9b334a45a8ff	723
bogdanm	0:9b334a45a8ff	724	/* Return function status */
bogdanm	0:9b334a45a8ff	725	return HAL_OK;
bogdanm	0:9b334a45a8ff	726	}
bogdanm	0:9b334a45a8ff	727
bogdanm	0:9b334a45a8ff	728	/**
bogdanm	0:9b334a45a8ff	729	* @brief Handles ADC interrupt request
bogdanm	0:9b334a45a8ff	730	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	731	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	732	* @retval None
bogdanm	0:9b334a45a8ff	733	*/
bogdanm	0:9b334a45a8ff	734	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	735	{
bogdanm	0:9b334a45a8ff	736	uint32_t tmp1 = 0, tmp2 = 0;
bogdanm	0:9b334a45a8ff	737
bogdanm	0:9b334a45a8ff	738	/* Check the parameters */
bogdanm	0:9b334a45a8ff	739	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	740	assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
bogdanm	0:9b334a45a8ff	741	assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
bogdanm	0:9b334a45a8ff	742
bogdanm	0:9b334a45a8ff	743	tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	744	tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	745	/* Check End of conversion flag for regular channels */
bogdanm	0:9b334a45a8ff	746	if(tmp1 && tmp2)
bogdanm	0:9b334a45a8ff	747	{
bogdanm	0:9b334a45a8ff	748	/* Check if an injected conversion is ready */
bogdanm	0:9b334a45a8ff	749	if(hadc->State == HAL_ADC_STATE_EOC_INJ)
bogdanm	0:9b334a45a8ff	750	{
bogdanm	0:9b334a45a8ff	751	/* Change ADC state */
bogdanm	0:9b334a45a8ff	752	hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm	0:9b334a45a8ff	753	}
bogdanm	0:9b334a45a8ff	754	else
bogdanm	0:9b334a45a8ff	755	{
bogdanm	0:9b334a45a8ff	756	/* Change ADC state */
bogdanm	0:9b334a45a8ff	757	hadc->State = HAL_ADC_STATE_EOC_REG;
bogdanm	0:9b334a45a8ff	758	}
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760	if((hadc->Init.ContinuousConvMode == DISABLE) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
bogdanm	0:9b334a45a8ff	761	{
bogdanm	0:9b334a45a8ff	762	if(hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
bogdanm	0:9b334a45a8ff	763	{
bogdanm	0:9b334a45a8ff	764	/* DISABLE the ADC end of conversion interrupt for regular group */
bogdanm	0:9b334a45a8ff	765	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	/* DISABLE the ADC overrun interrupt */
bogdanm	0:9b334a45a8ff	768	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	769	}
bogdanm	0:9b334a45a8ff	770	else
bogdanm	0:9b334a45a8ff	771	{
bogdanm	0:9b334a45a8ff	772	if (hadc->NbrOfCurrentConversionRank == 0)
bogdanm	0:9b334a45a8ff	773	{
bogdanm	0:9b334a45a8ff	774	hadc->NbrOfCurrentConversionRank = hadc->Init.NbrOfConversion;
bogdanm	0:9b334a45a8ff	775	}
bogdanm	0:9b334a45a8ff	776
bogdanm	0:9b334a45a8ff	777	/* Decrement the number of conversion when an interrupt occurs */
bogdanm	0:9b334a45a8ff	778	hadc->NbrOfCurrentConversionRank--;
bogdanm	0:9b334a45a8ff	779
bogdanm	0:9b334a45a8ff	780	/* Check if all conversions are finished */
bogdanm	0:9b334a45a8ff	781	if(hadc->NbrOfCurrentConversionRank == 0)
bogdanm	0:9b334a45a8ff	782	{
bogdanm	0:9b334a45a8ff	783	/* DISABLE the ADC end of conversion interrupt for regular group */
bogdanm	0:9b334a45a8ff	784	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
bogdanm	0:9b334a45a8ff	785
bogdanm	0:9b334a45a8ff	786	/* DISABLE the ADC overrun interrupt */
bogdanm	0:9b334a45a8ff	787	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	788	}
bogdanm	0:9b334a45a8ff	789	}
bogdanm	0:9b334a45a8ff	790	}
bogdanm	0:9b334a45a8ff	791
bogdanm	0:9b334a45a8ff	792	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	793	HAL_ADC_ConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	794
bogdanm	0:9b334a45a8ff	795	/* Clear the ADCx flag for regular end of conversion */
bogdanm	0:9b334a45a8ff	796	__HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_EOC);
bogdanm	0:9b334a45a8ff	797	}
bogdanm	0:9b334a45a8ff	798
bogdanm	0:9b334a45a8ff	799	tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);
bogdanm	0:9b334a45a8ff	800	tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);
bogdanm	0:9b334a45a8ff	801	/* Check End of conversion flag for injected channels */
bogdanm	0:9b334a45a8ff	802	if(tmp1 && tmp2)
bogdanm	0:9b334a45a8ff	803	{
bogdanm	0:9b334a45a8ff	804	/* Check if a regular conversion is ready */
bogdanm	0:9b334a45a8ff	805	if(hadc->State == HAL_ADC_STATE_EOC_REG)
bogdanm	0:9b334a45a8ff	806	{
bogdanm	0:9b334a45a8ff	807	/* Change ADC state */
bogdanm	0:9b334a45a8ff	808	hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm	0:9b334a45a8ff	809	}
bogdanm	0:9b334a45a8ff	810	else
bogdanm	0:9b334a45a8ff	811	{
bogdanm	0:9b334a45a8ff	812	/* Change ADC state */
bogdanm	0:9b334a45a8ff	813	hadc->State = HAL_ADC_STATE_EOC_INJ;
bogdanm	0:9b334a45a8ff	814	}
bogdanm	0:9b334a45a8ff	815
bogdanm	0:9b334a45a8ff	816	tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
bogdanm	0:9b334a45a8ff	817	tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
bogdanm	0:9b334a45a8ff	818	if(((hadc->Init.ContinuousConvMode == DISABLE) \|\| tmp1) && tmp2)
bogdanm	0:9b334a45a8ff	819	{
bogdanm	0:9b334a45a8ff	820	/* DISABLE the ADC end of conversion interrupt for injected group */
bogdanm	0:9b334a45a8ff	821	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
bogdanm	0:9b334a45a8ff	822	}
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	825	HAL_ADCEx_InjectedConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	826
bogdanm	0:9b334a45a8ff	827	/* Clear the ADCx flag for injected end of conversion */
bogdanm	0:9b334a45a8ff	828	__HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC);
bogdanm	0:9b334a45a8ff	829	}
bogdanm	0:9b334a45a8ff	830
bogdanm	0:9b334a45a8ff	831	tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);
bogdanm	0:9b334a45a8ff	832	tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);
bogdanm	0:9b334a45a8ff	833	/* Check Analog watchdog flag */
bogdanm	0:9b334a45a8ff	834	if(tmp1 && tmp2)
bogdanm	0:9b334a45a8ff	835	{
bogdanm	0:9b334a45a8ff	836	/* Change ADC state */
bogdanm	0:9b334a45a8ff	837	hadc->State = HAL_ADC_STATE_AWD;
bogdanm	0:9b334a45a8ff	838
bogdanm	0:9b334a45a8ff	839	/* Clear the ADCx's Analog watchdog flag */
bogdanm	0:9b334a45a8ff	840	__HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
bogdanm	0:9b334a45a8ff	841
bogdanm	0:9b334a45a8ff	842	/* Level out of window callback */
bogdanm	0:9b334a45a8ff	843	HAL_ADC_LevelOutOfWindowCallback(hadc);
bogdanm	0:9b334a45a8ff	844	}
bogdanm	0:9b334a45a8ff	845
bogdanm	0:9b334a45a8ff	846	tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);
bogdanm	0:9b334a45a8ff	847	tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	848	/* Check Overrun flag */
bogdanm	0:9b334a45a8ff	849	if(tmp1 && tmp2)
bogdanm	0:9b334a45a8ff	850	{
bogdanm	0:9b334a45a8ff	851	/* Change ADC state to overrun state */
bogdanm	0:9b334a45a8ff	852	hadc->State = HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	/* Set ADC error code to overrun */
bogdanm	0:9b334a45a8ff	855	hadc->ErrorCode \|= HAL_ADC_ERROR_OVR;
bogdanm	0:9b334a45a8ff	856
bogdanm	0:9b334a45a8ff	857	/* Clear the Overrun flag */
bogdanm	0:9b334a45a8ff	858	__HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_OVR);
bogdanm	0:9b334a45a8ff	859
bogdanm	0:9b334a45a8ff	860	/* Error callback */
bogdanm	0:9b334a45a8ff	861	HAL_ADC_ErrorCallback(hadc);
bogdanm	0:9b334a45a8ff	862	}
bogdanm	0:9b334a45a8ff	863	}
bogdanm	0:9b334a45a8ff	864
bogdanm	0:9b334a45a8ff	865	/**
bogdanm	0:9b334a45a8ff	866	* @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
bogdanm	0:9b334a45a8ff	867	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	868	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	869	* @param pData: The destination Buffer address.
bogdanm	0:9b334a45a8ff	870	* @param Length: The length of data to be transferred from ADC peripheral to memory.
bogdanm	0:9b334a45a8ff	871	* @retval HAL status
bogdanm	0:9b334a45a8ff	872	*/
bogdanm	0:9b334a45a8ff	873	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
bogdanm	0:9b334a45a8ff	874	{
bogdanm	0:9b334a45a8ff	875	__IO uint32_t counter = 0;
bogdanm	0:9b334a45a8ff	876
bogdanm	0:9b334a45a8ff	877	/* Check the parameters */
bogdanm	0:9b334a45a8ff	878	assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
bogdanm	0:9b334a45a8ff	879	assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
bogdanm	0:9b334a45a8ff	880
bogdanm	0:9b334a45a8ff	881	/* Process locked */
bogdanm	0:9b334a45a8ff	882	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	883
bogdanm	0:9b334a45a8ff	884	/* Enable ADC overrun interrupt */
bogdanm	0:9b334a45a8ff	885	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	886
bogdanm	0:9b334a45a8ff	887	/* Enable ADC DMA mode */
bogdanm	0:9b334a45a8ff	888	hadc->Instance->CR2 \|= ADC_CR2_DMA;
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/* Set the DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	891	hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
bogdanm	0:9b334a45a8ff	892
bogdanm	0:9b334a45a8ff	893	/* Set the DMA half transfer complete callback */
bogdanm	0:9b334a45a8ff	894	hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
bogdanm	0:9b334a45a8ff	895
bogdanm	0:9b334a45a8ff	896	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	897	hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
bogdanm	0:9b334a45a8ff	898
bogdanm	0:9b334a45a8ff	899	/* Enable the DMA Stream */
bogdanm	0:9b334a45a8ff	900	HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
bogdanm	0:9b334a45a8ff	901
bogdanm	0:9b334a45a8ff	902	/* Change ADC state */
bogdanm	0:9b334a45a8ff	903	hadc->State = HAL_ADC_STATE_BUSY_REG;
bogdanm	0:9b334a45a8ff	904
bogdanm	0:9b334a45a8ff	905	/* Process unlocked */
bogdanm	0:9b334a45a8ff	906	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	907
bogdanm	0:9b334a45a8ff	908	/* Check if ADC peripheral is disabled in order to enable it and wait during
bogdanm	0:9b334a45a8ff	909	Tstab time the ADC's stabilization */
bogdanm	0:9b334a45a8ff	910	if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
bogdanm	0:9b334a45a8ff	911	{
bogdanm	0:9b334a45a8ff	912	/* Enable the Peripheral */
bogdanm	0:9b334a45a8ff	913	__HAL_ADC_ENABLE(hadc);
bogdanm	0:9b334a45a8ff	914
bogdanm	0:9b334a45a8ff	915	/* Delay for ADC stabilization time */
bogdanm	0:9b334a45a8ff	916	/* Compute number of CPU cycles to wait for */
bogdanm	0:9b334a45a8ff	917	counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
bogdanm	0:9b334a45a8ff	918	while(counter != 0)
bogdanm	0:9b334a45a8ff	919	{
bogdanm	0:9b334a45a8ff	920	counter--;
bogdanm	0:9b334a45a8ff	921	}
bogdanm	0:9b334a45a8ff	922	}
bogdanm	0:9b334a45a8ff	923
bogdanm	0:9b334a45a8ff	924	/* if no external trigger present enable software conversion of regular channels */
bogdanm	0:9b334a45a8ff	925	if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
bogdanm	0:9b334a45a8ff	926	{
bogdanm	0:9b334a45a8ff	927	/* Enable the selected ADC software conversion for regular group */
bogdanm	0:9b334a45a8ff	928	hadc->Instance->CR2 \|= ADC_CR2_SWSTART;
bogdanm	0:9b334a45a8ff	929	}
bogdanm	0:9b334a45a8ff	930
bogdanm	0:9b334a45a8ff	931	/* Return function status */
bogdanm	0:9b334a45a8ff	932	return HAL_OK;
bogdanm	0:9b334a45a8ff	933	}
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	/**
bogdanm	0:9b334a45a8ff	936	* @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral
bogdanm	0:9b334a45a8ff	937	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	938	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	939	* @retval HAL status
bogdanm	0:9b334a45a8ff	940	*/
bogdanm	0:9b334a45a8ff	941	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	942	{
bogdanm	0:9b334a45a8ff	943	/* Disable the Peripheral */
bogdanm	0:9b334a45a8ff	944	__HAL_ADC_DISABLE(hadc);
bogdanm	0:9b334a45a8ff	945
bogdanm	0:9b334a45a8ff	946	/* Disable ADC overrun interrupt */
bogdanm	0:9b334a45a8ff	947	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
bogdanm	0:9b334a45a8ff	948
bogdanm	0:9b334a45a8ff	949	/* Disable the selected ADC DMA mode */
bogdanm	0:9b334a45a8ff	950	hadc->Instance->CR2 &= ~ADC_CR2_DMA;
bogdanm	0:9b334a45a8ff	951
bogdanm	0:9b334a45a8ff	952	/* Disable the ADC DMA Stream */
bogdanm	0:9b334a45a8ff	953	HAL_DMA_Abort(hadc->DMA_Handle);
bogdanm	0:9b334a45a8ff	954
bogdanm	0:9b334a45a8ff	955	/* Change ADC state */
bogdanm	0:9b334a45a8ff	956	hadc->State = HAL_ADC_STATE_READY;
bogdanm	0:9b334a45a8ff	957
bogdanm	0:9b334a45a8ff	958	/* Return function status */
bogdanm	0:9b334a45a8ff	959	return HAL_OK;
bogdanm	0:9b334a45a8ff	960	}
bogdanm	0:9b334a45a8ff	961
bogdanm	0:9b334a45a8ff	962	/**
bogdanm	0:9b334a45a8ff	963	* @brief Gets the converted value from data register of regular channel.
bogdanm	0:9b334a45a8ff	964	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	965	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	966	* @retval Converted value
bogdanm	0:9b334a45a8ff	967	*/
bogdanm	0:9b334a45a8ff	968	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	969	{
bogdanm	0:9b334a45a8ff	970	/* Return the selected ADC converted value */
bogdanm	0:9b334a45a8ff	971	return hadc->Instance->DR;
bogdanm	0:9b334a45a8ff	972	}
bogdanm	0:9b334a45a8ff	973
bogdanm	0:9b334a45a8ff	974	/**
bogdanm	0:9b334a45a8ff	975	* @brief Regular conversion complete callback in non blocking mode
bogdanm	0:9b334a45a8ff	976	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	977	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	978	* @retval None
bogdanm	0:9b334a45a8ff	979	*/
bogdanm	0:9b334a45a8ff	980	__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	981	{
bogdanm	0:9b334a45a8ff	982	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	983	the HAL_ADC_ConvCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	984	*/
bogdanm	0:9b334a45a8ff	985	}
bogdanm	0:9b334a45a8ff	986
bogdanm	0:9b334a45a8ff	987	/**
bogdanm	0:9b334a45a8ff	988	* @brief Regular conversion half DMA transfer callback in non blocking mode
bogdanm	0:9b334a45a8ff	989	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	990	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	991	* @retval None
bogdanm	0:9b334a45a8ff	992	*/
bogdanm	0:9b334a45a8ff	993	__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	994	{
bogdanm	0:9b334a45a8ff	995	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	996	the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	997	*/
bogdanm	0:9b334a45a8ff	998	}
bogdanm	0:9b334a45a8ff	999
bogdanm	0:9b334a45a8ff	1000	/**
bogdanm	0:9b334a45a8ff	1001	* @brief Analog watchdog callback in non blocking mode
bogdanm	0:9b334a45a8ff	1002	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1003	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	1004	* @retval None
bogdanm	0:9b334a45a8ff	1005	*/
bogdanm	0:9b334a45a8ff	1006	__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1007	{
bogdanm	0:9b334a45a8ff	1008	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1009	the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1010	*/
bogdanm	0:9b334a45a8ff	1011	}
bogdanm	0:9b334a45a8ff	1012
bogdanm	0:9b334a45a8ff	1013	/**
bogdanm	0:9b334a45a8ff	1014	* @brief Error ADC callback.
bogdanm	0:9b334a45a8ff	1015	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1016	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	1017	* @retval None
bogdanm	0:9b334a45a8ff	1018	*/
bogdanm	0:9b334a45a8ff	1019	__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
bogdanm	0:9b334a45a8ff	1020	{
bogdanm	0:9b334a45a8ff	1021	/* NOTE : This function Should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1022	the HAL_ADC_ErrorCallback could be implemented in the user file
bogdanm	0:9b334a45a8ff	1023	*/
bogdanm	0:9b334a45a8ff	1024	}
bogdanm	0:9b334a45a8ff	1025
bogdanm	0:9b334a45a8ff	1026	/**
bogdanm	0:9b334a45a8ff	1027	* @}
bogdanm	0:9b334a45a8ff	1028	*/
bogdanm	0:9b334a45a8ff	1029
bogdanm	0:9b334a45a8ff	1030	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
bogdanm	0:9b334a45a8ff	1031	* @brief Peripheral Control functions
bogdanm	0:9b334a45a8ff	1032	*
bogdanm	0:9b334a45a8ff	1033	@verbatim
bogdanm	0:9b334a45a8ff	1034	===============================================================================
bogdanm	0:9b334a45a8ff	1035	##### Peripheral Control functions #####
bogdanm	0:9b334a45a8ff	1036	===============================================================================
bogdanm	0:9b334a45a8ff	1037	[..] This section provides functions allowing to:
bogdanm	0:9b334a45a8ff	1038	(+) Configure regular channels.
bogdanm	0:9b334a45a8ff	1039	(+) Configure injected channels.
bogdanm	0:9b334a45a8ff	1040	(+) Configure multimode.
bogdanm	0:9b334a45a8ff	1041	(+) Configure the analog watch dog.
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	@endverbatim
bogdanm	0:9b334a45a8ff	1044	* @{
bogdanm	0:9b334a45a8ff	1045	*/
bogdanm	0:9b334a45a8ff	1046
bogdanm	0:9b334a45a8ff	1047	/**
bogdanm	0:9b334a45a8ff	1048	* @brief Configures for the selected ADC regular channel its corresponding
bogdanm	0:9b334a45a8ff	1049	* rank in the sequencer and its sample time.
bogdanm	0:9b334a45a8ff	1050	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1051	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	1052	* @param sConfig: ADC configuration structure.
bogdanm	0:9b334a45a8ff	1053	* @retval HAL status
bogdanm	0:9b334a45a8ff	1054	*/
bogdanm	0:9b334a45a8ff	1055	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
bogdanm	0:9b334a45a8ff	1056	{
bogdanm	0:9b334a45a8ff	1057	__IO uint32_t counter = 0;
bogdanm	0:9b334a45a8ff	1058
bogdanm	0:9b334a45a8ff	1059	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1060	assert_param(IS_ADC_CHANNEL(sConfig->Channel));
bogdanm	0:9b334a45a8ff	1061	assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
bogdanm	0:9b334a45a8ff	1062	assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	/* Process locked */
bogdanm	0:9b334a45a8ff	1065	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1066
bogdanm	0:9b334a45a8ff	1067	/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
bogdanm	0:9b334a45a8ff	1068	if (sConfig->Channel > ADC_CHANNEL_9)
bogdanm	0:9b334a45a8ff	1069	{
bogdanm	0:9b334a45a8ff	1070	/* Clear the old sample time */
bogdanm	0:9b334a45a8ff	1071	hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
bogdanm	0:9b334a45a8ff	1072
bogdanm	0:9b334a45a8ff	1073	/* Set the new sample time */
bogdanm	0:9b334a45a8ff	1074	hadc->Instance->SMPR1 \|= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
bogdanm	0:9b334a45a8ff	1075	}
bogdanm	0:9b334a45a8ff	1076	else /* ADC_Channel include in ADC_Channel_[0..9] */
bogdanm	0:9b334a45a8ff	1077	{
bogdanm	0:9b334a45a8ff	1078	/* Clear the old sample time */
bogdanm	0:9b334a45a8ff	1079	hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
bogdanm	0:9b334a45a8ff	1080
bogdanm	0:9b334a45a8ff	1081	/* Set the new sample time */
bogdanm	0:9b334a45a8ff	1082	hadc->Instance->SMPR2 \|= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
bogdanm	0:9b334a45a8ff	1083	}
bogdanm	0:9b334a45a8ff	1084
bogdanm	0:9b334a45a8ff	1085	/* For Rank 1 to 6 */
bogdanm	0:9b334a45a8ff	1086	if (sConfig->Rank < 7)
bogdanm	0:9b334a45a8ff	1087	{
bogdanm	0:9b334a45a8ff	1088	/* Clear the old SQx bits for the selected rank */
bogdanm	0:9b334a45a8ff	1089	hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
bogdanm	0:9b334a45a8ff	1090
bogdanm	0:9b334a45a8ff	1091	/* Set the SQx bits for the selected rank */
bogdanm	0:9b334a45a8ff	1092	hadc->Instance->SQR3 \|= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
bogdanm	0:9b334a45a8ff	1093	}
bogdanm	0:9b334a45a8ff	1094	/* For Rank 7 to 12 */
bogdanm	0:9b334a45a8ff	1095	else if (sConfig->Rank < 13)
bogdanm	0:9b334a45a8ff	1096	{
bogdanm	0:9b334a45a8ff	1097	/* Clear the old SQx bits for the selected rank */
bogdanm	0:9b334a45a8ff	1098	hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
bogdanm	0:9b334a45a8ff	1099
bogdanm	0:9b334a45a8ff	1100	/* Set the SQx bits for the selected rank */
bogdanm	0:9b334a45a8ff	1101	hadc->Instance->SQR2 \|= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
bogdanm	0:9b334a45a8ff	1102	}
bogdanm	0:9b334a45a8ff	1103	/* For Rank 13 to 16 */
bogdanm	0:9b334a45a8ff	1104	else
bogdanm	0:9b334a45a8ff	1105	{
bogdanm	0:9b334a45a8ff	1106	/* Clear the old SQx bits for the selected rank */
bogdanm	0:9b334a45a8ff	1107	hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	/* Set the SQx bits for the selected rank */
bogdanm	0:9b334a45a8ff	1110	hadc->Instance->SQR1 \|= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
bogdanm	0:9b334a45a8ff	1111	}
bogdanm	0:9b334a45a8ff	1112
bogdanm	0:9b334a45a8ff	1113	/* if ADC1 Channel_18 is selected enable VBAT Channel */
bogdanm	0:9b334a45a8ff	1114	if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
bogdanm	0:9b334a45a8ff	1115	{
bogdanm	0:9b334a45a8ff	1116	/* Enable the VBAT channel*/
bogdanm	0:9b334a45a8ff	1117	ADC->CCR \|= ADC_CCR_VBATE;
bogdanm	0:9b334a45a8ff	1118	}
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	/* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
bogdanm	0:9b334a45a8ff	1121	if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) \|\| (sConfig->Channel == ADC_CHANNEL_VREFINT)))
bogdanm	0:9b334a45a8ff	1122	{
bogdanm	0:9b334a45a8ff	1123	/* Enable the TSVREFE channel*/
bogdanm	0:9b334a45a8ff	1124	ADC->CCR \|= ADC_CCR_TSVREFE;
bogdanm	0:9b334a45a8ff	1125
bogdanm	0:9b334a45a8ff	1126	if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
bogdanm	0:9b334a45a8ff	1127	{
bogdanm	0:9b334a45a8ff	1128	/* Delay for temperature sensor stabilization time */
bogdanm	0:9b334a45a8ff	1129	/* Compute number of CPU cycles to wait for */
bogdanm	0:9b334a45a8ff	1130	counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
bogdanm	0:9b334a45a8ff	1131	while(counter != 0)
bogdanm	0:9b334a45a8ff	1132	{
bogdanm	0:9b334a45a8ff	1133	counter--;
bogdanm	0:9b334a45a8ff	1134	}
bogdanm	0:9b334a45a8ff	1135	}
bogdanm	0:9b334a45a8ff	1136	}
bogdanm	0:9b334a45a8ff	1137
bogdanm	0:9b334a45a8ff	1138	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1139	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1140
bogdanm	0:9b334a45a8ff	1141	/* Return function status */
bogdanm	0:9b334a45a8ff	1142	return HAL_OK;
bogdanm	0:9b334a45a8ff	1143	}
bogdanm	0:9b334a45a8ff	1144
bogdanm	0:9b334a45a8ff	1145	/**
bogdanm	0:9b334a45a8ff	1146	* @brief Configures the analog watchdog.
bogdanm	0:9b334a45a8ff	1147	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1148	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	1149	* @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure
bogdanm	0:9b334a45a8ff	1150	* that contains the configuration information of ADC analog watchdog.
bogdanm	0:9b334a45a8ff	1151	* @retval HAL status
bogdanm	0:9b334a45a8ff	1152	*/
bogdanm	0:9b334a45a8ff	1153	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
bogdanm	0:9b334a45a8ff	1154	{
bogdanm	0:9b334a45a8ff	1155	#ifdef USE_FULL_ASSERT
bogdanm	0:9b334a45a8ff	1156	uint32_t tmp = 0;
bogdanm	0:9b334a45a8ff	1157	#endif /* USE_FULL_ASSERT */
bogdanm	0:9b334a45a8ff	1158
bogdanm	0:9b334a45a8ff	1159	/* Check the parameters */
bogdanm	0:9b334a45a8ff	1160	assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));
bogdanm	0:9b334a45a8ff	1161	assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
bogdanm	0:9b334a45a8ff	1162	assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
bogdanm	0:9b334a45a8ff	1163
bogdanm	0:9b334a45a8ff	1164	#ifdef USE_FULL_ASSERT
bogdanm	0:9b334a45a8ff	1165	tmp = ADC_GET_RESOLUTION(hadc);
bogdanm	0:9b334a45a8ff	1166	assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));
bogdanm	0:9b334a45a8ff	1167	assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));
bogdanm	0:9b334a45a8ff	1168	#endif /* USE_FULL_ASSERT */
bogdanm	0:9b334a45a8ff	1169
bogdanm	0:9b334a45a8ff	1170	/* Process locked */
bogdanm	0:9b334a45a8ff	1171	__HAL_LOCK(hadc);
bogdanm	0:9b334a45a8ff	1172
bogdanm	0:9b334a45a8ff	1173	if(AnalogWDGConfig->ITMode == ENABLE)
bogdanm	0:9b334a45a8ff	1174	{
bogdanm	0:9b334a45a8ff	1175	/* Enable the ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	1176	__HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
bogdanm	0:9b334a45a8ff	1177	}
bogdanm	0:9b334a45a8ff	1178	else
bogdanm	0:9b334a45a8ff	1179	{
bogdanm	0:9b334a45a8ff	1180	/* Disable the ADC Analog watchdog interrupt */
bogdanm	0:9b334a45a8ff	1181	__HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
bogdanm	0:9b334a45a8ff	1182	}
bogdanm	0:9b334a45a8ff	1183
bogdanm	0:9b334a45a8ff	1184	/* Clear AWDEN, JAWDEN and AWDSGL bits */
bogdanm	0:9b334a45a8ff	1185	hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN);
bogdanm	0:9b334a45a8ff	1186
bogdanm	0:9b334a45a8ff	1187	/* Set the analog watchdog enable mode */
bogdanm	0:9b334a45a8ff	1188	hadc->Instance->CR1 \|= AnalogWDGConfig->WatchdogMode;
bogdanm	0:9b334a45a8ff	1189
bogdanm	0:9b334a45a8ff	1190	/* Set the high threshold */
bogdanm	0:9b334a45a8ff	1191	hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
bogdanm	0:9b334a45a8ff	1192
bogdanm	0:9b334a45a8ff	1193	/* Set the low threshold */
bogdanm	0:9b334a45a8ff	1194	hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
bogdanm	0:9b334a45a8ff	1195
bogdanm	0:9b334a45a8ff	1196	/* Clear the Analog watchdog channel select bits */
bogdanm	0:9b334a45a8ff	1197	hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;
bogdanm	0:9b334a45a8ff	1198
bogdanm	0:9b334a45a8ff	1199	/* Set the Analog watchdog channel */
bogdanm	0:9b334a45a8ff	1200	hadc->Instance->CR1 \|= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));
bogdanm	0:9b334a45a8ff	1201
bogdanm	0:9b334a45a8ff	1202	/* Process unlocked */
bogdanm	0:9b334a45a8ff	1203	__HAL_UNLOCK(hadc);
bogdanm	0:9b334a45a8ff	1204
bogdanm	0:9b334a45a8ff	1205	/* Return function status */
bogdanm	0:9b334a45a8ff	1206	return HAL_OK;
bogdanm	0:9b334a45a8ff	1207	}
bogdanm	0:9b334a45a8ff	1208
bogdanm	0:9b334a45a8ff	1209	/**
bogdanm	0:9b334a45a8ff	1210	* @}
bogdanm	0:9b334a45a8ff	1211	*/
bogdanm	0:9b334a45a8ff	1212
bogdanm	0:9b334a45a8ff	1213	/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions
bogdanm	0:9b334a45a8ff	1214	* @brief ADC Peripheral State functions
bogdanm	0:9b334a45a8ff	1215	*
bogdanm	0:9b334a45a8ff	1216	@verbatim
bogdanm	0:9b334a45a8ff	1217	===============================================================================
bogdanm	0:9b334a45a8ff	1218	##### Peripheral State and errors functions #####
bogdanm	0:9b334a45a8ff	1219	===============================================================================
bogdanm	0:9b334a45a8ff	1220	[..]
bogdanm	0:9b334a45a8ff	1221	This subsection provides functions allowing to
bogdanm	0:9b334a45a8ff	1222	(+) Check the ADC state
bogdanm	0:9b334a45a8ff	1223	(+) Check the ADC Error
bogdanm	0:9b334a45a8ff	1224
bogdanm	0:9b334a45a8ff	1225	@endverbatim
bogdanm	0:9b334a45a8ff	1226	* @{
bogdanm	0:9b334a45a8ff	1227	*/
bogdanm	0:9b334a45a8ff	1228
bogdanm	0:9b334a45a8ff	1229	/**
bogdanm	0:9b334a45a8ff	1230	* @brief return the ADC state
bogdanm	0:9b334a45a8ff	1231	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1232	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	1233	* @retval HAL state
bogdanm	0:9b334a45a8ff	1234	*/
bogdanm	0:9b334a45a8ff	1235	HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1236	{
bogdanm	0:9b334a45a8ff	1237	/* Return ADC state */
bogdanm	0:9b334a45a8ff	1238	return hadc->State;
bogdanm	0:9b334a45a8ff	1239	}
bogdanm	0:9b334a45a8ff	1240
bogdanm	0:9b334a45a8ff	1241	/**
bogdanm	0:9b334a45a8ff	1242	* @brief Return the ADC error code
bogdanm	0:9b334a45a8ff	1243	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1244	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	1245	* @retval ADC Error Code
bogdanm	0:9b334a45a8ff	1246	*/
bogdanm	0:9b334a45a8ff	1247	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
bogdanm	0:9b334a45a8ff	1248	{
bogdanm	0:9b334a45a8ff	1249	return hadc->ErrorCode;
bogdanm	0:9b334a45a8ff	1250	}
bogdanm	0:9b334a45a8ff	1251
bogdanm	0:9b334a45a8ff	1252	/**
bogdanm	0:9b334a45a8ff	1253	* @}
bogdanm	0:9b334a45a8ff	1254	*/
bogdanm	0:9b334a45a8ff	1255
bogdanm	0:9b334a45a8ff	1256	/** @addtogroup ADC_Private_Functions
bogdanm	0:9b334a45a8ff	1257	* @{
bogdanm	0:9b334a45a8ff	1258	*/
bogdanm	0:9b334a45a8ff	1259
bogdanm	0:9b334a45a8ff	1260	/**
bogdanm	0:9b334a45a8ff	1261	* @brief Initializes the ADCx peripheral according to the specified parameters
bogdanm	0:9b334a45a8ff	1262	* in the ADC_InitStruct without initializing the ADC MSP.
bogdanm	0:9b334a45a8ff	1263	* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1264	* the configuration information for the specified ADC.
bogdanm	0:9b334a45a8ff	1265	* @retval None
bogdanm	0:9b334a45a8ff	1266	*/
bogdanm	0:9b334a45a8ff	1267	static void ADC_Init(ADC_HandleTypeDef* hadc)
bogdanm	0:9b334a45a8ff	1268	{
bogdanm	0:9b334a45a8ff	1269	/* Set ADC parameters */
bogdanm	0:9b334a45a8ff	1270	/* Set the ADC clock prescaler */
bogdanm	0:9b334a45a8ff	1271	ADC->CCR &= ~(ADC_CCR_ADCPRE);
bogdanm	0:9b334a45a8ff	1272	ADC->CCR \|= hadc->Init.ClockPrescaler;
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/* Set ADC scan mode */
bogdanm	0:9b334a45a8ff	1275	hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
bogdanm	0:9b334a45a8ff	1276	hadc->Instance->CR1 \|= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
bogdanm	0:9b334a45a8ff	1277
bogdanm	0:9b334a45a8ff	1278	/* Set ADC resolution */
bogdanm	0:9b334a45a8ff	1279	hadc->Instance->CR1 &= ~(ADC_CR1_RES);
bogdanm	0:9b334a45a8ff	1280	hadc->Instance->CR1 \|= hadc->Init.Resolution;
bogdanm	0:9b334a45a8ff	1281
bogdanm	0:9b334a45a8ff	1282	/* Set ADC data alignment */
bogdanm	0:9b334a45a8ff	1283	hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
bogdanm	0:9b334a45a8ff	1284	hadc->Instance->CR2 \|= hadc->Init.DataAlign;
bogdanm	0:9b334a45a8ff	1285
bogdanm	0:9b334a45a8ff	1286	/* Enable external trigger if trigger selection is different of software */
bogdanm	0:9b334a45a8ff	1287	/* start. */
bogdanm	0:9b334a45a8ff	1288	/* Note: This configuration keeps the hardware feature of parameter */
bogdanm	0:9b334a45a8ff	1289	/* ExternalTrigConvEdge "trigger edge none" equivalent to */
bogdanm	0:9b334a45a8ff	1290	/* software start. */
bogdanm	0:9b334a45a8ff	1291	if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
bogdanm	0:9b334a45a8ff	1292	{
bogdanm	0:9b334a45a8ff	1293	/* Select external trigger to start conversion */
bogdanm	0:9b334a45a8ff	1294	hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
bogdanm	0:9b334a45a8ff	1295	hadc->Instance->CR2 \|= hadc->Init.ExternalTrigConv;
bogdanm	0:9b334a45a8ff	1296
bogdanm	0:9b334a45a8ff	1297	/* Select external trigger polarity */
bogdanm	0:9b334a45a8ff	1298	hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
bogdanm	0:9b334a45a8ff	1299	hadc->Instance->CR2 \|= hadc->Init.ExternalTrigConvEdge;
bogdanm	0:9b334a45a8ff	1300	}
bogdanm	0:9b334a45a8ff	1301	else
bogdanm	0:9b334a45a8ff	1302	{
bogdanm	0:9b334a45a8ff	1303	/* Reset the external trigger */
bogdanm	0:9b334a45a8ff	1304	hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
bogdanm	0:9b334a45a8ff	1305	hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
bogdanm	0:9b334a45a8ff	1306	}
bogdanm	0:9b334a45a8ff	1307
bogdanm	0:9b334a45a8ff	1308	/* Enable or disable ADC continuous conversion mode */
bogdanm	0:9b334a45a8ff	1309	hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
bogdanm	0:9b334a45a8ff	1310	hadc->Instance->CR2 \|= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode);
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	if(hadc->Init.DiscontinuousConvMode != DISABLE)
bogdanm	0:9b334a45a8ff	1313	{
bogdanm	0:9b334a45a8ff	1314	assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
bogdanm	0:9b334a45a8ff	1315
bogdanm	0:9b334a45a8ff	1316	/* Enable the selected ADC regular discontinuous mode */
bogdanm	0:9b334a45a8ff	1317	hadc->Instance->CR1 \|= (uint32_t)ADC_CR1_DISCEN;
bogdanm	0:9b334a45a8ff	1318
bogdanm	0:9b334a45a8ff	1319	/* Set the number of channels to be converted in discontinuous mode */
bogdanm	0:9b334a45a8ff	1320	hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
bogdanm	0:9b334a45a8ff	1321	hadc->Instance->CR1 \|= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
bogdanm	0:9b334a45a8ff	1322	}
bogdanm	0:9b334a45a8ff	1323	else
bogdanm	0:9b334a45a8ff	1324	{
bogdanm	0:9b334a45a8ff	1325	/* Disable the selected ADC regular discontinuous mode */
bogdanm	0:9b334a45a8ff	1326	hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
bogdanm	0:9b334a45a8ff	1327	}
bogdanm	0:9b334a45a8ff	1328
bogdanm	0:9b334a45a8ff	1329	/* Set ADC number of conversion */
bogdanm	0:9b334a45a8ff	1330	hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
bogdanm	0:9b334a45a8ff	1331	hadc->Instance->SQR1 \|= ADC_SQR1(hadc->Init.NbrOfConversion);
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333	/* Enable or disable ADC DMA continuous request */
bogdanm	0:9b334a45a8ff	1334	hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
bogdanm	0:9b334a45a8ff	1335	hadc->Instance->CR2 \|= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests);
bogdanm	0:9b334a45a8ff	1336
bogdanm	0:9b334a45a8ff	1337	/* Enable or disable ADC end of conversion selection */
bogdanm	0:9b334a45a8ff	1338	hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
bogdanm	0:9b334a45a8ff	1339	hadc->Instance->CR2 \|= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
bogdanm	0:9b334a45a8ff	1340	}
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	/**
bogdanm	0:9b334a45a8ff	1343	* @brief DMA transfer complete callback.
bogdanm	0:9b334a45a8ff	1344	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1345	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1346	* @retval None
bogdanm	0:9b334a45a8ff	1347	*/
bogdanm	0:9b334a45a8ff	1348	static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1349	{
bogdanm	0:9b334a45a8ff	1350	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1351
bogdanm	0:9b334a45a8ff	1352	/* Check if an injected conversion is ready */
bogdanm	0:9b334a45a8ff	1353	if(hadc->State == HAL_ADC_STATE_EOC_INJ)
bogdanm	0:9b334a45a8ff	1354	{
bogdanm	0:9b334a45a8ff	1355	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1356	hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
bogdanm	0:9b334a45a8ff	1357	}
bogdanm	0:9b334a45a8ff	1358	else
bogdanm	0:9b334a45a8ff	1359	{
bogdanm	0:9b334a45a8ff	1360	/* Change ADC state */
bogdanm	0:9b334a45a8ff	1361	hadc->State = HAL_ADC_STATE_EOC_REG;
bogdanm	0:9b334a45a8ff	1362	}
bogdanm	0:9b334a45a8ff	1363
bogdanm	0:9b334a45a8ff	1364	HAL_ADC_ConvCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1365	}
bogdanm	0:9b334a45a8ff	1366
bogdanm	0:9b334a45a8ff	1367	/**
bogdanm	0:9b334a45a8ff	1368	* @brief DMA half transfer complete callback.
bogdanm	0:9b334a45a8ff	1369	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1370	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1371	* @retval None
bogdanm	0:9b334a45a8ff	1372	*/
bogdanm	0:9b334a45a8ff	1373	static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1374	{
bogdanm	0:9b334a45a8ff	1375	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1376	/* Conversion complete callback */
bogdanm	0:9b334a45a8ff	1377	HAL_ADC_ConvHalfCpltCallback(hadc);
bogdanm	0:9b334a45a8ff	1378	}
bogdanm	0:9b334a45a8ff	1379
bogdanm	0:9b334a45a8ff	1380	/**
bogdanm	0:9b334a45a8ff	1381	* @brief DMA error callback
bogdanm	0:9b334a45a8ff	1382	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1383	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1384	* @retval None
bogdanm	0:9b334a45a8ff	1385	*/
bogdanm	0:9b334a45a8ff	1386	static void ADC_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1387	{
bogdanm	0:9b334a45a8ff	1388	ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1389	hadc->State= HAL_ADC_STATE_ERROR;
bogdanm	0:9b334a45a8ff	1390	/* Set ADC error code to DMA error */
bogdanm	0:9b334a45a8ff	1391	hadc->ErrorCode \|= HAL_ADC_ERROR_DMA;
bogdanm	0:9b334a45a8ff	1392	HAL_ADC_ErrorCallback(hadc);
bogdanm	0:9b334a45a8ff	1393	}
bogdanm	0:9b334a45a8ff	1394
bogdanm	0:9b334a45a8ff	1395	/**
bogdanm	0:9b334a45a8ff	1396	* @}
bogdanm	0:9b334a45a8ff	1397	*/
bogdanm	0:9b334a45a8ff	1398
bogdanm	0:9b334a45a8ff	1399	/**
bogdanm	0:9b334a45a8ff	1400	* @}
bogdanm	0:9b334a45a8ff	1401	*/
bogdanm	0:9b334a45a8ff	1402
bogdanm	0:9b334a45a8ff	1403	#endif /* HAL_ADC_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	1404	/**
bogdanm	0:9b334a45a8ff	1405	* @}
bogdanm	0:9b334a45a8ff	1406	*/
bogdanm	0:9b334a45a8ff	1407
bogdanm	0:9b334a45a8ff	1408	/**
bogdanm	0:9b334a45a8ff	1409	* @}
bogdanm	0:9b334a45a8ff	1410	*/
bogdanm	0:9b334a45a8ff	1411
bogdanm	0:9b334a45a8ff	1412	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.c@129:2e517c56bcfb, 2016-05-16 (annotated)

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