mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_hrtim.h@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:: nameless129
Date:: Mon May 16 16:50:30 2016 +0000
Revision:: 129:2e517c56bcfb
Parent:: 0:9b334a45a8ff

PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f3xx_hal_hrtim.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.1.0
bogdanm	0:9b334a45a8ff	6	* @date 12-Sept-2014
bogdanm	0:9b334a45a8ff	7	* @brief Header file of HRTIM HAL module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F3xx_HAL_HRTIM_H
bogdanm	0:9b334a45a8ff	40	#define __STM32F3xx_HAL_HRTIM_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	#if defined(STM32F334x8)
bogdanm	0:9b334a45a8ff	47
bogdanm	0:9b334a45a8ff	48	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	49	#include "stm32f3xx_hal_def.h"
bogdanm	0:9b334a45a8ff	50
bogdanm	0:9b334a45a8ff	51	/** @addtogroup STM32F3xx_HAL_Driver
bogdanm	0:9b334a45a8ff	52	* @{
bogdanm	0:9b334a45a8ff	53	*/
bogdanm	0:9b334a45a8ff	54
bogdanm	0:9b334a45a8ff	55	/** @addtogroup HRTIM HRTIM HAL module driver
bogdanm	0:9b334a45a8ff	56	* @{
bogdanm	0:9b334a45a8ff	57	*/
bogdanm	0:9b334a45a8ff	58
bogdanm	0:9b334a45a8ff	59	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	60	/** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
bogdanm	0:9b334a45a8ff	61	* @{
bogdanm	0:9b334a45a8ff	62	*/
bogdanm	0:9b334a45a8ff	63	/** @defgroup HRTIM_Max_Timer HRTIM Max Timer
bogdanm	0:9b334a45a8ff	64	* @{
bogdanm	0:9b334a45a8ff	65	*/
bogdanm	0:9b334a45a8ff	66	#define MAX_HRTIM_TIMER 6
bogdanm	0:9b334a45a8ff	67	/**
bogdanm	0:9b334a45a8ff	68	* @}
bogdanm	0:9b334a45a8ff	69	*/
bogdanm	0:9b334a45a8ff	70	/**
bogdanm	0:9b334a45a8ff	71	* @}
bogdanm	0:9b334a45a8ff	72	*/
bogdanm	0:9b334a45a8ff	73
bogdanm	0:9b334a45a8ff	74	/** @defgroup HRTIM_Exported_Types HRTIM Exported Types
bogdanm	0:9b334a45a8ff	75	* @{
bogdanm	0:9b334a45a8ff	76	*/
bogdanm	0:9b334a45a8ff	77
bogdanm	0:9b334a45a8ff	78	/**
bogdanm	0:9b334a45a8ff	79	* @brief HRTIM Configuration Structure definition - Time base related parameters
bogdanm	0:9b334a45a8ff	80	*/
bogdanm	0:9b334a45a8ff	81	typedef struct
bogdanm	0:9b334a45a8ff	82	{
bogdanm	0:9b334a45a8ff	83	uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance
bogdanm	0:9b334a45a8ff	84	This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */
bogdanm	0:9b334a45a8ff	85	uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals
bogdanm	0:9b334a45a8ff	86	This parameter can be a combination of @ref HRTIM_Synchronization_Options */
bogdanm	0:9b334a45a8ff	87	uint32_t SyncInputSource; /*!< Specifies the external synchronization input source
bogdanm	0:9b334a45a8ff	88	This parameter can be a value of @ref HRTIM_Synchronization_Input_Source */
bogdanm	0:9b334a45a8ff	89	uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
bogdanm	0:9b334a45a8ff	90	This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
bogdanm	0:9b334a45a8ff	91	uint32_t SyncOutputPolarity; /*!< Specifies the conditionning of the event to be sent on the external synchronization outputs
bogdanm	0:9b334a45a8ff	92	This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
bogdanm	0:9b334a45a8ff	93	} HRTIM_InitTypeDef;
bogdanm	0:9b334a45a8ff	94
bogdanm	0:9b334a45a8ff	95	/**
bogdanm	0:9b334a45a8ff	96	* @brief HAL State structures definition
bogdanm	0:9b334a45a8ff	97	*/
bogdanm	0:9b334a45a8ff	98	typedef enum
bogdanm	0:9b334a45a8ff	99	{
bogdanm	0:9b334a45a8ff	100	HAL_HRTIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	0:9b334a45a8ff	101	HAL_HRTIM_STATE_BUSY = 0x02, /!< an internal process is ongoing /
bogdanm	0:9b334a45a8ff	102	HAL_HRTIM_STATE_TIMEOUT = 0x06, /!< Timeout state /
bogdanm	0:9b334a45a8ff	103	HAL_HRTIM_STATE_ERROR = 0x07, /!< Error state /
bogdanm	0:9b334a45a8ff	104	} HAL_HRTIM_StateTypeDef;
bogdanm	0:9b334a45a8ff	105
bogdanm	0:9b334a45a8ff	106	/**
bogdanm	0:9b334a45a8ff	107	* @brief HRTIM Timer Structure definition
bogdanm	0:9b334a45a8ff	108	*/
bogdanm	0:9b334a45a8ff	109	typedef struct
bogdanm	0:9b334a45a8ff	110	{
bogdanm	0:9b334a45a8ff	111	uint32_t CaptureTrigger1; /!< Event(s) triggering capture unit 1 /
bogdanm	0:9b334a45a8ff	112	uint32_t CaptureTrigger2; /!< Event(s) triggering capture unit 2 /
bogdanm	0:9b334a45a8ff	113	uint32_t InterruptRequests; /!< Interrupts requests enabled for the timer /
bogdanm	0:9b334a45a8ff	114	uint32_t DMARequests; /!< DMA requests enabled for the timer /
bogdanm	0:9b334a45a8ff	115	uint32_t DMASrcAddress; /!< Address of the source address of the DMA transfer /
bogdanm	0:9b334a45a8ff	116	uint32_t DMADstAddress; /!< Address of the destination address of the DMA transfer /
bogdanm	0:9b334a45a8ff	117	uint32_t DMASize; /!< Ssize of the DMA transfer /
bogdanm	0:9b334a45a8ff	118	} HRTIM_TimerParamTypeDef;
bogdanm	0:9b334a45a8ff	119
bogdanm	0:9b334a45a8ff	120	/**
bogdanm	0:9b334a45a8ff	121	* @brief HRTIM Handle Structure definition
bogdanm	0:9b334a45a8ff	122	*/
bogdanm	0:9b334a45a8ff	123	typedef struct __HRTIM_HandleTypeDef
bogdanm	0:9b334a45a8ff	124	{
bogdanm	0:9b334a45a8ff	125	HRTIM_TypeDef * Instance; /!< Register base address /
bogdanm	0:9b334a45a8ff	126
bogdanm	0:9b334a45a8ff	127	HRTIM_InitTypeDef Init; /!< HRTIM required parameters /
bogdanm	0:9b334a45a8ff	128
bogdanm	0:9b334a45a8ff	129	HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /!< HRTIM timers - including the master - parameters /
bogdanm	0:9b334a45a8ff	130
bogdanm	0:9b334a45a8ff	131	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	__IO HAL_HRTIM_StateTypeDef State; /!< HRTIM communication state /
bogdanm	0:9b334a45a8ff	134
bogdanm	0:9b334a45a8ff	135	DMA_HandleTypeDef * hdmaMaster; /!< Master timer DMA handle parameters /
bogdanm	0:9b334a45a8ff	136	DMA_HandleTypeDef * hdmaTimerA; /!< Timer A DMA handle parameters /
bogdanm	0:9b334a45a8ff	137	DMA_HandleTypeDef * hdmaTimerB; /!< Timer B DMA handle parameters /
bogdanm	0:9b334a45a8ff	138	DMA_HandleTypeDef * hdmaTimerC; /!< Timer C DMA handle parameters /
bogdanm	0:9b334a45a8ff	139	DMA_HandleTypeDef * hdmaTimerD; /!< Timer D DMA handle parameters /
bogdanm	0:9b334a45a8ff	140	DMA_HandleTypeDef * hdmaTimerE; /!< Timer E DMA handle parameters /
bogdanm	0:9b334a45a8ff	141	} HRTIM_HandleTypeDef;
bogdanm	0:9b334a45a8ff	142
bogdanm	0:9b334a45a8ff	143	/**
bogdanm	0:9b334a45a8ff	144	* @brief Simple output compare mode configuration definition
bogdanm	0:9b334a45a8ff	145	*/
bogdanm	0:9b334a45a8ff	146	typedef struct {
bogdanm	0:9b334a45a8ff	147	uint32_t Period; /*!< Specifies the timer period
bogdanm	0:9b334a45a8ff	148	The period value must be above 3 periods of the fHRTIM clock.
bogdanm	0:9b334a45a8ff	149	Maximum value is = 0xFFDF */
bogdanm	0:9b334a45a8ff	150	uint32_t RepetitionCounter; /*!< Specifies the timer repetition period
bogdanm	0:9b334a45a8ff	151	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm	0:9b334a45a8ff	152	uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
bogdanm	0:9b334a45a8ff	153	This parameter can be any value of @ref HRTIM_Prescaler_Ratio */
bogdanm	0:9b334a45a8ff	154	uint32_t Mode; /*!< Specifies the counter operating mode
bogdanm	0:9b334a45a8ff	155	This parameter can be any value of @ref HRTIM_Mode */
bogdanm	0:9b334a45a8ff	156	} HRTIM_TimeBaseCfgTypeDef;
bogdanm	0:9b334a45a8ff	157
bogdanm	0:9b334a45a8ff	158	/**
bogdanm	0:9b334a45a8ff	159	* @brief Simple output compare mode configuration definition
bogdanm	0:9b334a45a8ff	160	*/
bogdanm	0:9b334a45a8ff	161	typedef struct {
bogdanm	0:9b334a45a8ff	162	uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive)
bogdanm	0:9b334a45a8ff	163	This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
bogdanm	0:9b334a45a8ff	164	uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
bogdanm	0:9b334a45a8ff	165	The compare value must be above or equal to 3 periods of the fHRTIM clock */
bogdanm	0:9b334a45a8ff	166	uint32_t Polarity; /*!< Specifies the output polarity
bogdanm	0:9b334a45a8ff	167	This parameter can be any value of @ref HRTIM_Output_Polarity */
bogdanm	0:9b334a45a8ff	168	uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
bogdanm	0:9b334a45a8ff	169	This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
bogdanm	0:9b334a45a8ff	170	} HRTIM_SimpleOCChannelCfgTypeDef;
bogdanm	0:9b334a45a8ff	171
bogdanm	0:9b334a45a8ff	172	/**
bogdanm	0:9b334a45a8ff	173	* @brief Simple PWM output mode configuration definition
bogdanm	0:9b334a45a8ff	174	*/
bogdanm	0:9b334a45a8ff	175	typedef struct {
bogdanm	0:9b334a45a8ff	176	uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
bogdanm	0:9b334a45a8ff	177	The compare value must be above or equal to 3 periods of the fHRTIM clock */
bogdanm	0:9b334a45a8ff	178	uint32_t Polarity; /*!< Specifies the output polarity
bogdanm	0:9b334a45a8ff	179	This parameter can be any value of @ref HRTIM_Output_Polarity */
bogdanm	0:9b334a45a8ff	180	uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
bogdanm	0:9b334a45a8ff	181	This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
bogdanm	0:9b334a45a8ff	182	} HRTIM_SimplePWMChannelCfgTypeDef;
bogdanm	0:9b334a45a8ff	183
bogdanm	0:9b334a45a8ff	184	/**
bogdanm	0:9b334a45a8ff	185	* @brief Simple capture mode configuration definition
bogdanm	0:9b334a45a8ff	186	*/
bogdanm	0:9b334a45a8ff	187	typedef struct {
bogdanm	0:9b334a45a8ff	188	uint32_t Event; /*!< Specifies the external event triggering the capture
bogdanm	0:9b334a45a8ff	189	This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
bogdanm	0:9b334a45a8ff	190	uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
bogdanm	0:9b334a45a8ff	191	This parameter can be a value of @ref HRTIM_External_Event_Polarity */
bogdanm	0:9b334a45a8ff	192	uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
bogdanm	0:9b334a45a8ff	193	This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
bogdanm	0:9b334a45a8ff	194	uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
bogdanm	0:9b334a45a8ff	195	This parameter can be a value of @ref HRTIM_External_Event_Filter */
bogdanm	0:9b334a45a8ff	196	} HRTIM_SimpleCaptureChannelCfgTypeDef;
bogdanm	0:9b334a45a8ff	197
bogdanm	0:9b334a45a8ff	198	/**
bogdanm	0:9b334a45a8ff	199	* @brief Simple One Pulse mode configuration definition
bogdanm	0:9b334a45a8ff	200	*/
bogdanm	0:9b334a45a8ff	201	typedef struct {
bogdanm	0:9b334a45a8ff	202	uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
bogdanm	0:9b334a45a8ff	203	The compare value must be above or equal to 3 periods of the fHRTIM clock */
bogdanm	0:9b334a45a8ff	204	uint32_t OutputPolarity; /*!< Specifies the output polarity
bogdanm	0:9b334a45a8ff	205	This parameter can be any value of @ref HRTIM_Output_Polarity */
bogdanm	0:9b334a45a8ff	206	uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
bogdanm	0:9b334a45a8ff	207	This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
bogdanm	0:9b334a45a8ff	208	uint32_t Event; /*!< Specifies the external event triggering the pulse generation
bogdanm	0:9b334a45a8ff	209	This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
bogdanm	0:9b334a45a8ff	210	uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
bogdanm	0:9b334a45a8ff	211	This parameter can be a value of @ref HRTIM_External_Event_Polarity */
bogdanm	0:9b334a45a8ff	212	uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
bogdanm	0:9b334a45a8ff	213	This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
bogdanm	0:9b334a45a8ff	214	uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
bogdanm	0:9b334a45a8ff	215	This parameter can be a value of @ref HRTIM_External_Event_Filter */
bogdanm	0:9b334a45a8ff	216	} HRTIM_SimpleOnePulseChannelCfgTypeDef;
bogdanm	0:9b334a45a8ff	217
bogdanm	0:9b334a45a8ff	218	/**
bogdanm	0:9b334a45a8ff	219	* @brief Timer configuration definition
bogdanm	0:9b334a45a8ff	220	*/
bogdanm	0:9b334a45a8ff	221	typedef struct {
bogdanm	0:9b334a45a8ff	222	uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	223	Specifies which interrupts requests must enabled for the timer
bogdanm	0:9b334a45a8ff	224	This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
bogdanm	0:9b334a45a8ff	225	or HRTIM_Timing_Unit_Interrupt_Enable */
bogdanm	0:9b334a45a8ff	226	uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	227	Specifies which DMA requests must be enabled for the timer
bogdanm	0:9b334a45a8ff	228	This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable
bogdanm	0:9b334a45a8ff	229	or HRTIM_Timing_Unit_DMA_Request_Enable */
bogdanm	0:9b334a45a8ff	230	uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	231	Specifies the address of the source address of the DMA transfer */
bogdanm	0:9b334a45a8ff	232	uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	233	Specifies the address of the destination address of the DMA transfer */
bogdanm	0:9b334a45a8ff	234	uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	235	Specifies the size of the DMA transfer */
bogdanm	0:9b334a45a8ff	236	uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	237	Specifies whether or not hald mode is enabled
bogdanm	0:9b334a45a8ff	238	This parameter can be any value of @ref HRTIM_Half_Mode_Enable */
bogdanm	0:9b334a45a8ff	239	uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	240	Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
bogdanm	0:9b334a45a8ff	241	This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */
bogdanm	0:9b334a45a8ff	242	uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	243	Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
bogdanm	0:9b334a45a8ff	244	This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */
bogdanm	0:9b334a45a8ff	245	uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	246	Indicates whether or not the a DAC synchronization event is generated
bogdanm	0:9b334a45a8ff	247	This parameter can be any value of @ref HRTIM_DAC_Synchronization */
bogdanm	0:9b334a45a8ff	248	uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	249	Specifies whether or not register preload is enabled
bogdanm	0:9b334a45a8ff	250	This parameter can be any value of @ref HRTIM_Register_Preload_Enable */
bogdanm	0:9b334a45a8ff	251	uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	252	Specifies how the update occurs with respect to a burst DMA transaction or
bogdanm	0:9b334a45a8ff	253	update enable inputs (Slave timers only)
bogdanm	0:9b334a45a8ff	254	This parameter can be any value of @ref HRTIM_Update_Gating */
bogdanm	0:9b334a45a8ff	255	uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	256	Specifies how the timer behaves during a burst mode operation
bogdanm	0:9b334a45a8ff	257	This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */
bogdanm	0:9b334a45a8ff	258	uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master
bogdanm	0:9b334a45a8ff	259	Specifies whether or not registers update is triggered by the repetition event
bogdanm	0:9b334a45a8ff	260	This parameter can be any valuen of @ref HRTIM_Timer_Repetition_Update */
bogdanm	0:9b334a45a8ff	261	uint32_t PushPull; /*!< Relevant for Timer A to Timer E
bogdanm	0:9b334a45a8ff	262	Specifies whether or not the push-pull mode is enabled
bogdanm	0:9b334a45a8ff	263	This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
bogdanm	0:9b334a45a8ff	264	uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E
bogdanm	0:9b334a45a8ff	265	Specifies which fault channels are enabled for the timer
bogdanm	0:9b334a45a8ff	266	This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */
bogdanm	0:9b334a45a8ff	267	uint32_t FaultLock; /*!< Relevant for Timer A to Timer E
bogdanm	0:9b334a45a8ff	268	Specifies whether or not fault enabling status is write protected
bogdanm	0:9b334a45a8ff	269	This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
bogdanm	0:9b334a45a8ff	270	uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E
bogdanm	0:9b334a45a8ff	271	Specifies whether or not deadtime insertion is enabled for the timer
bogdanm	0:9b334a45a8ff	272	This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
bogdanm	0:9b334a45a8ff	273	uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E
bogdanm	0:9b334a45a8ff	274	Specifies the delayed protection mode
bogdanm	0:9b334a45a8ff	275	This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
bogdanm	0:9b334a45a8ff	276	uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E
bogdanm	0:9b334a45a8ff	277	Specifies source(s) triggering the timer registers update
bogdanm	0:9b334a45a8ff	278	This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
bogdanm	0:9b334a45a8ff	279	uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E
bogdanm	0:9b334a45a8ff	280	Specifies source(s) triggering the timer counter reset
bogdanm	0:9b334a45a8ff	281	This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
bogdanm	0:9b334a45a8ff	282	uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E
bogdanm	0:9b334a45a8ff	283	Specifies whether or not registers update is triggered when the timer counter is reset
bogdanm	0:9b334a45a8ff	284	This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
bogdanm	0:9b334a45a8ff	285	} HRTIM_TimerCfgTypeDef;
bogdanm	0:9b334a45a8ff	286
bogdanm	0:9b334a45a8ff	287	/**
bogdanm	0:9b334a45a8ff	288	* @brief Compare unit configuration definition
bogdanm	0:9b334a45a8ff	289	*/
bogdanm	0:9b334a45a8ff	290	typedef struct {
bogdanm	0:9b334a45a8ff	291	uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit
bogdanm	0:9b334a45a8ff	292	the minimum value must be greater than or equal to 3 periods of the fHRTIM clock
bogdanm	0:9b334a45a8ff	293	the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
bogdanm	0:9b334a45a8ff	294	uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4
bogdanm	0:9b334a45a8ff	295	This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
bogdanm	0:9b334a45a8ff	296	uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected
bogdanm	0:9b334a45a8ff	297	CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
bogdanm	0:9b334a45a8ff	298	} HRTIM_CompareCfgTypeDef;
bogdanm	0:9b334a45a8ff	299
bogdanm	0:9b334a45a8ff	300	/**
bogdanm	0:9b334a45a8ff	301	* @brief Capture unit configuration definition
bogdanm	0:9b334a45a8ff	302	*/
bogdanm	0:9b334a45a8ff	303	typedef struct {
bogdanm	0:9b334a45a8ff	304	uint32_t Trigger; /*!< Specifies source(s) triggering the capture
bogdanm	0:9b334a45a8ff	305	This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
bogdanm	0:9b334a45a8ff	306	} HRTIM_CaptureCfgTypeDef;
bogdanm	0:9b334a45a8ff	307
bogdanm	0:9b334a45a8ff	308	/**
bogdanm	0:9b334a45a8ff	309	* @brief Output configuration definition
bogdanm	0:9b334a45a8ff	310	*/
bogdanm	0:9b334a45a8ff	311	typedef struct {
bogdanm	0:9b334a45a8ff	312	uint32_t Polarity; /*!< Specifies the output polarity
bogdanm	0:9b334a45a8ff	313	This parameter can be any value of @ref HRTIM_Output_Polarity */
bogdanm	0:9b334a45a8ff	314	uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level
bogdanm	0:9b334a45a8ff	315	This parameter can be a combination of @ref HRTIM_Output_Set_Source */
bogdanm	0:9b334a45a8ff	316	uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level
bogdanm	0:9b334a45a8ff	317	This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
bogdanm	0:9b334a45a8ff	318	uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation
bogdanm	0:9b334a45a8ff	319	This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
bogdanm	0:9b334a45a8ff	320	uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
bogdanm	0:9b334a45a8ff	321	This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
bogdanm	0:9b334a45a8ff	322	uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state
bogdanm	0:9b334a45a8ff	323	This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
bogdanm	0:9b334a45a8ff	324	uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
bogdanm	0:9b334a45a8ff	325	This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
bogdanm	0:9b334a45a8ff	326	uint32_t BurstModeEntryDelayed; /* !<Indicates whether or not deadtime is inserted when entering the IDLE state
bogdanm	0:9b334a45a8ff	327	during a burst mode operation
bogdanm	0:9b334a45a8ff	328	This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
bogdanm	0:9b334a45a8ff	329	} HRTIM_OutputCfgTypeDef;
bogdanm	0:9b334a45a8ff	330
bogdanm	0:9b334a45a8ff	331	/**
bogdanm	0:9b334a45a8ff	332	* @brief External event filtering in timing units configuration definition
bogdanm	0:9b334a45a8ff	333	*/
bogdanm	0:9b334a45a8ff	334	typedef struct {
bogdanm	0:9b334a45a8ff	335	uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit
bogdanm	0:9b334a45a8ff	336	This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
bogdanm	0:9b334a45a8ff	337	uint32_t Latch; /*!< Specifies whether or not the signal is latched
bogdanm	0:9b334a45a8ff	338	This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
bogdanm	0:9b334a45a8ff	339	} HRTIM_TimerEventFilteringCfgTypeDef;
bogdanm	0:9b334a45a8ff	340
bogdanm	0:9b334a45a8ff	341	/**
bogdanm	0:9b334a45a8ff	342	* @brief Dead time feature configuration definition
bogdanm	0:9b334a45a8ff	343	*/
bogdanm	0:9b334a45a8ff	344	typedef struct {
bogdanm	0:9b334a45a8ff	345	uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler
bogdanm	0:9b334a45a8ff	346	This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
bogdanm	0:9b334a45a8ff	347	uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge
bogdanm	0:9b334a45a8ff	348	This parameter can be a number between 0x0 and 0x1FF */
bogdanm	0:9b334a45a8ff	349	uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge
bogdanm	0:9b334a45a8ff	350	This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
bogdanm	0:9b334a45a8ff	351	uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected
bogdanm	0:9b334a45a8ff	352	This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
bogdanm	0:9b334a45a8ff	353	uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected
bogdanm	0:9b334a45a8ff	354	This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
bogdanm	0:9b334a45a8ff	355	uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge
bogdanm	0:9b334a45a8ff	356	This parameter can be a number between 0x0 and 0x1FF */
bogdanm	0:9b334a45a8ff	357	uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge
bogdanm	0:9b334a45a8ff	358	This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
bogdanm	0:9b334a45a8ff	359	uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected
bogdanm	0:9b334a45a8ff	360	This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
bogdanm	0:9b334a45a8ff	361	uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected
bogdanm	0:9b334a45a8ff	362	This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
bogdanm	0:9b334a45a8ff	363	} HRTIM_DeadTimeCfgTypeDef ;
bogdanm	0:9b334a45a8ff	364
bogdanm	0:9b334a45a8ff	365	/**
bogdanm	0:9b334a45a8ff	366	* @brief Chopper mode configuration definition
bogdanm	0:9b334a45a8ff	367	*/
bogdanm	0:9b334a45a8ff	368	typedef struct {
bogdanm	0:9b334a45a8ff	369	uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
bogdanm	0:9b334a45a8ff	370	This parameter can be a value of @ref HRTIM_Chopper_Frequency */
bogdanm	0:9b334a45a8ff	371	uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
bogdanm	0:9b334a45a8ff	372	This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
bogdanm	0:9b334a45a8ff	373	uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
bogdanm	0:9b334a45a8ff	374	This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
bogdanm	0:9b334a45a8ff	375	} HRTIM_ChopperModeCfgTypeDef;
bogdanm	0:9b334a45a8ff	376
bogdanm	0:9b334a45a8ff	377	/**
bogdanm	0:9b334a45a8ff	378	* @brief External event channel configuration definition
bogdanm	0:9b334a45a8ff	379	*/
bogdanm	0:9b334a45a8ff	380	typedef struct {
bogdanm	0:9b334a45a8ff	381	uint32_t Source; /*!< Identifies the source of the external event
bogdanm	0:9b334a45a8ff	382	This parameter can be a value of @ref HRTIM_External_Event_Sources */
bogdanm	0:9b334a45a8ff	383	uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
bogdanm	0:9b334a45a8ff	384	This parameter can be a value of @ref HRTIM_External_Event_Polarity */
bogdanm	0:9b334a45a8ff	385	uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event
bogdanm	0:9b334a45a8ff	386	This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
bogdanm	0:9b334a45a8ff	387	uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
bogdanm	0:9b334a45a8ff	388	This parameter can be a value of @ref HRTIM_External_Event_Filter */
bogdanm	0:9b334a45a8ff	389	uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event
bogdanm	0:9b334a45a8ff	390	This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
bogdanm	0:9b334a45a8ff	391	} HRTIM_EventCfgTypeDef;
bogdanm	0:9b334a45a8ff	392
bogdanm	0:9b334a45a8ff	393	/**
bogdanm	0:9b334a45a8ff	394	* @brief Fault channel configuration definition
bogdanm	0:9b334a45a8ff	395	*/
bogdanm	0:9b334a45a8ff	396	typedef struct {
bogdanm	0:9b334a45a8ff	397	uint32_t Source; /*!< Identifies the source of the fault
bogdanm	0:9b334a45a8ff	398	This parameter can be a value of @ref HRTIM_Fault_Sources */
bogdanm	0:9b334a45a8ff	399	uint32_t Polarity; /*!< Specifies the polarity of the fault event
bogdanm	0:9b334a45a8ff	400	This parameter can be a value of @ref HRTIM_Fault_Polarity */
bogdanm	0:9b334a45a8ff	401	uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter
bogdanm	0:9b334a45a8ff	402	This parameter can be a value of @ref HRTIM_Fault_Filter */
bogdanm	0:9b334a45a8ff	403	uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected
bogdanm	0:9b334a45a8ff	404	This parameter can be a value of @ref HRTIM_Fault_Lock */
bogdanm	0:9b334a45a8ff	405	} HRTIM_FaultCfgTypeDef;
bogdanm	0:9b334a45a8ff	406
bogdanm	0:9b334a45a8ff	407	/**
bogdanm	0:9b334a45a8ff	408	* @brief Burst mode configuration definition
bogdanm	0:9b334a45a8ff	409	*/
bogdanm	0:9b334a45a8ff	410	typedef struct {
bogdanm	0:9b334a45a8ff	411	uint32_t Mode; /*!< Specifies the burst mode operating mode
bogdanm	0:9b334a45a8ff	412	This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
bogdanm	0:9b334a45a8ff	413	uint32_t ClockSource; /*!< Specifies the burst mode clock source
bogdanm	0:9b334a45a8ff	414	This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
bogdanm	0:9b334a45a8ff	415	uint32_t Prescaler; /*!< Specifies the burst mode prescaler
bogdanm	0:9b334a45a8ff	416	This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
bogdanm	0:9b334a45a8ff	417	uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER)
bogdanm	0:9b334a45a8ff	418	This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */
bogdanm	0:9b334a45a8ff	419	uint32_t Trigger; /*!< Specifies the event(s) trigering the burst operation
bogdanm	0:9b334a45a8ff	420	This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */
bogdanm	0:9b334a45a8ff	421	uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state
bogdanm	0:9b334a45a8ff	422	This parameter can be a number between 0x0 and 0xFFFF */
bogdanm	0:9b334a45a8ff	423	uint32_t Period; /*!< Specifies burst mode repetition period
bogdanm	0:9b334a45a8ff	424	This parameter can be a number between 0x1 and 0xFFFF */
bogdanm	0:9b334a45a8ff	425	} HRTIM_BurstModeCfgTypeDef;
bogdanm	0:9b334a45a8ff	426
bogdanm	0:9b334a45a8ff	427	/**
bogdanm	0:9b334a45a8ff	428	* @brief ADC trigger configuration definition
bogdanm	0:9b334a45a8ff	429	*/
bogdanm	0:9b334a45a8ff	430	typedef struct {
bogdanm	0:9b334a45a8ff	431	uint32_t UpdateSource; /*!< Specifies the ADC trigger update source
bogdanm	0:9b334a45a8ff	432	This parameter can be a combination of @ref HRTIM_ADC_Trigger_Update_Source */
bogdanm	0:9b334a45a8ff	433	uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion
bogdanm	0:9b334a45a8ff	434	This parameter can be a value of @ref HRTIM_ADC_Trigger_Event */
bogdanm	0:9b334a45a8ff	435	} HRTIM_ADCTriggerCfgTypeDef;
bogdanm	0:9b334a45a8ff	436
bogdanm	0:9b334a45a8ff	437	/**
bogdanm	0:9b334a45a8ff	438	* @}
bogdanm	0:9b334a45a8ff	439	*/
bogdanm	0:9b334a45a8ff	440
bogdanm	0:9b334a45a8ff	441	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	442	/** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
bogdanm	0:9b334a45a8ff	443	* @{
bogdanm	0:9b334a45a8ff	444	*/
bogdanm	0:9b334a45a8ff	445
bogdanm	0:9b334a45a8ff	446	/** @defgroup HRTIM_Timer_Index HRTIM Timer Index
bogdanm	0:9b334a45a8ff	447	* @{
bogdanm	0:9b334a45a8ff	448	* @brief Constants defining the timer indexes
bogdanm	0:9b334a45a8ff	449	*/
bogdanm	0:9b334a45a8ff	450	#define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0 /!< Index used to access timer A registers /
bogdanm	0:9b334a45a8ff	451	#define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1 /!< Index used to access timer B registers /
bogdanm	0:9b334a45a8ff	452	#define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2 /!< Index used to access timer C registers /
bogdanm	0:9b334a45a8ff	453	#define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3 /!< Index used to access timer D registers /
bogdanm	0:9b334a45a8ff	454	#define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4 /!< Index used to access timer E registers /
bogdanm	0:9b334a45a8ff	455	#define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5 /!< Index used to access master registers /
bogdanm	0:9b334a45a8ff	456	#define HRTIM_TIMERINDEX_COMMON (uint32_t)0xFF /!< Index used to access HRTIM common registers /
bogdanm	0:9b334a45a8ff	457
bogdanm	0:9b334a45a8ff	458	#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
bogdanm	0:9b334a45a8ff	459	(((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) \|\| \
bogdanm	0:9b334a45a8ff	460	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) \|\| \
bogdanm	0:9b334a45a8ff	461	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) \|\| \
bogdanm	0:9b334a45a8ff	462	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) \|\| \
bogdanm	0:9b334a45a8ff	463	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) \|\| \
bogdanm	0:9b334a45a8ff	464	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
bogdanm	0:9b334a45a8ff	465
bogdanm	0:9b334a45a8ff	466	#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
bogdanm	0:9b334a45a8ff	467	(((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) \|\| \
bogdanm	0:9b334a45a8ff	468	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) \|\| \
bogdanm	0:9b334a45a8ff	469	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) \|\| \
bogdanm	0:9b334a45a8ff	470	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) \|\| \
bogdanm	0:9b334a45a8ff	471	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
bogdanm	0:9b334a45a8ff	472	/**
bogdanm	0:9b334a45a8ff	473	* @}
bogdanm	0:9b334a45a8ff	474	*/
bogdanm	0:9b334a45a8ff	475
bogdanm	0:9b334a45a8ff	476	/** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
bogdanm	0:9b334a45a8ff	477	* @{
bogdanm	0:9b334a45a8ff	478	* @brief Constants defining timer identifiers
bogdanm	0:9b334a45a8ff	479	*/
bogdanm	0:9b334a45a8ff	480	#define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /!< Master identifier/
bogdanm	0:9b334a45a8ff	481	#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /!< Timer A identifier /
bogdanm	0:9b334a45a8ff	482	#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /!< Timer B identifier /
bogdanm	0:9b334a45a8ff	483	#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /!< Timer C identifier /
bogdanm	0:9b334a45a8ff	484	#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /!< Timer D identifier /
bogdanm	0:9b334a45a8ff	485	#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /!< Timer E identifier /
bogdanm	0:9b334a45a8ff	486
bogdanm	0:9b334a45a8ff	487	#define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFF) == 0x00000000)
bogdanm	0:9b334a45a8ff	488
bogdanm	0:9b334a45a8ff	489	/**
bogdanm	0:9b334a45a8ff	490	* @}
bogdanm	0:9b334a45a8ff	491	*/
bogdanm	0:9b334a45a8ff	492
bogdanm	0:9b334a45a8ff	493	/** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
bogdanm	0:9b334a45a8ff	494	* @{
bogdanm	0:9b334a45a8ff	495	* @brief Constants defining compare unit identifiers
bogdanm	0:9b334a45a8ff	496	*/
bogdanm	0:9b334a45a8ff	497	#define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001 /!< Compare unit 1 identifier /
bogdanm	0:9b334a45a8ff	498	#define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002 /!< Compare unit 2 identifier /
bogdanm	0:9b334a45a8ff	499	#define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004 /!< Compare unit 3 identifier /
bogdanm	0:9b334a45a8ff	500	#define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008 /!< Compare unit 4 identifier /
bogdanm	0:9b334a45a8ff	501
bogdanm	0:9b334a45a8ff	502	#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
bogdanm	0:9b334a45a8ff	503	(((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) \|\| \
bogdanm	0:9b334a45a8ff	504	((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) \|\| \
bogdanm	0:9b334a45a8ff	505	((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) \|\| \
bogdanm	0:9b334a45a8ff	506	((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
bogdanm	0:9b334a45a8ff	507	/**
bogdanm	0:9b334a45a8ff	508	* @}
bogdanm	0:9b334a45a8ff	509	*/
bogdanm	0:9b334a45a8ff	510
bogdanm	0:9b334a45a8ff	511	/** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
bogdanm	0:9b334a45a8ff	512	* @{
bogdanm	0:9b334a45a8ff	513	* @brief Constants defining capture unit identifiers
bogdanm	0:9b334a45a8ff	514	*/
bogdanm	0:9b334a45a8ff	515	#define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001 /!< Capture unit 1 identifier /
bogdanm	0:9b334a45a8ff	516	#define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002 /!< Capture unit 2 identifier /
bogdanm	0:9b334a45a8ff	517
bogdanm	0:9b334a45a8ff	518	#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
bogdanm	0:9b334a45a8ff	519	(((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) \|\| \
bogdanm	0:9b334a45a8ff	520	((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
bogdanm	0:9b334a45a8ff	521	/**
bogdanm	0:9b334a45a8ff	522	* @}
bogdanm	0:9b334a45a8ff	523	*/
bogdanm	0:9b334a45a8ff	524
bogdanm	0:9b334a45a8ff	525	/** @defgroup HRTIM_Timer_Output HRTIM Timer Output
bogdanm	0:9b334a45a8ff	526	* @{
bogdanm	0:9b334a45a8ff	527	* @brief Constants defining timer output identifiers
bogdanm	0:9b334a45a8ff	528	*/
bogdanm	0:9b334a45a8ff	529	#define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001 /!< Timer A - Ouput 1 identifier /
bogdanm	0:9b334a45a8ff	530	#define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002 /!< Timer A - Ouput 2 identifier /
bogdanm	0:9b334a45a8ff	531	#define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004 /!< Timer B - Ouput 1 identifier /
bogdanm	0:9b334a45a8ff	532	#define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008 /!< Timer B - Ouput 2 identifier /
bogdanm	0:9b334a45a8ff	533	#define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010 /!< Timer C - Ouput 1 identifier /
bogdanm	0:9b334a45a8ff	534	#define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020 /!< Timer C - Ouput 2 identifier /
bogdanm	0:9b334a45a8ff	535	#define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040 /!< Timer D - Ouput 1 identifier /
bogdanm	0:9b334a45a8ff	536	#define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080 /!< Timer D - Ouput 2 identifier /
bogdanm	0:9b334a45a8ff	537	#define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100 /!< Timer E - Ouput 1 identifier /
bogdanm	0:9b334a45a8ff	538	#define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200 /!< Timer E - Ouput 2 identifier /
bogdanm	0:9b334a45a8ff	539
bogdanm	0:9b334a45a8ff	540	#define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00) == 0x00000000)
bogdanm	0:9b334a45a8ff	541
bogdanm	0:9b334a45a8ff	542	#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
bogdanm	0:9b334a45a8ff	543	((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
bogdanm	0:9b334a45a8ff	544	(((OUTPUT) == HRTIM_OUTPUT_TA1) \|\| \
bogdanm	0:9b334a45a8ff	545	((OUTPUT) == HRTIM_OUTPUT_TA2))) \
bogdanm	0:9b334a45a8ff	546	\|\| \
bogdanm	0:9b334a45a8ff	547	(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
bogdanm	0:9b334a45a8ff	548	(((OUTPUT) == HRTIM_OUTPUT_TB1) \|\| \
bogdanm	0:9b334a45a8ff	549	((OUTPUT) == HRTIM_OUTPUT_TB2))) \
bogdanm	0:9b334a45a8ff	550	\|\| \
bogdanm	0:9b334a45a8ff	551	(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
bogdanm	0:9b334a45a8ff	552	(((OUTPUT) == HRTIM_OUTPUT_TC1) \|\| \
bogdanm	0:9b334a45a8ff	553	((OUTPUT) == HRTIM_OUTPUT_TC2))) \
bogdanm	0:9b334a45a8ff	554	\|\| \
bogdanm	0:9b334a45a8ff	555	(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
bogdanm	0:9b334a45a8ff	556	(((OUTPUT) == HRTIM_OUTPUT_TD1) \|\| \
bogdanm	0:9b334a45a8ff	557	((OUTPUT) == HRTIM_OUTPUT_TD2))) \
bogdanm	0:9b334a45a8ff	558	\|\| \
bogdanm	0:9b334a45a8ff	559	(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
bogdanm	0:9b334a45a8ff	560	(((OUTPUT) == HRTIM_OUTPUT_TE1) \|\| \
bogdanm	0:9b334a45a8ff	561	((OUTPUT) == HRTIM_OUTPUT_TE2))))
bogdanm	0:9b334a45a8ff	562	/**
bogdanm	0:9b334a45a8ff	563	* @}
bogdanm	0:9b334a45a8ff	564	*/
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566	/** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
bogdanm	0:9b334a45a8ff	567	* @{
bogdanm	0:9b334a45a8ff	568	* @brief Constants defining ADC triggers identifiers
bogdanm	0:9b334a45a8ff	569	*/
bogdanm	0:9b334a45a8ff	570	#define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001 /!< ADC trigger 1 identifier /
bogdanm	0:9b334a45a8ff	571	#define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002 /!< ADC trigger 2 identifier /
bogdanm	0:9b334a45a8ff	572	#define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004 /!< ADC trigger 3 identifier /
bogdanm	0:9b334a45a8ff	573	#define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008 /!< ADC trigger 4 identifier /
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
bogdanm	0:9b334a45a8ff	576	(((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) \|\| \
bogdanm	0:9b334a45a8ff	577	((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) \|\| \
bogdanm	0:9b334a45a8ff	578	((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) \|\| \
bogdanm	0:9b334a45a8ff	579	((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
bogdanm	0:9b334a45a8ff	580	/**
bogdanm	0:9b334a45a8ff	581	* @}
bogdanm	0:9b334a45a8ff	582	*/
bogdanm	0:9b334a45a8ff	583
bogdanm	0:9b334a45a8ff	584	/** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
bogdanm	0:9b334a45a8ff	585	* @{
bogdanm	0:9b334a45a8ff	586	* @brief Constants defining external event channel identifiers
bogdanm	0:9b334a45a8ff	587	*/
bogdanm	0:9b334a45a8ff	588	#define HRTIM_EVENT_NONE ((uint32_t)0x00000000) /!< Undefined event channel /
bogdanm	0:9b334a45a8ff	589	#define HRTIM_EVENT_1 ((uint32_t)0x00000001) /!< External event channel 1 identifier /
bogdanm	0:9b334a45a8ff	590	#define HRTIM_EVENT_2 ((uint32_t)0x00000002) /!< External event channel 2 identifier /
bogdanm	0:9b334a45a8ff	591	#define HRTIM_EVENT_3 ((uint32_t)0x00000004) /!< External event channel 3 identifier /
bogdanm	0:9b334a45a8ff	592	#define HRTIM_EVENT_4 ((uint32_t)0x00000008) /!< External event channel 4 identifier /
bogdanm	0:9b334a45a8ff	593	#define HRTIM_EVENT_5 ((uint32_t)0x00000010) /!< External event channel 5 identifier /
bogdanm	0:9b334a45a8ff	594	#define HRTIM_EVENT_6 ((uint32_t)0x00000020) /!< External event channel 6 identifier /
bogdanm	0:9b334a45a8ff	595	#define HRTIM_EVENT_7 ((uint32_t)0x00000040) /!< External event channel 7 identifier /
bogdanm	0:9b334a45a8ff	596	#define HRTIM_EVENT_8 ((uint32_t)0x00000080) /!< External event channel 8 identifier /
bogdanm	0:9b334a45a8ff	597	#define HRTIM_EVENT_9 ((uint32_t)0x00000100) /!< External event channel 9 identifier /
bogdanm	0:9b334a45a8ff	598	#define HRTIM_EVENT_10 ((uint32_t)0x00000200) /!< External event channel 10 identifier /
bogdanm	0:9b334a45a8ff	599
bogdanm	0:9b334a45a8ff	600	#define IS_HRTIM_EVENT(EVENT)\
bogdanm	0:9b334a45a8ff	601	(((EVENT) == HRTIM_EVENT_1) \|\| \
bogdanm	0:9b334a45a8ff	602	((EVENT) == HRTIM_EVENT_2) \|\| \
bogdanm	0:9b334a45a8ff	603	((EVENT) == HRTIM_EVENT_3) \|\| \
bogdanm	0:9b334a45a8ff	604	((EVENT) == HRTIM_EVENT_4) \|\| \
bogdanm	0:9b334a45a8ff	605	((EVENT) == HRTIM_EVENT_5) \|\| \
bogdanm	0:9b334a45a8ff	606	((EVENT) == HRTIM_EVENT_6) \|\| \
bogdanm	0:9b334a45a8ff	607	((EVENT) == HRTIM_EVENT_7) \|\| \
bogdanm	0:9b334a45a8ff	608	((EVENT) == HRTIM_EVENT_8) \|\| \
bogdanm	0:9b334a45a8ff	609	((EVENT) == HRTIM_EVENT_9) \|\| \
bogdanm	0:9b334a45a8ff	610	((EVENT) == HRTIM_EVENT_10))
bogdanm	0:9b334a45a8ff	611	/**
bogdanm	0:9b334a45a8ff	612	* @}
bogdanm	0:9b334a45a8ff	613	*/
bogdanm	0:9b334a45a8ff	614
bogdanm	0:9b334a45a8ff	615	/** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
bogdanm	0:9b334a45a8ff	616	* @{
bogdanm	0:9b334a45a8ff	617	* @brief Constants defining fault channel identifiers
bogdanm	0:9b334a45a8ff	618	*/
bogdanm	0:9b334a45a8ff	619	#define HRTIM_FAULT_1 ((uint32_t)0x01) /!< Fault channel 1 identifier /
bogdanm	0:9b334a45a8ff	620	#define HRTIM_FAULT_2 ((uint32_t)0x02) /!< Fault channel 2 identifier /
bogdanm	0:9b334a45a8ff	621	#define HRTIM_FAULT_3 ((uint32_t)0x04) /!< Fault channel 3 identifier /
bogdanm	0:9b334a45a8ff	622	#define HRTIM_FAULT_4 ((uint32_t)0x08) /!< Fault channel 4 identifier /
bogdanm	0:9b334a45a8ff	623	#define HRTIM_FAULT_5 ((uint32_t)0x10) /!< Fault channel 5 identifier /
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625	#define IS_HRTIM_FAULT(FAULT)\
bogdanm	0:9b334a45a8ff	626	(((FAULT) == HRTIM_FAULT_1) \|\| \
bogdanm	0:9b334a45a8ff	627	((FAULT) == HRTIM_FAULT_2) \|\| \
bogdanm	0:9b334a45a8ff	628	((FAULT) == HRTIM_FAULT_3) \|\| \
bogdanm	0:9b334a45a8ff	629	((FAULT) == HRTIM_FAULT_4) \|\| \
bogdanm	0:9b334a45a8ff	630	((FAULT) == HRTIM_FAULT_5))
bogdanm	0:9b334a45a8ff	631	/**
bogdanm	0:9b334a45a8ff	632	* @}
bogdanm	0:9b334a45a8ff	633	*/
bogdanm	0:9b334a45a8ff	634
bogdanm	0:9b334a45a8ff	635
bogdanm	0:9b334a45a8ff	636	/** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
bogdanm	0:9b334a45a8ff	637	* @{
bogdanm	0:9b334a45a8ff	638	* @brief Constants defining timer high-resolution clock prescaler ratio.
bogdanm	0:9b334a45a8ff	639	*/
bogdanm	0:9b334a45a8ff	640	#define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000) /!< fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) /
bogdanm	0:9b334a45a8ff	641	#define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001) /!< fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) /
bogdanm	0:9b334a45a8ff	642	#define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002) /!< fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) /
bogdanm	0:9b334a45a8ff	643	#define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003) /!< fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) /
bogdanm	0:9b334a45a8ff	644	#define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004) /!< fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) /
bogdanm	0:9b334a45a8ff	645	#define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005) /!< fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) /
bogdanm	0:9b334a45a8ff	646	#define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006) /!< fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) /
bogdanm	0:9b334a45a8ff	647	#define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007) /!< fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) /
bogdanm	0:9b334a45a8ff	648
bogdanm	0:9b334a45a8ff	649	#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
bogdanm	0:9b334a45a8ff	650	(((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) \|\| \
bogdanm	0:9b334a45a8ff	651	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) \|\| \
bogdanm	0:9b334a45a8ff	652	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) \|\| \
bogdanm	0:9b334a45a8ff	653	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) \|\| \
bogdanm	0:9b334a45a8ff	654	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) \|\| \
bogdanm	0:9b334a45a8ff	655	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	656	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	657	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
bogdanm	0:9b334a45a8ff	658	/**
bogdanm	0:9b334a45a8ff	659	* @}
bogdanm	0:9b334a45a8ff	660	*/
bogdanm	0:9b334a45a8ff	661
bogdanm	0:9b334a45a8ff	662	/** @defgroup HRTIM_Mode HRTIM Mode
bogdanm	0:9b334a45a8ff	663	* @{
bogdanm	0:9b334a45a8ff	664	* @brief Constants defining timer counter operating mode.
bogdanm	0:9b334a45a8ff	665	*/
bogdanm	0:9b334a45a8ff	666	#define HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008) /!< The timer operates in continuous (free-running) mode /
bogdanm	0:9b334a45a8ff	667	#define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000) /!< The timer operates in non retriggerable single-shot mode /
bogdanm	0:9b334a45a8ff	668	#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010) /!< The timer operates in retriggerable single-shot mode /
bogdanm	0:9b334a45a8ff	669
bogdanm	0:9b334a45a8ff	670	#define IS_HRTIM_MODE(MODE)\
bogdanm	0:9b334a45a8ff	671	(((MODE) == HRTIM_MODE_CONTINUOUS) \|\| \
bogdanm	0:9b334a45a8ff	672	((MODE) == HRTIM_MODE_SINGLESHOT) \|\| \
bogdanm	0:9b334a45a8ff	673	((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
bogdanm	0:9b334a45a8ff	674
bogdanm	0:9b334a45a8ff	675	#define IS_HRTIM_MODE_ONEPULSE(MODE)\
bogdanm	0:9b334a45a8ff	676	(((MODE) == HRTIM_MODE_SINGLESHOT) \|\| \
bogdanm	0:9b334a45a8ff	677	((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
bogdanm	0:9b334a45a8ff	678
bogdanm	0:9b334a45a8ff	679	/**
bogdanm	0:9b334a45a8ff	680	* @}
bogdanm	0:9b334a45a8ff	681	*/
bogdanm	0:9b334a45a8ff	682
bogdanm	0:9b334a45a8ff	683	/** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
bogdanm	0:9b334a45a8ff	684	* @{
bogdanm	0:9b334a45a8ff	685	* @brief Constants defining half mode enabling status.
bogdanm	0:9b334a45a8ff	686	*/
bogdanm	0:9b334a45a8ff	687	#define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000) /!< Half mode is disabled /
bogdanm	0:9b334a45a8ff	688	#define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020) /!< Half mode is enabled /
bogdanm	0:9b334a45a8ff	689
bogdanm	0:9b334a45a8ff	690	#define IS_HRTIM_HALFMODE(HALFMODE)\
bogdanm	0:9b334a45a8ff	691	(((HALFMODE) == HRTIM_HALFMODE_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	692	((HALFMODE) == HRTIM_HALFMODE_ENABLED))
bogdanm	0:9b334a45a8ff	693	/**
bogdanm	0:9b334a45a8ff	694	* @}
bogdanm	0:9b334a45a8ff	695	*/
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697	/** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
bogdanm	0:9b334a45a8ff	698	* @{
bogdanm	0:9b334a45a8ff	699	* @brief Constants defining the timer behavior following the synchronization event
bogdanm	0:9b334a45a8ff	700	*/
bogdanm	0:9b334a45a8ff	701	#define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000) /!< Synchronization input event has effect on the timer /
bogdanm	0:9b334a45a8ff	702	#define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /!< Synchronization input event starts the timer /
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	#define IS_HRTIM_SYNCSTART(SYNCSTART)\
bogdanm	0:9b334a45a8ff	705	(((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	706	((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
bogdanm	0:9b334a45a8ff	707	/**
bogdanm	0:9b334a45a8ff	708	* @}
bogdanm	0:9b334a45a8ff	709	*/
bogdanm	0:9b334a45a8ff	710
bogdanm	0:9b334a45a8ff	711	/** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
bogdanm	0:9b334a45a8ff	712	* @{
bogdanm	0:9b334a45a8ff	713	* @brief Constants defining the timer behavior following the synchronization event
bogdanm	0:9b334a45a8ff	714	*/
bogdanm	0:9b334a45a8ff	715	#define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000) /!< Synchronization input event has effect on the timer /
bogdanm	0:9b334a45a8ff	716	#define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /!< Synchronization input event resets the timer /
bogdanm	0:9b334a45a8ff	717
bogdanm	0:9b334a45a8ff	718	#define IS_HRTIM_SYNCRESET(SYNCRESET)\
bogdanm	0:9b334a45a8ff	719	(((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	720	((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
bogdanm	0:9b334a45a8ff	721	/**
bogdanm	0:9b334a45a8ff	722	* @}
bogdanm	0:9b334a45a8ff	723	*/
bogdanm	0:9b334a45a8ff	724
bogdanm	0:9b334a45a8ff	725	/** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
bogdanm	0:9b334a45a8ff	726	* @{
bogdanm	0:9b334a45a8ff	727	* @brief Constants defining on which output the DAC synchronization event is sent
bogdanm	0:9b334a45a8ff	728	*/
bogdanm	0:9b334a45a8ff	729	#define HRTIM_DACSYNC_NONE (uint32_t)0x00000000 /!< No DAC synchronization event generated /
bogdanm	0:9b334a45a8ff	730	#define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /!< DAC synchronization event generated on DACTrigOut1 output upon timer update /
bogdanm	0:9b334a45a8ff	731	#define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /!< DAC synchronization event generated on DACTrigOut2 output upon timer update /
bogdanm	0:9b334a45a8ff	732	#define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 \| HRTIM_MCR_DACSYNC_0) /!< DAC update generated on DACTrigOut3 output upon timer update /
bogdanm	0:9b334a45a8ff	733
bogdanm	0:9b334a45a8ff	734	#define IS_HHRTIM_DACSYNC(DACSYNC)\
bogdanm	0:9b334a45a8ff	735	(((DACSYNC) == HRTIM_DACSYNC_NONE) \|\| \
bogdanm	0:9b334a45a8ff	736	((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) \|\| \
bogdanm	0:9b334a45a8ff	737	((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) \|\| \
bogdanm	0:9b334a45a8ff	738	((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
bogdanm	0:9b334a45a8ff	739	/**
bogdanm	0:9b334a45a8ff	740	* @}
bogdanm	0:9b334a45a8ff	741	*/
bogdanm	0:9b334a45a8ff	742
bogdanm	0:9b334a45a8ff	743	/** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
bogdanm	0:9b334a45a8ff	744	* @{
bogdanm	0:9b334a45a8ff	745	* @brief Constants defining whether a write access into a preloadable
bogdanm	0:9b334a45a8ff	746	* register is done into the active or the preload register.
bogdanm	0:9b334a45a8ff	747	*/
bogdanm	0:9b334a45a8ff	748	#define HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000) /!< Preload disabled: the write access is directly done into the active register /
bogdanm	0:9b334a45a8ff	749	#define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /!< Preload enabled: the write access is done into the preload register /
bogdanm	0:9b334a45a8ff	750
bogdanm	0:9b334a45a8ff	751	#define IS_HRTIM_PRELOAD(PRELOAD)\
bogdanm	0:9b334a45a8ff	752	(((PRELOAD) == HRTIM_PRELOAD_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	753	((PRELOAD) == HRTIM_PRELOAD_ENABLED))
bogdanm	0:9b334a45a8ff	754	/**
bogdanm	0:9b334a45a8ff	755	* @}
bogdanm	0:9b334a45a8ff	756	*/
bogdanm	0:9b334a45a8ff	757
bogdanm	0:9b334a45a8ff	758	/** @defgroup HRTIM_Update_Gating HRTIM Update Gating
bogdanm	0:9b334a45a8ff	759	* @{
bogdanm	0:9b334a45a8ff	760	* @brief Constants defining how the update occurs relatively to the burst DMA
bogdanm	0:9b334a45a8ff	761	* transaction and the external update request on update enable inputs 1 to 3.
bogdanm	0:9b334a45a8ff	762	*/
bogdanm	0:9b334a45a8ff	763	#define HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000 /!< Update done independently from the DMA burst transfer completion /
bogdanm	0:9b334a45a8ff	764	#define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /!< Update done when the DMA burst transfer is completed /
bogdanm	0:9b334a45a8ff	765	#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /!< Update done on timer roll-over following a DMA burst transfer completion/
bogdanm	0:9b334a45a8ff	766	#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 /
bogdanm	0:9b334a45a8ff	767	#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 /
bogdanm	0:9b334a45a8ff	768	#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 /
bogdanm	0:9b334a45a8ff	769	#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_1) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 /
bogdanm	0:9b334a45a8ff	770	#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_1 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 /
bogdanm	0:9b334a45a8ff	771	#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 /
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773	#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
bogdanm	0:9b334a45a8ff	774	(((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) \|\| \
bogdanm	0:9b334a45a8ff	775	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) \|\| \
bogdanm	0:9b334a45a8ff	776	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
bogdanm	0:9b334a45a8ff	777
bogdanm	0:9b334a45a8ff	778	#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
bogdanm	0:9b334a45a8ff	779	(((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) \|\| \
bogdanm	0:9b334a45a8ff	780	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) \|\| \
bogdanm	0:9b334a45a8ff	781	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	782	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) \|\| \
bogdanm	0:9b334a45a8ff	783	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) \|\| \
bogdanm	0:9b334a45a8ff	784	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) \|\| \
bogdanm	0:9b334a45a8ff	785	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	786	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	787	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
bogdanm	0:9b334a45a8ff	788	/**
bogdanm	0:9b334a45a8ff	789	* @}
bogdanm	0:9b334a45a8ff	790	*/
bogdanm	0:9b334a45a8ff	791
bogdanm	0:9b334a45a8ff	792	/** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
bogdanm	0:9b334a45a8ff	793	* @{
bogdanm	0:9b334a45a8ff	794	* @brief Constants defining how the timer behaves during a burst
bogdanm	0:9b334a45a8ff	795	mode operation.
bogdanm	0:9b334a45a8ff	796	*/
bogdanm	0:9b334a45a8ff	797	#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /!< Timer counter clock is maintained and the timer operates normally /
bogdanm	0:9b334a45a8ff	798	#define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /!< Timer counter clock is stopped and the counter is reset /
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	#define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
bogdanm	0:9b334a45a8ff	801	(((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) \|\| \
bogdanm	0:9b334a45a8ff	802	((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
bogdanm	0:9b334a45a8ff	803	/**
bogdanm	0:9b334a45a8ff	804	* @}
bogdanm	0:9b334a45a8ff	805	*/
bogdanm	0:9b334a45a8ff	806
bogdanm	0:9b334a45a8ff	807	/** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
bogdanm	0:9b334a45a8ff	808	* @{
bogdanm	0:9b334a45a8ff	809	* @brief Constants defining whether registers are updated when the timer
bogdanm	0:9b334a45a8ff	810	* repetition period is completed (either due to roll-over or
bogdanm	0:9b334a45a8ff	811	* reset events)
bogdanm	0:9b334a45a8ff	812	*/
bogdanm	0:9b334a45a8ff	813	#define HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000 /!< Update on repetition disabled /
bogdanm	0:9b334a45a8ff	814	#define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /!< Update on repetition enabled /
bogdanm	0:9b334a45a8ff	815
bogdanm	0:9b334a45a8ff	816	#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
bogdanm	0:9b334a45a8ff	817	(((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	818	((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
bogdanm	0:9b334a45a8ff	819	/**
bogdanm	0:9b334a45a8ff	820	* @}
bogdanm	0:9b334a45a8ff	821	*/
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	/** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
bogdanm	0:9b334a45a8ff	825	* @{
bogdanm	0:9b334a45a8ff	826	* @brief Constants defining whether or not the puhs-pull mode is enabled for
bogdanm	0:9b334a45a8ff	827	* a timer.
bogdanm	0:9b334a45a8ff	828	*/
bogdanm	0:9b334a45a8ff	829	#define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000) /!< Push-Pull mode disabled /
bogdanm	0:9b334a45a8ff	830	#define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /!< Push-Pull mode enabled /
bogdanm	0:9b334a45a8ff	831
bogdanm	0:9b334a45a8ff	832	#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
bogdanm	0:9b334a45a8ff	833	(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	834	((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
bogdanm	0:9b334a45a8ff	835	/**
bogdanm	0:9b334a45a8ff	836	* @}
bogdanm	0:9b334a45a8ff	837	*/
bogdanm	0:9b334a45a8ff	838
bogdanm	0:9b334a45a8ff	839	/** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
bogdanm	0:9b334a45a8ff	840	* @{
bogdanm	0:9b334a45a8ff	841	* @brief Constants defining whether a faut channel is enabled for a timer
bogdanm	0:9b334a45a8ff	842	*/
bogdanm	0:9b334a45a8ff	843	#define HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000 /!< No fault enabled /
bogdanm	0:9b334a45a8ff	844	#define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /!< Fault 1 enabled /
bogdanm	0:9b334a45a8ff	845	#define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /!< Fault 2 enabled /
bogdanm	0:9b334a45a8ff	846	#define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /!< Fault 3 enabled /
bogdanm	0:9b334a45a8ff	847	#define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /!< Fault 4 enabled /
bogdanm	0:9b334a45a8ff	848	#define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /!< Fault 5 enabled /
bogdanm	0:9b334a45a8ff	849
bogdanm	0:9b334a45a8ff	850	#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0) == 0x00000000)
bogdanm	0:9b334a45a8ff	851
bogdanm	0:9b334a45a8ff	852	/**
bogdanm	0:9b334a45a8ff	853	* @}
bogdanm	0:9b334a45a8ff	854	*/
bogdanm	0:9b334a45a8ff	855
bogdanm	0:9b334a45a8ff	856	/** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
bogdanm	0:9b334a45a8ff	857	* @{
bogdanm	0:9b334a45a8ff	858	* @brief Constants defining whether or not fault enabling bits are write
bogdanm	0:9b334a45a8ff	859	* protected for a timer
bogdanm	0:9b334a45a8ff	860	*/
bogdanm	0:9b334a45a8ff	861	#define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000) /!< Timer fault enabling bits are read/write /
bogdanm	0:9b334a45a8ff	862	#define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /!< Timer fault enabling bits are read only /
bogdanm	0:9b334a45a8ff	863
bogdanm	0:9b334a45a8ff	864	#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
bogdanm	0:9b334a45a8ff	865	(((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) \|\| \
bogdanm	0:9b334a45a8ff	866	((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
bogdanm	0:9b334a45a8ff	867	/**
bogdanm	0:9b334a45a8ff	868	* @}
bogdanm	0:9b334a45a8ff	869	*/
bogdanm	0:9b334a45a8ff	870
bogdanm	0:9b334a45a8ff	871	/** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Deadtime Insertion
bogdanm	0:9b334a45a8ff	872	* @{
bogdanm	0:9b334a45a8ff	873	* @brief Constants defining whether or not fault the dead time insertion
bogdanm	0:9b334a45a8ff	874	* feature is enabled for a timer
bogdanm	0:9b334a45a8ff	875	*/
bogdanm	0:9b334a45a8ff	876	#define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000) /!< Output 1 and output 2 signals are independent /
bogdanm	0:9b334a45a8ff	877	#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /!< Deadtime is inserted between output 1 and output 2 /
bogdanm	0:9b334a45a8ff	878
bogdanm	0:9b334a45a8ff	879	#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
bogdanm	0:9b334a45a8ff	880	((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \
bogdanm	0:9b334a45a8ff	881	((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	882	((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \
bogdanm	0:9b334a45a8ff	883	\|\| \
bogdanm	0:9b334a45a8ff	884	(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
bogdanm	0:9b334a45a8ff	885	((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
bogdanm	0:9b334a45a8ff	886	/**
bogdanm	0:9b334a45a8ff	887	* @}
bogdanm	0:9b334a45a8ff	888	*/
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
bogdanm	0:9b334a45a8ff	891	* @{
bogdanm	0:9b334a45a8ff	892	* @brief Constants defining all possible delayed protection modes
bogdanm	0:9b334a45a8ff	893	* for a timer. Also definethe source and outputs on which the delayed
bogdanm	0:9b334a45a8ff	894	* protection schemes are applied
bogdanm	0:9b334a45a8ff	895	*/
bogdanm	0:9b334a45a8ff	896	#define HRTIM_TIMDELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /!< No action /
bogdanm	0:9b334a45a8ff	897	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 (HRTIM_OUTR_DLYPRTEN) /!< Output 1 delayed Idle on external Event 6 or 8 /
bogdanm	0:9b334a45a8ff	898	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 (HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Output 2 delayed Idle on external Event 6 or 8 /
bogdanm	0:9b334a45a8ff	899	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRTEN) /!< Output 1 and output 2 delayed Idle on external Event 6 or 8 /
bogdanm	0:9b334a45a8ff	900	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Balanced Idle on external Event 6 or 8 /
bogdanm	0:9b334a45a8ff	901	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRTEN) /!< Output 1 delayed Idle on external Event 7 or 9 /
bogdanm	0:9b334a45a8ff	902	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Output 2 delayed Idle on external Event 7 or 9 /
bogdanm	0:9b334a45a8ff	903	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRTEN) /!< Output 1 and output2 delayed Idle on external Event 7 or 9 /
bogdanm	0:9b334a45a8ff	904	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Balanced Idle on external Event 7 or 9 /
bogdanm	0:9b334a45a8ff	905
bogdanm	0:9b334a45a8ff	906	#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
bogdanm	0:9b334a45a8ff	907	((((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	908	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68) \|\| \
bogdanm	0:9b334a45a8ff	909	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68) \|\| \
bogdanm	0:9b334a45a8ff	910	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68) \|\| \
bogdanm	0:9b334a45a8ff	911	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79) \|\| \
bogdanm	0:9b334a45a8ff	912	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79) \|\| \
bogdanm	0:9b334a45a8ff	913	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79)) \
bogdanm	0:9b334a45a8ff	914	\|\| \
bogdanm	0:9b334a45a8ff	915	(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
bogdanm	0:9b334a45a8ff	916	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68) \|\| \
bogdanm	0:9b334a45a8ff	917	((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79)))
bogdanm	0:9b334a45a8ff	918	/**
bogdanm	0:9b334a45a8ff	919	* @}
bogdanm	0:9b334a45a8ff	920	*/
bogdanm	0:9b334a45a8ff	921
bogdanm	0:9b334a45a8ff	922	/** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
bogdanm	0:9b334a45a8ff	923	* @{
bogdanm	0:9b334a45a8ff	924	* @brief Constants defining whether the registers update is done synchronously
bogdanm	0:9b334a45a8ff	925	* with any other timer or master update
bogdanm	0:9b334a45a8ff	926	*/
bogdanm	0:9b334a45a8ff	927	#define HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000 /!< Register update is disabled /
bogdanm	0:9b334a45a8ff	928	#define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /!< Register update is triggered by the master timer update /
bogdanm	0:9b334a45a8ff	929	#define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /!< Register update is triggered by the timer A update /
bogdanm	0:9b334a45a8ff	930	#define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /!< Register update is triggered by the timer B update /
bogdanm	0:9b334a45a8ff	931	#define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /!< Register update is triggered by the timer C update/
bogdanm	0:9b334a45a8ff	932	#define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /!< Register update is triggered by the timer D update /
bogdanm	0:9b334a45a8ff	933	#define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /!< Register update is triggered by the timer E update /
bogdanm	0:9b334a45a8ff	934
bogdanm	0:9b334a45a8ff	935	#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFF) == 0x00000000)
bogdanm	0:9b334a45a8ff	936	/**
bogdanm	0:9b334a45a8ff	937	* @}
bogdanm	0:9b334a45a8ff	938	*/
bogdanm	0:9b334a45a8ff	939
bogdanm	0:9b334a45a8ff	940	/** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
bogdanm	0:9b334a45a8ff	941	* @{
bogdanm	0:9b334a45a8ff	942	* @brief Constants defining the events that can be selected to trigger the reset
bogdanm	0:9b334a45a8ff	943	* of the timer counter
bogdanm	0:9b334a45a8ff	944	*/
bogdanm	0:9b334a45a8ff	945	#define HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000 /!< No counter reset trigger /
bogdanm	0:9b334a45a8ff	946	#define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /!< The timer counter is reset upon update event /
bogdanm	0:9b334a45a8ff	947	#define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /!< The timer counter is reset upon Timer Compare 2 event /
bogdanm	0:9b334a45a8ff	948	#define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /!< The timer counter is reset upon Timer Compare 4 event /
bogdanm	0:9b334a45a8ff	949	#define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /!< The timercounter is reset upon master timer period event /
bogdanm	0:9b334a45a8ff	950	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /!< The timer counter is reset upon master timer Compare 1 event /
bogdanm	0:9b334a45a8ff	951	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /!< The timer counter is reset upon master timer Compare 2 event /
bogdanm	0:9b334a45a8ff	952	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /!< The timer counter is reset upon master timer Compare 3 event /
bogdanm	0:9b334a45a8ff	953	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /!< The timer counter is reset upon master timer Compare 4 event /
bogdanm	0:9b334a45a8ff	954	#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /!< The timer counter is reset upon external event 1 /
bogdanm	0:9b334a45a8ff	955	#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /!< The timer counter is reset upon external event 2 /
bogdanm	0:9b334a45a8ff	956	#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /!< The timer counter is reset upon external event 3 /
bogdanm	0:9b334a45a8ff	957	#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /!< The timer counter is reset upon external event 4 /
bogdanm	0:9b334a45a8ff	958	#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /!< The timer counter is reset upon external event 5 /
bogdanm	0:9b334a45a8ff	959	#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /!< The timer counter is reset upon external event 6 /
bogdanm	0:9b334a45a8ff	960	#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /!< The timer counter is reset upon external event 7 /
bogdanm	0:9b334a45a8ff	961	#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /!< The timer counter is reset upon external event 8 /
bogdanm	0:9b334a45a8ff	962	#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /!< The timer counter is reset upon external event 9 /
bogdanm	0:9b334a45a8ff	963	#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /!< The timer counter is reset upon external event 10 /
bogdanm	0:9b334a45a8ff	964	#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /!< The timer counter is reset upon other timer Compare 1 event /
bogdanm	0:9b334a45a8ff	965	#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /!< The timer counter is reset upon other timer Compare 2 event /
bogdanm	0:9b334a45a8ff	966	#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /!< The timer counter is reset upon other timer Compare 4 event /
bogdanm	0:9b334a45a8ff	967	#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /!< The timer counter is reset upon other timer Compare 1 event /
bogdanm	0:9b334a45a8ff	968	#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /!< The timer counter is reset upon other timer Compare 2 event /
bogdanm	0:9b334a45a8ff	969	#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /!< The timer counter is reset upon other timer Compare 4 event /
bogdanm	0:9b334a45a8ff	970	#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /!< The timer counter is reset upon other timer Compare 1 event /
bogdanm	0:9b334a45a8ff	971	#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /!< The timer counter is reset upon other timer Compare 2 event /
bogdanm	0:9b334a45a8ff	972	#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /!< The timer counter is reset upon other timer Compare 4 event /
bogdanm	0:9b334a45a8ff	973	#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /!< The timer counter is reset upon other timer Compare 1 event /
bogdanm	0:9b334a45a8ff	974	#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /!< The timer counter is reset upon other timer Compare 2 event /
bogdanm	0:9b334a45a8ff	975	#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /!< The timer counter is reset upon other timer Compare 4 event /
bogdanm	0:9b334a45a8ff	976
bogdanm	0:9b334a45a8ff	977	#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001) == 0x00000000)
bogdanm	0:9b334a45a8ff	978
bogdanm	0:9b334a45a8ff	979	/**
bogdanm	0:9b334a45a8ff	980	* @}
bogdanm	0:9b334a45a8ff	981	*/
bogdanm	0:9b334a45a8ff	982
bogdanm	0:9b334a45a8ff	983	/** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
bogdanm	0:9b334a45a8ff	984	* @{
bogdanm	0:9b334a45a8ff	985	* @brief Constants defining whether the register are updated upon Timerx
bogdanm	0:9b334a45a8ff	986	* counter reset or roll-over to 0 after reaching the period value
bogdanm	0:9b334a45a8ff	987	* in continuous mode
bogdanm	0:9b334a45a8ff	988	*/
bogdanm	0:9b334a45a8ff	989	#define HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000 /!< Update by timer x reset / roll-over disabled /
bogdanm	0:9b334a45a8ff	990	#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /!< Update by timer x reset / roll-over enabled /
bogdanm	0:9b334a45a8ff	991
bogdanm	0:9b334a45a8ff	992	#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
bogdanm	0:9b334a45a8ff	993	(((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	994	((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
bogdanm	0:9b334a45a8ff	995	/**
bogdanm	0:9b334a45a8ff	996	* @}
bogdanm	0:9b334a45a8ff	997	*/
bogdanm	0:9b334a45a8ff	998
bogdanm	0:9b334a45a8ff	999	/** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
bogdanm	0:9b334a45a8ff	1000	* @{
bogdanm	0:9b334a45a8ff	1001	* @brief Constants defining whether the compare register is behaving in
bogdanm	0:9b334a45a8ff	1002	* regular mode (compare match issued as soon as counter equal compare),
bogdanm	0:9b334a45a8ff	1003	* or in auto-delayed mode
bogdanm	0:9b334a45a8ff	1004	*/
bogdanm	0:9b334a45a8ff	1005	#define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000) /!< standard compare mode /
bogdanm	0:9b334a45a8ff	1006	#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /!< Compare event generated only if a capture has occured /
bogdanm	0:9b334a45a8ff	1007	#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /!< Compare event generated if a capture has occured or after a Compare 1 match (timeout if capture event is missing) /
bogdanm	0:9b334a45a8ff	1008	#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 \| HRTIM_TIMCR_DELCMP2_0) /!< Compare event generated if a capture has occured or after a Compare 3 match (timeout if capture event is missing) /
bogdanm	0:9b334a45a8ff	1009
bogdanm	0:9b334a45a8ff	1010	#define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
bogdanm	0:9b334a45a8ff	1011	(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) \|\| \
bogdanm	0:9b334a45a8ff	1012	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) \|\| \
bogdanm	0:9b334a45a8ff	1013	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) \|\| \
bogdanm	0:9b334a45a8ff	1014	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
bogdanm	0:9b334a45a8ff	1015
bogdanm	0:9b334a45a8ff	1016	/* Auto delayed mode is only available for compare units 2 and 4 */
bogdanm	0:9b334a45a8ff	1017	#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
bogdanm	0:9b334a45a8ff	1018	((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
bogdanm	0:9b334a45a8ff	1019	(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) \|\| \
bogdanm	0:9b334a45a8ff	1020	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) \|\| \
bogdanm	0:9b334a45a8ff	1021	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) \|\| \
bogdanm	0:9b334a45a8ff	1022	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
bogdanm	0:9b334a45a8ff	1023	\|\| \
bogdanm	0:9b334a45a8ff	1024	(((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
bogdanm	0:9b334a45a8ff	1025	(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) \|\| \
bogdanm	0:9b334a45a8ff	1026	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) \|\| \
bogdanm	0:9b334a45a8ff	1027	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) \|\| \
bogdanm	0:9b334a45a8ff	1028	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
bogdanm	0:9b334a45a8ff	1029	/**
bogdanm	0:9b334a45a8ff	1030	* @}
bogdanm	0:9b334a45a8ff	1031	*/
bogdanm	0:9b334a45a8ff	1032
bogdanm	0:9b334a45a8ff	1033	/** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
bogdanm	0:9b334a45a8ff	1034	* @{
bogdanm	0:9b334a45a8ff	1035	* @brief Constants defining the behavior of the output signal when the timer
bogdanm	0:9b334a45a8ff	1036	operates in basic output compare mode
bogdanm	0:9b334a45a8ff	1037	*/
bogdanm	0:9b334a45a8ff	1038	#define HRTIM_BASICOCMODE_TOGGLE ((uint32_t)0x00000001) /!< Ouput toggles when the timer counter reaches the compare value /
bogdanm	0:9b334a45a8ff	1039	#define HRTIM_BASICOCMODE_INACTIVE ((uint32_t)0x00000002) /!< Ouput forced to active level when the timer counter reaches the compare value /
bogdanm	0:9b334a45a8ff	1040	#define HRTIM_BASICOCMODE_ACTIVE ((uint32_t)0x00000003) /!< Ouput forced to inactive level when the timer counter reaches the compare value /
bogdanm	0:9b334a45a8ff	1041
bogdanm	0:9b334a45a8ff	1042	#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
bogdanm	0:9b334a45a8ff	1043	(((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) \|\| \
bogdanm	0:9b334a45a8ff	1044	((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	1045	((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
bogdanm	0:9b334a45a8ff	1046	/**
bogdanm	0:9b334a45a8ff	1047	* @}
bogdanm	0:9b334a45a8ff	1048	*/
bogdanm	0:9b334a45a8ff	1049
bogdanm	0:9b334a45a8ff	1050	/** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
bogdanm	0:9b334a45a8ff	1051	* @{
bogdanm	0:9b334a45a8ff	1052	* @brief Constants defining the polarity of a timer output
bogdanm	0:9b334a45a8ff	1053	*/
bogdanm	0:9b334a45a8ff	1054	#define HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) /!< Output is acitve HIGH /
bogdanm	0:9b334a45a8ff	1055	#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /!< Output is active LOW /
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057	#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
bogdanm	0:9b334a45a8ff	1058	(((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	1059	((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
bogdanm	0:9b334a45a8ff	1060	/**
bogdanm	0:9b334a45a8ff	1061	* @}
bogdanm	0:9b334a45a8ff	1062	*/
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	/** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
bogdanm	0:9b334a45a8ff	1065	* @{
bogdanm	0:9b334a45a8ff	1066	* @brief Constants defining the events that can be selected to configure the
bogdanm	0:9b334a45a8ff	1067	* set crossbar of a timer output
bogdanm	0:9b334a45a8ff	1068	*/
bogdanm	0:9b334a45a8ff	1069	#define HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000 /!< Reset the output set crossbar /
bogdanm	0:9b334a45a8ff	1070	#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /!< Timer reset event coming solely from software or SYNC input forces the output to its active state /
bogdanm	0:9b334a45a8ff	1071	#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /!< Timer period event forces the output to its active state /
bogdanm	0:9b334a45a8ff	1072	#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /!< Timer compare 1 event forces the output to its active state /
bogdanm	0:9b334a45a8ff	1073	#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /!< Timer compare 2 event forces the output to its active state /
bogdanm	0:9b334a45a8ff	1074	#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /!< Timer compare 3 event forces the output to its active state /
bogdanm	0:9b334a45a8ff	1075	#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /!< Timer compare 4 event forces the output to its active state /
bogdanm	0:9b334a45a8ff	1076	#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /!< The master timer period event forces the output to its active state /
bogdanm	0:9b334a45a8ff	1077	#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /!< Master Timer compare 1 event forces the output to its active state /
bogdanm	0:9b334a45a8ff	1078	#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /!< Master Timer compare 2 event forces the output to its active state /
bogdanm	0:9b334a45a8ff	1079	#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /!< Master Timer compare 3 event forces the output to its active state /
bogdanm	0:9b334a45a8ff	1080	#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /!< Master Timer compare 4 event forces the output to its active state /
bogdanm	0:9b334a45a8ff	1081	#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /!< Timer event 1 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1082	#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /!< Timer event 2 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1083	#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /!< Timer event 3 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1084	#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /!< Timer event 4 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1085	#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /!< Timer event 5 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1086	#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /!< Timer event 6 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1087	#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /!< Timer event 7 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1088	#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /!< Timer event 8 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1089	#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /!< Timer event 9 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1090	#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /!< External event 1 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1091	#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /!< External event 2 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1092	#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /!< External event 3 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1093	#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /!< External event 4 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1094	#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /!< External event 5 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1095	#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /!< External event 6 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1096	#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /!< External event 7 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1097	#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /!< External event 8 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1098	#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /!< External event 9 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1099	#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /!< External event 10 forces the output to its active state /
bogdanm	0:9b334a45a8ff	1100	#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /!< Timer register update event forces the output to its active state /
bogdanm	0:9b334a45a8ff	1101
bogdanm	0:9b334a45a8ff	1102	#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
bogdanm	0:9b334a45a8ff	1103	(((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1104	((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) \|\| \
bogdanm	0:9b334a45a8ff	1105	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) \|\| \
bogdanm	0:9b334a45a8ff	1106	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) \|\| \
bogdanm	0:9b334a45a8ff	1107	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) \|\| \
bogdanm	0:9b334a45a8ff	1108	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) \|\| \
bogdanm	0:9b334a45a8ff	1109	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) \|\| \
bogdanm	0:9b334a45a8ff	1110	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) \|\| \
bogdanm	0:9b334a45a8ff	1111	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) \|\| \
bogdanm	0:9b334a45a8ff	1112	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) \|\| \
bogdanm	0:9b334a45a8ff	1113	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) \|\| \
bogdanm	0:9b334a45a8ff	1114	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) \|\| \
bogdanm	0:9b334a45a8ff	1115	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) \|\| \
bogdanm	0:9b334a45a8ff	1116	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) \|\| \
bogdanm	0:9b334a45a8ff	1117	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) \|\| \
bogdanm	0:9b334a45a8ff	1118	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) \|\| \
bogdanm	0:9b334a45a8ff	1119	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) \|\| \
bogdanm	0:9b334a45a8ff	1120	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) \|\| \
bogdanm	0:9b334a45a8ff	1121	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) \|\| \
bogdanm	0:9b334a45a8ff	1122	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) \|\| \
bogdanm	0:9b334a45a8ff	1123	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) \|\| \
bogdanm	0:9b334a45a8ff	1124	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) \|\| \
bogdanm	0:9b334a45a8ff	1125	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) \|\| \
bogdanm	0:9b334a45a8ff	1126	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) \|\| \
bogdanm	0:9b334a45a8ff	1127	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) \|\| \
bogdanm	0:9b334a45a8ff	1128	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) \|\| \
bogdanm	0:9b334a45a8ff	1129	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) \|\| \
bogdanm	0:9b334a45a8ff	1130	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) \|\| \
bogdanm	0:9b334a45a8ff	1131	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) \|\| \
bogdanm	0:9b334a45a8ff	1132	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) \|\| \
bogdanm	0:9b334a45a8ff	1133	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) \|\| \
bogdanm	0:9b334a45a8ff	1134	((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
bogdanm	0:9b334a45a8ff	1135	/**
bogdanm	0:9b334a45a8ff	1136	* @}
bogdanm	0:9b334a45a8ff	1137	*/
bogdanm	0:9b334a45a8ff	1138
bogdanm	0:9b334a45a8ff	1139	/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
bogdanm	0:9b334a45a8ff	1140	* @{
bogdanm	0:9b334a45a8ff	1141	* @brief Constants defining the events that can be selected to configure the
bogdanm	0:9b334a45a8ff	1142	* set crossbar of a timer output
bogdanm	0:9b334a45a8ff	1143	*/
bogdanm	0:9b334a45a8ff	1144	#define HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000 /!< Reset the output reset crossbar /
bogdanm	0:9b334a45a8ff	1145	#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1146	#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /!< Timer period event forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1147	#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /!< Timer compare 1 event forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1148	#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /!< Timer compare 2 event forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1149	#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /!< Timer compare 3 event forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1150	#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /!< Timer compare 4 event forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1151	#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /!< The master timer period event forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1152	#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /!< Master Timer compare 1 event forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1153	#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /!< Master Timer compare 2 event forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1154	#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /!< Master Timer compare 3 event forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1155	#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /!< Master Timer compare 4 event forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1156	#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /!< Timer event 1 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1157	#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /!< Timer event 2 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1158	#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /!< Timer event 3 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1159	#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /!< Timer event 4 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1160	#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /!< Timer event 5 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1161	#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /!< Timer event 6 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1162	#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /!< Timer event 7 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1163	#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /!< Timer event 8 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1164	#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /!< Timer event 9 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1165	#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /!< External event 1 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1166	#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /!< External event 2 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1167	#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /!< External event 3 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1168	#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /!< External event 4 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1169	#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /!< External event 5 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1170	#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /!< External event 6 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1171	#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /!< External event 7 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1172	#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /!< External event 8 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1173	#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /!< External event 9 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1174	#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /!< External event 10 forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1175	#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /!< Timer register update event forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	1176
bogdanm	0:9b334a45a8ff	1177	#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
bogdanm	0:9b334a45a8ff	1178	(((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1179	((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) \|\| \
bogdanm	0:9b334a45a8ff	1180	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) \|\| \
bogdanm	0:9b334a45a8ff	1181	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) \|\| \
bogdanm	0:9b334a45a8ff	1182	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) \|\| \
bogdanm	0:9b334a45a8ff	1183	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) \|\| \
bogdanm	0:9b334a45a8ff	1184	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) \|\| \
bogdanm	0:9b334a45a8ff	1185	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) \|\| \
bogdanm	0:9b334a45a8ff	1186	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) \|\| \
bogdanm	0:9b334a45a8ff	1187	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) \|\| \
bogdanm	0:9b334a45a8ff	1188	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) \|\| \
bogdanm	0:9b334a45a8ff	1189	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) \|\| \
bogdanm	0:9b334a45a8ff	1190	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) \|\| \
bogdanm	0:9b334a45a8ff	1191	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) \|\| \
bogdanm	0:9b334a45a8ff	1192	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) \|\| \
bogdanm	0:9b334a45a8ff	1193	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) \|\| \
bogdanm	0:9b334a45a8ff	1194	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) \|\| \
bogdanm	0:9b334a45a8ff	1195	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) \|\| \
bogdanm	0:9b334a45a8ff	1196	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) \|\| \
bogdanm	0:9b334a45a8ff	1197	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) \|\| \
bogdanm	0:9b334a45a8ff	1198	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) \|\| \
bogdanm	0:9b334a45a8ff	1199	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) \|\| \
bogdanm	0:9b334a45a8ff	1200	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) \|\| \
bogdanm	0:9b334a45a8ff	1201	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) \|\| \
bogdanm	0:9b334a45a8ff	1202	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) \|\| \
bogdanm	0:9b334a45a8ff	1203	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) \|\| \
bogdanm	0:9b334a45a8ff	1204	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) \|\| \
bogdanm	0:9b334a45a8ff	1205	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) \|\| \
bogdanm	0:9b334a45a8ff	1206	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) \|\| \
bogdanm	0:9b334a45a8ff	1207	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) \|\| \
bogdanm	0:9b334a45a8ff	1208	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) \|\| \
bogdanm	0:9b334a45a8ff	1209	((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
bogdanm	0:9b334a45a8ff	1210	/**
bogdanm	0:9b334a45a8ff	1211	* @}
bogdanm	0:9b334a45a8ff	1212	*/
bogdanm	0:9b334a45a8ff	1213
bogdanm	0:9b334a45a8ff	1214	/** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
bogdanm	0:9b334a45a8ff	1215	* @{
bogdanm	0:9b334a45a8ff	1216	* @brief Constants defining whether or not the timer output transition to its
bogdanm	0:9b334a45a8ff	1217	IDLE state when burst mode is entered
bogdanm	0:9b334a45a8ff	1218	*/
bogdanm	0:9b334a45a8ff	1219	#define HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000 /!< The output is not affected by the burst mode operation /
bogdanm	0:9b334a45a8ff	1220	#define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /!< The output is in idle state when requested by the burst mode controller /
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
bogdanm	0:9b334a45a8ff	1223	(((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1224	((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
bogdanm	0:9b334a45a8ff	1225	/**
bogdanm	0:9b334a45a8ff	1226	* @}
bogdanm	0:9b334a45a8ff	1227	*/
bogdanm	0:9b334a45a8ff	1228
bogdanm	0:9b334a45a8ff	1229	/** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
bogdanm	0:9b334a45a8ff	1230	* @{
bogdanm	0:9b334a45a8ff	1231	* @brief Constants defining the output level when output is in IDLE state
bogdanm	0:9b334a45a8ff	1232	*/
bogdanm	0:9b334a45a8ff	1233	#define HRTIM_OUTPUTIDLELEVEL_INACTIVE (uint32_t)0x00000000 /!< Output at inactive level when in IDLE state /
bogdanm	0:9b334a45a8ff	1234	#define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /!< Output at active level when in IDLE state /
bogdanm	0:9b334a45a8ff	1235
bogdanm	0:9b334a45a8ff	1236	#define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
bogdanm	0:9b334a45a8ff	1237	(((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	1238	((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
bogdanm	0:9b334a45a8ff	1239	/**
bogdanm	0:9b334a45a8ff	1240	* @}
bogdanm	0:9b334a45a8ff	1241	*/
bogdanm	0:9b334a45a8ff	1242
bogdanm	0:9b334a45a8ff	1243	/** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
bogdanm	0:9b334a45a8ff	1244	* @{
bogdanm	0:9b334a45a8ff	1245	* @brief Constants defining the output level when output is in FAULT state
bogdanm	0:9b334a45a8ff	1246	*/
bogdanm	0:9b334a45a8ff	1247	#define HRTIM_OUTPUTFAULTLEVEL_NONE (uint32_t)0x00000000 /!< The output is not affected by the fault input /
bogdanm	0:9b334a45a8ff	1248	#define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /!< Output at active level when in FAULT state /
bogdanm	0:9b334a45a8ff	1249	#define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /!< Output at inactive level when in FAULT state /
bogdanm	0:9b334a45a8ff	1250	#define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 \| HRTIM_OUTR_FAULT1_0) /!< Output is tri-stated when in FAULT state /
bogdanm	0:9b334a45a8ff	1251
bogdanm	0:9b334a45a8ff	1252	#define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
bogdanm	0:9b334a45a8ff	1253	(((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1254	((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	1255	((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	1256	((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
bogdanm	0:9b334a45a8ff	1257	/**
bogdanm	0:9b334a45a8ff	1258	* @}
bogdanm	0:9b334a45a8ff	1259	*/
bogdanm	0:9b334a45a8ff	1260
bogdanm	0:9b334a45a8ff	1261	/** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
bogdanm	0:9b334a45a8ff	1262	* @{
bogdanm	0:9b334a45a8ff	1263	* @brief Constants defining whether or not chopper mode is enabled for a timer
bogdanm	0:9b334a45a8ff	1264	output
bogdanm	0:9b334a45a8ff	1265	*/
bogdanm	0:9b334a45a8ff	1266	#define HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000 /!< Output signal is not altered /
bogdanm	0:9b334a45a8ff	1267	#define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /!< Output signal is chopped by a carrier signal /
bogdanm	0:9b334a45a8ff	1268
bogdanm	0:9b334a45a8ff	1269	#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
bogdanm	0:9b334a45a8ff	1270	(((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	1271	((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
bogdanm	0:9b334a45a8ff	1272	/**
bogdanm	0:9b334a45a8ff	1273	* @}
bogdanm	0:9b334a45a8ff	1274	*/
bogdanm	0:9b334a45a8ff	1275
bogdanm	0:9b334a45a8ff	1276	/** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
bogdanm	0:9b334a45a8ff	1277	* @{
bogdanm	0:9b334a45a8ff	1278	* @brief Constants defining the idle mode entry is delayed by forcing a
bogdanm	0:9b334a45a8ff	1279	deadtime insertion before switching the outputs to their idle state
bogdanm	0:9b334a45a8ff	1280	*/
bogdanm	0:9b334a45a8ff	1281	#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000 /!< The programmed Idle state is applied immediately to the Output /
bogdanm	0:9b334a45a8ff	1282	#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /!< Deadtime is inserted on output before entering the idle mode /
bogdanm	0:9b334a45a8ff	1283
bogdanm	0:9b334a45a8ff	1284	#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
bogdanm	0:9b334a45a8ff	1285	(((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) \|\| \
bogdanm	0:9b334a45a8ff	1286	((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
bogdanm	0:9b334a45a8ff	1287	/**
bogdanm	0:9b334a45a8ff	1288	* @}
bogdanm	0:9b334a45a8ff	1289	*/
bogdanm	0:9b334a45a8ff	1290
bogdanm	0:9b334a45a8ff	1291	/** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
bogdanm	0:9b334a45a8ff	1292	* @{
bogdanm	0:9b334a45a8ff	1293	* @brief Constants defining the events that can be selected to trigger the
bogdanm	0:9b334a45a8ff	1294	* capture of the timing unit counter
bogdanm	0:9b334a45a8ff	1295	*/
bogdanm	0:9b334a45a8ff	1296	#define HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000 /!< Capture trigger is disabled /
bogdanm	0:9b334a45a8ff	1297	#define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /!< The update event triggers the Capture /
bogdanm	0:9b334a45a8ff	1298	#define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /!< The External event 1 triggers the Capture /
bogdanm	0:9b334a45a8ff	1299	#define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /!< The External event 2 triggers the Capture /
bogdanm	0:9b334a45a8ff	1300	#define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /!< The External event 3 triggers the Capture /
bogdanm	0:9b334a45a8ff	1301	#define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /!< The External event 4 triggers the Capture /
bogdanm	0:9b334a45a8ff	1302	#define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /!< The External event 5 triggers the Capture /
bogdanm	0:9b334a45a8ff	1303	#define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /!< The External event 6 triggers the Capture /
bogdanm	0:9b334a45a8ff	1304	#define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /!< The External event 7 triggers the Capture /
bogdanm	0:9b334a45a8ff	1305	#define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /!< The External event 8 triggers the Capture /
bogdanm	0:9b334a45a8ff	1306	#define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /!< The External event 9 triggers the Capture /
bogdanm	0:9b334a45a8ff	1307	#define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /!< The External event 10 triggers the Capture /
bogdanm	0:9b334a45a8ff	1308	#define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /!< Capture is triggered by TA1 output inactive to active transition /
bogdanm	0:9b334a45a8ff	1309	#define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /!< Capture is triggered by TA1 output active to inactive transition /
bogdanm	0:9b334a45a8ff	1310	#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /!< Timer A Compare 1 triggers Capture /
bogdanm	0:9b334a45a8ff	1311	#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /!< Timer A Compare 2 triggers Capture /
bogdanm	0:9b334a45a8ff	1312	#define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /!< Capture is triggered by TB1 output inactive to active transition /
bogdanm	0:9b334a45a8ff	1313	#define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /!< Capture is triggered by TB1 output active to inactive transition /
bogdanm	0:9b334a45a8ff	1314	#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /!< Timer B Compare 1 triggers Capture /
bogdanm	0:9b334a45a8ff	1315	#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /!< Timer B Compare 2 triggers Capture /
bogdanm	0:9b334a45a8ff	1316	#define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /!< Capture is triggered by TC1 output inactive to active transition /
bogdanm	0:9b334a45a8ff	1317	#define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /!< Capture is triggered by TC1 output active to inactive transition /
bogdanm	0:9b334a45a8ff	1318	#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /!< Timer C Compare 1 triggers Capture /
bogdanm	0:9b334a45a8ff	1319	#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /!< Timer C Compare 2 triggers Capture /
bogdanm	0:9b334a45a8ff	1320	#define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /!< Capture is triggered by TD1 output inactive to active transition /
bogdanm	0:9b334a45a8ff	1321	#define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /!< Capture is triggered by TD1 output active to inactive transition /
bogdanm	0:9b334a45a8ff	1322	#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /!< Timer D Compare 1 triggers Capture /
bogdanm	0:9b334a45a8ff	1323	#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /!< Timer D Compare 2 triggers Capture /
bogdanm	0:9b334a45a8ff	1324	#define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /!< Capture is triggered by TE1 output inactive to active transition /
bogdanm	0:9b334a45a8ff	1325	#define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /!< Capture is triggered by TE1 output active to inactive transition /
bogdanm	0:9b334a45a8ff	1326	#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /!< Timer E Compare 1 triggers Capture /
bogdanm	0:9b334a45a8ff	1327	#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /!< Timer E Compare 2 triggers Capture /
bogdanm	0:9b334a45a8ff	1328
bogdanm	0:9b334a45a8ff	1329	#define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
bogdanm	0:9b334a45a8ff	1330	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1331	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) \|\| \
bogdanm	0:9b334a45a8ff	1332	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) \|\| \
bogdanm	0:9b334a45a8ff	1333	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) \|\| \
bogdanm	0:9b334a45a8ff	1334	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) \|\| \
bogdanm	0:9b334a45a8ff	1335	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) \|\| \
bogdanm	0:9b334a45a8ff	1336	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) \|\| \
bogdanm	0:9b334a45a8ff	1337	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) \|\| \
bogdanm	0:9b334a45a8ff	1338	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) \|\| \
bogdanm	0:9b334a45a8ff	1339	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) \|\| \
bogdanm	0:9b334a45a8ff	1340	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) \|\| \
bogdanm	0:9b334a45a8ff	1341	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
bogdanm	0:9b334a45a8ff	1342	\|\| \
bogdanm	0:9b334a45a8ff	1343	(((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
bogdanm	0:9b334a45a8ff	1344	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1345	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1346	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1347	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1348	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1349	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1350	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1351	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1352	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1353	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1354	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1355	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1356	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1357	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1358	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1359	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
bogdanm	0:9b334a45a8ff	1360	\|\| \
bogdanm	0:9b334a45a8ff	1361	(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
bogdanm	0:9b334a45a8ff	1362	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1363	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1364	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1365	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1366	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1367	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1368	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1369	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1370	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1371	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1372	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1373	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1374	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1375	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1376	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1377	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
bogdanm	0:9b334a45a8ff	1378	\|\| \
bogdanm	0:9b334a45a8ff	1379	(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
bogdanm	0:9b334a45a8ff	1380	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1381	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1382	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1383	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1384	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1385	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1386	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1387	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1388	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1389	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1390	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1391	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1392	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1393	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1394	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1395	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
bogdanm	0:9b334a45a8ff	1396	\|\| \
bogdanm	0:9b334a45a8ff	1397	(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
bogdanm	0:9b334a45a8ff	1398	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1399	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1400	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1401	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1402	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1403	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1404	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1405	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1406	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1407	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1408	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1409	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1410	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1411	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1412	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1413	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
bogdanm	0:9b334a45a8ff	1414	\|\| \
bogdanm	0:9b334a45a8ff	1415	(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
bogdanm	0:9b334a45a8ff	1416	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1417	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1418	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1419	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1420	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1421	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1422	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1423	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1424	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1425	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1426	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1427	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	1428	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
bogdanm	0:9b334a45a8ff	1429	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
bogdanm	0:9b334a45a8ff	1430	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1431	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
bogdanm	0:9b334a45a8ff	1432	/**
bogdanm	0:9b334a45a8ff	1433	* @}
bogdanm	0:9b334a45a8ff	1434	*/
bogdanm	0:9b334a45a8ff	1435
bogdanm	0:9b334a45a8ff	1436	/** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
bogdanm	0:9b334a45a8ff	1437	* @{
bogdanm	0:9b334a45a8ff	1438	* @brief Constants defining the event filtering apploed to external events
bogdanm	0:9b334a45a8ff	1439	* by a timer
bogdanm	0:9b334a45a8ff	1440	*/
bogdanm	0:9b334a45a8ff	1441	#define HRTIM_TIMEVENTFILTER_NONE (0x00000000)
bogdanm	0:9b334a45a8ff	1442	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from counter reset/roll-over to Compare 1 /
bogdanm	0:9b334a45a8ff	1443	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from counter reset/roll-over to Compare 2 /
bogdanm	0:9b334a45a8ff	1444	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from counter reset/roll-over to Compare 3 /
bogdanm	0:9b334a45a8ff	1445	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /!< Blanking from counter reset/roll-over to Compare 4 /
bogdanm	0:9b334a45a8ff	1446	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR1 source /
bogdanm	0:9b334a45a8ff	1447	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from another timing unit: TIMFLTR2 source /
bogdanm	0:9b334a45a8ff	1448	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR3 source /
bogdanm	0:9b334a45a8ff	1449	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /!< Blanking from another timing unit: TIMFLTR4 source /
bogdanm	0:9b334a45a8ff	1450	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR5 source /
bogdanm	0:9b334a45a8ff	1451	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from another timing unit: TIMFLTR6 source /
bogdanm	0:9b334a45a8ff	1452	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR7 source /
bogdanm	0:9b334a45a8ff	1453	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2) /!< Blanking from another timing unit: TIMFLTR8 source /
bogdanm	0:9b334a45a8ff	1454	#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Windowing from counter reset/roll-over to Compare 2 /
bogdanm	0:9b334a45a8ff	1455	#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1) /!< Windowing from counter reset/roll-over to Compare 3 /
bogdanm	0:9b334a45a8ff	1456	#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Windowing from another timing unit: TIMWIN source /
bogdanm	0:9b334a45a8ff	1457
bogdanm	0:9b334a45a8ff	1458	#define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
bogdanm	0:9b334a45a8ff	1459	(((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1460	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) \|\| \
bogdanm	0:9b334a45a8ff	1461	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) \|\| \
bogdanm	0:9b334a45a8ff	1462	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) \|\| \
bogdanm	0:9b334a45a8ff	1463	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) \|\| \
bogdanm	0:9b334a45a8ff	1464	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) \|\| \
bogdanm	0:9b334a45a8ff	1465	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) \|\| \
bogdanm	0:9b334a45a8ff	1466	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) \|\| \
bogdanm	0:9b334a45a8ff	1467	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) \|\| \
bogdanm	0:9b334a45a8ff	1468	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) \|\| \
bogdanm	0:9b334a45a8ff	1469	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) \|\| \
bogdanm	0:9b334a45a8ff	1470	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) \|\| \
bogdanm	0:9b334a45a8ff	1471	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) \|\| \
bogdanm	0:9b334a45a8ff	1472	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) \|\| \
bogdanm	0:9b334a45a8ff	1473	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) \|\| \
bogdanm	0:9b334a45a8ff	1474	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
bogdanm	0:9b334a45a8ff	1475	/**
bogdanm	0:9b334a45a8ff	1476	* @}
bogdanm	0:9b334a45a8ff	1477	*/
bogdanm	0:9b334a45a8ff	1478
bogdanm	0:9b334a45a8ff	1479	/** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
bogdanm	0:9b334a45a8ff	1480	* @{
bogdanm	0:9b334a45a8ff	1481	* @brief Constants defining whether or not the external event is
bogdanm	0:9b334a45a8ff	1482	* memorized (latched) and generated as soon as the blanking period
bogdanm	0:9b334a45a8ff	1483	* is completed or the window ends
bogdanm	0:9b334a45a8ff	1484	*/
bogdanm	0:9b334a45a8ff	1485	#define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000) /!< Event is ignored if it happens during a blank, or passed through during a window /
bogdanm	0:9b334a45a8ff	1486	#define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /!< Event is latched and delayed till the end of the blanking or windowing period /
bogdanm	0:9b334a45a8ff	1487
bogdanm	0:9b334a45a8ff	1488	#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
bogdanm	0:9b334a45a8ff	1489	(((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	1490	((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
bogdanm	0:9b334a45a8ff	1491	/**
bogdanm	0:9b334a45a8ff	1492	* @}
bogdanm	0:9b334a45a8ff	1493	*/
bogdanm	0:9b334a45a8ff	1494
bogdanm	0:9b334a45a8ff	1495	/** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Deadtime Prescaler Ratio
bogdanm	0:9b334a45a8ff	1496	* @{
bogdanm	0:9b334a45a8ff	1497	* @brief Constants defining division ratio between the timer clock frequency
bogdanm	0:9b334a45a8ff	1498	* (fHRTIM) and the deadtime generator clock (fDTG)
bogdanm	0:9b334a45a8ff	1499	*/
bogdanm	0:9b334a45a8ff	1500	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 ((uint32_t)0x00000000) /!< fDTG = fHRTIM 8 */
bogdanm	0:9b334a45a8ff	1501	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM 4 */
bogdanm	0:9b334a45a8ff	1502	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /!< fDTG = fHRTIM 2 */
bogdanm	0:9b334a45a8ff	1503	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 \| HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM /
bogdanm	0:9b334a45a8ff	1504	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /!< fDTG = fHRTIM / 2 /
bogdanm	0:9b334a45a8ff	1505	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 \| HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM / 4 /
bogdanm	0:9b334a45a8ff	1506	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 \| HRTIM_DTR_DTPRSC_1) /!< fDTG = fHRTIM / 8 /
bogdanm	0:9b334a45a8ff	1507	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 \| HRTIM_DTR_DTPRSC_1 \| HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM / 16 /
bogdanm	0:9b334a45a8ff	1508
bogdanm	0:9b334a45a8ff	1509	#define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
bogdanm	0:9b334a45a8ff	1510	(((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) \|\| \
bogdanm	0:9b334a45a8ff	1511	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) \|\| \
bogdanm	0:9b334a45a8ff	1512	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) \|\| \
bogdanm	0:9b334a45a8ff	1513	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1514	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1515	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	1516	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	1517	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
bogdanm	0:9b334a45a8ff	1518	/**
bogdanm	0:9b334a45a8ff	1519	* @}
bogdanm	0:9b334a45a8ff	1520	*/
bogdanm	0:9b334a45a8ff	1521
bogdanm	0:9b334a45a8ff	1522	/** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Deadtime Rising Sign
bogdanm	0:9b334a45a8ff	1523	* @{
bogdanm	0:9b334a45a8ff	1524	* @brief Constants defining whether the deadtime is positive or negative
bogdanm	0:9b334a45a8ff	1525	* (overlapping signal) on rising edge
bogdanm	0:9b334a45a8ff	1526	*/
bogdanm	0:9b334a45a8ff	1527	#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000) /!< Positive deadtime on rising edge /
bogdanm	0:9b334a45a8ff	1528	#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /!< Negative deadtime on rising edge /
bogdanm	0:9b334a45a8ff	1529
bogdanm	0:9b334a45a8ff	1530	#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
bogdanm	0:9b334a45a8ff	1531	(((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) \|\| \
bogdanm	0:9b334a45a8ff	1532	((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
bogdanm	0:9b334a45a8ff	1533	/**
bogdanm	0:9b334a45a8ff	1534	* @}
bogdanm	0:9b334a45a8ff	1535	*/
bogdanm	0:9b334a45a8ff	1536
bogdanm	0:9b334a45a8ff	1537	/** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Deadtime Rising Lock
bogdanm	0:9b334a45a8ff	1538	* @{
bogdanm	0:9b334a45a8ff	1539	* @brief Constants defining whether or not the deadtime (rising sign and
bogdanm	0:9b334a45a8ff	1540	* value) is write protected
bogdanm	0:9b334a45a8ff	1541	*/
bogdanm	0:9b334a45a8ff	1542	#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000) /!< Deadtime rising value and sign is writable /
bogdanm	0:9b334a45a8ff	1543	#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /!< Deadtime rising value and sign is read-only /
bogdanm	0:9b334a45a8ff	1544
bogdanm	0:9b334a45a8ff	1545	#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
bogdanm	0:9b334a45a8ff	1546	(((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) \|\| \
bogdanm	0:9b334a45a8ff	1547	((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
bogdanm	0:9b334a45a8ff	1548	/**
bogdanm	0:9b334a45a8ff	1549	* @}
bogdanm	0:9b334a45a8ff	1550	*/
bogdanm	0:9b334a45a8ff	1551
bogdanm	0:9b334a45a8ff	1552	/** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Deadtime Rising Sign Lock
bogdanm	0:9b334a45a8ff	1553	* @{
bogdanm	0:9b334a45a8ff	1554	* @brief Constants defining whether or not the deadtime rising sign is write
bogdanm	0:9b334a45a8ff	1555	* protected
bogdanm	0:9b334a45a8ff	1556	*/
bogdanm	0:9b334a45a8ff	1557	#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /!< Deadtime rising sign is writable /
bogdanm	0:9b334a45a8ff	1558	#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /!< Deadtime rising sign is read-only /
bogdanm	0:9b334a45a8ff	1559
bogdanm	0:9b334a45a8ff	1560	#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
bogdanm	0:9b334a45a8ff	1561	(((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) \|\| \
bogdanm	0:9b334a45a8ff	1562	((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
bogdanm	0:9b334a45a8ff	1563	/**
bogdanm	0:9b334a45a8ff	1564	* @}
bogdanm	0:9b334a45a8ff	1565	*/
bogdanm	0:9b334a45a8ff	1566
bogdanm	0:9b334a45a8ff	1567	/** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Deadtime Falling Sign
bogdanm	0:9b334a45a8ff	1568	* @{
bogdanm	0:9b334a45a8ff	1569	* @brief Constants defining whether the deadtime is positive or negative
bogdanm	0:9b334a45a8ff	1570	* (overlapping signal) on falling edge
bogdanm	0:9b334a45a8ff	1571	*/
bogdanm	0:9b334a45a8ff	1572	#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000) /!< Positive deadtime on falling edge /
bogdanm	0:9b334a45a8ff	1573	#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /!< Negative deadtime on falling edge /
bogdanm	0:9b334a45a8ff	1574
bogdanm	0:9b334a45a8ff	1575	#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
bogdanm	0:9b334a45a8ff	1576	(((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) \|\| \
bogdanm	0:9b334a45a8ff	1577	((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
bogdanm	0:9b334a45a8ff	1578	/**
bogdanm	0:9b334a45a8ff	1579	* @}
bogdanm	0:9b334a45a8ff	1580	*/
bogdanm	0:9b334a45a8ff	1581
bogdanm	0:9b334a45a8ff	1582	/** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Deadtime Falling Lock
bogdanm	0:9b334a45a8ff	1583	* @{
bogdanm	0:9b334a45a8ff	1584	* @brief Constants defining whether or not the deadtime (falling sign and
bogdanm	0:9b334a45a8ff	1585	* value) is write protected
bogdanm	0:9b334a45a8ff	1586	*/
bogdanm	0:9b334a45a8ff	1587	#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000) /!< Deadtime falling value and sign is writable /
bogdanm	0:9b334a45a8ff	1588	#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /!< Deadtime falling value and sign is read-only /
bogdanm	0:9b334a45a8ff	1589
bogdanm	0:9b334a45a8ff	1590	#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
bogdanm	0:9b334a45a8ff	1591	(((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) \|\| \
bogdanm	0:9b334a45a8ff	1592	((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
bogdanm	0:9b334a45a8ff	1593	/**
bogdanm	0:9b334a45a8ff	1594	* @}
bogdanm	0:9b334a45a8ff	1595	*/
bogdanm	0:9b334a45a8ff	1596
bogdanm	0:9b334a45a8ff	1597	/** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Deadtime Falling Sign Lock
bogdanm	0:9b334a45a8ff	1598	* @{
bogdanm	0:9b334a45a8ff	1599	* @brief Constants defining whether or not the deadtime falling sign is write
bogdanm	0:9b334a45a8ff	1600	* protected
bogdanm	0:9b334a45a8ff	1601	*/
bogdanm	0:9b334a45a8ff	1602	#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /!< Deadtime falling sign is writable /
bogdanm	0:9b334a45a8ff	1603	#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /!< Deadtime falling sign is read-only /
bogdanm	0:9b334a45a8ff	1604
bogdanm	0:9b334a45a8ff	1605	#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
bogdanm	0:9b334a45a8ff	1606	(((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) \|\| \
bogdanm	0:9b334a45a8ff	1607	((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
bogdanm	0:9b334a45a8ff	1608	/**
bogdanm	0:9b334a45a8ff	1609	* @}
bogdanm	0:9b334a45a8ff	1610	*/
bogdanm	0:9b334a45a8ff	1611
bogdanm	0:9b334a45a8ff	1612	/** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
bogdanm	0:9b334a45a8ff	1613	* @{
bogdanm	0:9b334a45a8ff	1614	* @brief Constants defining the frequency of the generated high frequency carrier
bogdanm	0:9b334a45a8ff	1615	*/
bogdanm	0:9b334a45a8ff	1616	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 ((uint32_t)0x000000) /!< fCHPFRQ = fHRTIM / 16 /
bogdanm	0:9b334a45a8ff	1617	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 32 /
bogdanm	0:9b334a45a8ff	1618	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 48 /
bogdanm	0:9b334a45a8ff	1619	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 64 /
bogdanm	0:9b334a45a8ff	1620	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /!< fCHPFRQ = fHRTIM / 80 /
bogdanm	0:9b334a45a8ff	1621	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 96 /
bogdanm	0:9b334a45a8ff	1622	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 112 /
bogdanm	0:9b334a45a8ff	1623	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 128 /
bogdanm	0:9b334a45a8ff	1624	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /!< fCHPFRQ = fHRTIM / 144 /
bogdanm	0:9b334a45a8ff	1625	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 160 /
bogdanm	0:9b334a45a8ff	1626	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 176 /
bogdanm	0:9b334a45a8ff	1627	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 192 /
bogdanm	0:9b334a45a8ff	1628	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2) /!< fCHPFRQ = fHRTIM / 208 /
bogdanm	0:9b334a45a8ff	1629	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 224 /
bogdanm	0:9b334a45a8ff	1630	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 240 /
bogdanm	0:9b334a45a8ff	1631	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 256 /
bogdanm	0:9b334a45a8ff	1632
bogdanm	0:9b334a45a8ff	1633	#define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
bogdanm	0:9b334a45a8ff	1634	(((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) \|\| \
bogdanm	0:9b334a45a8ff	1635	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) \|\| \
bogdanm	0:9b334a45a8ff	1636	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) \|\| \
bogdanm	0:9b334a45a8ff	1637	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) \|\| \
bogdanm	0:9b334a45a8ff	1638	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) \|\| \
bogdanm	0:9b334a45a8ff	1639	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) \|\| \
bogdanm	0:9b334a45a8ff	1640	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) \|\| \
bogdanm	0:9b334a45a8ff	1641	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) \|\| \
bogdanm	0:9b334a45a8ff	1642	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) \|\| \
bogdanm	0:9b334a45a8ff	1643	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) \|\| \
bogdanm	0:9b334a45a8ff	1644	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) \|\| \
bogdanm	0:9b334a45a8ff	1645	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) \|\| \
bogdanm	0:9b334a45a8ff	1646	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) \|\| \
bogdanm	0:9b334a45a8ff	1647	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) \|\| \
bogdanm	0:9b334a45a8ff	1648	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) \|\| \
bogdanm	0:9b334a45a8ff	1649	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
bogdanm	0:9b334a45a8ff	1650	/**
bogdanm	0:9b334a45a8ff	1651	* @}
bogdanm	0:9b334a45a8ff	1652	*/
bogdanm	0:9b334a45a8ff	1653
bogdanm	0:9b334a45a8ff	1654	/** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
bogdanm	0:9b334a45a8ff	1655	* @{
bogdanm	0:9b334a45a8ff	1656	* @brief Constants defining the duty cycle of the generated high frequency carrier
bogdanm	0:9b334a45a8ff	1657	* Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
bogdanm	0:9b334a45a8ff	1658	*/
bogdanm	0:9b334a45a8ff	1659	#define HRTIM_CHOPPER_DUTYCYCLE_0 ((uint32_t)0x000000) /!< 0/8 (i.e. only 1st pulse is present) / /!< fCHPFRQ = fHRTIM / 16 /
bogdanm	0:9b334a45a8ff	1660	#define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /!< 1/8 (12.5 %)/ /!< fCHPFRQ = fHRTIM / 16 /
bogdanm	0:9b334a45a8ff	1661	#define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /!< 2/8 (25 %) / /!< fCHPFRQ = fHRTIM / 16 /
bogdanm	0:9b334a45a8ff	1662	#define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 \| HRTIM_CHPR_CARDTY_0) /!< 3/8 (37.5 %) / /!< fCHPFRQ = fHRTIM / 16 /
bogdanm	0:9b334a45a8ff	1663	#define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /!< 4/8 (50 %) / /!< fCHPFRQ = fHRTIM / 16 /
bogdanm	0:9b334a45a8ff	1664	#define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 \| HRTIM_CHPR_CARDTY_0) /!< 5/8 (62.5 %) / /!< fCHPFRQ = fHRTIM / 16 /
bogdanm	0:9b334a45a8ff	1665	#define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 \| HRTIM_CHPR_CARDTY_1) /!< 6/8 (75 %) / /!< fCHPFRQ = fHRTIM / 16 /
bogdanm	0:9b334a45a8ff	1666	#define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 \| HRTIM_CHPR_CARDTY_1 \| HRTIM_CHPR_CARDTY_0) /!< 7/8 (87.5 %) / /!< fCHPFRQ = fHRTIM / 16 /
bogdanm	0:9b334a45a8ff	1667
bogdanm	0:9b334a45a8ff	1668	#define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
bogdanm	0:9b334a45a8ff	1669	(((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) \|\| \
bogdanm	0:9b334a45a8ff	1670	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) \|\| \
bogdanm	0:9b334a45a8ff	1671	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) \|\| \
bogdanm	0:9b334a45a8ff	1672	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) \|\| \
bogdanm	0:9b334a45a8ff	1673	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) \|\| \
bogdanm	0:9b334a45a8ff	1674	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) \|\| \
bogdanm	0:9b334a45a8ff	1675	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) \|\| \
bogdanm	0:9b334a45a8ff	1676	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
bogdanm	0:9b334a45a8ff	1677	/**
bogdanm	0:9b334a45a8ff	1678	* @}
bogdanm	0:9b334a45a8ff	1679	*/
bogdanm	0:9b334a45a8ff	1680
bogdanm	0:9b334a45a8ff	1681	/** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
bogdanm	0:9b334a45a8ff	1682	* @{
bogdanm	0:9b334a45a8ff	1683	* @brief Constants defining the pulse width of the first pulse of the generated
bogdanm	0:9b334a45a8ff	1684	* high frequency carrier
bogdanm	0:9b334a45a8ff	1685	*/
bogdanm	0:9b334a45a8ff	1686	#define HRTIM_CHOPPER_PULSEWIDTH_16 ((uint32_t)0x000000) /!< tSTPW = tHRTIM x 16 /
bogdanm	0:9b334a45a8ff	1687	#define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 32 /
bogdanm	0:9b334a45a8ff	1688	#define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 48 /
bogdanm	0:9b334a45a8ff	1689	#define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 64 /
bogdanm	0:9b334a45a8ff	1690	#define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /!< tSTPW = tHRTIM x 80 /
bogdanm	0:9b334a45a8ff	1691	#define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 96 /
bogdanm	0:9b334a45a8ff	1692	#define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 112 /
bogdanm	0:9b334a45a8ff	1693	#define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 128 /
bogdanm	0:9b334a45a8ff	1694	#define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /!< tSTPW = tHRTIM x 144 /
bogdanm	0:9b334a45a8ff	1695	#define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 160 /
bogdanm	0:9b334a45a8ff	1696	#define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 176 /
bogdanm	0:9b334a45a8ff	1697	#define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 192 /
bogdanm	0:9b334a45a8ff	1698	#define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2) /!< tSTPW = tHRTIM x 208 /
bogdanm	0:9b334a45a8ff	1699	#define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 224 /
bogdanm	0:9b334a45a8ff	1700	#define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 240 /
bogdanm	0:9b334a45a8ff	1701	#define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 256 /
bogdanm	0:9b334a45a8ff	1702
bogdanm	0:9b334a45a8ff	1703	#define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
bogdanm	0:9b334a45a8ff	1704	(((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) \|\| \
bogdanm	0:9b334a45a8ff	1705	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) \|\| \
bogdanm	0:9b334a45a8ff	1706	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) \|\| \
bogdanm	0:9b334a45a8ff	1707	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) \|\| \
bogdanm	0:9b334a45a8ff	1708	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) \|\| \
bogdanm	0:9b334a45a8ff	1709	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) \|\| \
bogdanm	0:9b334a45a8ff	1710	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) \|\| \
bogdanm	0:9b334a45a8ff	1711	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) \|\| \
bogdanm	0:9b334a45a8ff	1712	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) \|\| \
bogdanm	0:9b334a45a8ff	1713	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) \|\| \
bogdanm	0:9b334a45a8ff	1714	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) \|\| \
bogdanm	0:9b334a45a8ff	1715	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) \|\| \
bogdanm	0:9b334a45a8ff	1716	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) \|\| \
bogdanm	0:9b334a45a8ff	1717	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) \|\| \
bogdanm	0:9b334a45a8ff	1718	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) \|\| \
bogdanm	0:9b334a45a8ff	1719	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
bogdanm	0:9b334a45a8ff	1720	/**
bogdanm	0:9b334a45a8ff	1721	* @}
bogdanm	0:9b334a45a8ff	1722	*/
bogdanm	0:9b334a45a8ff	1723
bogdanm	0:9b334a45a8ff	1724	/** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
bogdanm	0:9b334a45a8ff	1725	* @{
bogdanm	0:9b334a45a8ff	1726	* @brief Constants defining the options for synchronizing multiple HRTIM
bogdanm	0:9b334a45a8ff	1727	* instances, as a master unit (generating a synchronization signal)
bogdanm	0:9b334a45a8ff	1728	* or as a slave (waiting for a trigger to be synchronized)
bogdanm	0:9b334a45a8ff	1729	*/
bogdanm	0:9b334a45a8ff	1730	#define HRTIM_SYNCOPTION_NONE (uint32_t)0x00000000 /!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) /
bogdanm	0:9b334a45a8ff	1731	#define HRTIM_SYNCOPTION_MASTER (uint32_t)0x00000001 /!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)/
bogdanm	0:9b334a45a8ff	1732	#define HRTIM_SYNCOPTION_SLAVE (uint32_t)0x00000002 /!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) /
bogdanm	0:9b334a45a8ff	1733	/**
bogdanm	0:9b334a45a8ff	1734	* @}
bogdanm	0:9b334a45a8ff	1735	*/
bogdanm	0:9b334a45a8ff	1736
bogdanm	0:9b334a45a8ff	1737	/** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
bogdanm	0:9b334a45a8ff	1738	* @{
bogdanm	0:9b334a45a8ff	1739	* @brief Constants defining defining the synchronization input source
bogdanm	0:9b334a45a8ff	1740	*/
bogdanm	0:9b334a45a8ff	1741	#define HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000 /!< disabled. HRTIM is not synchronized and runs in standalone mode /
bogdanm	0:9b334a45a8ff	1742	#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /!< The HRTIM is synchronized with the on-chip timer /
bogdanm	0:9b334a45a8ff	1743	#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 \| HRTIM_MCR_SYNC_IN_0) /!< A positive pulse on SYNCIN input triggers the HRTIM /
bogdanm	0:9b334a45a8ff	1744
bogdanm	0:9b334a45a8ff	1745	#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
bogdanm	0:9b334a45a8ff	1746	(((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1747	((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) \|\| \
bogdanm	0:9b334a45a8ff	1748	((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
bogdanm	0:9b334a45a8ff	1749	/**
bogdanm	0:9b334a45a8ff	1750	* @}
bogdanm	0:9b334a45a8ff	1751	*/
bogdanm	0:9b334a45a8ff	1752
bogdanm	0:9b334a45a8ff	1753	/** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
bogdanm	0:9b334a45a8ff	1754	* @{
bogdanm	0:9b334a45a8ff	1755	* @brief Constants defining the source and event to be sent on the
bogdanm	0:9b334a45a8ff	1756	* synchronization outputs
bogdanm	0:9b334a45a8ff	1757	*/
bogdanm	0:9b334a45a8ff	1758	#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000 /!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer start event /
bogdanm	0:9b334a45a8ff	1759	#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer compare 1 event/
bogdanm	0:9b334a45a8ff	1760	#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A start or reset events /
bogdanm	0:9b334a45a8ff	1761	#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 \| HRTIM_MCR_SYNC_SRC_0) /!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A compare 1 event /
bogdanm	0:9b334a45a8ff	1762
bogdanm	0:9b334a45a8ff	1763	#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
bogdanm	0:9b334a45a8ff	1764	(((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) \|\| \
bogdanm	0:9b334a45a8ff	1765	((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	1766	((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) \|\| \
bogdanm	0:9b334a45a8ff	1767	((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
bogdanm	0:9b334a45a8ff	1768	/**
bogdanm	0:9b334a45a8ff	1769	* @}
bogdanm	0:9b334a45a8ff	1770	*/
bogdanm	0:9b334a45a8ff	1771
bogdanm	0:9b334a45a8ff	1772	/** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
bogdanm	0:9b334a45a8ff	1773	* @{
bogdanm	0:9b334a45a8ff	1774	* @brief Constants defining the routing and conditioning of the synchronization output event
bogdanm	0:9b334a45a8ff	1775	*/
bogdanm	0:9b334a45a8ff	1776	#define HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000 /!< Synchronization output event is disabled /
bogdanm	0:9b334a45a8ff	1777	#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) /
bogdanm	0:9b334a45a8ff	1778	#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 \| HRTIM_MCR_SYNC_OUT_0) /!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) /
bogdanm	0:9b334a45a8ff	1779
bogdanm	0:9b334a45a8ff	1780	#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
bogdanm	0:9b334a45a8ff	1781	(((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1782	((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) \|\| \
bogdanm	0:9b334a45a8ff	1783	((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
bogdanm	0:9b334a45a8ff	1784	/**
bogdanm	0:9b334a45a8ff	1785	* @}
bogdanm	0:9b334a45a8ff	1786	*/
bogdanm	0:9b334a45a8ff	1787
bogdanm	0:9b334a45a8ff	1788	/** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
bogdanm	0:9b334a45a8ff	1789	* @{
bogdanm	0:9b334a45a8ff	1790	* @brief Constants defining available sources associated to external events
bogdanm	0:9b334a45a8ff	1791	*/
bogdanm	0:9b334a45a8ff	1792	#define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000) /!< External event source 1 /
bogdanm	0:9b334a45a8ff	1793	#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /!< External event source 2 /
bogdanm	0:9b334a45a8ff	1794	#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /!< External event source 3 /
bogdanm	0:9b334a45a8ff	1795	#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 \| HRTIM_EECR1_EE1SRC_0) /!< External event source 4 /
bogdanm	0:9b334a45a8ff	1796
bogdanm	0:9b334a45a8ff	1797	#define IS_HRTIM_EVENTSRC(EVENTSRC)\
bogdanm	0:9b334a45a8ff	1798	(((EVENTSRC) == HRTIM_EVENTSRC_1) \|\| \
bogdanm	0:9b334a45a8ff	1799	((EVENTSRC) == HRTIM_EVENTSRC_2) \|\| \
bogdanm	0:9b334a45a8ff	1800	((EVENTSRC) == HRTIM_EVENTSRC_3) \|\| \
bogdanm	0:9b334a45a8ff	1801	((EVENTSRC) == HRTIM_EVENTSRC_4))
bogdanm	0:9b334a45a8ff	1802	/**
bogdanm	0:9b334a45a8ff	1803	* @}
bogdanm	0:9b334a45a8ff	1804	*/
bogdanm	0:9b334a45a8ff	1805
bogdanm	0:9b334a45a8ff	1806	/** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
bogdanm	0:9b334a45a8ff	1807	* @{
bogdanm	0:9b334a45a8ff	1808	* @brief Constants defining the polarity of an external event
bogdanm	0:9b334a45a8ff	1809	*/
bogdanm	0:9b334a45a8ff	1810	#define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000) /!< External event is active high /
bogdanm	0:9b334a45a8ff	1811	#define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /!< External event is active low /
bogdanm	0:9b334a45a8ff	1812
bogdanm	0:9b334a45a8ff	1813	#define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
bogdanm	0:9b334a45a8ff	1814	((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
bogdanm	0:9b334a45a8ff	1815	(((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) \|\| \
bogdanm	0:9b334a45a8ff	1816	((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \
bogdanm	0:9b334a45a8ff	1817	\|\| \
bogdanm	0:9b334a45a8ff	1818	(((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) \|\| \
bogdanm	0:9b334a45a8ff	1819	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)\|\| \
bogdanm	0:9b334a45a8ff	1820	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
bogdanm	0:9b334a45a8ff	1821	/**
bogdanm	0:9b334a45a8ff	1822	* @}
bogdanm	0:9b334a45a8ff	1823	*/
bogdanm	0:9b334a45a8ff	1824
bogdanm	0:9b334a45a8ff	1825	/** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
bogdanm	0:9b334a45a8ff	1826	* @{
bogdanm	0:9b334a45a8ff	1827	* @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
bogdanm	0:9b334a45a8ff	1828	* of an external event
bogdanm	0:9b334a45a8ff	1829	*/
bogdanm	0:9b334a45a8ff	1830	#define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000) /!< External event is active on level /
bogdanm	0:9b334a45a8ff	1831	#define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /!< External event is active on Rising edge /
bogdanm	0:9b334a45a8ff	1832	#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /!< External event is active on Falling edge /
bogdanm	0:9b334a45a8ff	1833	#define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 \| HRTIM_EECR1_EE1SNS_0) /!< External event is active on Rising and Falling edges /
bogdanm	0:9b334a45a8ff	1834
bogdanm	0:9b334a45a8ff	1835	#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
bogdanm	0:9b334a45a8ff	1836	(((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) \|\| \
bogdanm	0:9b334a45a8ff	1837	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) \|\| \
bogdanm	0:9b334a45a8ff	1838	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) \|\| \
bogdanm	0:9b334a45a8ff	1839	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
bogdanm	0:9b334a45a8ff	1840	/**
bogdanm	0:9b334a45a8ff	1841	* @}
bogdanm	0:9b334a45a8ff	1842	*/
bogdanm	0:9b334a45a8ff	1843
bogdanm	0:9b334a45a8ff	1844	/** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
bogdanm	0:9b334a45a8ff	1845	* @{
bogdanm	0:9b334a45a8ff	1846	* @brief Constants defining whether or not an external event is programmed in
bogdanm	0:9b334a45a8ff	1847	fast mode
bogdanm	0:9b334a45a8ff	1848	*/
bogdanm	0:9b334a45a8ff	1849	#define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000) /!< External Event is acting asynchronously on outputs (low latency mode) /
bogdanm	0:9b334a45a8ff	1850	#define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /!< External Event is re-synchronized by the HRTIM logic before acting on outputs /
bogdanm	0:9b334a45a8ff	1851
bogdanm	0:9b334a45a8ff	1852	#define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
bogdanm	0:9b334a45a8ff	1853	(((((EVENT) == HRTIM_EVENT_1) \|\| \
bogdanm	0:9b334a45a8ff	1854	((EVENT) == HRTIM_EVENT_2) \|\| \
bogdanm	0:9b334a45a8ff	1855	((EVENT) == HRTIM_EVENT_3) \|\| \
bogdanm	0:9b334a45a8ff	1856	((EVENT) == HRTIM_EVENT_4) \|\| \
bogdanm	0:9b334a45a8ff	1857	((EVENT) == HRTIM_EVENT_5)) && \
bogdanm	0:9b334a45a8ff	1858	(((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) \|\| \
bogdanm	0:9b334a45a8ff	1859	((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
bogdanm	0:9b334a45a8ff	1860	\|\| \
bogdanm	0:9b334a45a8ff	1861	(((EVENT) == HRTIM_EVENT_6) \|\| \
bogdanm	0:9b334a45a8ff	1862	((EVENT) == HRTIM_EVENT_7) \|\| \
bogdanm	0:9b334a45a8ff	1863	((EVENT) == HRTIM_EVENT_8) \|\| \
bogdanm	0:9b334a45a8ff	1864	((EVENT) == HRTIM_EVENT_9) \|\| \
bogdanm	0:9b334a45a8ff	1865	((EVENT) == HRTIM_EVENT_10)))
bogdanm	0:9b334a45a8ff	1866
bogdanm	0:9b334a45a8ff	1867	/**
bogdanm	0:9b334a45a8ff	1868	* @}
bogdanm	0:9b334a45a8ff	1869	*/
bogdanm	0:9b334a45a8ff	1870
bogdanm	0:9b334a45a8ff	1871	/** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
bogdanm	0:9b334a45a8ff	1872	* @{
bogdanm	0:9b334a45a8ff	1873	* @brief Constants defining the frequency used to sample an external event 6
bogdanm	0:9b334a45a8ff	1874	* input and the length (N) of the digital filter applied
bogdanm	0:9b334a45a8ff	1875	*/
bogdanm	0:9b334a45a8ff	1876	#define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000) /!< Filter disabled /
bogdanm	0:9b334a45a8ff	1877	#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fHRTIM, N=2 /
bogdanm	0:9b334a45a8ff	1878	#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fHRTIM, N=4 /
bogdanm	0:9b334a45a8ff	1879	#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fHRTIM, N=8 /
bogdanm	0:9b334a45a8ff	1880	#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /!< fSAMPLING= fEEVS/2, N=6 /
bogdanm	0:9b334a45a8ff	1881	#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/2, N=8 /
bogdanm	0:9b334a45a8ff	1882	#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fEEVS/4, N=6 /
bogdanm	0:9b334a45a8ff	1883	#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/4, N=8 /
bogdanm	0:9b334a45a8ff	1884	#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /!< fSAMPLING= fEEVS/8, N=6 /
bogdanm	0:9b334a45a8ff	1885	#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/8, N=8 /
bogdanm	0:9b334a45a8ff	1886	#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fEEVS/16, N=5 /
bogdanm	0:9b334a45a8ff	1887	#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/16, N=6 /
bogdanm	0:9b334a45a8ff	1888	#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2) /!< fSAMPLING= fEEVS/16, N=8 /
bogdanm	0:9b334a45a8ff	1889	#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/32, N=5 /
bogdanm	0:9b334a45a8ff	1890	#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fEEVS/32, N=6 /
bogdanm	0:9b334a45a8ff	1891	#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/32, N=8 /
bogdanm	0:9b334a45a8ff	1892
bogdanm	0:9b334a45a8ff	1893	#define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
bogdanm	0:9b334a45a8ff	1894	((((EVENT) == HRTIM_EVENT_1) \|\| \
bogdanm	0:9b334a45a8ff	1895	((EVENT) == HRTIM_EVENT_2) \|\| \
bogdanm	0:9b334a45a8ff	1896	((EVENT) == HRTIM_EVENT_3) \|\| \
bogdanm	0:9b334a45a8ff	1897	((EVENT) == HRTIM_EVENT_4) \|\| \
bogdanm	0:9b334a45a8ff	1898	((EVENT) == HRTIM_EVENT_5)) \
bogdanm	0:9b334a45a8ff	1899	\|\| \
bogdanm	0:9b334a45a8ff	1900	((((EVENT) == HRTIM_EVENT_6) \|\| \
bogdanm	0:9b334a45a8ff	1901	((EVENT) == HRTIM_EVENT_7) \|\| \
bogdanm	0:9b334a45a8ff	1902	((EVENT) == HRTIM_EVENT_8) \|\| \
bogdanm	0:9b334a45a8ff	1903	((EVENT) == HRTIM_EVENT_9) \|\| \
bogdanm	0:9b334a45a8ff	1904	((EVENT) == HRTIM_EVENT_10)) && \
bogdanm	0:9b334a45a8ff	1905	(((FILTER) == HRTIM_EVENTFILTER_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1906	((FILTER) == HRTIM_EVENTFILTER_1) \|\| \
bogdanm	0:9b334a45a8ff	1907	((FILTER) == HRTIM_EVENTFILTER_2) \|\| \
bogdanm	0:9b334a45a8ff	1908	((FILTER) == HRTIM_EVENTFILTER_3) \|\| \
bogdanm	0:9b334a45a8ff	1909	((FILTER) == HRTIM_EVENTFILTER_4) \|\| \
bogdanm	0:9b334a45a8ff	1910	((FILTER) == HRTIM_EVENTFILTER_5) \|\| \
bogdanm	0:9b334a45a8ff	1911	((FILTER) == HRTIM_EVENTFILTER_6) \|\| \
bogdanm	0:9b334a45a8ff	1912	((FILTER) == HRTIM_EVENTFILTER_7) \|\| \
bogdanm	0:9b334a45a8ff	1913	((FILTER) == HRTIM_EVENTFILTER_8) \|\| \
bogdanm	0:9b334a45a8ff	1914	((FILTER) == HRTIM_EVENTFILTER_9) \|\| \
bogdanm	0:9b334a45a8ff	1915	((FILTER) == HRTIM_EVENTFILTER_10) \|\| \
bogdanm	0:9b334a45a8ff	1916	((FILTER) == HRTIM_EVENTFILTER_11) \|\| \
bogdanm	0:9b334a45a8ff	1917	((FILTER) == HRTIM_EVENTFILTER_12) \|\| \
bogdanm	0:9b334a45a8ff	1918	((FILTER) == HRTIM_EVENTFILTER_13) \|\| \
bogdanm	0:9b334a45a8ff	1919	((FILTER) == HRTIM_EVENTFILTER_14) \|\| \
bogdanm	0:9b334a45a8ff	1920	((FILTER) == HRTIM_EVENTFILTER_15))))
bogdanm	0:9b334a45a8ff	1921	/**
bogdanm	0:9b334a45a8ff	1922	* @}
bogdanm	0:9b334a45a8ff	1923	*/
bogdanm	0:9b334a45a8ff	1924
bogdanm	0:9b334a45a8ff	1925	/** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
bogdanm	0:9b334a45a8ff	1926	* @{
bogdanm	0:9b334a45a8ff	1927	* @brief Constants defining division ratio between the timer clock frequency
bogdanm	0:9b334a45a8ff	1928	* fHRTIM) and the external event signal sampling clock (fEEVS)
bogdanm	0:9b334a45a8ff	1929	* used by the digital filters
bogdanm	0:9b334a45a8ff	1930	*/
bogdanm	0:9b334a45a8ff	1931	#define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000) /!< fEEVS=fHRTIM /
bogdanm	0:9b334a45a8ff	1932	#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /!< fEEVS=fHRTIM / 2 /
bogdanm	0:9b334a45a8ff	1933	#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /!< fEEVS=fHRTIM / 4 /
bogdanm	0:9b334a45a8ff	1934	#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 \| HRTIM_EECR3_EEVSD_0) /!< fEEVS=fHRTIM / 8 /
bogdanm	0:9b334a45a8ff	1935
bogdanm	0:9b334a45a8ff	1936	#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
bogdanm	0:9b334a45a8ff	1937	(((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	1938	((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	1939	((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	1940	((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	1941	/**
bogdanm	0:9b334a45a8ff	1942	* @}
bogdanm	0:9b334a45a8ff	1943	*/
bogdanm	0:9b334a45a8ff	1944
bogdanm	0:9b334a45a8ff	1945	/** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
bogdanm	0:9b334a45a8ff	1946	* @{
bogdanm	0:9b334a45a8ff	1947	* @brief Constants defining whether a faults is be triggered by any external
bogdanm	0:9b334a45a8ff	1948	* or internal fault source
bogdanm	0:9b334a45a8ff	1949	*/
bogdanm	0:9b334a45a8ff	1950	#define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000) /!< Fault input is FLT input pin /
bogdanm	0:9b334a45a8ff	1951	#define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /!< Fault input is FLT_Int signal (e.g. internal comparator) /
bogdanm	0:9b334a45a8ff	1952
bogdanm	0:9b334a45a8ff	1953
bogdanm	0:9b334a45a8ff	1954	#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
bogdanm	0:9b334a45a8ff	1955	(((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) \|\| \
bogdanm	0:9b334a45a8ff	1956	((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
bogdanm	0:9b334a45a8ff	1957	/**
bogdanm	0:9b334a45a8ff	1958	* @}
bogdanm	0:9b334a45a8ff	1959	*/
bogdanm	0:9b334a45a8ff	1960
bogdanm	0:9b334a45a8ff	1961	/** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
bogdanm	0:9b334a45a8ff	1962	* @{
bogdanm	0:9b334a45a8ff	1963	* @brief Constants defining the polarity of a fault event
bogdanm	0:9b334a45a8ff	1964	*/
bogdanm	0:9b334a45a8ff	1965	#define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000) /!< Fault input is active low /
bogdanm	0:9b334a45a8ff	1966	#define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /!< Fault input is active high /
bogdanm	0:9b334a45a8ff	1967
bogdanm	0:9b334a45a8ff	1968	#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
bogdanm	0:9b334a45a8ff	1969	(((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) \|\| \
bogdanm	0:9b334a45a8ff	1970	((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
bogdanm	0:9b334a45a8ff	1971	/**
bogdanm	0:9b334a45a8ff	1972	* @}
bogdanm	0:9b334a45a8ff	1973	*/
bogdanm	0:9b334a45a8ff	1974
bogdanm	0:9b334a45a8ff	1975	/** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
bogdanm	0:9b334a45a8ff	1976	* @{
bogdanm	0:9b334a45a8ff	1977	* @ brief Constants defining the frequency used to sample the fault input and
bogdanm	0:9b334a45a8ff	1978	* the length (N) of the digital filter applied
bogdanm	0:9b334a45a8ff	1979	*/
bogdanm	0:9b334a45a8ff	1980	#define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000) /!< Filter disabled /
bogdanm	0:9b334a45a8ff	1981	#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fHRTIM, N=2 /
bogdanm	0:9b334a45a8ff	1982	#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fHRTIM, N=4 /
bogdanm	0:9b334a45a8ff	1983	#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fHRTIM, N=8 /
bogdanm	0:9b334a45a8ff	1984	#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /!< fSAMPLING= fFLTS/2, N=6 /
bogdanm	0:9b334a45a8ff	1985	#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/2, N=8 /
bogdanm	0:9b334a45a8ff	1986	#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/4, N=6 /
bogdanm	0:9b334a45a8ff	1987	#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/4, N=8 /
bogdanm	0:9b334a45a8ff	1988	#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /!< fSAMPLING= fFLTS/8, N=6 /
bogdanm	0:9b334a45a8ff	1989	#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/8, N=8 /
bogdanm	0:9b334a45a8ff	1990	#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/16, N=5 /
bogdanm	0:9b334a45a8ff	1991	#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/16, N=6 /
bogdanm	0:9b334a45a8ff	1992	#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2) /!< fSAMPLING= fFLTS/16, N=8 /
bogdanm	0:9b334a45a8ff	1993	#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/32, N=5 /
bogdanm	0:9b334a45a8ff	1994	#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/32, N=6 /
bogdanm	0:9b334a45a8ff	1995	#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/32, N=8 /
bogdanm	0:9b334a45a8ff	1996
bogdanm	0:9b334a45a8ff	1997	#define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
bogdanm	0:9b334a45a8ff	1998	(((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) \|\| \
bogdanm	0:9b334a45a8ff	1999	((FAULTFILTER) == HRTIM_FAULTFILTER_1) \|\| \
bogdanm	0:9b334a45a8ff	2000	((FAULTFILTER) == HRTIM_FAULTFILTER_2) \|\| \
bogdanm	0:9b334a45a8ff	2001	((FAULTFILTER) == HRTIM_FAULTFILTER_3) \|\| \
bogdanm	0:9b334a45a8ff	2002	((FAULTFILTER) == HRTIM_FAULTFILTER_4) \|\| \
bogdanm	0:9b334a45a8ff	2003	((FAULTFILTER) == HRTIM_FAULTFILTER_5) \|\| \
bogdanm	0:9b334a45a8ff	2004	((FAULTFILTER) == HRTIM_FAULTFILTER_6) \|\| \
bogdanm	0:9b334a45a8ff	2005	((FAULTFILTER) == HRTIM_FAULTFILTER_7) \|\| \
bogdanm	0:9b334a45a8ff	2006	((FAULTFILTER) == HRTIM_FAULTFILTER_8) \|\| \
bogdanm	0:9b334a45a8ff	2007	((FAULTFILTER) == HRTIM_FAULTFILTER_9) \|\| \
bogdanm	0:9b334a45a8ff	2008	((FAULTFILTER) == HRTIM_FAULTFILTER_10) \|\| \
bogdanm	0:9b334a45a8ff	2009	((FAULTFILTER) == HRTIM_FAULTFILTER_11) \|\| \
bogdanm	0:9b334a45a8ff	2010	((FAULTFILTER) == HRTIM_FAULTFILTER_12) \|\| \
bogdanm	0:9b334a45a8ff	2011	((FAULTFILTER) == HRTIM_FAULTFILTER_13) \|\| \
bogdanm	0:9b334a45a8ff	2012	((FAULTFILTER) == HRTIM_FAULTFILTER_14) \|\| \
bogdanm	0:9b334a45a8ff	2013	((FAULTFILTER) == HRTIM_FAULTFILTER_15))
bogdanm	0:9b334a45a8ff	2014	/**
bogdanm	0:9b334a45a8ff	2015	* @}
bogdanm	0:9b334a45a8ff	2016	*/
bogdanm	0:9b334a45a8ff	2017
bogdanm	0:9b334a45a8ff	2018	/** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
bogdanm	0:9b334a45a8ff	2019	* @{
bogdanm	0:9b334a45a8ff	2020	* @brief Constants defining whether or not the fault programming bits are
bogdanm	0:9b334a45a8ff	2021	write protected
bogdanm	0:9b334a45a8ff	2022	*/
bogdanm	0:9b334a45a8ff	2023	#define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000) /!< Fault settings bits are read/write /
bogdanm	0:9b334a45a8ff	2024	#define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /!< Fault settings bits are read only /
bogdanm	0:9b334a45a8ff	2025
bogdanm	0:9b334a45a8ff	2026	#define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
bogdanm	0:9b334a45a8ff	2027	(((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) \|\| \
bogdanm	0:9b334a45a8ff	2028	((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
bogdanm	0:9b334a45a8ff	2029	/**
bogdanm	0:9b334a45a8ff	2030	* @}
bogdanm	0:9b334a45a8ff	2031	*/
bogdanm	0:9b334a45a8ff	2032
bogdanm	0:9b334a45a8ff	2033	/** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
bogdanm	0:9b334a45a8ff	2034	* @{
bogdanm	0:9b334a45a8ff	2035	* @brief Constants defining the division ratio between the timer clock
bogdanm	0:9b334a45a8ff	2036	* frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
bogdanm	0:9b334a45a8ff	2037	* by the digital filters.
bogdanm	0:9b334a45a8ff	2038	*/
bogdanm	0:9b334a45a8ff	2039	#define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000) /!< fFLTS=fHRTIM /
bogdanm	0:9b334a45a8ff	2040	#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /!< fFLTS=fHRTIM / 2 /
bogdanm	0:9b334a45a8ff	2041	#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /!< fFLTS=fHRTIM / 4 /
bogdanm	0:9b334a45a8ff	2042	#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 \| HRTIM_FLTINR2_FLTSD_0) /!< fFLTS=fHRTIM / 8 /
bogdanm	0:9b334a45a8ff	2043
bogdanm	0:9b334a45a8ff	2044	#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
bogdanm	0:9b334a45a8ff	2045	(((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	2046	((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	2047	((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	2048	((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
bogdanm	0:9b334a45a8ff	2049	/**
bogdanm	0:9b334a45a8ff	2050	* @}
bogdanm	0:9b334a45a8ff	2051	*/
bogdanm	0:9b334a45a8ff	2052
bogdanm	0:9b334a45a8ff	2053	/** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
bogdanm	0:9b334a45a8ff	2054	* @{
bogdanm	0:9b334a45a8ff	2055	* @brief Constants defining if the burst mode is entered once or if it is
bogdanm	0:9b334a45a8ff	2056	* continuously operating
bogdanm	0:9b334a45a8ff	2057	*/
bogdanm	0:9b334a45a8ff	2058	#define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000) /!< Burst mode operates in single shot mode /
bogdanm	0:9b334a45a8ff	2059	#define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /!< Burst mode operates in continuous mode /
bogdanm	0:9b334a45a8ff	2060
bogdanm	0:9b334a45a8ff	2061	#define IS_HRTIM_BURSTMODE(BURSTMODE)\
bogdanm	0:9b334a45a8ff	2062	(((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) \|\| \
bogdanm	0:9b334a45a8ff	2063	((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
bogdanm	0:9b334a45a8ff	2064	/**
bogdanm	0:9b334a45a8ff	2065	* @}
bogdanm	0:9b334a45a8ff	2066	*/
bogdanm	0:9b334a45a8ff	2067
bogdanm	0:9b334a45a8ff	2068	/** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
bogdanm	0:9b334a45a8ff	2069	* @{
bogdanm	0:9b334a45a8ff	2070	* @brief Constants defining the clock source for the burst mode counter
bogdanm	0:9b334a45a8ff	2071	*/
bogdanm	0:9b334a45a8ff	2072	#define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000) /!< Master timer counter reset/roll-over is used as clock source for the burst mode counter /
bogdanm	0:9b334a45a8ff	2073	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /!< Timer A counter reset/roll-over is used as clock source for the burst mode counter /
bogdanm	0:9b334a45a8ff	2074	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /!< Timer B counter reset/roll-over is used as clock source for the burst mode counter /
bogdanm	0:9b334a45a8ff	2075	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 \| HRTIM_BMCR_BMCLK_0) /!< Timer C counter reset/roll-over is used as clock source for the burst mode counter /
bogdanm	0:9b334a45a8ff	2076	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /!< Timer D counter reset/roll-over is used as clock source for the burst mode counter /
bogdanm	0:9b334a45a8ff	2077	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_0) /!< Timer E counter reset/roll-over is used as clock source for the burst mode counter /
bogdanm	0:9b334a45a8ff	2078	#define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_1) /!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock /
bogdanm	0:9b334a45a8ff	2079	#define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_1 \| HRTIM_BMCR_BMCLK_0) /!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock /
bogdanm	0:9b334a45a8ff	2080	#define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock /
bogdanm	0:9b334a45a8ff	2081	#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 \| HRTIM_BMCR_BMCLK_1) /!< Prescaled fHRTIM clock is used as clock source for the burst mode counter /
bogdanm	0:9b334a45a8ff	2082
bogdanm	0:9b334a45a8ff	2083	#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
bogdanm	0:9b334a45a8ff	2084	(((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) \|\| \
bogdanm	0:9b334a45a8ff	2085	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) \|\| \
bogdanm	0:9b334a45a8ff	2086	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) \|\| \
bogdanm	0:9b334a45a8ff	2087	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) \|\| \
bogdanm	0:9b334a45a8ff	2088	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) \|\| \
bogdanm	0:9b334a45a8ff	2089	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) \|\| \
bogdanm	0:9b334a45a8ff	2090	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) \|\| \
bogdanm	0:9b334a45a8ff	2091	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) \|\| \
bogdanm	0:9b334a45a8ff	2092	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) \|\| \
bogdanm	0:9b334a45a8ff	2093	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
bogdanm	0:9b334a45a8ff	2094	/**
bogdanm	0:9b334a45a8ff	2095	* @}
bogdanm	0:9b334a45a8ff	2096	*/
bogdanm	0:9b334a45a8ff	2097
bogdanm	0:9b334a45a8ff	2098	/** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
bogdanm	0:9b334a45a8ff	2099	* @{
bogdanm	0:9b334a45a8ff	2100	* @brief Constants defining the prescaling ratio of the fHRTIM clock
bogdanm	0:9b334a45a8ff	2101	* for the burst mode controller
bogdanm	0:9b334a45a8ff	2102	*/
bogdanm	0:9b334a45a8ff	2103	#define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000) /!< fBRST = fHRTIM /
bogdanm	0:9b334a45a8ff	2104	#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/2 /
bogdanm	0:9b334a45a8ff	2105	#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/4 /
bogdanm	0:9b334a45a8ff	2106	#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/8 /
bogdanm	0:9b334a45a8ff	2107	#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /!< fBRST = fHRTIM/16 /
bogdanm	0:9b334a45a8ff	2108	#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/32 /
bogdanm	0:9b334a45a8ff	2109	#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/64 /
bogdanm	0:9b334a45a8ff	2110	#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/128 /
bogdanm	0:9b334a45a8ff	2111	#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /!< fBRST = fHRTIM/256 /
bogdanm	0:9b334a45a8ff	2112	#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/512 /
bogdanm	0:9b334a45a8ff	2113	#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/1024 /
bogdanm	0:9b334a45a8ff	2114	#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/2048/
bogdanm	0:9b334a45a8ff	2115	#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2) /!< fBRST = fHRTIM/4096 /
bogdanm	0:9b334a45a8ff	2116	#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/8192 /
bogdanm	0:9b334a45a8ff	2117	#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/16384 /
bogdanm	0:9b334a45a8ff	2118	#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/32768 /
bogdanm	0:9b334a45a8ff	2119
bogdanm	0:9b334a45a8ff	2120	#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
bogdanm	0:9b334a45a8ff	2121	(((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) \|\| \
bogdanm	0:9b334a45a8ff	2122	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	2123	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) \|\| \
bogdanm	0:9b334a45a8ff	2124	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	2125	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) \|\| \
bogdanm	0:9b334a45a8ff	2126	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) \|\| \
bogdanm	0:9b334a45a8ff	2127	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) \|\| \
bogdanm	0:9b334a45a8ff	2128	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) \|\| \
bogdanm	0:9b334a45a8ff	2129	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) \|\| \
bogdanm	0:9b334a45a8ff	2130	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) \|\| \
bogdanm	0:9b334a45a8ff	2131	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) \|\| \
bogdanm	0:9b334a45a8ff	2132	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) \|\| \
bogdanm	0:9b334a45a8ff	2133	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) \|\| \
bogdanm	0:9b334a45a8ff	2134	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) \|\| \
bogdanm	0:9b334a45a8ff	2135	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) \|\| \
bogdanm	0:9b334a45a8ff	2136	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
bogdanm	0:9b334a45a8ff	2137	/**
bogdanm	0:9b334a45a8ff	2138	* @}
bogdanm	0:9b334a45a8ff	2139	*/
bogdanm	0:9b334a45a8ff	2140
bogdanm	0:9b334a45a8ff	2141	/** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
bogdanm	0:9b334a45a8ff	2142	* @{
bogdanm	0:9b334a45a8ff	2143	* @brief Constants defining whether or not burst mode registers preload
bogdanm	0:9b334a45a8ff	2144	mechanism is enabled, i.e. a write access into a preloadable register
bogdanm	0:9b334a45a8ff	2145	(HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
bogdanm	0:9b334a45a8ff	2146	*/
bogdanm	0:9b334a45a8ff	2147	#define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000) /!< Preload disabled: the write access is directly done into active registers /
bogdanm	0:9b334a45a8ff	2148	#define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /!< Preload enabled: the write access is done into preload registers /
bogdanm	0:9b334a45a8ff	2149
bogdanm	0:9b334a45a8ff	2150	#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
bogdanm	0:9b334a45a8ff	2151	(((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	2152	((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
bogdanm	0:9b334a45a8ff	2153	/**
bogdanm	0:9b334a45a8ff	2154	* @}
bogdanm	0:9b334a45a8ff	2155	*/
bogdanm	0:9b334a45a8ff	2156
bogdanm	0:9b334a45a8ff	2157	/** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
bogdanm	0:9b334a45a8ff	2158	* @{
bogdanm	0:9b334a45a8ff	2159	* @brief Constants defining the events that can be used tor trig the burst
bogdanm	0:9b334a45a8ff	2160	* mode operation
bogdanm	0:9b334a45a8ff	2161	*/
bogdanm	0:9b334a45a8ff	2162	#define HRTIM_BURSTMODETRIGGER_NONE (uint32_t)0x00000000 /!< No trigger /
bogdanm	0:9b334a45a8ff	2163	#define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /!< Master reset /
bogdanm	0:9b334a45a8ff	2164	#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /!< Master repetition /
bogdanm	0:9b334a45a8ff	2165	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /!< Master compare 1 /
bogdanm	0:9b334a45a8ff	2166	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /!< Master compare 2 /
bogdanm	0:9b334a45a8ff	2167	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /!< Master compare 3 /
bogdanm	0:9b334a45a8ff	2168	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /!< Master compare 4 /
bogdanm	0:9b334a45a8ff	2169	#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /!< Timer A reset /
bogdanm	0:9b334a45a8ff	2170	#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /!< Timer A repetition /
bogdanm	0:9b334a45a8ff	2171	#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /!< Timer A compare 1 /
bogdanm	0:9b334a45a8ff	2172	#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /!< Timer A compare 2 /
bogdanm	0:9b334a45a8ff	2173	#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /!< Timer B reset /
bogdanm	0:9b334a45a8ff	2174	#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /!< Timer B repetition /
bogdanm	0:9b334a45a8ff	2175	#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /!< Timer B compare 1 /
bogdanm	0:9b334a45a8ff	2176	#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /!< Timer B compare 2 /
bogdanm	0:9b334a45a8ff	2177	#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /!< Timer C reset /
bogdanm	0:9b334a45a8ff	2178	#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /!< Timer C repetition /
bogdanm	0:9b334a45a8ff	2179	#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /!< Timer C compare 1 /
bogdanm	0:9b334a45a8ff	2180	#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /!< Timer C compare 2 /
bogdanm	0:9b334a45a8ff	2181	#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /!< Timer D reset /
bogdanm	0:9b334a45a8ff	2182	#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /!< Timer D repetition /
bogdanm	0:9b334a45a8ff	2183	#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /!< Timer D compare 1 /
bogdanm	0:9b334a45a8ff	2184	#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /!< Timer D compare 2 /
bogdanm	0:9b334a45a8ff	2185	#define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /!< Timer E reset /
bogdanm	0:9b334a45a8ff	2186	#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /!< Timer E repetition /
bogdanm	0:9b334a45a8ff	2187	#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /!< Timer E compare 1 /
bogdanm	0:9b334a45a8ff	2188	#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /!< Timer E compare 2 /
bogdanm	0:9b334a45a8ff	2189	#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /!< Timer A period following External Event 7 /
bogdanm	0:9b334a45a8ff	2190	#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /!< Timer D period following External Event 8 /
bogdanm	0:9b334a45a8ff	2191	#define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /!< External Event 7 (timer A filters applied) /
bogdanm	0:9b334a45a8ff	2192	#define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /!< External Event 8 (timer D filters applied)/
bogdanm	0:9b334a45a8ff	2193	#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /!< On-chip Event /
bogdanm	0:9b334a45a8ff	2194
bogdanm	0:9b334a45a8ff	2195	#define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
bogdanm	0:9b334a45a8ff	2196	(((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) \|\| \
bogdanm	0:9b334a45a8ff	2197	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) \|\| \
bogdanm	0:9b334a45a8ff	2198	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) \|\| \
bogdanm	0:9b334a45a8ff	2199	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	2200	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	2201	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) \|\| \
bogdanm	0:9b334a45a8ff	2202	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) \|\| \
bogdanm	0:9b334a45a8ff	2203	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) \|\| \
bogdanm	0:9b334a45a8ff	2204	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) \|\| \
bogdanm	0:9b334a45a8ff	2205	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	2206	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	2207	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) \|\| \
bogdanm	0:9b334a45a8ff	2208	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) \|\| \
bogdanm	0:9b334a45a8ff	2209	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	2210	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	2211	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) \|\| \
bogdanm	0:9b334a45a8ff	2212	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) \|\| \
bogdanm	0:9b334a45a8ff	2213	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	2214	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	2215	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) \|\| \
bogdanm	0:9b334a45a8ff	2216	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) \|\| \
bogdanm	0:9b334a45a8ff	2217	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	2218	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	2219	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) \|\| \
bogdanm	0:9b334a45a8ff	2220	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) \|\| \
bogdanm	0:9b334a45a8ff	2221	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) \|\| \
bogdanm	0:9b334a45a8ff	2222	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) \|\| \
bogdanm	0:9b334a45a8ff	2223	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) \|\| \
bogdanm	0:9b334a45a8ff	2224	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) \|\| \
bogdanm	0:9b334a45a8ff	2225	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) \|\| \
bogdanm	0:9b334a45a8ff	2226	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) \|\| \
bogdanm	0:9b334a45a8ff	2227	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
bogdanm	0:9b334a45a8ff	2228	/**
bogdanm	0:9b334a45a8ff	2229	* @}
bogdanm	0:9b334a45a8ff	2230	*/
bogdanm	0:9b334a45a8ff	2231
bogdanm	0:9b334a45a8ff	2232	/** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
bogdanm	0:9b334a45a8ff	2233	* @{
bogdanm	0:9b334a45a8ff	2234	* @brief constants defining the source triggering the update of the
bogdanm	0:9b334a45a8ff	2235	HRTIM_ADCxR register (transfer from preload to active register).
bogdanm	0:9b334a45a8ff	2236	*/
bogdanm	0:9b334a45a8ff	2237	#define HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000 /!< Master timer /
bogdanm	0:9b334a45a8ff	2238	#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /!< Timer A /
bogdanm	0:9b334a45a8ff	2239	#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /!< Timer B /
bogdanm	0:9b334a45a8ff	2240	#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 \| HRTIM_CR1_ADC1USRC_0) /!< Timer C /
bogdanm	0:9b334a45a8ff	2241	#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /!< Timer D /
bogdanm	0:9b334a45a8ff	2242	#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 \| HRTIM_CR1_ADC1USRC_0) /!< Timer E /
bogdanm	0:9b334a45a8ff	2243
bogdanm	0:9b334a45a8ff	2244	#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
bogdanm	0:9b334a45a8ff	2245	(((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) \|\| \
bogdanm	0:9b334a45a8ff	2246	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) \|\| \
bogdanm	0:9b334a45a8ff	2247	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) \|\| \
bogdanm	0:9b334a45a8ff	2248	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) \|\| \
bogdanm	0:9b334a45a8ff	2249	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) \|\| \
bogdanm	0:9b334a45a8ff	2250	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
bogdanm	0:9b334a45a8ff	2251	/**
bogdanm	0:9b334a45a8ff	2252	* @}
bogdanm	0:9b334a45a8ff	2253	*/
bogdanm	0:9b334a45a8ff	2254
bogdanm	0:9b334a45a8ff	2255	/** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
bogdanm	0:9b334a45a8ff	2256	* @{
bogdanm	0:9b334a45a8ff	2257	* @brief constants defining the events triggering ADC conversion.
bogdanm	0:9b334a45a8ff	2258	* HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
bogdanm	0:9b334a45a8ff	2259	* HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
bogdanm	0:9b334a45a8ff	2260	*/
bogdanm	0:9b334a45a8ff	2261	#define HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000 /!< No ADC trigger event /
bogdanm	0:9b334a45a8ff	2262	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /!< ADC Trigger on master compare 1 /
bogdanm	0:9b334a45a8ff	2263	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /!< ADC Trigger on master compare 2 /
bogdanm	0:9b334a45a8ff	2264	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /!< ADC Trigger on master compare 3 /
bogdanm	0:9b334a45a8ff	2265	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /!< ADC Trigger on master compare 4 /
bogdanm	0:9b334a45a8ff	2266	#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /!< ADC Trigger on master period /
bogdanm	0:9b334a45a8ff	2267	#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /!< ADC Trigger on external event 1 /
bogdanm	0:9b334a45a8ff	2268	#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /!< ADC Trigger on external event 2 /
bogdanm	0:9b334a45a8ff	2269	#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /!< ADC Trigger on external event 3 /
bogdanm	0:9b334a45a8ff	2270	#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /!< ADC Trigger on external event 4 /
bogdanm	0:9b334a45a8ff	2271	#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /!< ADC Trigger on external event 5 /
bogdanm	0:9b334a45a8ff	2272	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /!< ADC Trigger on Timer A compare 2 /
bogdanm	0:9b334a45a8ff	2273	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /!< ADC Trigger on Timer A compare 3 /
bogdanm	0:9b334a45a8ff	2274	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /!< ADC Trigger on Timer A compare 4 /
bogdanm	0:9b334a45a8ff	2275	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /!< ADC Trigger on Timer A period /
bogdanm	0:9b334a45a8ff	2276	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /!< ADC Trigger on Timer A reset /
bogdanm	0:9b334a45a8ff	2277	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /!< ADC Trigger on Timer B compare 2 /
bogdanm	0:9b334a45a8ff	2278	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /!< ADC Trigger on Timer B compare 3 /
bogdanm	0:9b334a45a8ff	2279	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /!< ADC Trigger on Timer B compare 4 /
bogdanm	0:9b334a45a8ff	2280	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /!< ADC Trigger on Timer B period /
bogdanm	0:9b334a45a8ff	2281	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /!< ADC Trigger on Timer B reset /
bogdanm	0:9b334a45a8ff	2282	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /!< ADC Trigger on Timer C compare 2 /
bogdanm	0:9b334a45a8ff	2283	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /!< ADC Trigger on Timer C compare 3 /
bogdanm	0:9b334a45a8ff	2284	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /!< ADC Trigger on Timer C compare 4 /
bogdanm	0:9b334a45a8ff	2285	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /!< ADC Trigger on Timer C period /
bogdanm	0:9b334a45a8ff	2286	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /!< ADC Trigger on Timer D compare 2 /
bogdanm	0:9b334a45a8ff	2287	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /!< ADC Trigger on Timer D compare 3 /
bogdanm	0:9b334a45a8ff	2288	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /!< ADC Trigger on Timer D compare 4 /
bogdanm	0:9b334a45a8ff	2289	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /!< ADC Trigger on Timer D period /
bogdanm	0:9b334a45a8ff	2290	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /!< ADC Trigger on Timer E compare 2 /
bogdanm	0:9b334a45a8ff	2291	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /!< ADC Trigger on Timer E compare 3 /
bogdanm	0:9b334a45a8ff	2292	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /!< ADC Trigger on Timer E compare 4 /
bogdanm	0:9b334a45a8ff	2293	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /!< ADC Trigger on Timer E period /
bogdanm	0:9b334a45a8ff	2294
bogdanm	0:9b334a45a8ff	2295	#define HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000 /!< No ADC trigger event /
bogdanm	0:9b334a45a8ff	2296	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /!< ADC Trigger on master compare 1 /
bogdanm	0:9b334a45a8ff	2297	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /!< ADC Trigger on master compare 2 /
bogdanm	0:9b334a45a8ff	2298	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /!< ADC Trigger on master compare 3 /
bogdanm	0:9b334a45a8ff	2299	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /!< ADC Trigger on master compare 4 /
bogdanm	0:9b334a45a8ff	2300	#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /!< ADC Trigger on master period /
bogdanm	0:9b334a45a8ff	2301	#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /!< ADC Trigger on external event 6 /
bogdanm	0:9b334a45a8ff	2302	#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /!< ADC Trigger on external event 7 /
bogdanm	0:9b334a45a8ff	2303	#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /!< ADC Trigger on external event 8 /
bogdanm	0:9b334a45a8ff	2304	#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /!< ADC Trigger on external event 9 /
bogdanm	0:9b334a45a8ff	2305	#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /!< ADC Trigger on external event 10 /
bogdanm	0:9b334a45a8ff	2306	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /!< ADC Trigger on Timer A compare 2 /
bogdanm	0:9b334a45a8ff	2307	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /!< ADC Trigger on Timer A compare 3 /
bogdanm	0:9b334a45a8ff	2308	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /!< ADC Trigger on Timer A compare 4 /
bogdanm	0:9b334a45a8ff	2309	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /!< ADC Trigger on Timer A period /
bogdanm	0:9b334a45a8ff	2310	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /!< ADC Trigger on Timer B compare 2 /
bogdanm	0:9b334a45a8ff	2311	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /!< ADC Trigger on Timer B compare 3 /
bogdanm	0:9b334a45a8ff	2312	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /!< ADC Trigger on Timer B compare 4 /
bogdanm	0:9b334a45a8ff	2313	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /!< ADC Trigger on Timer B period /
bogdanm	0:9b334a45a8ff	2314	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /!< ADC Trigger on Timer C compare 2 /
bogdanm	0:9b334a45a8ff	2315	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /!< ADC Trigger on Timer C compare 3 /
bogdanm	0:9b334a45a8ff	2316	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /!< ADC Trigger on Timer C compare 4 /
bogdanm	0:9b334a45a8ff	2317	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /!< ADC Trigger on Timer C period /
bogdanm	0:9b334a45a8ff	2318	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /!< ADC Trigger on Timer C reset /
bogdanm	0:9b334a45a8ff	2319	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /!< ADC Trigger on Timer D compare 2 /
bogdanm	0:9b334a45a8ff	2320	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /!< ADC Trigger on Timer D compare 3 /
bogdanm	0:9b334a45a8ff	2321	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /!< ADC Trigger on Timer D compare 4 /
bogdanm	0:9b334a45a8ff	2322	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /!< ADC Trigger on Timer D period /
bogdanm	0:9b334a45a8ff	2323	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /!< ADC Trigger on Timer D reset /
bogdanm	0:9b334a45a8ff	2324	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /!< ADC Trigger on Timer E compare 2 /
bogdanm	0:9b334a45a8ff	2325	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /!< ADC Trigger on Timer E compare 3 /
bogdanm	0:9b334a45a8ff	2326	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /!< ADC Trigger on Timer E compare 4 /
bogdanm	0:9b334a45a8ff	2327	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /!< ADC Trigger on Timer E reset /
bogdanm	0:9b334a45a8ff	2328
bogdanm	0:9b334a45a8ff	2329	/**
bogdanm	0:9b334a45a8ff	2330	* @}
bogdanm	0:9b334a45a8ff	2331	*/
bogdanm	0:9b334a45a8ff	2332
bogdanm	0:9b334a45a8ff	2333	/** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate
bogdanm	0:9b334a45a8ff	2334	* @{
bogdanm	0:9b334a45a8ff	2335	* @brief Constants defining the DLL calibration periods (in micro seconds)
bogdanm	0:9b334a45a8ff	2336	*/
bogdanm	0:9b334a45a8ff	2337	#define HRTIM_SINGLE_CALIBRATION (uint32_t)0xFFFFFFFF /!< Non periodic DLL calibration /
bogdanm	0:9b334a45a8ff	2338	#define HRTIM_CALIBRATIONRATE_7300 (uint32_t)0x00000000 /!< Periodic DLL calibration: T = 1048576 tHRTIM (7.3 ms) */
bogdanm	0:9b334a45a8ff	2339	#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /!< Periodic DLL calibration: T = 131072 tHRTIM (910 µs) */
bogdanm	0:9b334a45a8ff	2340	#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /!< Periodic DLL calibration: T = 16384 tHRTIM (114 µs) */
bogdanm	0:9b334a45a8ff	2341	#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 \| HRTIM_DLLCR_CALRTE_0) /!< Periodic DLL calibration: T = 2048 tHRTIM (14 µs) */
bogdanm	0:9b334a45a8ff	2342
bogdanm	0:9b334a45a8ff	2343	#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
bogdanm	0:9b334a45a8ff	2344	(((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) \|\| \
bogdanm	0:9b334a45a8ff	2345	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) \|\| \
bogdanm	0:9b334a45a8ff	2346	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) \|\| \
bogdanm	0:9b334a45a8ff	2347	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) \|\| \
bogdanm	0:9b334a45a8ff	2348	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
bogdanm	0:9b334a45a8ff	2349	/**
bogdanm	0:9b334a45a8ff	2350	* @}
bogdanm	0:9b334a45a8ff	2351	*/
bogdanm	0:9b334a45a8ff	2352
bogdanm	0:9b334a45a8ff	2353	/** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
bogdanm	0:9b334a45a8ff	2354	* @{
bogdanm	0:9b334a45a8ff	2355	* @brief Constants defining the registers that can be written during a burst
bogdanm	0:9b334a45a8ff	2356	* DMA operation
bogdanm	0:9b334a45a8ff	2357	*/
bogdanm	0:9b334a45a8ff	2358	#define HRTIM_BURSTDMA_NONE (uint32_t)0x00000000 /!< No register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2359	#define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /!< MCR or TIMxCR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2360	#define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /!< MICR or TIMxICR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2361	#define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /!< MDIER or TIMxDIER register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2362	#define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /!< MCNTR or CNTxCR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2363	#define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /!< MPER or PERxR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2364	#define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /!< MREPR or REPxR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2365	#define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /!< MCMP1R or CMP1xR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2366	#define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /!< MCMP2R or CMP2xR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2367	#define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /!< MCMP3R or CMP3xR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2368	#define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /!< MCMP4R or CMP4xR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2369	#define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /!< TDxR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2370	#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /!< SET1R register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2371	#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /!< RST1R register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2372	#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /!< SET2R register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2373	#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /!< RST1R register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2374	#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /!< EEFxR1 register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2375	#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /!< EEFxR2 register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2376	#define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /!< RSTxR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2377	#define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /!< CHPxR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2378	#define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /!< OUTxR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2379	#define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /!< FLTxR register is updated by Burst DMA accesses /
bogdanm	0:9b334a45a8ff	2380
bogdanm	0:9b334a45a8ff	2381	#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
bogdanm	0:9b334a45a8ff	2382	((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000) == 0x00000000)) \
bogdanm	0:9b334a45a8ff	2383	\|\| \
bogdanm	0:9b334a45a8ff	2384	(((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
bogdanm	0:9b334a45a8ff	2385	\|\| \
bogdanm	0:9b334a45a8ff	2386	(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
bogdanm	0:9b334a45a8ff	2387	\|\| \
bogdanm	0:9b334a45a8ff	2388	(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
bogdanm	0:9b334a45a8ff	2389	\|\| \
bogdanm	0:9b334a45a8ff	2390	(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
bogdanm	0:9b334a45a8ff	2391	\|\| \
bogdanm	0:9b334a45a8ff	2392	(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)))
bogdanm	0:9b334a45a8ff	2393	/**
bogdanm	0:9b334a45a8ff	2394	* @}
bogdanm	0:9b334a45a8ff	2395	*/
bogdanm	0:9b334a45a8ff	2396
bogdanm	0:9b334a45a8ff	2397	/** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
bogdanm	0:9b334a45a8ff	2398	* @{
bogdanm	0:9b334a45a8ff	2399	* @brief Constants used to enable or disable the burst mode controller
bogdanm	0:9b334a45a8ff	2400	*/
bogdanm	0:9b334a45a8ff	2401	#define HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000 /!< Burst mode disabled /
bogdanm	0:9b334a45a8ff	2402	#define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /!< Burst mode enabled /
bogdanm	0:9b334a45a8ff	2403
bogdanm	0:9b334a45a8ff	2404	#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
bogdanm	0:9b334a45a8ff	2405	(((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	2406	((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
bogdanm	0:9b334a45a8ff	2407	/**
bogdanm	0:9b334a45a8ff	2408	* @}
bogdanm	0:9b334a45a8ff	2409	*/
bogdanm	0:9b334a45a8ff	2410
bogdanm	0:9b334a45a8ff	2411	/** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control
bogdanm	0:9b334a45a8ff	2412	* @{
bogdanm	0:9b334a45a8ff	2413	* @brief Constants used to enable or disable a fault channel
bogdanm	0:9b334a45a8ff	2414	*/
bogdanm	0:9b334a45a8ff	2415	#define HRTIM_FAULTMODECTL_DISABLED (uint32_t)0x00000000 /!< Fault channel is disabled /
bogdanm	0:9b334a45a8ff	2416	#define HRTIM_FAULTMODECTL_ENABLED (uint32_t)0x00000001 /!< Fault channel is enabled /
bogdanm	0:9b334a45a8ff	2417
bogdanm	0:9b334a45a8ff	2418	#define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
bogdanm	0:9b334a45a8ff	2419	(((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) \|\| \
bogdanm	0:9b334a45a8ff	2420	((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
bogdanm	0:9b334a45a8ff	2421	/**
bogdanm	0:9b334a45a8ff	2422	* @}
bogdanm	0:9b334a45a8ff	2423	*/
bogdanm	0:9b334a45a8ff	2424
bogdanm	0:9b334a45a8ff	2425	/** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
bogdanm	0:9b334a45a8ff	2426	* @{
bogdanm	0:9b334a45a8ff	2427	* @brief Constants used to force timer registers update
bogdanm	0:9b334a45a8ff	2428	*/
bogdanm	0:9b334a45a8ff	2429	#define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /!< Forces an immediate transfer from the preload to the active register in the master timer /
bogdanm	0:9b334a45a8ff	2430	#define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /!< Forces an immediate transfer from the preload to the active register in the timer A /
bogdanm	0:9b334a45a8ff	2431	#define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /!< Forces an immediate transfer from the preload to the active register in the timer B /
bogdanm	0:9b334a45a8ff	2432	#define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /!< Forces an immediate transfer from the preload to the active register in the timer C /
bogdanm	0:9b334a45a8ff	2433	#define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /!< Forces an immediate transfer from the preload to the active register in the timer D /
bogdanm	0:9b334a45a8ff	2434	#define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /!< Forces an immediate transfer from the preload to the active register in the timer E /
bogdanm	0:9b334a45a8ff	2435
bogdanm	0:9b334a45a8ff	2436	#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0) == 0x00000000)
bogdanm	0:9b334a45a8ff	2437	/**
bogdanm	0:9b334a45a8ff	2438	* @}
bogdanm	0:9b334a45a8ff	2439	*/
bogdanm	0:9b334a45a8ff	2440
bogdanm	0:9b334a45a8ff	2441	/** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
bogdanm	0:9b334a45a8ff	2442	* @{
bogdanm	0:9b334a45a8ff	2443	* @brief Constants used to force timer counter reset
bogdanm	0:9b334a45a8ff	2444	*/
bogdanm	0:9b334a45a8ff	2445	#define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /!< Resets the master timer counter /
bogdanm	0:9b334a45a8ff	2446	#define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /!< Resets the timer A counter /
bogdanm	0:9b334a45a8ff	2447	#define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /!< Resets the timer B counter /
bogdanm	0:9b334a45a8ff	2448	#define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /!< Resets the timer C counter /
bogdanm	0:9b334a45a8ff	2449	#define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /!< Resets the timer D counter /
bogdanm	0:9b334a45a8ff	2450	#define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /!< Resets the timer E counter /
bogdanm	0:9b334a45a8ff	2451
bogdanm	0:9b334a45a8ff	2452	#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FF) == 0x00000000)
bogdanm	0:9b334a45a8ff	2453	/**
bogdanm	0:9b334a45a8ff	2454	* @}
bogdanm	0:9b334a45a8ff	2455	*/
bogdanm	0:9b334a45a8ff	2456
bogdanm	0:9b334a45a8ff	2457	/** @defgroup HRTIM_Output_Level HRTIM Output Level
bogdanm	0:9b334a45a8ff	2458	* @{
bogdanm	0:9b334a45a8ff	2459	* @brief Constants defining the level of a timer output
bogdanm	0:9b334a45a8ff	2460	*/
bogdanm	0:9b334a45a8ff	2461	#define HRTIM_OUTPUTLEVEL_ACTIVE (uint32_t)0x00000001 /!< Forces the output to its active state /
bogdanm	0:9b334a45a8ff	2462	#define HRTIM_OUTPUTLEVEL_INACTIVE (uint32_t)0x00000002 /!< Forces the output to its inactive state /
bogdanm	0:9b334a45a8ff	2463
bogdanm	0:9b334a45a8ff	2464	#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
bogdanm	0:9b334a45a8ff	2465	(((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) \|\| \
bogdanm	0:9b334a45a8ff	2466	((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
bogdanm	0:9b334a45a8ff	2467	/**
bogdanm	0:9b334a45a8ff	2468	* @}
bogdanm	0:9b334a45a8ff	2469	*/
bogdanm	0:9b334a45a8ff	2470
bogdanm	0:9b334a45a8ff	2471	/** @defgroup HRTIM_Output_State HRTIM Output State
bogdanm	0:9b334a45a8ff	2472	* @{
bogdanm	0:9b334a45a8ff	2473	* @brief Constants defining the state of a timer output
bogdanm	0:9b334a45a8ff	2474	*/
bogdanm	0:9b334a45a8ff	2475	#define HRTIM_OUTPUTSTATE_IDLE (uint32_t)0x00000001 /*!< Main operating mode, where the output can take the active or
bogdanm	0:9b334a45a8ff	2476	inactive level as programmed in the crossbar unit */
bogdanm	0:9b334a45a8ff	2477	#define HRTIM_OUTPUTSTATE_RUN (uint32_t)0x00000002 /*!< Default operating state (e.g. after an HRTIM reset, when the
bogdanm	0:9b334a45a8ff	2478	outputs are disabled by software or during a burst mode operation */
bogdanm	0:9b334a45a8ff	2479	#define HRTIM_OUTPUTSTATE_FAULT (uint32_t)0x00000003 /*!< Safety state, entered in case of a shut-down request on
bogdanm	0:9b334a45a8ff	2480	FAULTx inputs */
bogdanm	0:9b334a45a8ff	2481	/**
bogdanm	0:9b334a45a8ff	2482	* @}
bogdanm	0:9b334a45a8ff	2483	*/
bogdanm	0:9b334a45a8ff	2484
bogdanm	0:9b334a45a8ff	2485	/** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
bogdanm	0:9b334a45a8ff	2486	* @{
bogdanm	0:9b334a45a8ff	2487	* @brief Constants defining the operating state of the burst mode controller
bogdanm	0:9b334a45a8ff	2488	*/
bogdanm	0:9b334a45a8ff	2489	#define HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000 /!< Normal operation /
bogdanm	0:9b334a45a8ff	2490	#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /!< Burst operation on-going /
bogdanm	0:9b334a45a8ff	2491	/**
bogdanm	0:9b334a45a8ff	2492	* @}
bogdanm	0:9b334a45a8ff	2493	*/
bogdanm	0:9b334a45a8ff	2494
bogdanm	0:9b334a45a8ff	2495	/** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
bogdanm	0:9b334a45a8ff	2496	* @{
bogdanm	0:9b334a45a8ff	2497	* @brief Constants defining on which output the signal is currently applied
bogdanm	0:9b334a45a8ff	2498	* in push-pull mode
bogdanm	0:9b334a45a8ff	2499	*/
bogdanm	0:9b334a45a8ff	2500	#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000 /!< Signal applied on output 1 and output 2 forced inactive /
bogdanm	0:9b334a45a8ff	2501	#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /!< Signal applied on output 2 and output 1 forced inactive /
bogdanm	0:9b334a45a8ff	2502	/**
bogdanm	0:9b334a45a8ff	2503	* @}
bogdanm	0:9b334a45a8ff	2504	*/
bogdanm	0:9b334a45a8ff	2505
bogdanm	0:9b334a45a8ff	2506	/** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
bogdanm	0:9b334a45a8ff	2507	* @{
bogdanm	0:9b334a45a8ff	2508	* @brief Constants defining on which output the signal was applied, in
bogdanm	0:9b334a45a8ff	2509	* push-pull mode balanced fault mode or delayed idle mode, when the
bogdanm	0:9b334a45a8ff	2510	* protection was triggered
bogdanm	0:9b334a45a8ff	2511	*/
bogdanm	0:9b334a45a8ff	2512	#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000 /!< Protection occurred when the output 1 was active and output 2 forced inactive /
bogdanm	0:9b334a45a8ff	2513	#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /!< Protection occurred when the output 2 was active and output 1 forced inactive /
bogdanm	0:9b334a45a8ff	2514	/**
bogdanm	0:9b334a45a8ff	2515	* @}
bogdanm	0:9b334a45a8ff	2516	*/
bogdanm	0:9b334a45a8ff	2517
bogdanm	0:9b334a45a8ff	2518	/** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
bogdanm	0:9b334a45a8ff	2519	* @{
bogdanm	0:9b334a45a8ff	2520	*/
bogdanm	0:9b334a45a8ff	2521	#define HRTIM_IT_NONE (uint32_t)0x00000000 /!< No interrupt enabled /
bogdanm	0:9b334a45a8ff	2522	#define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /!< Fault 1 interrupt enable /
bogdanm	0:9b334a45a8ff	2523	#define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /!< Fault 2 interrupt enable /
bogdanm	0:9b334a45a8ff	2524	#define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /!< Fault 3 interrupt enable /
bogdanm	0:9b334a45a8ff	2525	#define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /!< Fault 4 interrupt enable /
bogdanm	0:9b334a45a8ff	2526	#define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /!< Fault 5 interrupt enable /
bogdanm	0:9b334a45a8ff	2527	#define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /!< System Fault interrupt enable /
bogdanm	0:9b334a45a8ff	2528	#define HRTIM_IT_DLLRDY HRTIM_IER_DLLRDY /!< DLL ready interrupt enable /
bogdanm	0:9b334a45a8ff	2529	#define HRTIM_IT_BMPER HRTIM_IER_BMPER /!< Burst mode period interrupt enable /
bogdanm	0:9b334a45a8ff	2530
bogdanm	0:9b334a45a8ff	2531	#define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0) == 0x00000000)
bogdanm	0:9b334a45a8ff	2532
bogdanm	0:9b334a45a8ff	2533	/**
bogdanm	0:9b334a45a8ff	2534	* @}
bogdanm	0:9b334a45a8ff	2535	*/
bogdanm	0:9b334a45a8ff	2536
bogdanm	0:9b334a45a8ff	2537	/** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
bogdanm	0:9b334a45a8ff	2538	* @{
bogdanm	0:9b334a45a8ff	2539	*/
bogdanm	0:9b334a45a8ff	2540	#define HRTIM_MASTER_IT_NONE (uint32_t)0x00000000 /!< No interrupt enabled /
bogdanm	0:9b334a45a8ff	2541	#define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /!< Master compare 1 interrupt enable /
bogdanm	0:9b334a45a8ff	2542	#define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /!< Master compare 2 interrupt enable /
bogdanm	0:9b334a45a8ff	2543	#define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /!< Master compare 3 interrupt enable /
bogdanm	0:9b334a45a8ff	2544	#define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /!< Master compare 4 interrupt enable /
bogdanm	0:9b334a45a8ff	2545	#define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /!< Master Repetition interrupt enable /
bogdanm	0:9b334a45a8ff	2546	#define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /!< Synchronization input interrupt enable /
bogdanm	0:9b334a45a8ff	2547	#define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /!< Master update interrupt enable /
bogdanm	0:9b334a45a8ff	2548
bogdanm	0:9b334a45a8ff	2549	#define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80) == 0x00000000)
bogdanm	0:9b334a45a8ff	2550
bogdanm	0:9b334a45a8ff	2551	/**
bogdanm	0:9b334a45a8ff	2552	* @}
bogdanm	0:9b334a45a8ff	2553	*/
bogdanm	0:9b334a45a8ff	2554
bogdanm	0:9b334a45a8ff	2555	/** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
bogdanm	0:9b334a45a8ff	2556	* @{
bogdanm	0:9b334a45a8ff	2557	*/
bogdanm	0:9b334a45a8ff	2558	#define HRTIM_TIM_IT_NONE (uint32_t)0x00000000 /!< No interrupt enabled /
bogdanm	0:9b334a45a8ff	2559	#define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /!< Timer compare 1 interrupt enable /
bogdanm	0:9b334a45a8ff	2560	#define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /!< Timer compare 2 interrupt enable /
bogdanm	0:9b334a45a8ff	2561	#define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /!< Timer compare 3 interrupt enable /
bogdanm	0:9b334a45a8ff	2562	#define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /!< Timer compare 4 interrupt enable /
bogdanm	0:9b334a45a8ff	2563	#define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /!< Timer repetition interrupt enable /
bogdanm	0:9b334a45a8ff	2564	#define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /!< Timer update interrupt enable /
bogdanm	0:9b334a45a8ff	2565	#define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /!< Timer capture 1 interrupt enable /
bogdanm	0:9b334a45a8ff	2566	#define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /!< Timer capture 2 interrupt enable /
bogdanm	0:9b334a45a8ff	2567	#define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /!< Timer output 1 set interrupt enable /
bogdanm	0:9b334a45a8ff	2568	#define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /!< Timer output 1 reset interrupt enable /
bogdanm	0:9b334a45a8ff	2569	#define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /!< Timer output 2 set interrupt enable /
bogdanm	0:9b334a45a8ff	2570	#define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /!< Timer output 2 reset interrupt enable /
bogdanm	0:9b334a45a8ff	2571	#define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /!< Timer reset interrupt enable /
bogdanm	0:9b334a45a8ff	2572	#define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /!< Timer delay protection interrupt enable /
bogdanm	0:9b334a45a8ff	2573
bogdanm	0:9b334a45a8ff	2574	#define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020) == 0x00000000)
bogdanm	0:9b334a45a8ff	2575
bogdanm	0:9b334a45a8ff	2576	/**
bogdanm	0:9b334a45a8ff	2577	* @}
bogdanm	0:9b334a45a8ff	2578	*/
bogdanm	0:9b334a45a8ff	2579
bogdanm	0:9b334a45a8ff	2580	/** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
bogdanm	0:9b334a45a8ff	2581	* @{
bogdanm	0:9b334a45a8ff	2582	*/
bogdanm	0:9b334a45a8ff	2583	#define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /!< Fault 1 interrupt flag /
bogdanm	0:9b334a45a8ff	2584	#define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /!< Fault 2 interrupt flag /
bogdanm	0:9b334a45a8ff	2585	#define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /!< Fault 3 interrupt flag /
bogdanm	0:9b334a45a8ff	2586	#define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /!< Fault 4 interrupt flag /
bogdanm	0:9b334a45a8ff	2587	#define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /!< Fault 5 interrupt flag /
bogdanm	0:9b334a45a8ff	2588	#define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /!< System Fault interrupt flag /
bogdanm	0:9b334a45a8ff	2589	#define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /!< DLL ready interrupt flag /
bogdanm	0:9b334a45a8ff	2590	#define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /!< Burst mode period interrupt flag /
bogdanm	0:9b334a45a8ff	2591
bogdanm	0:9b334a45a8ff	2592	/**
bogdanm	0:9b334a45a8ff	2593	* @}
bogdanm	0:9b334a45a8ff	2594	*/
bogdanm	0:9b334a45a8ff	2595
bogdanm	0:9b334a45a8ff	2596	/** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
bogdanm	0:9b334a45a8ff	2597	* @{
bogdanm	0:9b334a45a8ff	2598	*/
bogdanm	0:9b334a45a8ff	2599	#define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /!< Master compare 1 interrupt flag /
bogdanm	0:9b334a45a8ff	2600	#define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /!< Master compare 2 interrupt flag /
bogdanm	0:9b334a45a8ff	2601	#define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /!< Master compare 3 interrupt flag /
bogdanm	0:9b334a45a8ff	2602	#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /!< Master compare 4 interrupt flag /
bogdanm	0:9b334a45a8ff	2603	#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /!< Master Repetition interrupt flag /
bogdanm	0:9b334a45a8ff	2604	#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /!< Synchronization input interrupt flag /
bogdanm	0:9b334a45a8ff	2605	#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /!< Master update interrupt flag /
bogdanm	0:9b334a45a8ff	2606
bogdanm	0:9b334a45a8ff	2607	/**
bogdanm	0:9b334a45a8ff	2608	* @}
bogdanm	0:9b334a45a8ff	2609	*/
bogdanm	0:9b334a45a8ff	2610
bogdanm	0:9b334a45a8ff	2611	/** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
bogdanm	0:9b334a45a8ff	2612	* @{
bogdanm	0:9b334a45a8ff	2613	*/
bogdanm	0:9b334a45a8ff	2614	#define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /!< Timer compare 1 interrupt flag /
bogdanm	0:9b334a45a8ff	2615	#define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /!< Timer compare 2 interrupt flag /
bogdanm	0:9b334a45a8ff	2616	#define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /!< Timer compare 3 interrupt flag /
bogdanm	0:9b334a45a8ff	2617	#define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /!< Timer compare 4 interrupt flag /
bogdanm	0:9b334a45a8ff	2618	#define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /!< Timer repetition interrupt flag /
bogdanm	0:9b334a45a8ff	2619	#define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /!< Timer update interrupt flag /
bogdanm	0:9b334a45a8ff	2620	#define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /!< Timer capture 1 interrupt flag /
bogdanm	0:9b334a45a8ff	2621	#define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /!< Timer capture 2 interrupt flag /
bogdanm	0:9b334a45a8ff	2622	#define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /!< Timer output 1 set interrupt flag /
bogdanm	0:9b334a45a8ff	2623	#define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /!< Timer output 1 reset interrupt flag /
bogdanm	0:9b334a45a8ff	2624	#define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /!< Timer output 2 set interrupt flag /
bogdanm	0:9b334a45a8ff	2625	#define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /!< Timer output 2 reset interrupt flag /
bogdanm	0:9b334a45a8ff	2626	#define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /!< Timer reset interrupt flag /
bogdanm	0:9b334a45a8ff	2627	#define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /!< Timer delay protection interrupt flag /
bogdanm	0:9b334a45a8ff	2628
bogdanm	0:9b334a45a8ff	2629	/**
bogdanm	0:9b334a45a8ff	2630	* @}
bogdanm	0:9b334a45a8ff	2631	*/
bogdanm	0:9b334a45a8ff	2632
bogdanm	0:9b334a45a8ff	2633	/** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
bogdanm	0:9b334a45a8ff	2634	* @{
bogdanm	0:9b334a45a8ff	2635	*/
bogdanm	0:9b334a45a8ff	2636	#define HRTIM_MASTER_DMA_NONE (uint32_t)0x00000000 /!< No DMA request enable /
bogdanm	0:9b334a45a8ff	2637	#define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /!< Master compare 1 DMA request enable /
bogdanm	0:9b334a45a8ff	2638	#define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /!< Master compare 2 DMA request enable /
bogdanm	0:9b334a45a8ff	2639	#define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /!< Master compare 3 DMA request enable /
bogdanm	0:9b334a45a8ff	2640	#define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /!< Master compare 4 DMA request enable /
bogdanm	0:9b334a45a8ff	2641	#define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /!< Master Repetition DMA request enable /
bogdanm	0:9b334a45a8ff	2642	#define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /!< Synchronization input DMA request enable /
bogdanm	0:9b334a45a8ff	2643	#define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /!< Master update DMA request enable /
bogdanm	0:9b334a45a8ff	2644
bogdanm	0:9b334a45a8ff	2645	#define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFF) == 0x00000000)
bogdanm	0:9b334a45a8ff	2646	/**
bogdanm	0:9b334a45a8ff	2647	* @}
bogdanm	0:9b334a45a8ff	2648	*/
bogdanm	0:9b334a45a8ff	2649
bogdanm	0:9b334a45a8ff	2650	/** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
bogdanm	0:9b334a45a8ff	2651	* @{
bogdanm	0:9b334a45a8ff	2652	*/
bogdanm	0:9b334a45a8ff	2653	#define HRTIM_TIM_DMA_NONE (uint32_t)0x00000000 /!< No DMA request enable /
bogdanm	0:9b334a45a8ff	2654	#define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /!< Timer compare 1 DMA request enable /
bogdanm	0:9b334a45a8ff	2655	#define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /!< Timer compare 2 DMA request enable /
bogdanm	0:9b334a45a8ff	2656	#define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /!< Timer compare 3 DMA request enable /
bogdanm	0:9b334a45a8ff	2657	#define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /!< Timer compare 4 DMA request enable /
bogdanm	0:9b334a45a8ff	2658	#define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /!< Timer repetition DMA request enable /
bogdanm	0:9b334a45a8ff	2659	#define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /!< Timer update DMA request enable /
bogdanm	0:9b334a45a8ff	2660	#define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /!< Timer capture 1 DMA request enable /
bogdanm	0:9b334a45a8ff	2661	#define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /!< Timer capture 2 DMA request enable /
bogdanm	0:9b334a45a8ff	2662	#define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /!< Timer output 1 set DMA request enable /
bogdanm	0:9b334a45a8ff	2663	#define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /!< Timer output 1 reset DMA request enable /
bogdanm	0:9b334a45a8ff	2664	#define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /!< Timer output 2 set DMA request enable /
bogdanm	0:9b334a45a8ff	2665	#define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /!< Timer output 2 reset DMA request enable /
bogdanm	0:9b334a45a8ff	2666	#define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /!< Timer reset DMA request enable /
bogdanm	0:9b334a45a8ff	2667	#define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /!< Timer delay protection DMA request enable /
bogdanm	0:9b334a45a8ff	2668
bogdanm	0:9b334a45a8ff	2669	#define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFF) == 0x00000000)
bogdanm	0:9b334a45a8ff	2670
bogdanm	0:9b334a45a8ff	2671	/**
bogdanm	0:9b334a45a8ff	2672	* @}
bogdanm	0:9b334a45a8ff	2673	*/
bogdanm	0:9b334a45a8ff	2674
bogdanm	0:9b334a45a8ff	2675	/**
bogdanm	0:9b334a45a8ff	2676	* @}
bogdanm	0:9b334a45a8ff	2677	*/
bogdanm	0:9b334a45a8ff	2678
bogdanm	0:9b334a45a8ff	2679	/* Exported macros -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2680	/** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
bogdanm	0:9b334a45a8ff	2681	* @{
bogdanm	0:9b334a45a8ff	2682	*/
bogdanm	0:9b334a45a8ff	2683
bogdanm	0:9b334a45a8ff	2684	/** @brief Reset HRTIM handle state
bogdanm	0:9b334a45a8ff	2685	* @param __HANDLE__: HRTIM handle.
bogdanm	0:9b334a45a8ff	2686	* @retval None
bogdanm	0:9b334a45a8ff	2687	*/
bogdanm	0:9b334a45a8ff	2688	#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
bogdanm	0:9b334a45a8ff	2689
bogdanm	0:9b334a45a8ff	2690	/** @brief Enables or disables the timer counter(s)
bogdanm	0:9b334a45a8ff	2691	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2692	* @param __TIMERS__: timersto enable/disable
bogdanm	0:9b334a45a8ff	2693	* This parameter can be any combinations of the following values:
bogdanm	0:9b334a45a8ff	2694	* @arg HRTIM_TIMERID_MASTER: Master timer identifier
bogdanm	0:9b334a45a8ff	2695	* @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
bogdanm	0:9b334a45a8ff	2696	* @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
bogdanm	0:9b334a45a8ff	2697	* @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
bogdanm	0:9b334a45a8ff	2698	* @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
bogdanm	0:9b334a45a8ff	2699	* @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
bogdanm	0:9b334a45a8ff	2700	* @retval None
bogdanm	0:9b334a45a8ff	2701	*/
bogdanm	0:9b334a45a8ff	2702	#define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR \|= (__TIMERS__))
bogdanm	0:9b334a45a8ff	2703
bogdanm	0:9b334a45a8ff	2704	/* The counter of a timing unit is disabled only if all the timer outputs */
bogdanm	0:9b334a45a8ff	2705	/* are disabled and no capture is configured */
bogdanm	0:9b334a45a8ff	2706	#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN \| HRTIM_OENR_TA1OEN)
bogdanm	0:9b334a45a8ff	2707	#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN \| HRTIM_OENR_TB1OEN)
bogdanm	0:9b334a45a8ff	2708	#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN \| HRTIM_OENR_TC1OEN)
bogdanm	0:9b334a45a8ff	2709	#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN \| HRTIM_OENR_TD1OEN)
bogdanm	0:9b334a45a8ff	2710	#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN \| HRTIM_OENR_TE1OEN)
bogdanm	0:9b334a45a8ff	2711	#define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
bogdanm	0:9b334a45a8ff	2712	do {\
bogdanm	0:9b334a45a8ff	2713	if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
bogdanm	0:9b334a45a8ff	2714	{\
bogdanm	0:9b334a45a8ff	2715	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
bogdanm	0:9b334a45a8ff	2716	}\
bogdanm	0:9b334a45a8ff	2717	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
bogdanm	0:9b334a45a8ff	2718	{\
bogdanm	0:9b334a45a8ff	2719	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == RESET)\
bogdanm	0:9b334a45a8ff	2720	{\
bogdanm	0:9b334a45a8ff	2721	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
bogdanm	0:9b334a45a8ff	2722	}\
bogdanm	0:9b334a45a8ff	2723	}\
bogdanm	0:9b334a45a8ff	2724	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
bogdanm	0:9b334a45a8ff	2725	{\
bogdanm	0:9b334a45a8ff	2726	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == RESET)\
bogdanm	0:9b334a45a8ff	2727	{\
bogdanm	0:9b334a45a8ff	2728	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
bogdanm	0:9b334a45a8ff	2729	}\
bogdanm	0:9b334a45a8ff	2730	}\
bogdanm	0:9b334a45a8ff	2731	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
bogdanm	0:9b334a45a8ff	2732	{\
bogdanm	0:9b334a45a8ff	2733	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == RESET)\
bogdanm	0:9b334a45a8ff	2734	{\
bogdanm	0:9b334a45a8ff	2735	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
bogdanm	0:9b334a45a8ff	2736	}\
bogdanm	0:9b334a45a8ff	2737	}\
bogdanm	0:9b334a45a8ff	2738	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
bogdanm	0:9b334a45a8ff	2739	{\
bogdanm	0:9b334a45a8ff	2740	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == RESET)\
bogdanm	0:9b334a45a8ff	2741	{\
bogdanm	0:9b334a45a8ff	2742	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
bogdanm	0:9b334a45a8ff	2743	}\
bogdanm	0:9b334a45a8ff	2744	}\
bogdanm	0:9b334a45a8ff	2745	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
bogdanm	0:9b334a45a8ff	2746	{\
bogdanm	0:9b334a45a8ff	2747	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == RESET)\
bogdanm	0:9b334a45a8ff	2748	{\
bogdanm	0:9b334a45a8ff	2749	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
bogdanm	0:9b334a45a8ff	2750	}\
bogdanm	0:9b334a45a8ff	2751	}\
bogdanm	0:9b334a45a8ff	2752	} while(0)
bogdanm	0:9b334a45a8ff	2753
bogdanm	0:9b334a45a8ff	2754	/** @brief Enables or disables the specified HRTIM common interrupts.
bogdanm	0:9b334a45a8ff	2755	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2756	* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm	0:9b334a45a8ff	2757	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2758	* @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
bogdanm	0:9b334a45a8ff	2759	* @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
bogdanm	0:9b334a45a8ff	2760	* @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
bogdanm	0:9b334a45a8ff	2761	* @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
bogdanm	0:9b334a45a8ff	2762	* @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
bogdanm	0:9b334a45a8ff	2763	* @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
bogdanm	0:9b334a45a8ff	2764	* @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
bogdanm	0:9b334a45a8ff	2765	* @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
bogdanm	0:9b334a45a8ff	2766	* @retval None
bogdanm	0:9b334a45a8ff	2767	*/
bogdanm	0:9b334a45a8ff	2768	#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2769	#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2770
bogdanm	0:9b334a45a8ff	2771	/** @brief Enables or disables the specified HRTIM Master timer interrupts.
bogdanm	0:9b334a45a8ff	2772	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2773	* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm	0:9b334a45a8ff	2774	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2775	* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
bogdanm	0:9b334a45a8ff	2776	* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
bogdanm	0:9b334a45a8ff	2777	* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
bogdanm	0:9b334a45a8ff	2778	* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
bogdanm	0:9b334a45a8ff	2779	* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
bogdanm	0:9b334a45a8ff	2780	* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
bogdanm	0:9b334a45a8ff	2781	* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
bogdanm	0:9b334a45a8ff	2782	* @retval None
bogdanm	0:9b334a45a8ff	2783	*/
bogdanm	0:9b334a45a8ff	2784	#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2785	#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2786
bogdanm	0:9b334a45a8ff	2787	/** @brief Enables or disables the specified HRTIM Timerx interrupts.
bogdanm	0:9b334a45a8ff	2788	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2789	* @param __TIMER__: specified the timing unit (Timer A to E)
bogdanm	0:9b334a45a8ff	2790	* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm	0:9b334a45a8ff	2791	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2792	* @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
bogdanm	0:9b334a45a8ff	2793	* @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
bogdanm	0:9b334a45a8ff	2794	* @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
bogdanm	0:9b334a45a8ff	2795	* @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
bogdanm	0:9b334a45a8ff	2796	* @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
bogdanm	0:9b334a45a8ff	2797	* @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
bogdanm	0:9b334a45a8ff	2798	* @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
bogdanm	0:9b334a45a8ff	2799	* @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
bogdanm	0:9b334a45a8ff	2800	* @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
bogdanm	0:9b334a45a8ff	2801	* @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
bogdanm	0:9b334a45a8ff	2802	* @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
bogdanm	0:9b334a45a8ff	2803	* @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
bogdanm	0:9b334a45a8ff	2804	* @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
bogdanm	0:9b334a45a8ff	2805	* @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
bogdanm	0:9b334a45a8ff	2806	* @retval None
bogdanm	0:9b334a45a8ff	2807	*/
bogdanm	0:9b334a45a8ff	2808	#define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2809	#define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2810
bogdanm	0:9b334a45a8ff	2811	/** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled.
bogdanm	0:9b334a45a8ff	2812	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2813	* @param __INTERRUPT__: specifies the interrupt source to check.
bogdanm	0:9b334a45a8ff	2814	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2815	* @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
bogdanm	0:9b334a45a8ff	2816	* @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
bogdanm	0:9b334a45a8ff	2817	* @arg HRTIM_IT_FLT3: Fault 3 enable
bogdanm	0:9b334a45a8ff	2818	* @arg HRTIM_IT_FLT4: Fault 4 enable
bogdanm	0:9b334a45a8ff	2819	* @arg HRTIM_IT_FLT5: Fault 5 enable
bogdanm	0:9b334a45a8ff	2820	* @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
bogdanm	0:9b334a45a8ff	2821	* @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
bogdanm	0:9b334a45a8ff	2822	* @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
bogdanm	0:9b334a45a8ff	2823	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	2824	*/
bogdanm	0:9b334a45a8ff	2825	#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	0:9b334a45a8ff	2826
bogdanm	0:9b334a45a8ff	2827	/** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled.
bogdanm	0:9b334a45a8ff	2828	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2829	* @param __INTERRUPT__: specifies the interrupt source to check.
bogdanm	0:9b334a45a8ff	2830	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2831	* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
bogdanm	0:9b334a45a8ff	2832	* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
bogdanm	0:9b334a45a8ff	2833	* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
bogdanm	0:9b334a45a8ff	2834	* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
bogdanm	0:9b334a45a8ff	2835	* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
bogdanm	0:9b334a45a8ff	2836	* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
bogdanm	0:9b334a45a8ff	2837	* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
bogdanm	0:9b334a45a8ff	2838	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	2839	*/
bogdanm	0:9b334a45a8ff	2840	#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	0:9b334a45a8ff	2841
bogdanm	0:9b334a45a8ff	2842	/** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
bogdanm	0:9b334a45a8ff	2843	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2844	* @param __TIMER__: specified the timing unit (Timer A to E)
bogdanm	0:9b334a45a8ff	2845	* @param __INTERRUPT__: specifies the interrupt source to check.
bogdanm	0:9b334a45a8ff	2846	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2847	* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
bogdanm	0:9b334a45a8ff	2848	* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
bogdanm	0:9b334a45a8ff	2849	* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
bogdanm	0:9b334a45a8ff	2850	* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
bogdanm	0:9b334a45a8ff	2851	* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
bogdanm	0:9b334a45a8ff	2852	* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
bogdanm	0:9b334a45a8ff	2853	* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
bogdanm	0:9b334a45a8ff	2854	* @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
bogdanm	0:9b334a45a8ff	2855	* @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
bogdanm	0:9b334a45a8ff	2856	* @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
bogdanm	0:9b334a45a8ff	2857	* @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
bogdanm	0:9b334a45a8ff	2858	* @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
bogdanm	0:9b334a45a8ff	2859	* @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
bogdanm	0:9b334a45a8ff	2860	* @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
bogdanm	0:9b334a45a8ff	2861	* @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
bogdanm	0:9b334a45a8ff	2862	* @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
bogdanm	0:9b334a45a8ff	2863	* @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
bogdanm	0:9b334a45a8ff	2864	* @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
bogdanm	0:9b334a45a8ff	2865	* @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
bogdanm	0:9b334a45a8ff	2866	* @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
bogdanm	0:9b334a45a8ff	2867	* @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
bogdanm	0:9b334a45a8ff	2868	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	2869	*/
bogdanm	0:9b334a45a8ff	2870	#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	0:9b334a45a8ff	2871
bogdanm	0:9b334a45a8ff	2872	/** @brief Clears the specified HRTIM common pending flag.
bogdanm	0:9b334a45a8ff	2873	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2874	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	2875	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2876	* @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
bogdanm	0:9b334a45a8ff	2877	* @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
bogdanm	0:9b334a45a8ff	2878	* @arg HRTIM_IT_FLT3: Fault 3 clear flag
bogdanm	0:9b334a45a8ff	2879	* @arg HRTIM_IT_FLT4: Fault 4 clear flag
bogdanm	0:9b334a45a8ff	2880	* @arg HRTIM_IT_FLT5: Fault 5 clear flag
bogdanm	0:9b334a45a8ff	2881	* @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
bogdanm	0:9b334a45a8ff	2882	* @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
bogdanm	0:9b334a45a8ff	2883	* @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
bogdanm	0:9b334a45a8ff	2884	* @retval None
bogdanm	0:9b334a45a8ff	2885	*/
bogdanm	0:9b334a45a8ff	2886	#define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2887
bogdanm	0:9b334a45a8ff	2888	/** @brief Clears the specified HRTIM Master pending flag.
bogdanm	0:9b334a45a8ff	2889	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2890	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	2891	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2892	* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
bogdanm	0:9b334a45a8ff	2893	* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
bogdanm	0:9b334a45a8ff	2894	* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
bogdanm	0:9b334a45a8ff	2895	* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
bogdanm	0:9b334a45a8ff	2896	* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
bogdanm	0:9b334a45a8ff	2897	* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
bogdanm	0:9b334a45a8ff	2898	* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
bogdanm	0:9b334a45a8ff	2899	* @retval None
bogdanm	0:9b334a45a8ff	2900	*/
bogdanm	0:9b334a45a8ff	2901	#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2902
bogdanm	0:9b334a45a8ff	2903	/** @brief Clears the specified HRTIM Timerx pending flag.
bogdanm	0:9b334a45a8ff	2904	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2905	* @param __TIMER__: specified the timing unit (Timer A to E)
bogdanm	0:9b334a45a8ff	2906	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	2907	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2908	* @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
bogdanm	0:9b334a45a8ff	2909	* @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
bogdanm	0:9b334a45a8ff	2910	* @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
bogdanm	0:9b334a45a8ff	2911	* @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
bogdanm	0:9b334a45a8ff	2912	* @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
bogdanm	0:9b334a45a8ff	2913	* @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
bogdanm	0:9b334a45a8ff	2914	* @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
bogdanm	0:9b334a45a8ff	2915	* @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
bogdanm	0:9b334a45a8ff	2916	* @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
bogdanm	0:9b334a45a8ff	2917	* @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
bogdanm	0:9b334a45a8ff	2918	* @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
bogdanm	0:9b334a45a8ff	2919	* @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
bogdanm	0:9b334a45a8ff	2920	* @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
bogdanm	0:9b334a45a8ff	2921	* @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
bogdanm	0:9b334a45a8ff	2922	* @retval None
bogdanm	0:9b334a45a8ff	2923	*/
bogdanm	0:9b334a45a8ff	2924	#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2925
bogdanm	0:9b334a45a8ff	2926	/* DMA HANDLING */
bogdanm	0:9b334a45a8ff	2927	/** @brief Enables or disables the specified HRTIM common interrupts.
bogdanm	0:9b334a45a8ff	2928	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2929	* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm	0:9b334a45a8ff	2930	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2931	* @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
bogdanm	0:9b334a45a8ff	2932	* @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
bogdanm	0:9b334a45a8ff	2933	* @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
bogdanm	0:9b334a45a8ff	2934	* @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
bogdanm	0:9b334a45a8ff	2935	* @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
bogdanm	0:9b334a45a8ff	2936	* @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
bogdanm	0:9b334a45a8ff	2937	* @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
bogdanm	0:9b334a45a8ff	2938	* @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
bogdanm	0:9b334a45a8ff	2939	* @retval None
bogdanm	0:9b334a45a8ff	2940	*/
bogdanm	0:9b334a45a8ff	2941	#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2942	#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2943
bogdanm	0:9b334a45a8ff	2944	/** @brief Enables or disables the specified HRTIM Master timer DMA requets.
bogdanm	0:9b334a45a8ff	2945	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2946	* @param __DMA__: specifies the DMA request to enable or disable.
bogdanm	0:9b334a45a8ff	2947	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2948	* @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
bogdanm	0:9b334a45a8ff	2949	* @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
bogdanm	0:9b334a45a8ff	2950	* @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
bogdanm	0:9b334a45a8ff	2951	* @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
bogdanm	0:9b334a45a8ff	2952	* @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
bogdanm	0:9b334a45a8ff	2953	* @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
bogdanm	0:9b334a45a8ff	2954	* @arg HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
bogdanm	0:9b334a45a8ff	2955	* @retval None
bogdanm	0:9b334a45a8ff	2956	*/
bogdanm	0:9b334a45a8ff	2957	#define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \|= (__DMA__))
bogdanm	0:9b334a45a8ff	2958	#define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
bogdanm	0:9b334a45a8ff	2959
bogdanm	0:9b334a45a8ff	2960	/** @brief Enables or disables the specified HRTIM Timerx DMA requests.
bogdanm	0:9b334a45a8ff	2961	* @param __HANDLE__: specifies the HRTIM Handle.
bogdanm	0:9b334a45a8ff	2962	* @param __TIMER__: specified the timing unit (Timer A to E)
bogdanm	0:9b334a45a8ff	2963	* @param __DMA__: specifies the DMA request to enable or disable.
bogdanm	0:9b334a45a8ff	2964	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2965	* @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
bogdanm	0:9b334a45a8ff	2966	* @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
bogdanm	0:9b334a45a8ff	2967	* @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
bogdanm	0:9b334a45a8ff	2968	* @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
bogdanm	0:9b334a45a8ff	2969	* @arg HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
bogdanm	0:9b334a45a8ff	2970	* @arg HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
bogdanm	0:9b334a45a8ff	2971	* @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
bogdanm	0:9b334a45a8ff	2972	* @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
bogdanm	0:9b334a45a8ff	2973	* @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
bogdanm	0:9b334a45a8ff	2974	* @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
bogdanm	0:9b334a45a8ff	2975	* @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
bogdanm	0:9b334a45a8ff	2976	* @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
bogdanm	0:9b334a45a8ff	2977	* @arg HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
bogdanm	0:9b334a45a8ff	2978	* @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
bogdanm	0:9b334a45a8ff	2979	* @retval None
bogdanm	0:9b334a45a8ff	2980	*/
bogdanm	0:9b334a45a8ff	2981	#define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER \|= (__DMA__))
bogdanm	0:9b334a45a8ff	2982	#define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
bogdanm	0:9b334a45a8ff	2983
bogdanm	0:9b334a45a8ff	2984	#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	2985	#define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
bogdanm	0:9b334a45a8ff	2986
bogdanm	0:9b334a45a8ff	2987	#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	2988	#define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
bogdanm	0:9b334a45a8ff	2989
bogdanm	0:9b334a45a8ff	2990	#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	2991	#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
bogdanm	0:9b334a45a8ff	2992
bogdanm	0:9b334a45a8ff	2993	/** @brief Sets the HRTIM timer Counter Register value on runtime
bogdanm	0:9b334a45a8ff	2994	* @param __HANDLE__: HRTIM Handle.
bogdanm	0:9b334a45a8ff	2995	* @param __TIMER__: HRTIM timer
bogdanm	0:9b334a45a8ff	2996	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2997	* @arg 0x5 for master timer
bogdanm	0:9b334a45a8ff	2998	* @arg 0x0 to 0x4 for timers A to E
bogdanm	0:9b334a45a8ff	2999	* @param __COUNTER__: specifies the Counter Register new value.
bogdanm	0:9b334a45a8ff	3000	* @retval None
bogdanm	0:9b334a45a8ff	3001	*/
bogdanm	0:9b334a45a8ff	3002	#define __HAL_HRTIM_SetCounter(__HANDLE__, __TIMER__, __COUNTER__) \
bogdanm	0:9b334a45a8ff	3003	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
bogdanm	0:9b334a45a8ff	3004	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
bogdanm	0:9b334a45a8ff	3005
bogdanm	0:9b334a45a8ff	3006	/** @brief Gets the HRTIM timer Counter Register value on runtime
bogdanm	0:9b334a45a8ff	3007	* @param __HANDLE__: HRTIM Handle.
bogdanm	0:9b334a45a8ff	3008	* @param __TIMER__: HRTIM timer
bogdanm	0:9b334a45a8ff	3009	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3010	* @arg 0x5 for master timer
bogdanm	0:9b334a45a8ff	3011	* @arg 0x0 to 0x4 for timers A to E
bogdanm	0:9b334a45a8ff	3012	* @retval HRTIM timer Counter Register value
bogdanm	0:9b334a45a8ff	3013	*/
bogdanm	0:9b334a45a8ff	3014	#define __HAL_HRTIM_GetCounter(__HANDLE__, __TIMER__) \
bogdanm	0:9b334a45a8ff	3015	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
bogdanm	0:9b334a45a8ff	3016	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
bogdanm	0:9b334a45a8ff	3017
bogdanm	0:9b334a45a8ff	3018	/** @brief Sets the HRTIM timer Period value on runtime
bogdanm	0:9b334a45a8ff	3019	* @param __HANDLE__: HRTIM Handle.
bogdanm	0:9b334a45a8ff	3020	* @param __TIMER__: HRTIM timer
bogdanm	0:9b334a45a8ff	3021	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3022	* @arg 0x5 for master timer
bogdanm	0:9b334a45a8ff	3023	* @arg 0x0 to 0x4 for timers A to E
bogdanm	0:9b334a45a8ff	3024	* @param __PERIOD__: specifies the Period Register new value.
bogdanm	0:9b334a45a8ff	3025	* @retval None
bogdanm	0:9b334a45a8ff	3026	*/
bogdanm	0:9b334a45a8ff	3027	#define __HAL_HRTIM_SetPeriod(__HANDLE__, __TIMER__, __PERIOD__) \
bogdanm	0:9b334a45a8ff	3028	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
bogdanm	0:9b334a45a8ff	3029	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
bogdanm	0:9b334a45a8ff	3030
bogdanm	0:9b334a45a8ff	3031	/** @brief Gets the HRTIM timer Period Register value on runtime
bogdanm	0:9b334a45a8ff	3032	* @param __HANDLE__: HRTIM Handle.
bogdanm	0:9b334a45a8ff	3033	* @param __TIMER__: HRTIM timer
bogdanm	0:9b334a45a8ff	3034	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3035	* @arg 0x5 for master timer
bogdanm	0:9b334a45a8ff	3036	* @arg 0x0 to 0x4 for timers A to E
bogdanm	0:9b334a45a8ff	3037	* @retval timer Period Register
bogdanm	0:9b334a45a8ff	3038	*/
bogdanm	0:9b334a45a8ff	3039	#define __HAL_HRTIM_GetPeriod(__HANDLE__, __TIMER__) \
bogdanm	0:9b334a45a8ff	3040	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
bogdanm	0:9b334a45a8ff	3041	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
bogdanm	0:9b334a45a8ff	3042
bogdanm	0:9b334a45a8ff	3043	/** @brief Sets the HRTIM timer clock prescaler value on runtime
bogdanm	0:9b334a45a8ff	3044	* @param __HANDLE__: HRTIM Handle.
bogdanm	0:9b334a45a8ff	3045	* @param __TIMER__: HRTIM timer
bogdanm	0:9b334a45a8ff	3046	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3047	* @arg 0x5 for master timer
bogdanm	0:9b334a45a8ff	3048	* @arg 0x0 to 0x4 for timers A to E
bogdanm	0:9b334a45a8ff	3049	* @param __PRESCALER__: specifies the clock prescaler new value.
bogdanm	0:9b334a45a8ff	3050	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3051	* @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
bogdanm	0:9b334a45a8ff	3052	* @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
bogdanm	0:9b334a45a8ff	3053	* @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
bogdanm	0:9b334a45a8ff	3054	* @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
bogdanm	0:9b334a45a8ff	3055	* @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
bogdanm	0:9b334a45a8ff	3056	* @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
bogdanm	0:9b334a45a8ff	3057	* @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
bogdanm	0:9b334a45a8ff	3058	* @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
bogdanm	0:9b334a45a8ff	3059	* @retval None
bogdanm	0:9b334a45a8ff	3060	*/
bogdanm	0:9b334a45a8ff	3061	#define __HAL_HRTIM_SetClockPrescaler(__HANDLE__, __TIMER__, __PRESCALER__) \
bogdanm	0:9b334a45a8ff	3062	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR \|= (__PRESCALER__)) :\
bogdanm	0:9b334a45a8ff	3063	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR \|= (__PRESCALER__)))
bogdanm	0:9b334a45a8ff	3064
bogdanm	0:9b334a45a8ff	3065	/** @brief Gets the HRTIM timer clock prescaler value on runtime
bogdanm	0:9b334a45a8ff	3066	* @param __HANDLE__: HRTIM Handle.
bogdanm	0:9b334a45a8ff	3067	* @param __TIMER__: HRTIM timer
bogdanm	0:9b334a45a8ff	3068	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3069	* @arg 0x5 for master timer
bogdanm	0:9b334a45a8ff	3070	* @arg 0x0 to 0x4 for timers A to E
bogdanm	0:9b334a45a8ff	3071	* @retval timer clock prescaler value
bogdanm	0:9b334a45a8ff	3072	*/
bogdanm	0:9b334a45a8ff	3073	#define __HAL_HRTIM_GetClockPrescaler(__HANDLE__, __TIMER__) \
bogdanm	0:9b334a45a8ff	3074	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
bogdanm	0:9b334a45a8ff	3075	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC))
bogdanm	0:9b334a45a8ff	3076
bogdanm	0:9b334a45a8ff	3077	/** @brief Sets the HRTIM timer Compare Register value on runtime
bogdanm	0:9b334a45a8ff	3078	* @param __HANDLE__: HRTIM Handle.
bogdanm	0:9b334a45a8ff	3079	* @param __TIMER__: HRTIM timer
bogdanm	0:9b334a45a8ff	3080	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3081	* @arg 0x0 to 0x4 for timers A to E
bogdanm	0:9b334a45a8ff	3082	* @param __COMPAREUNIT__: timer compare unit
bogdanm	0:9b334a45a8ff	3083	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3084	* @arg HRTIM_COMPAREUNIT_1: Compare unit 1
bogdanm	0:9b334a45a8ff	3085	* @arg HRTIM_COMPAREUNIT_2: Compare unit 2
bogdanm	0:9b334a45a8ff	3086	* @arg HRTIM_COMPAREUNIT_3: Compare unit 3
bogdanm	0:9b334a45a8ff	3087	* @arg HRTIM_COMPAREUNIT_4: Compare unit 4
bogdanm	0:9b334a45a8ff	3088	* @param __COMPARE__: specifies the Compare new value.
bogdanm	0:9b334a45a8ff	3089	* @retval None
bogdanm	0:9b334a45a8ff	3090	*/
bogdanm	0:9b334a45a8ff	3091	#define __HAL_HRTIM_SetCompare(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
bogdanm	0:9b334a45a8ff	3092	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
bogdanm	0:9b334a45a8ff	3093	(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	3094	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	3095	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	3096	((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
bogdanm	0:9b334a45a8ff	3097	: \
bogdanm	0:9b334a45a8ff	3098	(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	3099	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	3100	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
bogdanm	0:9b334a45a8ff	3101	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
bogdanm	0:9b334a45a8ff	3102
bogdanm	0:9b334a45a8ff	3103	/** @brief Gets the HRTIM timer Compare Register value on runtime
bogdanm	0:9b334a45a8ff	3104	* @param __HANDLE__: HRTIM Handle.
bogdanm	0:9b334a45a8ff	3105	* @param __TIMER__: HRTIM timer
bogdanm	0:9b334a45a8ff	3106	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3107	* @arg 0x0 to 0x4 for timers A to E
bogdanm	0:9b334a45a8ff	3108	* @param __COMPAREUNIT__: timer compare unit
bogdanm	0:9b334a45a8ff	3109	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	3110	* @arg HRTIM_COMPAREUNIT_1: Compare unit 1
bogdanm	0:9b334a45a8ff	3111	* @arg HRTIM_COMPAREUNIT_2: Compare unit 2
bogdanm	0:9b334a45a8ff	3112	* @arg HRTIM_COMPAREUNIT_3: Compare unit 3
bogdanm	0:9b334a45a8ff	3113	* @arg HRTIM_COMPAREUNIT_4: Compare unit 4
bogdanm	0:9b334a45a8ff	3114	* @retval Compare value
bogdanm	0:9b334a45a8ff	3115	*/
bogdanm	0:9b334a45a8ff	3116	#define __HAL_HRTIM_GetCompare(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
bogdanm	0:9b334a45a8ff	3117	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
bogdanm	0:9b334a45a8ff	3118	(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
bogdanm	0:9b334a45a8ff	3119	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
bogdanm	0:9b334a45a8ff	3120	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
bogdanm	0:9b334a45a8ff	3121	((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
bogdanm	0:9b334a45a8ff	3122	: \
bogdanm	0:9b334a45a8ff	3123	(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
bogdanm	0:9b334a45a8ff	3124	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
bogdanm	0:9b334a45a8ff	3125	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
bogdanm	0:9b334a45a8ff	3126	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
bogdanm	0:9b334a45a8ff	3127
bogdanm	0:9b334a45a8ff	3128	/**
bogdanm	0:9b334a45a8ff	3129	* @}
bogdanm	0:9b334a45a8ff	3130	*/
bogdanm	0:9b334a45a8ff	3131
bogdanm	0:9b334a45a8ff	3132	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	3133	/** @addtogroup HRTIM_Exported_Functions HRTIM Exported Functions
bogdanm	0:9b334a45a8ff	3134	* @{
bogdanm	0:9b334a45a8ff	3135	*/
bogdanm	0:9b334a45a8ff	3136
bogdanm	0:9b334a45a8ff	3137	/** @addtogroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	3138	* @{
bogdanm	0:9b334a45a8ff	3139	*/
bogdanm	0:9b334a45a8ff	3140
bogdanm	0:9b334a45a8ff	3141	/* Initialization and Configuration functions ********************************/
bogdanm	0:9b334a45a8ff	3142	HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3143
bogdanm	0:9b334a45a8ff	3144	HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3145
bogdanm	0:9b334a45a8ff	3146	void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3147
bogdanm	0:9b334a45a8ff	3148	void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3149
bogdanm	0:9b334a45a8ff	3150	HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3151	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3152	HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
bogdanm	0:9b334a45a8ff	3153
bogdanm	0:9b334a45a8ff	3154	HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3155	uint32_t CalibrationRate);
bogdanm	0:9b334a45a8ff	3156
bogdanm	0:9b334a45a8ff	3157	HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3158	uint32_t CalibrationRate);
bogdanm	0:9b334a45a8ff	3159
bogdanm	0:9b334a45a8ff	3160	HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3161	uint32_t Timeout);
bogdanm	0:9b334a45a8ff	3162
bogdanm	0:9b334a45a8ff	3163	/**
bogdanm	0:9b334a45a8ff	3164	* @}
bogdanm	0:9b334a45a8ff	3165	*/
bogdanm	0:9b334a45a8ff	3166
bogdanm	0:9b334a45a8ff	3167	/** @addtogroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
bogdanm	0:9b334a45a8ff	3168	* @{
bogdanm	0:9b334a45a8ff	3169	*/
bogdanm	0:9b334a45a8ff	3170
bogdanm	0:9b334a45a8ff	3171	/* Simple time base related functions *****************************************/
bogdanm	0:9b334a45a8ff	3172	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3173	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3174
bogdanm	0:9b334a45a8ff	3175	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3176	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3177
bogdanm	0:9b334a45a8ff	3178	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3179	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3180
bogdanm	0:9b334a45a8ff	3181	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3182	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3183
bogdanm	0:9b334a45a8ff	3184	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3185	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3186	uint32_t SrcAddr,
bogdanm	0:9b334a45a8ff	3187	uint32_t DestAddr,
bogdanm	0:9b334a45a8ff	3188	uint32_t Length);
bogdanm	0:9b334a45a8ff	3189
bogdanm	0:9b334a45a8ff	3190	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3191	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3192
bogdanm	0:9b334a45a8ff	3193	/**
bogdanm	0:9b334a45a8ff	3194	* @}
bogdanm	0:9b334a45a8ff	3195	*/
bogdanm	0:9b334a45a8ff	3196
bogdanm	0:9b334a45a8ff	3197	/** @addtogroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
bogdanm	0:9b334a45a8ff	3198	* @{
bogdanm	0:9b334a45a8ff	3199	*/
bogdanm	0:9b334a45a8ff	3200	/* Simple output compare related functions ************************************/
bogdanm	0:9b334a45a8ff	3201	HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3202	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3203	uint32_t OCChannel,
bogdanm	0:9b334a45a8ff	3204	HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
bogdanm	0:9b334a45a8ff	3205
bogdanm	0:9b334a45a8ff	3206	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3207	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3208	uint32_t OCChannel);
bogdanm	0:9b334a45a8ff	3209
bogdanm	0:9b334a45a8ff	3210	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3211	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3212	uint32_t OCChannel);
bogdanm	0:9b334a45a8ff	3213
bogdanm	0:9b334a45a8ff	3214	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3215	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3216	uint32_t OCChannel);
bogdanm	0:9b334a45a8ff	3217
bogdanm	0:9b334a45a8ff	3218	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3219	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3220	uint32_t OCChannel);
bogdanm	0:9b334a45a8ff	3221
bogdanm	0:9b334a45a8ff	3222	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3223	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3224	uint32_t OCChannel,
bogdanm	0:9b334a45a8ff	3225	uint32_t SrcAddr,
bogdanm	0:9b334a45a8ff	3226	uint32_t DestAddr,
bogdanm	0:9b334a45a8ff	3227	uint32_t Length);
bogdanm	0:9b334a45a8ff	3228
bogdanm	0:9b334a45a8ff	3229	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3230	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3231	uint32_t OCChannel);
bogdanm	0:9b334a45a8ff	3232
bogdanm	0:9b334a45a8ff	3233	/**
bogdanm	0:9b334a45a8ff	3234	* @}
bogdanm	0:9b334a45a8ff	3235	*/
bogdanm	0:9b334a45a8ff	3236
bogdanm	0:9b334a45a8ff	3237	/** @addtogroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
bogdanm	0:9b334a45a8ff	3238	* @{
bogdanm	0:9b334a45a8ff	3239	*/
bogdanm	0:9b334a45a8ff	3240	/* Simple PWM output related functions ****************************************/
bogdanm	0:9b334a45a8ff	3241	HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3242	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3243	uint32_t PWMChannel,
bogdanm	0:9b334a45a8ff	3244	HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
bogdanm	0:9b334a45a8ff	3245
bogdanm	0:9b334a45a8ff	3246	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3247	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3248	uint32_t PWMChannel);
bogdanm	0:9b334a45a8ff	3249
bogdanm	0:9b334a45a8ff	3250	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3251	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3252	uint32_t PWMChannel);
bogdanm	0:9b334a45a8ff	3253
bogdanm	0:9b334a45a8ff	3254	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3255	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3256	uint32_t PWMChannel);
bogdanm	0:9b334a45a8ff	3257
bogdanm	0:9b334a45a8ff	3258	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3259	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3260	uint32_t PWMChannel);
bogdanm	0:9b334a45a8ff	3261
bogdanm	0:9b334a45a8ff	3262	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3263	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3264	uint32_t PWMChannel,
bogdanm	0:9b334a45a8ff	3265	uint32_t SrcAddr,
bogdanm	0:9b334a45a8ff	3266	uint32_t DestAddr,
bogdanm	0:9b334a45a8ff	3267	uint32_t Length);
bogdanm	0:9b334a45a8ff	3268
bogdanm	0:9b334a45a8ff	3269	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3270	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3271	uint32_t PWMChannel);
bogdanm	0:9b334a45a8ff	3272
bogdanm	0:9b334a45a8ff	3273	/**
bogdanm	0:9b334a45a8ff	3274	* @}
bogdanm	0:9b334a45a8ff	3275	*/
bogdanm	0:9b334a45a8ff	3276
bogdanm	0:9b334a45a8ff	3277	/** @addtogroup HRTIM_Exported_Functions_Group5 Simple input capture functions
bogdanm	0:9b334a45a8ff	3278	* @{
bogdanm	0:9b334a45a8ff	3279	*/
bogdanm	0:9b334a45a8ff	3280	/* Simple capture related functions *******************************************/
bogdanm	0:9b334a45a8ff	3281	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3282	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3283	uint32_t CaptureChannel,
bogdanm	0:9b334a45a8ff	3284	HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
bogdanm	0:9b334a45a8ff	3285
bogdanm	0:9b334a45a8ff	3286	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3287	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3288	uint32_t CaptureChannel);
bogdanm	0:9b334a45a8ff	3289
bogdanm	0:9b334a45a8ff	3290	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3291	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3292	uint32_t CaptureChannel);
bogdanm	0:9b334a45a8ff	3293
bogdanm	0:9b334a45a8ff	3294	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3295	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3296	uint32_t CaptureChannel);
bogdanm	0:9b334a45a8ff	3297
bogdanm	0:9b334a45a8ff	3298	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3299	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3300	uint32_t CaptureChannel);
bogdanm	0:9b334a45a8ff	3301
bogdanm	0:9b334a45a8ff	3302	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3303	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3304	uint32_t CaptureChannel,
bogdanm	0:9b334a45a8ff	3305	uint32_t SrcAddr,
bogdanm	0:9b334a45a8ff	3306	uint32_t DestAddr,
bogdanm	0:9b334a45a8ff	3307	uint32_t Length);
bogdanm	0:9b334a45a8ff	3308
bogdanm	0:9b334a45a8ff	3309	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3310	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3311	uint32_t CaptureChannel);
bogdanm	0:9b334a45a8ff	3312
bogdanm	0:9b334a45a8ff	3313	/**
bogdanm	0:9b334a45a8ff	3314	* @}
bogdanm	0:9b334a45a8ff	3315	*/
bogdanm	0:9b334a45a8ff	3316
bogdanm	0:9b334a45a8ff	3317	/** @addtogroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
bogdanm	0:9b334a45a8ff	3318	* @{
bogdanm	0:9b334a45a8ff	3319	*/
bogdanm	0:9b334a45a8ff	3320	/* Simple one pulse related functions *****************************************/
bogdanm	0:9b334a45a8ff	3321	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3322	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3323	uint32_t OnePulseChannel,
bogdanm	0:9b334a45a8ff	3324	HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
bogdanm	0:9b334a45a8ff	3325
bogdanm	0:9b334a45a8ff	3326	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3327	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3328	uint32_t OnePulseChannel);
bogdanm	0:9b334a45a8ff	3329
bogdanm	0:9b334a45a8ff	3330	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3331	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3332	uint32_t OnePulseChannel);
bogdanm	0:9b334a45a8ff	3333
bogdanm	0:9b334a45a8ff	3334	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3335	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3336	uint32_t OnePulseChannel);
bogdanm	0:9b334a45a8ff	3337
bogdanm	0:9b334a45a8ff	3338	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3339	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3340	uint32_t OnePulseChannel);
bogdanm	0:9b334a45a8ff	3341
bogdanm	0:9b334a45a8ff	3342	/**
bogdanm	0:9b334a45a8ff	3343	* @}
bogdanm	0:9b334a45a8ff	3344	*/
bogdanm	0:9b334a45a8ff	3345
bogdanm	0:9b334a45a8ff	3346	/** @addtogroup HRTIM_Exported_Functions_Group7 Configuration functions
bogdanm	0:9b334a45a8ff	3347	* @{
bogdanm	0:9b334a45a8ff	3348	*/
bogdanm	0:9b334a45a8ff	3349	HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3350	HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
bogdanm	0:9b334a45a8ff	3351
bogdanm	0:9b334a45a8ff	3352	HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3353	uint32_t Event,
bogdanm	0:9b334a45a8ff	3354	HRTIM_EventCfgTypeDef* pEventCfg);
bogdanm	0:9b334a45a8ff	3355
bogdanm	0:9b334a45a8ff	3356	HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3357	uint32_t Prescaler);
bogdanm	0:9b334a45a8ff	3358
bogdanm	0:9b334a45a8ff	3359	HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3360	uint32_t Fault,
bogdanm	0:9b334a45a8ff	3361	HRTIM_FaultCfgTypeDef* pFaultCfg);
bogdanm	0:9b334a45a8ff	3362
bogdanm	0:9b334a45a8ff	3363	HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3364	uint32_t Prescaler);
bogdanm	0:9b334a45a8ff	3365
bogdanm	0:9b334a45a8ff	3366	void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
bogdanm	0:9b334a45a8ff	3367	uint32_t Faults,
bogdanm	0:9b334a45a8ff	3368	uint32_t Enable);
bogdanm	0:9b334a45a8ff	3369
bogdanm	0:9b334a45a8ff	3370	HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3371	uint32_t ADCTrigger,
bogdanm	0:9b334a45a8ff	3372	HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
bogdanm	0:9b334a45a8ff	3373
bogdanm	0:9b334a45a8ff	3374	/**
bogdanm	0:9b334a45a8ff	3375	* @}
bogdanm	0:9b334a45a8ff	3376	*/
bogdanm	0:9b334a45a8ff	3377
bogdanm	0:9b334a45a8ff	3378	/** @addtogroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
bogdanm	0:9b334a45a8ff	3379	* @{
bogdanm	0:9b334a45a8ff	3380	*/
bogdanm	0:9b334a45a8ff	3381	/* Waveform related functions *************************************************/
bogdanm	0:9b334a45a8ff	3382	HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3383	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3384	HRTIM_TimerCfgTypeDef * pTimerCfg);
bogdanm	0:9b334a45a8ff	3385
bogdanm	0:9b334a45a8ff	3386	HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3387	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3388	uint32_t CompareUnit,
bogdanm	0:9b334a45a8ff	3389	HRTIM_CompareCfgTypeDef* pCompareCfg);
bogdanm	0:9b334a45a8ff	3390
bogdanm	0:9b334a45a8ff	3391	HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3392	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3393	uint32_t CaptureUnit,
bogdanm	0:9b334a45a8ff	3394	HRTIM_CaptureCfgTypeDef* pCaptureCfg);
bogdanm	0:9b334a45a8ff	3395
bogdanm	0:9b334a45a8ff	3396	HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3397	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3398	uint32_t Output,
bogdanm	0:9b334a45a8ff	3399	HRTIM_OutputCfgTypeDef * pOutputCfg);
bogdanm	0:9b334a45a8ff	3400
bogdanm	0:9b334a45a8ff	3401	HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3402	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3403	uint32_t Output,
bogdanm	0:9b334a45a8ff	3404	uint32_t OutputLevel);
bogdanm	0:9b334a45a8ff	3405
bogdanm	0:9b334a45a8ff	3406	HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3407	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3408	uint32_t Event,
bogdanm	0:9b334a45a8ff	3409	HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
bogdanm	0:9b334a45a8ff	3410
bogdanm	0:9b334a45a8ff	3411	HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3412	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3413	HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
bogdanm	0:9b334a45a8ff	3414
bogdanm	0:9b334a45a8ff	3415	HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3416	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3417	HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
bogdanm	0:9b334a45a8ff	3418
bogdanm	0:9b334a45a8ff	3419	HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3420	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3421	uint32_t RegistersToUpdate);
bogdanm	0:9b334a45a8ff	3422
bogdanm	0:9b334a45a8ff	3423
bogdanm	0:9b334a45a8ff	3424	HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3425	uint32_t Timers);
bogdanm	0:9b334a45a8ff	3426
bogdanm	0:9b334a45a8ff	3427	HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3428	uint32_t Timers);
bogdanm	0:9b334a45a8ff	3429
bogdanm	0:9b334a45a8ff	3430
bogdanm	0:9b334a45a8ff	3431	HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3432	uint32_t Timers);
bogdanm	0:9b334a45a8ff	3433
bogdanm	0:9b334a45a8ff	3434	HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3435	uint32_t Timers);
bogdanm	0:9b334a45a8ff	3436
bogdanm	0:9b334a45a8ff	3437
bogdanm	0:9b334a45a8ff	3438	HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3439	uint32_t Timers);
bogdanm	0:9b334a45a8ff	3440
bogdanm	0:9b334a45a8ff	3441	HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3442	uint32_t Timers);
bogdanm	0:9b334a45a8ff	3443
bogdanm	0:9b334a45a8ff	3444	HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3445	uint32_t OutputsToStart);
bogdanm	0:9b334a45a8ff	3446
bogdanm	0:9b334a45a8ff	3447	HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3448	uint32_t OutputsToStop);
bogdanm	0:9b334a45a8ff	3449
bogdanm	0:9b334a45a8ff	3450	HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3451	uint32_t Enable);
bogdanm	0:9b334a45a8ff	3452
bogdanm	0:9b334a45a8ff	3453	HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3454
bogdanm	0:9b334a45a8ff	3455	HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3456	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3457	uint32_t CaptureUnit);
bogdanm	0:9b334a45a8ff	3458
bogdanm	0:9b334a45a8ff	3459	HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3460	uint32_t Timers);
bogdanm	0:9b334a45a8ff	3461
bogdanm	0:9b334a45a8ff	3462	HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3463	uint32_t Timers);
bogdanm	0:9b334a45a8ff	3464
bogdanm	0:9b334a45a8ff	3465	HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3466	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3467	uint32_t BurstBufferAddress,
bogdanm	0:9b334a45a8ff	3468	uint32_t BurstBufferLength);
bogdanm	0:9b334a45a8ff	3469
bogdanm	0:9b334a45a8ff	3470	HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3471	uint32_t Timers);
bogdanm	0:9b334a45a8ff	3472
bogdanm	0:9b334a45a8ff	3473	HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3474	uint32_t Timers);
bogdanm	0:9b334a45a8ff	3475
bogdanm	0:9b334a45a8ff	3476	/**
bogdanm	0:9b334a45a8ff	3477	* @}
bogdanm	0:9b334a45a8ff	3478	*/
bogdanm	0:9b334a45a8ff	3479
bogdanm	0:9b334a45a8ff	3480	/** @addtogroup HRTIM_Exported_Functions_Group9 Peripheral state functions
bogdanm	0:9b334a45a8ff	3481	* @{
bogdanm	0:9b334a45a8ff	3482	*/
bogdanm	0:9b334a45a8ff	3483	/* HRTIM peripheral state functions */
bogdanm	0:9b334a45a8ff	3484	HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
bogdanm	0:9b334a45a8ff	3485
bogdanm	0:9b334a45a8ff	3486	uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3487	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3488	uint32_t CaptureUnit);
bogdanm	0:9b334a45a8ff	3489
bogdanm	0:9b334a45a8ff	3490	uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3491	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3492	uint32_t Output);
bogdanm	0:9b334a45a8ff	3493
bogdanm	0:9b334a45a8ff	3494	uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
bogdanm	0:9b334a45a8ff	3495	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3496	uint32_t Output);
bogdanm	0:9b334a45a8ff	3497
bogdanm	0:9b334a45a8ff	3498	uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3499	uint32_t TimerIdx,
bogdanm	0:9b334a45a8ff	3500	uint32_t Output);
bogdanm	0:9b334a45a8ff	3501
bogdanm	0:9b334a45a8ff	3502	uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3503
bogdanm	0:9b334a45a8ff	3504	uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3505	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3506
bogdanm	0:9b334a45a8ff	3507	uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3508	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3509
bogdanm	0:9b334a45a8ff	3510	/**
bogdanm	0:9b334a45a8ff	3511	* @}
bogdanm	0:9b334a45a8ff	3512	*/
bogdanm	0:9b334a45a8ff	3513
bogdanm	0:9b334a45a8ff	3514	/** @addtogroup HRTIM_Exported_Functions_Group10 Interrupts handling
bogdanm	0:9b334a45a8ff	3515	* @{
bogdanm	0:9b334a45a8ff	3516	*/
bogdanm	0:9b334a45a8ff	3517	/* IRQ handler */
bogdanm	0:9b334a45a8ff	3518	void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3519	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3520
bogdanm	0:9b334a45a8ff	3521	/* HRTIM events related callback functions */
bogdanm	0:9b334a45a8ff	3522	void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3523	void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3524	void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3525	void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3526	void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3527	void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3528	void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3529	void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3530	void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3531
bogdanm	0:9b334a45a8ff	3532	/* Timer events related callback functions */
bogdanm	0:9b334a45a8ff	3533	void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3534	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3535	void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3536	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3537	void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3538	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3539	void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3540	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3541	void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3542	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3543	void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3544	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3545	void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3546	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3547	void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3548	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3549	void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3550	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3551	void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3552	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3553	void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3554	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3555	void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3556	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3557	void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3558	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3559	void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3560	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3561	void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm	0:9b334a45a8ff	3562	uint32_t TimerIdx);
bogdanm	0:9b334a45a8ff	3563	void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
bogdanm	0:9b334a45a8ff	3564
bogdanm	0:9b334a45a8ff	3565	/**
bogdanm	0:9b334a45a8ff	3566	* @}
bogdanm	0:9b334a45a8ff	3567	*/
bogdanm	0:9b334a45a8ff	3568
bogdanm	0:9b334a45a8ff	3569	/**
bogdanm	0:9b334a45a8ff	3570	* @}
bogdanm	0:9b334a45a8ff	3571	*/
bogdanm	0:9b334a45a8ff	3572
bogdanm	0:9b334a45a8ff	3573	/**
bogdanm	0:9b334a45a8ff	3574	* @}
bogdanm	0:9b334a45a8ff	3575	*/
bogdanm	0:9b334a45a8ff	3576
bogdanm	0:9b334a45a8ff	3577	/**
bogdanm	0:9b334a45a8ff	3578	* @}
bogdanm	0:9b334a45a8ff	3579	*/
bogdanm	0:9b334a45a8ff	3580
bogdanm	0:9b334a45a8ff	3581	#endif /* defined(STM32F334x8) */
bogdanm	0:9b334a45a8ff	3582
bogdanm	0:9b334a45a8ff	3583	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	3584	}
bogdanm	0:9b334a45a8ff	3585	#endif
bogdanm	0:9b334a45a8ff	3586
bogdanm	0:9b334a45a8ff	3587	#endif /* __STM32F3xx_HAL_HRTIM_H */
bogdanm	0:9b334a45a8ff	3588
bogdanm	0:9b334a45a8ff	3589	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_hrtim.h@129:2e517c56bcfb, 2016-05-16 (annotated)

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