fix LPC812 PWM
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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.c@129:2e517c56bcfb, 2016-05-16 (annotated)
- Committer:
- nameless129
- Date:
- Mon May 16 16:50:30 2016 +0000
- Revision:
- 129:2e517c56bcfb
- Parent:
- 0:9b334a45a8ff
PWM Fix:Duty 0%??H???????????????
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /** |
bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f0xx_hal_adc.c |
bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
bogdanm | 0:9b334a45a8ff | 5 | * @version V1.3.0 |
bogdanm | 0:9b334a45a8ff | 6 | * @date 26-June-2015 |
bogdanm | 0:9b334a45a8ff | 7 | * @brief This file provides firmware functions to manage the following |
bogdanm | 0:9b334a45a8ff | 8 | * functionalities of the Analog to Digital Convertor (ADC) |
bogdanm | 0:9b334a45a8ff | 9 | * peripheral: |
bogdanm | 0:9b334a45a8ff | 10 | * + Initialization and de-initialization functions |
bogdanm | 0:9b334a45a8ff | 11 | * ++ Initialization and Configuration of ADC |
bogdanm | 0:9b334a45a8ff | 12 | * + Operation functions |
bogdanm | 0:9b334a45a8ff | 13 | * ++ Start, stop, get result of conversions of regular |
bogdanm | 0:9b334a45a8ff | 14 | * group, using 3 possible modes: polling, interruption or DMA. |
bogdanm | 0:9b334a45a8ff | 15 | * + Control functions |
bogdanm | 0:9b334a45a8ff | 16 | * ++ Channels configuration on regular group |
bogdanm | 0:9b334a45a8ff | 17 | * ++ Analog Watchdog configuration |
bogdanm | 0:9b334a45a8ff | 18 | * + State functions |
bogdanm | 0:9b334a45a8ff | 19 | * ++ ADC state machine management |
bogdanm | 0:9b334a45a8ff | 20 | * ++ Interrupts and flags management |
bogdanm | 0:9b334a45a8ff | 21 | * Other functions (extended functions) are available in file |
bogdanm | 0:9b334a45a8ff | 22 | * "stm32f0xx_hal_adc_ex.c". |
bogdanm | 0:9b334a45a8ff | 23 | * |
bogdanm | 0:9b334a45a8ff | 24 | @verbatim |
bogdanm | 0:9b334a45a8ff | 25 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 26 | ##### ADC peripheral features ##### |
bogdanm | 0:9b334a45a8ff | 27 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 28 | [..] |
bogdanm | 0:9b334a45a8ff | 29 | (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution |
bogdanm | 0:9b334a45a8ff | 30 | |
bogdanm | 0:9b334a45a8ff | 31 | (+) Interrupt generation at the end of regular conversion and in case of |
bogdanm | 0:9b334a45a8ff | 32 | analog watchdog or overrun events. |
bogdanm | 0:9b334a45a8ff | 33 | |
bogdanm | 0:9b334a45a8ff | 34 | (+) Single and continuous conversion modes. |
bogdanm | 0:9b334a45a8ff | 35 | |
bogdanm | 0:9b334a45a8ff | 36 | (+) Scan mode for conversion of several channels sequentially. |
bogdanm | 0:9b334a45a8ff | 37 | |
bogdanm | 0:9b334a45a8ff | 38 | (+) Data alignment with in-built data coherency. |
bogdanm | 0:9b334a45a8ff | 39 | |
bogdanm | 0:9b334a45a8ff | 40 | (+) Programmable sampling time (common for all channels) |
bogdanm | 0:9b334a45a8ff | 41 | |
bogdanm | 0:9b334a45a8ff | 42 | (+) ADC conversion of regular group. |
bogdanm | 0:9b334a45a8ff | 43 | |
bogdanm | 0:9b334a45a8ff | 44 | (+) External trigger (timer or EXTI) with configurable polarity |
bogdanm | 0:9b334a45a8ff | 45 | |
bogdanm | 0:9b334a45a8ff | 46 | (+) DMA request generation for transfer of conversions data of regular group. |
bogdanm | 0:9b334a45a8ff | 47 | |
bogdanm | 0:9b334a45a8ff | 48 | (+) ADC calibration |
bogdanm | 0:9b334a45a8ff | 49 | |
bogdanm | 0:9b334a45a8ff | 50 | (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at |
bogdanm | 0:9b334a45a8ff | 51 | slower speed. |
bogdanm | 0:9b334a45a8ff | 52 | |
bogdanm | 0:9b334a45a8ff | 53 | (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to |
bogdanm | 0:9b334a45a8ff | 54 | Vdda or to an external voltage reference). |
bogdanm | 0:9b334a45a8ff | 55 | |
bogdanm | 0:9b334a45a8ff | 56 | |
bogdanm | 0:9b334a45a8ff | 57 | ##### How to use this driver ##### |
bogdanm | 0:9b334a45a8ff | 58 | ============================================================================== |
bogdanm | 0:9b334a45a8ff | 59 | [..] |
bogdanm | 0:9b334a45a8ff | 60 | |
bogdanm | 0:9b334a45a8ff | 61 | *** Configuration of top level parameters related to ADC *** |
bogdanm | 0:9b334a45a8ff | 62 | ============================================================ |
bogdanm | 0:9b334a45a8ff | 63 | [..] |
bogdanm | 0:9b334a45a8ff | 64 | |
bogdanm | 0:9b334a45a8ff | 65 | (#) Enable the ADC interface |
bogdanm | 0:9b334a45a8ff | 66 | (++) As prerequisite, ADC clock must be configured at RCC top level. |
bogdanm | 0:9b334a45a8ff | 67 | Caution: On STM32F0, ADC clock frequency max is 14MHz (refer |
bogdanm | 0:9b334a45a8ff | 68 | to device datasheet). |
bogdanm | 0:9b334a45a8ff | 69 | Therefore, ADC clock prescaler must be configured in |
bogdanm | 0:9b334a45a8ff | 70 | function of ADC clock source frequency to remain below |
bogdanm | 0:9b334a45a8ff | 71 | this maximum frequency. |
bogdanm | 0:9b334a45a8ff | 72 | |
bogdanm | 0:9b334a45a8ff | 73 | (++) Two clock settings are mandatory: |
bogdanm | 0:9b334a45a8ff | 74 | (+++) ADC clock (core clock, also possibly conversion clock). |
bogdanm | 0:9b334a45a8ff | 75 | |
bogdanm | 0:9b334a45a8ff | 76 | (+++) ADC clock (conversions clock). |
bogdanm | 0:9b334a45a8ff | 77 | Two possible clock sources: synchronous clock derived from APB clock |
bogdanm | 0:9b334a45a8ff | 78 | or asynchronous clock derived from ADC dedicated HSI RC oscillator |
bogdanm | 0:9b334a45a8ff | 79 | 14MHz. |
bogdanm | 0:9b334a45a8ff | 80 | If asynchronous clock is selected, parameter "HSI14State" must be set either: |
bogdanm | 0:9b334a45a8ff | 81 | - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control |
bogdanm | 0:9b334a45a8ff | 82 | the HSI14 oscillator enable/disable (if not used to supply the main |
bogdanm | 0:9b334a45a8ff | 83 | system clock): feature used if ADC mode LowPowerAutoPowerOff is |
bogdanm | 0:9b334a45a8ff | 84 | enabled. |
bogdanm | 0:9b334a45a8ff | 85 | - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator |
bogdanm | 0:9b334a45a8ff | 86 | always enabled: can be used to supply the main system clock. |
bogdanm | 0:9b334a45a8ff | 87 | |
bogdanm | 0:9b334a45a8ff | 88 | (+++) Example: |
bogdanm | 0:9b334a45a8ff | 89 | Into HAL_ADC_MspInit() (recommended code location) or with |
bogdanm | 0:9b334a45a8ff | 90 | other device clock parameters configuration: |
bogdanm | 0:9b334a45a8ff | 91 | (+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory) |
bogdanm | 0:9b334a45a8ff | 92 | |
bogdanm | 0:9b334a45a8ff | 93 | HI14 enable or let under control of ADC: (optional: if asynchronous clock selected) |
bogdanm | 0:9b334a45a8ff | 94 | (+++) RCC_OscInitTypeDef RCC_OscInitStructure; |
bogdanm | 0:9b334a45a8ff | 95 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; |
bogdanm | 0:9b334a45a8ff | 96 | (+++) RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; |
bogdanm | 0:9b334a45a8ff | 97 | (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL; |
bogdanm | 0:9b334a45a8ff | 98 | (+++) RCC_OscInitStructure.PLL... (optional if used for system clock) |
bogdanm | 0:9b334a45a8ff | 99 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
bogdanm | 0:9b334a45a8ff | 100 | |
bogdanm | 0:9b334a45a8ff | 101 | (++) ADC clock source and clock prescaler are configured at ADC level with |
bogdanm | 0:9b334a45a8ff | 102 | parameter "ClockPrescaler" using function HAL_ADC_Init(). |
bogdanm | 0:9b334a45a8ff | 103 | |
bogdanm | 0:9b334a45a8ff | 104 | (#) ADC pins configuration |
bogdanm | 0:9b334a45a8ff | 105 | (++) Enable the clock for the ADC GPIOs |
bogdanm | 0:9b334a45a8ff | 106 | using macro __HAL_RCC_GPIOx_CLK_ENABLE() |
bogdanm | 0:9b334a45a8ff | 107 | (++) Configure these ADC pins in analog mode |
bogdanm | 0:9b334a45a8ff | 108 | using function HAL_GPIO_Init() |
bogdanm | 0:9b334a45a8ff | 109 | |
bogdanm | 0:9b334a45a8ff | 110 | (#) Optionally, in case of usage of ADC with interruptions: |
bogdanm | 0:9b334a45a8ff | 111 | (++) Configure the NVIC for ADC |
bogdanm | 0:9b334a45a8ff | 112 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
bogdanm | 0:9b334a45a8ff | 113 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
bogdanm | 0:9b334a45a8ff | 114 | into the function of corresponding ADC interruption vector |
bogdanm | 0:9b334a45a8ff | 115 | ADCx_IRQHandler(). |
bogdanm | 0:9b334a45a8ff | 116 | |
bogdanm | 0:9b334a45a8ff | 117 | (#) Optionally, in case of usage of DMA: |
bogdanm | 0:9b334a45a8ff | 118 | (++) Configure the DMA (DMA channel, mode normal or circular, ...) |
bogdanm | 0:9b334a45a8ff | 119 | using function HAL_DMA_Init(). |
bogdanm | 0:9b334a45a8ff | 120 | (++) Configure the NVIC for DMA |
bogdanm | 0:9b334a45a8ff | 121 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
bogdanm | 0:9b334a45a8ff | 122 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
bogdanm | 0:9b334a45a8ff | 123 | into the function of corresponding DMA interruption vector |
bogdanm | 0:9b334a45a8ff | 124 | DMAx_Channelx_IRQHandler(). |
bogdanm | 0:9b334a45a8ff | 125 | |
bogdanm | 0:9b334a45a8ff | 126 | *** Configuration of ADC, group regular, channels parameters *** |
bogdanm | 0:9b334a45a8ff | 127 | ================================================================ |
bogdanm | 0:9b334a45a8ff | 128 | [..] |
bogdanm | 0:9b334a45a8ff | 129 | |
bogdanm | 0:9b334a45a8ff | 130 | (#) Configure the ADC parameters (resolution, data alignment, ...) |
bogdanm | 0:9b334a45a8ff | 131 | and regular group parameters (conversion trigger, sequencer, ...) |
bogdanm | 0:9b334a45a8ff | 132 | using function HAL_ADC_Init(). |
bogdanm | 0:9b334a45a8ff | 133 | |
bogdanm | 0:9b334a45a8ff | 134 | (#) Configure the channels for regular group parameters (channel number, |
bogdanm | 0:9b334a45a8ff | 135 | channel rank into sequencer, ..., into regular group) |
bogdanm | 0:9b334a45a8ff | 136 | using function HAL_ADC_ConfigChannel(). |
bogdanm | 0:9b334a45a8ff | 137 | |
bogdanm | 0:9b334a45a8ff | 138 | (#) Optionally, configure the analog watchdog parameters (channels |
bogdanm | 0:9b334a45a8ff | 139 | monitored, thresholds, ...) |
bogdanm | 0:9b334a45a8ff | 140 | using function HAL_ADC_AnalogWDGConfig(). |
bogdanm | 0:9b334a45a8ff | 141 | |
bogdanm | 0:9b334a45a8ff | 142 | *** Execution of ADC conversions *** |
bogdanm | 0:9b334a45a8ff | 143 | ==================================== |
bogdanm | 0:9b334a45a8ff | 144 | [..] |
bogdanm | 0:9b334a45a8ff | 145 | |
bogdanm | 0:9b334a45a8ff | 146 | (#) Optionally, perform an automatic ADC calibration to improve the |
bogdanm | 0:9b334a45a8ff | 147 | conversion accuracy |
bogdanm | 0:9b334a45a8ff | 148 | using function HAL_ADCEx_Calibration_Start(). |
bogdanm | 0:9b334a45a8ff | 149 | |
bogdanm | 0:9b334a45a8ff | 150 | (#) ADC driver can be used among three modes: polling, interruption, |
bogdanm | 0:9b334a45a8ff | 151 | transfer by DMA. |
bogdanm | 0:9b334a45a8ff | 152 | |
bogdanm | 0:9b334a45a8ff | 153 | (++) ADC conversion by polling: |
bogdanm | 0:9b334a45a8ff | 154 | (+++) Activate the ADC peripheral and start conversions |
bogdanm | 0:9b334a45a8ff | 155 | using function HAL_ADC_Start() |
bogdanm | 0:9b334a45a8ff | 156 | (+++) Wait for ADC conversion completion |
bogdanm | 0:9b334a45a8ff | 157 | using function HAL_ADC_PollForConversion() |
bogdanm | 0:9b334a45a8ff | 158 | (+++) Retrieve conversion results |
bogdanm | 0:9b334a45a8ff | 159 | using function HAL_ADC_GetValue() |
bogdanm | 0:9b334a45a8ff | 160 | (+++) Stop conversion and disable the ADC peripheral |
bogdanm | 0:9b334a45a8ff | 161 | using function HAL_ADC_Stop() |
bogdanm | 0:9b334a45a8ff | 162 | |
bogdanm | 0:9b334a45a8ff | 163 | (++) ADC conversion by interruption: |
bogdanm | 0:9b334a45a8ff | 164 | (+++) Activate the ADC peripheral and start conversions |
bogdanm | 0:9b334a45a8ff | 165 | using function HAL_ADC_Start_IT() |
bogdanm | 0:9b334a45a8ff | 166 | (+++) Wait for ADC conversion completion by call of function |
bogdanm | 0:9b334a45a8ff | 167 | HAL_ADC_ConvCpltCallback() |
bogdanm | 0:9b334a45a8ff | 168 | (this function must be implemented in user program) |
bogdanm | 0:9b334a45a8ff | 169 | (+++) Retrieve conversion results |
bogdanm | 0:9b334a45a8ff | 170 | using function HAL_ADC_GetValue() |
bogdanm | 0:9b334a45a8ff | 171 | (+++) Stop conversion and disable the ADC peripheral |
bogdanm | 0:9b334a45a8ff | 172 | using function HAL_ADC_Stop_IT() |
bogdanm | 0:9b334a45a8ff | 173 | |
bogdanm | 0:9b334a45a8ff | 174 | (++) ADC conversion with transfer by DMA: |
bogdanm | 0:9b334a45a8ff | 175 | (+++) Activate the ADC peripheral and start conversions |
bogdanm | 0:9b334a45a8ff | 176 | using function HAL_ADC_Start_DMA() |
bogdanm | 0:9b334a45a8ff | 177 | (+++) Wait for ADC conversion completion by call of function |
bogdanm | 0:9b334a45a8ff | 178 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
bogdanm | 0:9b334a45a8ff | 179 | (these functions must be implemented in user program) |
bogdanm | 0:9b334a45a8ff | 180 | (+++) Conversion results are automatically transferred by DMA into |
bogdanm | 0:9b334a45a8ff | 181 | destination variable address. |
bogdanm | 0:9b334a45a8ff | 182 | (+++) Stop conversion and disable the ADC peripheral |
bogdanm | 0:9b334a45a8ff | 183 | using function HAL_ADC_Stop_DMA() |
bogdanm | 0:9b334a45a8ff | 184 | |
bogdanm | 0:9b334a45a8ff | 185 | [..] |
bogdanm | 0:9b334a45a8ff | 186 | |
bogdanm | 0:9b334a45a8ff | 187 | (@) Callback functions must be implemented in user program: |
bogdanm | 0:9b334a45a8ff | 188 | (+@) HAL_ADC_ErrorCallback() |
bogdanm | 0:9b334a45a8ff | 189 | (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) |
bogdanm | 0:9b334a45a8ff | 190 | (+@) HAL_ADC_ConvCpltCallback() |
bogdanm | 0:9b334a45a8ff | 191 | (+@) HAL_ADC_ConvHalfCpltCallback |
bogdanm | 0:9b334a45a8ff | 192 | |
bogdanm | 0:9b334a45a8ff | 193 | *** Deinitialization of ADC *** |
bogdanm | 0:9b334a45a8ff | 194 | ============================================================ |
bogdanm | 0:9b334a45a8ff | 195 | [..] |
bogdanm | 0:9b334a45a8ff | 196 | |
bogdanm | 0:9b334a45a8ff | 197 | (#) Disable the ADC interface |
bogdanm | 0:9b334a45a8ff | 198 | (++) ADC clock can be hard reset and disabled at RCC top level. |
bogdanm | 0:9b334a45a8ff | 199 | (++) Hard reset of ADC peripherals |
bogdanm | 0:9b334a45a8ff | 200 | using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). |
bogdanm | 0:9b334a45a8ff | 201 | (++) ADC clock disable |
bogdanm | 0:9b334a45a8ff | 202 | using the equivalent macro/functions as configuration step. |
bogdanm | 0:9b334a45a8ff | 203 | (+++) Example: |
bogdanm | 0:9b334a45a8ff | 204 | Into HAL_ADC_MspDeInit() (recommended code location) or with |
bogdanm | 0:9b334a45a8ff | 205 | other device clock parameters configuration: |
bogdanm | 0:9b334a45a8ff | 206 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; |
bogdanm | 0:9b334a45a8ff | 207 | (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) |
bogdanm | 0:9b334a45a8ff | 208 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
bogdanm | 0:9b334a45a8ff | 209 | |
bogdanm | 0:9b334a45a8ff | 210 | (#) ADC pins configuration |
bogdanm | 0:9b334a45a8ff | 211 | (++) Disable the clock for the ADC GPIOs |
bogdanm | 0:9b334a45a8ff | 212 | using macro __HAL_RCC_GPIOx_CLK_DISABLE() |
bogdanm | 0:9b334a45a8ff | 213 | |
bogdanm | 0:9b334a45a8ff | 214 | (#) Optionally, in case of usage of ADC with interruptions: |
bogdanm | 0:9b334a45a8ff | 215 | (++) Disable the NVIC for ADC |
bogdanm | 0:9b334a45a8ff | 216 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
bogdanm | 0:9b334a45a8ff | 217 | |
bogdanm | 0:9b334a45a8ff | 218 | (#) Optionally, in case of usage of DMA: |
bogdanm | 0:9b334a45a8ff | 219 | (++) Deinitialize the DMA |
bogdanm | 0:9b334a45a8ff | 220 | using function HAL_DMA_Init(). |
bogdanm | 0:9b334a45a8ff | 221 | (++) Disable the NVIC for DMA |
bogdanm | 0:9b334a45a8ff | 222 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
bogdanm | 0:9b334a45a8ff | 223 | |
bogdanm | 0:9b334a45a8ff | 224 | [..] |
bogdanm | 0:9b334a45a8ff | 225 | |
bogdanm | 0:9b334a45a8ff | 226 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 227 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 228 | * @attention |
bogdanm | 0:9b334a45a8ff | 229 | * |
bogdanm | 0:9b334a45a8ff | 230 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
bogdanm | 0:9b334a45a8ff | 231 | * |
bogdanm | 0:9b334a45a8ff | 232 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 0:9b334a45a8ff | 233 | * are permitted provided that the following conditions are met: |
bogdanm | 0:9b334a45a8ff | 234 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 235 | * this list of conditions and the following disclaimer. |
bogdanm | 0:9b334a45a8ff | 236 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 237 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 0:9b334a45a8ff | 238 | * and/or other materials provided with the distribution. |
bogdanm | 0:9b334a45a8ff | 239 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 0:9b334a45a8ff | 240 | * may be used to endorse or promote products derived from this software |
bogdanm | 0:9b334a45a8ff | 241 | * without specific prior written permission. |
bogdanm | 0:9b334a45a8ff | 242 | * |
bogdanm | 0:9b334a45a8ff | 243 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 0:9b334a45a8ff | 244 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 0:9b334a45a8ff | 245 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 0:9b334a45a8ff | 246 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 0:9b334a45a8ff | 247 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 0:9b334a45a8ff | 248 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 0:9b334a45a8ff | 249 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 0:9b334a45a8ff | 250 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 0:9b334a45a8ff | 251 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 0:9b334a45a8ff | 252 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 0:9b334a45a8ff | 253 | * |
bogdanm | 0:9b334a45a8ff | 254 | ****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 255 | */ |
bogdanm | 0:9b334a45a8ff | 256 | |
bogdanm | 0:9b334a45a8ff | 257 | /* Includes ------------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 258 | #include "stm32f0xx_hal.h" |
bogdanm | 0:9b334a45a8ff | 259 | |
bogdanm | 0:9b334a45a8ff | 260 | /** @addtogroup STM32F0xx_HAL_Driver |
bogdanm | 0:9b334a45a8ff | 261 | * @{ |
bogdanm | 0:9b334a45a8ff | 262 | */ |
bogdanm | 0:9b334a45a8ff | 263 | |
bogdanm | 0:9b334a45a8ff | 264 | /** @defgroup ADC ADC |
bogdanm | 0:9b334a45a8ff | 265 | * @brief ADC HAL module driver |
bogdanm | 0:9b334a45a8ff | 266 | * @{ |
bogdanm | 0:9b334a45a8ff | 267 | */ |
bogdanm | 0:9b334a45a8ff | 268 | |
bogdanm | 0:9b334a45a8ff | 269 | #ifdef HAL_ADC_MODULE_ENABLED |
bogdanm | 0:9b334a45a8ff | 270 | |
bogdanm | 0:9b334a45a8ff | 271 | /* Private typedef -----------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 272 | /* Private define ------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 273 | /** @defgroup ADC_Private_Constants ADC Private Constants |
bogdanm | 0:9b334a45a8ff | 274 | * @{ |
bogdanm | 0:9b334a45a8ff | 275 | */ |
bogdanm | 0:9b334a45a8ff | 276 | |
bogdanm | 0:9b334a45a8ff | 277 | /* Fixed timeout values for ADC calibration, enable settling time, disable */ |
bogdanm | 0:9b334a45a8ff | 278 | /* settling time. */ |
bogdanm | 0:9b334a45a8ff | 279 | /* Values defined to be higher than worst cases: low clock frequency, */ |
bogdanm | 0:9b334a45a8ff | 280 | /* maximum prescaler. */ |
bogdanm | 0:9b334a45a8ff | 281 | /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ |
bogdanm | 0:9b334a45a8ff | 282 | /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ |
bogdanm | 0:9b334a45a8ff | 283 | /* Unit: ms */ |
bogdanm | 0:9b334a45a8ff | 284 | #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) |
bogdanm | 0:9b334a45a8ff | 285 | #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) |
bogdanm | 0:9b334a45a8ff | 286 | #define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 2) |
bogdanm | 0:9b334a45a8ff | 287 | |
bogdanm | 0:9b334a45a8ff | 288 | /* Delay for ADC stabilization time. */ |
bogdanm | 0:9b334a45a8ff | 289 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
bogdanm | 0:9b334a45a8ff | 290 | /* Unit: us */ |
bogdanm | 0:9b334a45a8ff | 291 | #define ADC_STAB_DELAY_US ((uint32_t) 1) |
bogdanm | 0:9b334a45a8ff | 292 | |
bogdanm | 0:9b334a45a8ff | 293 | /* Delay for temperature sensor stabilization time. */ |
bogdanm | 0:9b334a45a8ff | 294 | /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
bogdanm | 0:9b334a45a8ff | 295 | /* Unit: us */ |
bogdanm | 0:9b334a45a8ff | 296 | #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) |
bogdanm | 0:9b334a45a8ff | 297 | |
bogdanm | 0:9b334a45a8ff | 298 | /** |
bogdanm | 0:9b334a45a8ff | 299 | * @} |
bogdanm | 0:9b334a45a8ff | 300 | */ |
bogdanm | 0:9b334a45a8ff | 301 | |
bogdanm | 0:9b334a45a8ff | 302 | /* Private macro -------------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 303 | /* Private variables ---------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 304 | /* Private function prototypes -----------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 305 | /** @defgroup ADC_Private_Functions ADC Private Functions |
bogdanm | 0:9b334a45a8ff | 306 | * @{ |
bogdanm | 0:9b334a45a8ff | 307 | */ |
bogdanm | 0:9b334a45a8ff | 308 | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); |
bogdanm | 0:9b334a45a8ff | 309 | static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); |
bogdanm | 0:9b334a45a8ff | 310 | static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc); |
bogdanm | 0:9b334a45a8ff | 311 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
bogdanm | 0:9b334a45a8ff | 312 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
bogdanm | 0:9b334a45a8ff | 313 | static void ADC_DMAError(DMA_HandleTypeDef *hdma); |
bogdanm | 0:9b334a45a8ff | 314 | /** |
bogdanm | 0:9b334a45a8ff | 315 | * @} |
bogdanm | 0:9b334a45a8ff | 316 | */ |
bogdanm | 0:9b334a45a8ff | 317 | |
bogdanm | 0:9b334a45a8ff | 318 | /* Exported functions ---------------------------------------------------------*/ |
bogdanm | 0:9b334a45a8ff | 319 | |
bogdanm | 0:9b334a45a8ff | 320 | /** @defgroup ADC_Exported_Functions ADC Exported Functions |
bogdanm | 0:9b334a45a8ff | 321 | * @{ |
bogdanm | 0:9b334a45a8ff | 322 | */ |
bogdanm | 0:9b334a45a8ff | 323 | |
bogdanm | 0:9b334a45a8ff | 324 | /** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions |
bogdanm | 0:9b334a45a8ff | 325 | * @brief Initialization and Configuration functions |
bogdanm | 0:9b334a45a8ff | 326 | * |
bogdanm | 0:9b334a45a8ff | 327 | @verbatim |
bogdanm | 0:9b334a45a8ff | 328 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 329 | ##### Initialization and de-initialization functions ##### |
bogdanm | 0:9b334a45a8ff | 330 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 331 | [..] This section provides functions allowing to: |
bogdanm | 0:9b334a45a8ff | 332 | (+) Initialize and configure the ADC. |
bogdanm | 0:9b334a45a8ff | 333 | (+) De-initialize the ADC |
bogdanm | 0:9b334a45a8ff | 334 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 335 | * @{ |
bogdanm | 0:9b334a45a8ff | 336 | */ |
bogdanm | 0:9b334a45a8ff | 337 | |
bogdanm | 0:9b334a45a8ff | 338 | /** |
bogdanm | 0:9b334a45a8ff | 339 | * @brief Initializes the ADC peripheral and regular group according to |
bogdanm | 0:9b334a45a8ff | 340 | * parameters specified in structure "ADC_InitTypeDef". |
bogdanm | 0:9b334a45a8ff | 341 | * @note As prerequisite, ADC clock must be configured at RCC top level |
bogdanm | 0:9b334a45a8ff | 342 | * depending on both possible clock sources: APB clock of HSI clock. |
bogdanm | 0:9b334a45a8ff | 343 | * See commented example code below that can be copied and uncommented |
bogdanm | 0:9b334a45a8ff | 344 | * into HAL_ADC_MspInit(). |
bogdanm | 0:9b334a45a8ff | 345 | * @note Possibility to update parameters on the fly: |
bogdanm | 0:9b334a45a8ff | 346 | * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when |
bogdanm | 0:9b334a45a8ff | 347 | * coming from ADC state reset. Following calls to this function can |
bogdanm | 0:9b334a45a8ff | 348 | * be used to reconfigure some parameters of ADC_InitTypeDef |
bogdanm | 0:9b334a45a8ff | 349 | * structure on the fly, without modifying MSP configuration. If ADC |
bogdanm | 0:9b334a45a8ff | 350 | * MSP has to be modified again, HAL_ADC_DeInit() must be called |
bogdanm | 0:9b334a45a8ff | 351 | * before HAL_ADC_Init(). |
bogdanm | 0:9b334a45a8ff | 352 | * The setting of these parameters is conditioned to ADC state. |
bogdanm | 0:9b334a45a8ff | 353 | * For parameters constraints, see comments of structure |
bogdanm | 0:9b334a45a8ff | 354 | * "ADC_InitTypeDef". |
bogdanm | 0:9b334a45a8ff | 355 | * @note This function configures the ADC within 2 scopes: scope of entire |
bogdanm | 0:9b334a45a8ff | 356 | * ADC and scope of regular group. For parameters details, see comments |
bogdanm | 0:9b334a45a8ff | 357 | * of structure "ADC_InitTypeDef". |
bogdanm | 0:9b334a45a8ff | 358 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 359 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 360 | */ |
bogdanm | 0:9b334a45a8ff | 361 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 362 | { |
bogdanm | 0:9b334a45a8ff | 363 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 364 | uint32_t tmpCFGR1 = 0; |
bogdanm | 0:9b334a45a8ff | 365 | |
bogdanm | 0:9b334a45a8ff | 366 | /* Check ADC handle */ |
bogdanm | 0:9b334a45a8ff | 367 | if(hadc == NULL) |
bogdanm | 0:9b334a45a8ff | 368 | { |
bogdanm | 0:9b334a45a8ff | 369 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 370 | } |
bogdanm | 0:9b334a45a8ff | 371 | |
bogdanm | 0:9b334a45a8ff | 372 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 373 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 374 | assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); |
bogdanm | 0:9b334a45a8ff | 375 | assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); |
bogdanm | 0:9b334a45a8ff | 376 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
bogdanm | 0:9b334a45a8ff | 377 | assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); |
bogdanm | 0:9b334a45a8ff | 378 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
bogdanm | 0:9b334a45a8ff | 379 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
bogdanm | 0:9b334a45a8ff | 380 | assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
bogdanm | 0:9b334a45a8ff | 381 | assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); |
bogdanm | 0:9b334a45a8ff | 382 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); |
bogdanm | 0:9b334a45a8ff | 383 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
bogdanm | 0:9b334a45a8ff | 384 | assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); |
bogdanm | 0:9b334a45a8ff | 385 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); |
bogdanm | 0:9b334a45a8ff | 386 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); |
bogdanm | 0:9b334a45a8ff | 387 | |
bogdanm | 0:9b334a45a8ff | 388 | /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ |
bogdanm | 0:9b334a45a8ff | 389 | /* at RCC top level depending on both possible clock sources: */ |
bogdanm | 0:9b334a45a8ff | 390 | /* APB clock or HSI clock. */ |
bogdanm | 0:9b334a45a8ff | 391 | /* Refer to header of this file for more details on clock enabling procedure*/ |
bogdanm | 0:9b334a45a8ff | 392 | |
bogdanm | 0:9b334a45a8ff | 393 | /* Actions performed only if ADC is coming from state reset: */ |
bogdanm | 0:9b334a45a8ff | 394 | /* - Initialization of ADC MSP */ |
bogdanm | 0:9b334a45a8ff | 395 | /* - ADC voltage regulator enable */ |
bogdanm | 0:9b334a45a8ff | 396 | if (hadc->State == HAL_ADC_STATE_RESET) |
bogdanm | 0:9b334a45a8ff | 397 | { |
bogdanm | 0:9b334a45a8ff | 398 | /* Initialize ADC error code */ |
bogdanm | 0:9b334a45a8ff | 399 | ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 400 | |
bogdanm | 0:9b334a45a8ff | 401 | /* Allocate lock resource and initialize it */ |
bogdanm | 0:9b334a45a8ff | 402 | hadc->Lock = HAL_UNLOCKED; |
bogdanm | 0:9b334a45a8ff | 403 | |
bogdanm | 0:9b334a45a8ff | 404 | /* Init the low level hardware */ |
bogdanm | 0:9b334a45a8ff | 405 | HAL_ADC_MspInit(hadc); |
bogdanm | 0:9b334a45a8ff | 406 | } |
bogdanm | 0:9b334a45a8ff | 407 | |
bogdanm | 0:9b334a45a8ff | 408 | /* Configuration of ADC parameters if previous preliminary actions are */ |
bogdanm | 0:9b334a45a8ff | 409 | /* correctly completed. */ |
bogdanm | 0:9b334a45a8ff | 410 | /* and if there is no conversion on going on regular group (ADC can be */ |
bogdanm | 0:9b334a45a8ff | 411 | /* enabled anyway, in case of call of this function to update a parameter */ |
bogdanm | 0:9b334a45a8ff | 412 | /* on the fly). */ |
bogdanm | 0:9b334a45a8ff | 413 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && |
bogdanm | 0:9b334a45a8ff | 414 | (tmp_hal_status == HAL_OK) && |
bogdanm | 0:9b334a45a8ff | 415 | (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) |
bogdanm | 0:9b334a45a8ff | 416 | { |
bogdanm | 0:9b334a45a8ff | 417 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 418 | ADC_STATE_CLR_SET(hadc->State, |
bogdanm | 0:9b334a45a8ff | 419 | HAL_ADC_STATE_REG_BUSY, |
bogdanm | 0:9b334a45a8ff | 420 | HAL_ADC_STATE_BUSY_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 421 | |
bogdanm | 0:9b334a45a8ff | 422 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 423 | /* Parameters that can be updated only when ADC is disabled: */ |
bogdanm | 0:9b334a45a8ff | 424 | /* - ADC clock mode */ |
bogdanm | 0:9b334a45a8ff | 425 | /* - ADC clock prescaler */ |
bogdanm | 0:9b334a45a8ff | 426 | /* - ADC resolution */ |
bogdanm | 0:9b334a45a8ff | 427 | if (ADC_IS_ENABLE(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 428 | { |
bogdanm | 0:9b334a45a8ff | 429 | /* Some parameters of this register are not reset, since they are set */ |
bogdanm | 0:9b334a45a8ff | 430 | /* by other functions and must be kept in case of usage of this */ |
bogdanm | 0:9b334a45a8ff | 431 | /* function on the fly (update of a parameter of ADC_InitTypeDef */ |
bogdanm | 0:9b334a45a8ff | 432 | /* without needing to reconfigure all other ADC groups/channels */ |
bogdanm | 0:9b334a45a8ff | 433 | /* parameters): */ |
bogdanm | 0:9b334a45a8ff | 434 | /* - internal measurement paths: Vbat, temperature sensor, Vref */ |
bogdanm | 0:9b334a45a8ff | 435 | /* (set into HAL_ADC_ConfigChannel() ) */ |
bogdanm | 0:9b334a45a8ff | 436 | |
bogdanm | 0:9b334a45a8ff | 437 | /* Configuration of ADC resolution */ |
bogdanm | 0:9b334a45a8ff | 438 | MODIFY_REG(hadc->Instance->CFGR1, |
bogdanm | 0:9b334a45a8ff | 439 | ADC_CFGR1_RES , |
bogdanm | 0:9b334a45a8ff | 440 | hadc->Init.Resolution ); |
bogdanm | 0:9b334a45a8ff | 441 | |
bogdanm | 0:9b334a45a8ff | 442 | /* Configuration of ADC clock mode: clock source AHB or HSI with */ |
bogdanm | 0:9b334a45a8ff | 443 | /* selectable prescaler */ |
bogdanm | 0:9b334a45a8ff | 444 | MODIFY_REG(hadc->Instance->CFGR2 , |
bogdanm | 0:9b334a45a8ff | 445 | ADC_CFGR2_CKMODE , |
bogdanm | 0:9b334a45a8ff | 446 | hadc->Init.ClockPrescaler ); |
bogdanm | 0:9b334a45a8ff | 447 | } |
bogdanm | 0:9b334a45a8ff | 448 | |
bogdanm | 0:9b334a45a8ff | 449 | /* Configuration of ADC: */ |
bogdanm | 0:9b334a45a8ff | 450 | /* - discontinuous mode */ |
bogdanm | 0:9b334a45a8ff | 451 | /* - LowPowerAutoWait mode */ |
bogdanm | 0:9b334a45a8ff | 452 | /* - LowPowerAutoPowerOff mode */ |
bogdanm | 0:9b334a45a8ff | 453 | /* - continuous conversion mode */ |
bogdanm | 0:9b334a45a8ff | 454 | /* - overrun */ |
bogdanm | 0:9b334a45a8ff | 455 | /* - external trigger to start conversion */ |
bogdanm | 0:9b334a45a8ff | 456 | /* - external trigger polarity */ |
bogdanm | 0:9b334a45a8ff | 457 | /* - data alignment */ |
bogdanm | 0:9b334a45a8ff | 458 | /* - resolution */ |
bogdanm | 0:9b334a45a8ff | 459 | /* - scan direction */ |
bogdanm | 0:9b334a45a8ff | 460 | /* - DMA continuous request */ |
bogdanm | 0:9b334a45a8ff | 461 | hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN | |
bogdanm | 0:9b334a45a8ff | 462 | ADC_CFGR1_AUTOFF | |
bogdanm | 0:9b334a45a8ff | 463 | ADC_CFGR1_AUTDLY | |
bogdanm | 0:9b334a45a8ff | 464 | ADC_CFGR1_CONT | |
bogdanm | 0:9b334a45a8ff | 465 | ADC_CFGR1_OVRMOD | |
bogdanm | 0:9b334a45a8ff | 466 | ADC_CFGR1_EXTSEL | |
bogdanm | 0:9b334a45a8ff | 467 | ADC_CFGR1_EXTEN | |
bogdanm | 0:9b334a45a8ff | 468 | ADC_CFGR1_ALIGN | |
bogdanm | 0:9b334a45a8ff | 469 | ADC_CFGR1_SCANDIR | |
bogdanm | 0:9b334a45a8ff | 470 | ADC_CFGR1_DMACFG ); |
bogdanm | 0:9b334a45a8ff | 471 | |
bogdanm | 0:9b334a45a8ff | 472 | tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT(hadc->Init.LowPowerAutoWait) | |
bogdanm | 0:9b334a45a8ff | 473 | ADC_CFGR1_AUTOOFF(hadc->Init.LowPowerAutoPowerOff) | |
bogdanm | 0:9b334a45a8ff | 474 | ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) | |
bogdanm | 0:9b334a45a8ff | 475 | ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | |
bogdanm | 0:9b334a45a8ff | 476 | hadc->Init.DataAlign | |
bogdanm | 0:9b334a45a8ff | 477 | ADC_SCANDIR(hadc->Init.ScanConvMode) | |
bogdanm | 0:9b334a45a8ff | 478 | ADC_CFGR1_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); |
bogdanm | 0:9b334a45a8ff | 479 | |
bogdanm | 0:9b334a45a8ff | 480 | /* Enable discontinuous mode only if continuous mode is disabled */ |
bogdanm | 0:9b334a45a8ff | 481 | if ((hadc->Init.DiscontinuousConvMode == ENABLE) && |
bogdanm | 0:9b334a45a8ff | 482 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
bogdanm | 0:9b334a45a8ff | 483 | { |
bogdanm | 0:9b334a45a8ff | 484 | /* Enable discontinuous mode of regular group */ |
bogdanm | 0:9b334a45a8ff | 485 | tmpCFGR1 |= ADC_CFGR1_DISCEN; |
bogdanm | 0:9b334a45a8ff | 486 | } |
bogdanm | 0:9b334a45a8ff | 487 | |
bogdanm | 0:9b334a45a8ff | 488 | /* Enable external trigger if trigger selection is different of software */ |
bogdanm | 0:9b334a45a8ff | 489 | /* start. */ |
bogdanm | 0:9b334a45a8ff | 490 | /* Note: This configuration keeps the hardware feature of parameter */ |
bogdanm | 0:9b334a45a8ff | 491 | /* ExternalTrigConvEdge "trigger edge none" equivalent to */ |
bogdanm | 0:9b334a45a8ff | 492 | /* software start. */ |
bogdanm | 0:9b334a45a8ff | 493 | if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
bogdanm | 0:9b334a45a8ff | 494 | { |
bogdanm | 0:9b334a45a8ff | 495 | tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | |
bogdanm | 0:9b334a45a8ff | 496 | hadc->Init.ExternalTrigConvEdge ); |
bogdanm | 0:9b334a45a8ff | 497 | } |
bogdanm | 0:9b334a45a8ff | 498 | |
bogdanm | 0:9b334a45a8ff | 499 | /* Update ADC configuration register with previous settings */ |
bogdanm | 0:9b334a45a8ff | 500 | hadc->Instance->CFGR1 |= tmpCFGR1; |
bogdanm | 0:9b334a45a8ff | 501 | |
bogdanm | 0:9b334a45a8ff | 502 | /* Channel sampling time configuration */ |
bogdanm | 0:9b334a45a8ff | 503 | /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ |
bogdanm | 0:9b334a45a8ff | 504 | /* (obsolete): sampling time set in this function if parameter */ |
bogdanm | 0:9b334a45a8ff | 505 | /* "SamplingTimeCommon" has been set to a valid sampling time. */ |
bogdanm | 0:9b334a45a8ff | 506 | /* Otherwise, sampling time is set into ADC channel initialization */ |
bogdanm | 0:9b334a45a8ff | 507 | /* structure with parameter "SamplingTime" (obsolete). */ |
bogdanm | 0:9b334a45a8ff | 508 | if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) |
bogdanm | 0:9b334a45a8ff | 509 | { |
bogdanm | 0:9b334a45a8ff | 510 | /* Channel sampling time configuration */ |
bogdanm | 0:9b334a45a8ff | 511 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 512 | hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); |
bogdanm | 0:9b334a45a8ff | 513 | |
bogdanm | 0:9b334a45a8ff | 514 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 515 | hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon); |
bogdanm | 0:9b334a45a8ff | 516 | } |
bogdanm | 0:9b334a45a8ff | 517 | |
bogdanm | 0:9b334a45a8ff | 518 | /* Check back that ADC registers have effectively been configured to */ |
bogdanm | 0:9b334a45a8ff | 519 | /* ensure of no potential problem of ADC core IP clocking. */ |
bogdanm | 0:9b334a45a8ff | 520 | /* Check through register CFGR1 (excluding analog watchdog configuration: */ |
bogdanm | 0:9b334a45a8ff | 521 | /* set into separate dedicated function, and bits of ADC resolution set */ |
bogdanm | 0:9b334a45a8ff | 522 | /* out of temporary variable 'tmpCFGR1'). */ |
bogdanm | 0:9b334a45a8ff | 523 | if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) |
bogdanm | 0:9b334a45a8ff | 524 | == tmpCFGR1) |
bogdanm | 0:9b334a45a8ff | 525 | { |
bogdanm | 0:9b334a45a8ff | 526 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 527 | ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 528 | |
bogdanm | 0:9b334a45a8ff | 529 | /* Set the ADC state */ |
bogdanm | 0:9b334a45a8ff | 530 | ADC_STATE_CLR_SET(hadc->State, |
bogdanm | 0:9b334a45a8ff | 531 | HAL_ADC_STATE_BUSY_INTERNAL, |
bogdanm | 0:9b334a45a8ff | 532 | HAL_ADC_STATE_READY); |
bogdanm | 0:9b334a45a8ff | 533 | } |
bogdanm | 0:9b334a45a8ff | 534 | else |
bogdanm | 0:9b334a45a8ff | 535 | { |
bogdanm | 0:9b334a45a8ff | 536 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 537 | ADC_STATE_CLR_SET(hadc->State, |
bogdanm | 0:9b334a45a8ff | 538 | HAL_ADC_STATE_BUSY_INTERNAL, |
bogdanm | 0:9b334a45a8ff | 539 | HAL_ADC_STATE_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 540 | |
bogdanm | 0:9b334a45a8ff | 541 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 542 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 543 | |
bogdanm | 0:9b334a45a8ff | 544 | tmp_hal_status = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 545 | } |
bogdanm | 0:9b334a45a8ff | 546 | |
bogdanm | 0:9b334a45a8ff | 547 | } |
bogdanm | 0:9b334a45a8ff | 548 | else |
bogdanm | 0:9b334a45a8ff | 549 | { |
bogdanm | 0:9b334a45a8ff | 550 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 551 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 552 | |
bogdanm | 0:9b334a45a8ff | 553 | tmp_hal_status = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 554 | } |
bogdanm | 0:9b334a45a8ff | 555 | |
bogdanm | 0:9b334a45a8ff | 556 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 557 | return tmp_hal_status; |
bogdanm | 0:9b334a45a8ff | 558 | } |
bogdanm | 0:9b334a45a8ff | 559 | |
bogdanm | 0:9b334a45a8ff | 560 | |
bogdanm | 0:9b334a45a8ff | 561 | /** |
bogdanm | 0:9b334a45a8ff | 562 | * @brief Deinitialize the ADC peripheral registers to their default reset |
bogdanm | 0:9b334a45a8ff | 563 | * values, with deinitialization of the ADC MSP. |
bogdanm | 0:9b334a45a8ff | 564 | * @note For devices with several ADCs: reset of ADC common registers is done |
bogdanm | 0:9b334a45a8ff | 565 | * only if all ADCs sharing the same common group are disabled. |
bogdanm | 0:9b334a45a8ff | 566 | * If this is not the case, reset of these common parameters reset is |
bogdanm | 0:9b334a45a8ff | 567 | * bypassed without error reporting: it can be the intended behaviour in |
bogdanm | 0:9b334a45a8ff | 568 | * case of reset of a single ADC while the other ADCs sharing the same |
bogdanm | 0:9b334a45a8ff | 569 | * common group is still running. |
bogdanm | 0:9b334a45a8ff | 570 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 571 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 572 | */ |
bogdanm | 0:9b334a45a8ff | 573 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 574 | { |
bogdanm | 0:9b334a45a8ff | 575 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 576 | |
bogdanm | 0:9b334a45a8ff | 577 | /* Check ADC handle */ |
bogdanm | 0:9b334a45a8ff | 578 | if(hadc == NULL) |
bogdanm | 0:9b334a45a8ff | 579 | { |
bogdanm | 0:9b334a45a8ff | 580 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 581 | } |
bogdanm | 0:9b334a45a8ff | 582 | |
bogdanm | 0:9b334a45a8ff | 583 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 584 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 585 | |
bogdanm | 0:9b334a45a8ff | 586 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 587 | SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 588 | |
bogdanm | 0:9b334a45a8ff | 589 | /* Stop potential conversion on going, on regular group */ |
bogdanm | 0:9b334a45a8ff | 590 | tmp_hal_status = ADC_ConversionStop(hadc); |
bogdanm | 0:9b334a45a8ff | 591 | |
bogdanm | 0:9b334a45a8ff | 592 | /* Disable ADC peripheral if conversions are effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 593 | if (tmp_hal_status == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 594 | { |
bogdanm | 0:9b334a45a8ff | 595 | /* Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 596 | tmp_hal_status = ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 597 | |
bogdanm | 0:9b334a45a8ff | 598 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 599 | if (tmp_hal_status != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 600 | { |
bogdanm | 0:9b334a45a8ff | 601 | /* Change ADC state */ |
bogdanm | 0:9b334a45a8ff | 602 | hadc->State = HAL_ADC_STATE_READY; |
bogdanm | 0:9b334a45a8ff | 603 | } |
bogdanm | 0:9b334a45a8ff | 604 | } |
bogdanm | 0:9b334a45a8ff | 605 | |
bogdanm | 0:9b334a45a8ff | 606 | |
bogdanm | 0:9b334a45a8ff | 607 | /* Configuration of ADC parameters if previous preliminary actions are */ |
bogdanm | 0:9b334a45a8ff | 608 | /* correctly completed. */ |
bogdanm | 0:9b334a45a8ff | 609 | if (tmp_hal_status != HAL_ERROR) |
bogdanm | 0:9b334a45a8ff | 610 | { |
bogdanm | 0:9b334a45a8ff | 611 | |
bogdanm | 0:9b334a45a8ff | 612 | /* ========== Reset ADC registers ========== */ |
bogdanm | 0:9b334a45a8ff | 613 | /* Reset register IER */ |
bogdanm | 0:9b334a45a8ff | 614 | __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | |
bogdanm | 0:9b334a45a8ff | 615 | ADC_IT_EOS | ADC_IT_EOC | |
bogdanm | 0:9b334a45a8ff | 616 | ADC_IT_EOSMP | ADC_IT_RDY ) ); |
bogdanm | 0:9b334a45a8ff | 617 | |
bogdanm | 0:9b334a45a8ff | 618 | /* Reset register ISR */ |
bogdanm | 0:9b334a45a8ff | 619 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_OVR | |
bogdanm | 0:9b334a45a8ff | 620 | ADC_FLAG_EOS | ADC_FLAG_EOC | |
bogdanm | 0:9b334a45a8ff | 621 | ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); |
bogdanm | 0:9b334a45a8ff | 622 | |
bogdanm | 0:9b334a45a8ff | 623 | /* Reset register CR */ |
bogdanm | 0:9b334a45a8ff | 624 | /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ |
bogdanm | 0:9b334a45a8ff | 625 | /* "read-set": no direct reset applicable. */ |
bogdanm | 0:9b334a45a8ff | 626 | |
bogdanm | 0:9b334a45a8ff | 627 | /* Reset register CFGR1 */ |
bogdanm | 0:9b334a45a8ff | 628 | hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN | |
bogdanm | 0:9b334a45a8ff | 629 | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | |
bogdanm | 0:9b334a45a8ff | 630 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | |
bogdanm | 0:9b334a45a8ff | 631 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ); |
bogdanm | 0:9b334a45a8ff | 632 | |
bogdanm | 0:9b334a45a8ff | 633 | /* Reset register CFGR2 */ |
bogdanm | 0:9b334a45a8ff | 634 | /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ |
bogdanm | 0:9b334a45a8ff | 635 | /* already done above. */ |
bogdanm | 0:9b334a45a8ff | 636 | hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; |
bogdanm | 0:9b334a45a8ff | 637 | |
bogdanm | 0:9b334a45a8ff | 638 | /* Reset register SMPR */ |
bogdanm | 0:9b334a45a8ff | 639 | hadc->Instance->SMPR &= ~ADC_SMPR_SMP; |
bogdanm | 0:9b334a45a8ff | 640 | |
bogdanm | 0:9b334a45a8ff | 641 | /* Reset register TR1 */ |
bogdanm | 0:9b334a45a8ff | 642 | hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); |
bogdanm | 0:9b334a45a8ff | 643 | |
bogdanm | 0:9b334a45a8ff | 644 | /* Reset register CHSELR */ |
bogdanm | 0:9b334a45a8ff | 645 | hadc->Instance->CHSELR &= ~(ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 | |
bogdanm | 0:9b334a45a8ff | 646 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 | |
bogdanm | 0:9b334a45a8ff | 647 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 | |
bogdanm | 0:9b334a45a8ff | 648 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 | |
bogdanm | 0:9b334a45a8ff | 649 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ); |
bogdanm | 0:9b334a45a8ff | 650 | |
bogdanm | 0:9b334a45a8ff | 651 | /* Reset register DR */ |
bogdanm | 0:9b334a45a8ff | 652 | /* bits in access mode read only, no direct reset applicable*/ |
bogdanm | 0:9b334a45a8ff | 653 | |
bogdanm | 0:9b334a45a8ff | 654 | /* Reset register CCR */ |
bogdanm | 0:9b334a45a8ff | 655 | ADC->CCR &= ~(ADC_CCR_ALL); |
bogdanm | 0:9b334a45a8ff | 656 | |
bogdanm | 0:9b334a45a8ff | 657 | /* ========== Hard reset ADC peripheral ========== */ |
bogdanm | 0:9b334a45a8ff | 658 | /* Performs a global reset of the entire ADC peripheral: ADC state is */ |
bogdanm | 0:9b334a45a8ff | 659 | /* forced to a similar state after device power-on. */ |
bogdanm | 0:9b334a45a8ff | 660 | /* If needed, copy-paste and uncomment the following reset code into */ |
bogdanm | 0:9b334a45a8ff | 661 | /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ |
bogdanm | 0:9b334a45a8ff | 662 | /* */ |
bogdanm | 0:9b334a45a8ff | 663 | /* __HAL_RCC_ADC1_FORCE_RESET() */ |
bogdanm | 0:9b334a45a8ff | 664 | /* __HAL_RCC_ADC1_RELEASE_RESET() */ |
bogdanm | 0:9b334a45a8ff | 665 | |
bogdanm | 0:9b334a45a8ff | 666 | /* DeInit the low level hardware */ |
bogdanm | 0:9b334a45a8ff | 667 | HAL_ADC_MspDeInit(hadc); |
bogdanm | 0:9b334a45a8ff | 668 | |
bogdanm | 0:9b334a45a8ff | 669 | /* Set ADC error code to none */ |
bogdanm | 0:9b334a45a8ff | 670 | ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 671 | |
bogdanm | 0:9b334a45a8ff | 672 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 673 | hadc->State = HAL_ADC_STATE_RESET; |
bogdanm | 0:9b334a45a8ff | 674 | } |
bogdanm | 0:9b334a45a8ff | 675 | |
bogdanm | 0:9b334a45a8ff | 676 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 677 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 678 | |
bogdanm | 0:9b334a45a8ff | 679 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 680 | return tmp_hal_status; |
bogdanm | 0:9b334a45a8ff | 681 | } |
bogdanm | 0:9b334a45a8ff | 682 | |
bogdanm | 0:9b334a45a8ff | 683 | |
bogdanm | 0:9b334a45a8ff | 684 | /** |
bogdanm | 0:9b334a45a8ff | 685 | * @brief Initializes the ADC MSP. |
bogdanm | 0:9b334a45a8ff | 686 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 687 | * @retval None |
bogdanm | 0:9b334a45a8ff | 688 | */ |
bogdanm | 0:9b334a45a8ff | 689 | __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 690 | { |
bogdanm | 0:9b334a45a8ff | 691 | /* NOTE : This function should not be modified. When the callback is needed, |
bogdanm | 0:9b334a45a8ff | 692 | function HAL_ADC_MspInit must be implemented in the user file. |
bogdanm | 0:9b334a45a8ff | 693 | */ |
bogdanm | 0:9b334a45a8ff | 694 | } |
bogdanm | 0:9b334a45a8ff | 695 | |
bogdanm | 0:9b334a45a8ff | 696 | /** |
bogdanm | 0:9b334a45a8ff | 697 | * @brief DeInitializes the ADC MSP. |
bogdanm | 0:9b334a45a8ff | 698 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 699 | * @retval None |
bogdanm | 0:9b334a45a8ff | 700 | */ |
bogdanm | 0:9b334a45a8ff | 701 | __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 702 | { |
bogdanm | 0:9b334a45a8ff | 703 | /* NOTE : This function should not be modified. When the callback is needed, |
bogdanm | 0:9b334a45a8ff | 704 | function HAL_ADC_MspDeInit must be implemented in the user file. |
bogdanm | 0:9b334a45a8ff | 705 | */ |
bogdanm | 0:9b334a45a8ff | 706 | } |
bogdanm | 0:9b334a45a8ff | 707 | |
bogdanm | 0:9b334a45a8ff | 708 | /** |
bogdanm | 0:9b334a45a8ff | 709 | * @} |
bogdanm | 0:9b334a45a8ff | 710 | */ |
bogdanm | 0:9b334a45a8ff | 711 | |
bogdanm | 0:9b334a45a8ff | 712 | /** @defgroup ADC_Exported_Functions_Group2 IO operation functions |
bogdanm | 0:9b334a45a8ff | 713 | * @brief IO operation functions |
bogdanm | 0:9b334a45a8ff | 714 | * |
bogdanm | 0:9b334a45a8ff | 715 | @verbatim |
bogdanm | 0:9b334a45a8ff | 716 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 717 | ##### IO operation functions ##### |
bogdanm | 0:9b334a45a8ff | 718 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 719 | [..] This section provides functions allowing to: |
bogdanm | 0:9b334a45a8ff | 720 | (+) Start conversion of regular group. |
bogdanm | 0:9b334a45a8ff | 721 | (+) Stop conversion of regular group. |
bogdanm | 0:9b334a45a8ff | 722 | (+) Poll for conversion complete on regular group. |
bogdanm | 0:9b334a45a8ff | 723 | (+) Poll for conversion event. |
bogdanm | 0:9b334a45a8ff | 724 | (+) Get result of regular channel conversion. |
bogdanm | 0:9b334a45a8ff | 725 | (+) Start conversion of regular group and enable interruptions. |
bogdanm | 0:9b334a45a8ff | 726 | (+) Stop conversion of regular group and disable interruptions. |
bogdanm | 0:9b334a45a8ff | 727 | (+) Handle ADC interrupt request |
bogdanm | 0:9b334a45a8ff | 728 | (+) Start conversion of regular group and enable DMA transfer. |
bogdanm | 0:9b334a45a8ff | 729 | (+) Stop conversion of regular group and disable ADC DMA transfer. |
bogdanm | 0:9b334a45a8ff | 730 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 731 | * @{ |
bogdanm | 0:9b334a45a8ff | 732 | */ |
bogdanm | 0:9b334a45a8ff | 733 | |
bogdanm | 0:9b334a45a8ff | 734 | /** |
bogdanm | 0:9b334a45a8ff | 735 | * @brief Enables ADC, starts conversion of regular group. |
bogdanm | 0:9b334a45a8ff | 736 | * Interruptions enabled in this function: None. |
bogdanm | 0:9b334a45a8ff | 737 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 738 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 739 | */ |
bogdanm | 0:9b334a45a8ff | 740 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 741 | { |
bogdanm | 0:9b334a45a8ff | 742 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 743 | |
bogdanm | 0:9b334a45a8ff | 744 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 745 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 746 | |
bogdanm | 0:9b334a45a8ff | 747 | /* Perform ADC enable and conversion start if no conversion is on going */ |
bogdanm | 0:9b334a45a8ff | 748 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 749 | { |
bogdanm | 0:9b334a45a8ff | 750 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 751 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 752 | |
bogdanm | 0:9b334a45a8ff | 753 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 754 | /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
bogdanm | 0:9b334a45a8ff | 755 | /* performed automatically by hardware. */ |
bogdanm | 0:9b334a45a8ff | 756 | if (hadc->Init.LowPowerAutoPowerOff != ENABLE) |
bogdanm | 0:9b334a45a8ff | 757 | { |
bogdanm | 0:9b334a45a8ff | 758 | tmp_hal_status = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 759 | } |
bogdanm | 0:9b334a45a8ff | 760 | |
bogdanm | 0:9b334a45a8ff | 761 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 762 | if (tmp_hal_status == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 763 | { |
bogdanm | 0:9b334a45a8ff | 764 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 765 | /* - Clear state bitfield related to regular group conversion results */ |
bogdanm | 0:9b334a45a8ff | 766 | /* - Set state bitfield related to regular operation */ |
bogdanm | 0:9b334a45a8ff | 767 | ADC_STATE_CLR_SET(hadc->State, |
bogdanm | 0:9b334a45a8ff | 768 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
bogdanm | 0:9b334a45a8ff | 769 | HAL_ADC_STATE_REG_BUSY); |
bogdanm | 0:9b334a45a8ff | 770 | |
bogdanm | 0:9b334a45a8ff | 771 | /* Reset ADC all error code fields */ |
bogdanm | 0:9b334a45a8ff | 772 | ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 773 | |
bogdanm | 0:9b334a45a8ff | 774 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 775 | /* Unlock before starting ADC conversions: in case of potential */ |
bogdanm | 0:9b334a45a8ff | 776 | /* interruption, to let the process to ADC IRQ Handler. */ |
bogdanm | 0:9b334a45a8ff | 777 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 778 | |
bogdanm | 0:9b334a45a8ff | 779 | /* Clear regular group conversion flag and overrun flag */ |
bogdanm | 0:9b334a45a8ff | 780 | /* (To ensure of no unknown state from potential previous ADC */ |
bogdanm | 0:9b334a45a8ff | 781 | /* operations) */ |
bogdanm | 0:9b334a45a8ff | 782 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
bogdanm | 0:9b334a45a8ff | 783 | |
bogdanm | 0:9b334a45a8ff | 784 | /* Enable conversion of regular group. */ |
bogdanm | 0:9b334a45a8ff | 785 | /* If software start has been selected, conversion starts immediately. */ |
bogdanm | 0:9b334a45a8ff | 786 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 787 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 788 | hadc->Instance->CR |= ADC_CR_ADSTART; |
bogdanm | 0:9b334a45a8ff | 789 | } |
bogdanm | 0:9b334a45a8ff | 790 | } |
bogdanm | 0:9b334a45a8ff | 791 | else |
bogdanm | 0:9b334a45a8ff | 792 | { |
bogdanm | 0:9b334a45a8ff | 793 | tmp_hal_status = HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 794 | } |
bogdanm | 0:9b334a45a8ff | 795 | |
bogdanm | 0:9b334a45a8ff | 796 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 797 | return tmp_hal_status; |
bogdanm | 0:9b334a45a8ff | 798 | } |
bogdanm | 0:9b334a45a8ff | 799 | |
bogdanm | 0:9b334a45a8ff | 800 | /** |
bogdanm | 0:9b334a45a8ff | 801 | * @brief Stop ADC conversion of regular group, disable ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 802 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 803 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 804 | */ |
bogdanm | 0:9b334a45a8ff | 805 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 806 | { |
bogdanm | 0:9b334a45a8ff | 807 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 808 | |
bogdanm | 0:9b334a45a8ff | 809 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 810 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 811 | |
bogdanm | 0:9b334a45a8ff | 812 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 813 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 814 | |
bogdanm | 0:9b334a45a8ff | 815 | /* 1. Stop potential conversion on going, on regular group */ |
bogdanm | 0:9b334a45a8ff | 816 | tmp_hal_status = ADC_ConversionStop(hadc); |
bogdanm | 0:9b334a45a8ff | 817 | |
bogdanm | 0:9b334a45a8ff | 818 | /* Disable ADC peripheral if conversions are effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 819 | if (tmp_hal_status == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 820 | { |
bogdanm | 0:9b334a45a8ff | 821 | /* 2. Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 822 | tmp_hal_status = ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 823 | |
bogdanm | 0:9b334a45a8ff | 824 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 825 | if (tmp_hal_status == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 826 | { |
bogdanm | 0:9b334a45a8ff | 827 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 828 | ADC_STATE_CLR_SET(hadc->State, |
bogdanm | 0:9b334a45a8ff | 829 | HAL_ADC_STATE_REG_BUSY, |
bogdanm | 0:9b334a45a8ff | 830 | HAL_ADC_STATE_READY); |
bogdanm | 0:9b334a45a8ff | 831 | } |
bogdanm | 0:9b334a45a8ff | 832 | } |
bogdanm | 0:9b334a45a8ff | 833 | |
bogdanm | 0:9b334a45a8ff | 834 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 835 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 836 | |
bogdanm | 0:9b334a45a8ff | 837 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 838 | return tmp_hal_status; |
bogdanm | 0:9b334a45a8ff | 839 | } |
bogdanm | 0:9b334a45a8ff | 840 | |
bogdanm | 0:9b334a45a8ff | 841 | /** |
bogdanm | 0:9b334a45a8ff | 842 | * @brief Wait for regular group conversion to be completed. |
bogdanm | 0:9b334a45a8ff | 843 | * @note ADC conversion flags EOS (end of sequence) and EOC (end of |
bogdanm | 0:9b334a45a8ff | 844 | * conversion) are cleared by this function, with an exception: |
bogdanm | 0:9b334a45a8ff | 845 | * if low power feature "LowPowerAutoWait" is enabled, flags are |
bogdanm | 0:9b334a45a8ff | 846 | * not cleared to not interfere with this feature until data register |
bogdanm | 0:9b334a45a8ff | 847 | * is read using function HAL_ADC_GetValue(). |
bogdanm | 0:9b334a45a8ff | 848 | * @note This function cannot be used in a particular setup: ADC configured |
bogdanm | 0:9b334a45a8ff | 849 | * in DMA mode and polling for end of each conversion (ADC init |
bogdanm | 0:9b334a45a8ff | 850 | * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). |
bogdanm | 0:9b334a45a8ff | 851 | * In this case, DMA resets the flag EOC and polling cannot be |
bogdanm | 0:9b334a45a8ff | 852 | * performed on each conversion. Nevertheless, polling can still |
bogdanm | 0:9b334a45a8ff | 853 | * be performed on the complete sequence (ADC init |
bogdanm | 0:9b334a45a8ff | 854 | * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). |
bogdanm | 0:9b334a45a8ff | 855 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 856 | * @param Timeout: Timeout value in millisecond. |
bogdanm | 0:9b334a45a8ff | 857 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 858 | */ |
bogdanm | 0:9b334a45a8ff | 859 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
bogdanm | 0:9b334a45a8ff | 860 | { |
bogdanm | 0:9b334a45a8ff | 861 | uint32_t tickstart; |
bogdanm | 0:9b334a45a8ff | 862 | uint32_t tmp_Flag_EOC; |
bogdanm | 0:9b334a45a8ff | 863 | |
bogdanm | 0:9b334a45a8ff | 864 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 865 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 866 | |
bogdanm | 0:9b334a45a8ff | 867 | /* If end of conversion selected to end of sequence */ |
bogdanm | 0:9b334a45a8ff | 868 | if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) |
bogdanm | 0:9b334a45a8ff | 869 | { |
bogdanm | 0:9b334a45a8ff | 870 | tmp_Flag_EOC = ADC_FLAG_EOS; |
bogdanm | 0:9b334a45a8ff | 871 | } |
bogdanm | 0:9b334a45a8ff | 872 | /* If end of conversion selected to end of each conversion */ |
bogdanm | 0:9b334a45a8ff | 873 | else /* ADC_EOC_SINGLE_CONV */ |
bogdanm | 0:9b334a45a8ff | 874 | { |
bogdanm | 0:9b334a45a8ff | 875 | /* Verification that ADC configuration is compliant with polling for */ |
bogdanm | 0:9b334a45a8ff | 876 | /* each conversion: */ |
bogdanm | 0:9b334a45a8ff | 877 | /* Particular case is ADC configured in DMA mode and ADC sequencer with */ |
bogdanm | 0:9b334a45a8ff | 878 | /* several ranks and polling for end of each conversion. */ |
bogdanm | 0:9b334a45a8ff | 879 | /* For code simplicity sake, this particular case is generalized to */ |
bogdanm | 0:9b334a45a8ff | 880 | /* ADC configured in DMA mode and and polling for end of each conversion. */ |
bogdanm | 0:9b334a45a8ff | 881 | if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)) |
bogdanm | 0:9b334a45a8ff | 882 | { |
bogdanm | 0:9b334a45a8ff | 883 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 884 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
bogdanm | 0:9b334a45a8ff | 885 | |
bogdanm | 0:9b334a45a8ff | 886 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 887 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 888 | |
bogdanm | 0:9b334a45a8ff | 889 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 890 | } |
bogdanm | 0:9b334a45a8ff | 891 | else |
bogdanm | 0:9b334a45a8ff | 892 | { |
bogdanm | 0:9b334a45a8ff | 893 | tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); |
bogdanm | 0:9b334a45a8ff | 894 | } |
bogdanm | 0:9b334a45a8ff | 895 | } |
bogdanm | 0:9b334a45a8ff | 896 | |
bogdanm | 0:9b334a45a8ff | 897 | /* Get tick count */ |
bogdanm | 0:9b334a45a8ff | 898 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 899 | |
bogdanm | 0:9b334a45a8ff | 900 | /* Wait until End of Conversion flag is raised */ |
bogdanm | 0:9b334a45a8ff | 901 | while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) |
bogdanm | 0:9b334a45a8ff | 902 | { |
bogdanm | 0:9b334a45a8ff | 903 | /* Check if timeout is disabled (set to infinite wait) */ |
bogdanm | 0:9b334a45a8ff | 904 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 905 | { |
bogdanm | 0:9b334a45a8ff | 906 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 907 | { |
bogdanm | 0:9b334a45a8ff | 908 | /* Update ADC state machine to timeout */ |
bogdanm | 0:9b334a45a8ff | 909 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
bogdanm | 0:9b334a45a8ff | 910 | |
bogdanm | 0:9b334a45a8ff | 911 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 912 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 913 | |
bogdanm | 0:9b334a45a8ff | 914 | return HAL_TIMEOUT; |
bogdanm | 0:9b334a45a8ff | 915 | } |
bogdanm | 0:9b334a45a8ff | 916 | } |
bogdanm | 0:9b334a45a8ff | 917 | } |
bogdanm | 0:9b334a45a8ff | 918 | |
bogdanm | 0:9b334a45a8ff | 919 | /* Update ADC state machine */ |
bogdanm | 0:9b334a45a8ff | 920 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
bogdanm | 0:9b334a45a8ff | 921 | |
bogdanm | 0:9b334a45a8ff | 922 | /* Determine whether any further conversion upcoming on group regular */ |
bogdanm | 0:9b334a45a8ff | 923 | /* by external trigger, continuous mode or scan sequence on going. */ |
bogdanm | 0:9b334a45a8ff | 924 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
bogdanm | 0:9b334a45a8ff | 925 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
bogdanm | 0:9b334a45a8ff | 926 | { |
bogdanm | 0:9b334a45a8ff | 927 | /* If End of Sequence is reached, disable interrupts */ |
bogdanm | 0:9b334a45a8ff | 928 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
bogdanm | 0:9b334a45a8ff | 929 | { |
bogdanm | 0:9b334a45a8ff | 930 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
bogdanm | 0:9b334a45a8ff | 931 | /* ADSTART==0 (no conversion on going) */ |
bogdanm | 0:9b334a45a8ff | 932 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 933 | { |
bogdanm | 0:9b334a45a8ff | 934 | /* Disable ADC end of single conversion interrupt on group regular */ |
bogdanm | 0:9b334a45a8ff | 935 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
bogdanm | 0:9b334a45a8ff | 936 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
bogdanm | 0:9b334a45a8ff | 937 | /* by overrun IRQ process below. */ |
bogdanm | 0:9b334a45a8ff | 938 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
bogdanm | 0:9b334a45a8ff | 939 | |
bogdanm | 0:9b334a45a8ff | 940 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 941 | ADC_STATE_CLR_SET(hadc->State, |
bogdanm | 0:9b334a45a8ff | 942 | HAL_ADC_STATE_REG_BUSY, |
bogdanm | 0:9b334a45a8ff | 943 | HAL_ADC_STATE_READY); |
bogdanm | 0:9b334a45a8ff | 944 | } |
bogdanm | 0:9b334a45a8ff | 945 | else |
bogdanm | 0:9b334a45a8ff | 946 | { |
bogdanm | 0:9b334a45a8ff | 947 | /* Change ADC state to error state */ |
bogdanm | 0:9b334a45a8ff | 948 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
bogdanm | 0:9b334a45a8ff | 949 | |
bogdanm | 0:9b334a45a8ff | 950 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 951 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 952 | } |
bogdanm | 0:9b334a45a8ff | 953 | } |
bogdanm | 0:9b334a45a8ff | 954 | } |
bogdanm | 0:9b334a45a8ff | 955 | |
bogdanm | 0:9b334a45a8ff | 956 | /* Clear end of conversion flag of regular group if low power feature */ |
bogdanm | 0:9b334a45a8ff | 957 | /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ |
bogdanm | 0:9b334a45a8ff | 958 | /* until data register is read using function HAL_ADC_GetValue(). */ |
bogdanm | 0:9b334a45a8ff | 959 | if (hadc->Init.LowPowerAutoWait == DISABLE) |
bogdanm | 0:9b334a45a8ff | 960 | { |
bogdanm | 0:9b334a45a8ff | 961 | /* Clear regular group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 962 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); |
bogdanm | 0:9b334a45a8ff | 963 | } |
bogdanm | 0:9b334a45a8ff | 964 | |
bogdanm | 0:9b334a45a8ff | 965 | /* Return ADC state */ |
bogdanm | 0:9b334a45a8ff | 966 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 967 | } |
bogdanm | 0:9b334a45a8ff | 968 | |
bogdanm | 0:9b334a45a8ff | 969 | /** |
bogdanm | 0:9b334a45a8ff | 970 | * @brief Poll for conversion event. |
bogdanm | 0:9b334a45a8ff | 971 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 972 | * @param EventType: the ADC event type. |
bogdanm | 0:9b334a45a8ff | 973 | * This parameter can be one of the following values: |
bogdanm | 0:9b334a45a8ff | 974 | * @arg ADC_AWD_EVENT: ADC Analog watchdog event |
bogdanm | 0:9b334a45a8ff | 975 | * @arg ADC_OVR_EVENT: ADC Overrun event |
bogdanm | 0:9b334a45a8ff | 976 | * @param Timeout: Timeout value in millisecond. |
bogdanm | 0:9b334a45a8ff | 977 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 978 | */ |
bogdanm | 0:9b334a45a8ff | 979 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
bogdanm | 0:9b334a45a8ff | 980 | { |
bogdanm | 0:9b334a45a8ff | 981 | uint32_t tickstart=0; |
bogdanm | 0:9b334a45a8ff | 982 | |
bogdanm | 0:9b334a45a8ff | 983 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 984 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 985 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
bogdanm | 0:9b334a45a8ff | 986 | |
bogdanm | 0:9b334a45a8ff | 987 | /* Get tick count */ |
bogdanm | 0:9b334a45a8ff | 988 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 989 | |
bogdanm | 0:9b334a45a8ff | 990 | /* Check selected event flag */ |
bogdanm | 0:9b334a45a8ff | 991 | while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
bogdanm | 0:9b334a45a8ff | 992 | { |
bogdanm | 0:9b334a45a8ff | 993 | /* Check if timeout is disabled (set to infinite wait) */ |
bogdanm | 0:9b334a45a8ff | 994 | if(Timeout != HAL_MAX_DELAY) |
bogdanm | 0:9b334a45a8ff | 995 | { |
bogdanm | 0:9b334a45a8ff | 996 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
bogdanm | 0:9b334a45a8ff | 997 | { |
bogdanm | 0:9b334a45a8ff | 998 | /* Update ADC state machine to timeout */ |
bogdanm | 0:9b334a45a8ff | 999 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
bogdanm | 0:9b334a45a8ff | 1000 | |
bogdanm | 0:9b334a45a8ff | 1001 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1002 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1003 | |
bogdanm | 0:9b334a45a8ff | 1004 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1005 | } |
bogdanm | 0:9b334a45a8ff | 1006 | } |
bogdanm | 0:9b334a45a8ff | 1007 | } |
bogdanm | 0:9b334a45a8ff | 1008 | |
bogdanm | 0:9b334a45a8ff | 1009 | switch(EventType) |
bogdanm | 0:9b334a45a8ff | 1010 | { |
bogdanm | 0:9b334a45a8ff | 1011 | /* Analog watchdog (level out of window) event */ |
bogdanm | 0:9b334a45a8ff | 1012 | case ADC_AWD_EVENT: |
bogdanm | 0:9b334a45a8ff | 1013 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 1014 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
bogdanm | 0:9b334a45a8ff | 1015 | |
bogdanm | 0:9b334a45a8ff | 1016 | /* Clear ADC analog watchdog flag */ |
bogdanm | 0:9b334a45a8ff | 1017 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
bogdanm | 0:9b334a45a8ff | 1018 | break; |
bogdanm | 0:9b334a45a8ff | 1019 | |
bogdanm | 0:9b334a45a8ff | 1020 | /* Overrun event */ |
bogdanm | 0:9b334a45a8ff | 1021 | default: /* Case ADC_OVR_EVENT */ |
bogdanm | 0:9b334a45a8ff | 1022 | /* If overrun is set to overwrite previous data, overrun event is not */ |
bogdanm | 0:9b334a45a8ff | 1023 | /* considered as an error. */ |
bogdanm | 0:9b334a45a8ff | 1024 | /* (cf ref manual "Managing conversions without using the DMA and without */ |
bogdanm | 0:9b334a45a8ff | 1025 | /* overrun ") */ |
bogdanm | 0:9b334a45a8ff | 1026 | if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) |
bogdanm | 0:9b334a45a8ff | 1027 | { |
bogdanm | 0:9b334a45a8ff | 1028 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 1029 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); |
bogdanm | 0:9b334a45a8ff | 1030 | |
bogdanm | 0:9b334a45a8ff | 1031 | /* Set ADC error code to overrun */ |
bogdanm | 0:9b334a45a8ff | 1032 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
bogdanm | 0:9b334a45a8ff | 1033 | } |
bogdanm | 0:9b334a45a8ff | 1034 | |
bogdanm | 0:9b334a45a8ff | 1035 | /* Clear ADC Overrun flag */ |
bogdanm | 0:9b334a45a8ff | 1036 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
bogdanm | 0:9b334a45a8ff | 1037 | break; |
bogdanm | 0:9b334a45a8ff | 1038 | } |
bogdanm | 0:9b334a45a8ff | 1039 | |
bogdanm | 0:9b334a45a8ff | 1040 | /* Return ADC state */ |
bogdanm | 0:9b334a45a8ff | 1041 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1042 | } |
bogdanm | 0:9b334a45a8ff | 1043 | |
bogdanm | 0:9b334a45a8ff | 1044 | /** |
bogdanm | 0:9b334a45a8ff | 1045 | * @brief Enables ADC, starts conversion of regular group with interruption. |
bogdanm | 0:9b334a45a8ff | 1046 | * Interruptions enabled in this function: |
bogdanm | 0:9b334a45a8ff | 1047 | * - EOC (end of conversion of regular group) or EOS (end of |
bogdanm | 0:9b334a45a8ff | 1048 | * sequence of regular group) depending on ADC initialization |
bogdanm | 0:9b334a45a8ff | 1049 | * parameter "EOCSelection" |
bogdanm | 0:9b334a45a8ff | 1050 | * - overrun (if available) |
bogdanm | 0:9b334a45a8ff | 1051 | * Each of these interruptions has its dedicated callback function. |
bogdanm | 0:9b334a45a8ff | 1052 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1053 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1054 | */ |
bogdanm | 0:9b334a45a8ff | 1055 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1056 | { |
bogdanm | 0:9b334a45a8ff | 1057 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1058 | |
bogdanm | 0:9b334a45a8ff | 1059 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1060 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1061 | |
bogdanm | 0:9b334a45a8ff | 1062 | /* Perform ADC enable and conversion start if no conversion is on going */ |
bogdanm | 0:9b334a45a8ff | 1063 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 1064 | { |
bogdanm | 0:9b334a45a8ff | 1065 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 1066 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1067 | |
bogdanm | 0:9b334a45a8ff | 1068 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1069 | /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
bogdanm | 0:9b334a45a8ff | 1070 | /* performed automatically by hardware. */ |
bogdanm | 0:9b334a45a8ff | 1071 | if (hadc->Init.LowPowerAutoPowerOff != ENABLE) |
bogdanm | 0:9b334a45a8ff | 1072 | { |
bogdanm | 0:9b334a45a8ff | 1073 | tmp_hal_status = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 1074 | } |
bogdanm | 0:9b334a45a8ff | 1075 | |
bogdanm | 0:9b334a45a8ff | 1076 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 1077 | if (tmp_hal_status == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 1078 | { |
bogdanm | 0:9b334a45a8ff | 1079 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 1080 | /* - Clear state bitfield related to regular group conversion results */ |
bogdanm | 0:9b334a45a8ff | 1081 | /* - Set state bitfield related to regular operation */ |
bogdanm | 0:9b334a45a8ff | 1082 | ADC_STATE_CLR_SET(hadc->State, |
bogdanm | 0:9b334a45a8ff | 1083 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
bogdanm | 0:9b334a45a8ff | 1084 | HAL_ADC_STATE_REG_BUSY); |
bogdanm | 0:9b334a45a8ff | 1085 | |
bogdanm | 0:9b334a45a8ff | 1086 | /* Reset ADC all error code fields */ |
bogdanm | 0:9b334a45a8ff | 1087 | ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 1088 | |
bogdanm | 0:9b334a45a8ff | 1089 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1090 | /* Unlock before starting ADC conversions: in case of potential */ |
bogdanm | 0:9b334a45a8ff | 1091 | /* interruption, to let the process to ADC IRQ Handler. */ |
bogdanm | 0:9b334a45a8ff | 1092 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1093 | |
bogdanm | 0:9b334a45a8ff | 1094 | /* Clear regular group conversion flag and overrun flag */ |
bogdanm | 0:9b334a45a8ff | 1095 | /* (To ensure of no unknown state from potential previous ADC */ |
bogdanm | 0:9b334a45a8ff | 1096 | /* operations) */ |
bogdanm | 0:9b334a45a8ff | 1097 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
bogdanm | 0:9b334a45a8ff | 1098 | |
bogdanm | 0:9b334a45a8ff | 1099 | /* Enable ADC end of conversion interrupt */ |
bogdanm | 0:9b334a45a8ff | 1100 | /* Enable ADC overrun interrupt */ |
bogdanm | 0:9b334a45a8ff | 1101 | switch(hadc->Init.EOCSelection) |
bogdanm | 0:9b334a45a8ff | 1102 | { |
bogdanm | 0:9b334a45a8ff | 1103 | case ADC_EOC_SEQ_CONV: |
bogdanm | 0:9b334a45a8ff | 1104 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
bogdanm | 0:9b334a45a8ff | 1105 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR)); |
bogdanm | 0:9b334a45a8ff | 1106 | break; |
bogdanm | 0:9b334a45a8ff | 1107 | /* case ADC_EOC_SINGLE_CONV */ |
bogdanm | 0:9b334a45a8ff | 1108 | default: |
bogdanm | 0:9b334a45a8ff | 1109 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); |
bogdanm | 0:9b334a45a8ff | 1110 | break; |
bogdanm | 0:9b334a45a8ff | 1111 | } |
bogdanm | 0:9b334a45a8ff | 1112 | |
bogdanm | 0:9b334a45a8ff | 1113 | /* Enable conversion of regular group. */ |
bogdanm | 0:9b334a45a8ff | 1114 | /* If software start has been selected, conversion starts immediately. */ |
bogdanm | 0:9b334a45a8ff | 1115 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 1116 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 1117 | hadc->Instance->CR |= ADC_CR_ADSTART; |
bogdanm | 0:9b334a45a8ff | 1118 | } |
bogdanm | 0:9b334a45a8ff | 1119 | } |
bogdanm | 0:9b334a45a8ff | 1120 | else |
bogdanm | 0:9b334a45a8ff | 1121 | { |
bogdanm | 0:9b334a45a8ff | 1122 | tmp_hal_status = HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 1123 | } |
bogdanm | 0:9b334a45a8ff | 1124 | |
bogdanm | 0:9b334a45a8ff | 1125 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1126 | return tmp_hal_status; |
bogdanm | 0:9b334a45a8ff | 1127 | } |
bogdanm | 0:9b334a45a8ff | 1128 | |
bogdanm | 0:9b334a45a8ff | 1129 | |
bogdanm | 0:9b334a45a8ff | 1130 | /** |
bogdanm | 0:9b334a45a8ff | 1131 | * @brief Stop ADC conversion of regular group, disable interruption of |
bogdanm | 0:9b334a45a8ff | 1132 | * end-of-conversion, disable ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 1133 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1134 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 1135 | */ |
bogdanm | 0:9b334a45a8ff | 1136 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1137 | { |
bogdanm | 0:9b334a45a8ff | 1138 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1139 | |
bogdanm | 0:9b334a45a8ff | 1140 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1141 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1142 | |
bogdanm | 0:9b334a45a8ff | 1143 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 1144 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1145 | |
bogdanm | 0:9b334a45a8ff | 1146 | /* 1. Stop potential conversion on going, on regular group */ |
bogdanm | 0:9b334a45a8ff | 1147 | tmp_hal_status = ADC_ConversionStop(hadc); |
bogdanm | 0:9b334a45a8ff | 1148 | |
bogdanm | 0:9b334a45a8ff | 1149 | /* Disable ADC peripheral if conversions are effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 1150 | if (tmp_hal_status == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 1151 | { |
bogdanm | 0:9b334a45a8ff | 1152 | /* Disable ADC end of conversion interrupt for regular group */ |
bogdanm | 0:9b334a45a8ff | 1153 | /* Disable ADC overrun interrupt */ |
bogdanm | 0:9b334a45a8ff | 1154 | __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); |
bogdanm | 0:9b334a45a8ff | 1155 | |
bogdanm | 0:9b334a45a8ff | 1156 | /* 2. Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1157 | tmp_hal_status = ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 1158 | |
bogdanm | 0:9b334a45a8ff | 1159 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 1160 | if (tmp_hal_status == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 1161 | { |
bogdanm | 0:9b334a45a8ff | 1162 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 1163 | ADC_STATE_CLR_SET(hadc->State, |
bogdanm | 0:9b334a45a8ff | 1164 | HAL_ADC_STATE_REG_BUSY, |
bogdanm | 0:9b334a45a8ff | 1165 | HAL_ADC_STATE_READY); |
bogdanm | 0:9b334a45a8ff | 1166 | } |
bogdanm | 0:9b334a45a8ff | 1167 | } |
bogdanm | 0:9b334a45a8ff | 1168 | |
bogdanm | 0:9b334a45a8ff | 1169 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1170 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1171 | |
bogdanm | 0:9b334a45a8ff | 1172 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1173 | return tmp_hal_status; |
bogdanm | 0:9b334a45a8ff | 1174 | } |
bogdanm | 0:9b334a45a8ff | 1175 | |
bogdanm | 0:9b334a45a8ff | 1176 | /** |
bogdanm | 0:9b334a45a8ff | 1177 | * @brief Enables ADC, starts conversion of regular group and transfers result |
bogdanm | 0:9b334a45a8ff | 1178 | * through DMA. |
bogdanm | 0:9b334a45a8ff | 1179 | * Interruptions enabled in this function: |
bogdanm | 0:9b334a45a8ff | 1180 | * - DMA transfer complete |
bogdanm | 0:9b334a45a8ff | 1181 | * - DMA half transfer |
bogdanm | 0:9b334a45a8ff | 1182 | * - overrun |
bogdanm | 0:9b334a45a8ff | 1183 | * Each of these interruptions has its dedicated callback function. |
bogdanm | 0:9b334a45a8ff | 1184 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1185 | * @param pData: The destination Buffer address. |
bogdanm | 0:9b334a45a8ff | 1186 | * @param Length: The length of data to be transferred from ADC peripheral to memory. |
bogdanm | 0:9b334a45a8ff | 1187 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1188 | */ |
bogdanm | 0:9b334a45a8ff | 1189 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
bogdanm | 0:9b334a45a8ff | 1190 | { |
bogdanm | 0:9b334a45a8ff | 1191 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1192 | |
bogdanm | 0:9b334a45a8ff | 1193 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1194 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1195 | |
bogdanm | 0:9b334a45a8ff | 1196 | /* Perform ADC enable and conversion start if no conversion is on going */ |
bogdanm | 0:9b334a45a8ff | 1197 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 1198 | { |
bogdanm | 0:9b334a45a8ff | 1199 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 1200 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1201 | |
bogdanm | 0:9b334a45a8ff | 1202 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1203 | /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
bogdanm | 0:9b334a45a8ff | 1204 | /* performed automatically by hardware. */ |
bogdanm | 0:9b334a45a8ff | 1205 | if (hadc->Init.LowPowerAutoPowerOff != ENABLE) |
bogdanm | 0:9b334a45a8ff | 1206 | { |
bogdanm | 0:9b334a45a8ff | 1207 | tmp_hal_status = ADC_Enable(hadc); |
bogdanm | 0:9b334a45a8ff | 1208 | } |
bogdanm | 0:9b334a45a8ff | 1209 | |
bogdanm | 0:9b334a45a8ff | 1210 | /* Start conversion if ADC is effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 1211 | if (tmp_hal_status == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 1212 | { |
bogdanm | 0:9b334a45a8ff | 1213 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 1214 | /* - Clear state bitfield related to regular group conversion results */ |
bogdanm | 0:9b334a45a8ff | 1215 | /* - Set state bitfield related to regular operation */ |
bogdanm | 0:9b334a45a8ff | 1216 | ADC_STATE_CLR_SET(hadc->State, |
bogdanm | 0:9b334a45a8ff | 1217 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
bogdanm | 0:9b334a45a8ff | 1218 | HAL_ADC_STATE_REG_BUSY); |
bogdanm | 0:9b334a45a8ff | 1219 | |
bogdanm | 0:9b334a45a8ff | 1220 | /* Reset ADC all error code fields */ |
bogdanm | 0:9b334a45a8ff | 1221 | ADC_CLEAR_ERRORCODE(hadc); |
bogdanm | 0:9b334a45a8ff | 1222 | |
bogdanm | 0:9b334a45a8ff | 1223 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1224 | /* Unlock before starting ADC conversions: in case of potential */ |
bogdanm | 0:9b334a45a8ff | 1225 | /* interruption, to let the process to ADC IRQ Handler. */ |
bogdanm | 0:9b334a45a8ff | 1226 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1227 | |
bogdanm | 0:9b334a45a8ff | 1228 | /* Set the DMA transfer complete callback */ |
bogdanm | 0:9b334a45a8ff | 1229 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
bogdanm | 0:9b334a45a8ff | 1230 | |
bogdanm | 0:9b334a45a8ff | 1231 | /* Set the DMA half transfer complete callback */ |
bogdanm | 0:9b334a45a8ff | 1232 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
bogdanm | 0:9b334a45a8ff | 1233 | |
bogdanm | 0:9b334a45a8ff | 1234 | /* Set the DMA error callback */ |
bogdanm | 0:9b334a45a8ff | 1235 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
bogdanm | 0:9b334a45a8ff | 1236 | |
bogdanm | 0:9b334a45a8ff | 1237 | |
bogdanm | 0:9b334a45a8ff | 1238 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
bogdanm | 0:9b334a45a8ff | 1239 | /* start (in case of SW start): */ |
bogdanm | 0:9b334a45a8ff | 1240 | |
bogdanm | 0:9b334a45a8ff | 1241 | /* Clear regular group conversion flag and overrun flag */ |
bogdanm | 0:9b334a45a8ff | 1242 | /* (To ensure of no unknown state from potential previous ADC */ |
bogdanm | 0:9b334a45a8ff | 1243 | /* operations) */ |
bogdanm | 0:9b334a45a8ff | 1244 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
bogdanm | 0:9b334a45a8ff | 1245 | |
bogdanm | 0:9b334a45a8ff | 1246 | /* Enable ADC overrun interrupt */ |
bogdanm | 0:9b334a45a8ff | 1247 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); |
bogdanm | 0:9b334a45a8ff | 1248 | |
bogdanm | 0:9b334a45a8ff | 1249 | /* Enable ADC DMA mode */ |
bogdanm | 0:9b334a45a8ff | 1250 | hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; |
bogdanm | 0:9b334a45a8ff | 1251 | |
bogdanm | 0:9b334a45a8ff | 1252 | /* Start the DMA channel */ |
bogdanm | 0:9b334a45a8ff | 1253 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
bogdanm | 0:9b334a45a8ff | 1254 | |
bogdanm | 0:9b334a45a8ff | 1255 | /* Enable conversion of regular group. */ |
bogdanm | 0:9b334a45a8ff | 1256 | /* If software start has been selected, conversion starts immediately. */ |
bogdanm | 0:9b334a45a8ff | 1257 | /* If external trigger has been selected, conversion will start at next */ |
bogdanm | 0:9b334a45a8ff | 1258 | /* trigger event. */ |
bogdanm | 0:9b334a45a8ff | 1259 | hadc->Instance->CR |= ADC_CR_ADSTART; |
bogdanm | 0:9b334a45a8ff | 1260 | } |
bogdanm | 0:9b334a45a8ff | 1261 | } |
bogdanm | 0:9b334a45a8ff | 1262 | else |
bogdanm | 0:9b334a45a8ff | 1263 | { |
bogdanm | 0:9b334a45a8ff | 1264 | tmp_hal_status = HAL_BUSY; |
bogdanm | 0:9b334a45a8ff | 1265 | } |
bogdanm | 0:9b334a45a8ff | 1266 | |
bogdanm | 0:9b334a45a8ff | 1267 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1268 | return tmp_hal_status; |
bogdanm | 0:9b334a45a8ff | 1269 | } |
bogdanm | 0:9b334a45a8ff | 1270 | |
bogdanm | 0:9b334a45a8ff | 1271 | /** |
bogdanm | 0:9b334a45a8ff | 1272 | * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable |
bogdanm | 0:9b334a45a8ff | 1273 | * ADC peripheral. |
bogdanm | 0:9b334a45a8ff | 1274 | * Each of these interruptions has its dedicated callback function. |
bogdanm | 0:9b334a45a8ff | 1275 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1276 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 1277 | */ |
bogdanm | 0:9b334a45a8ff | 1278 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1279 | { |
bogdanm | 0:9b334a45a8ff | 1280 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1281 | |
bogdanm | 0:9b334a45a8ff | 1282 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1283 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1284 | |
bogdanm | 0:9b334a45a8ff | 1285 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 1286 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1287 | |
bogdanm | 0:9b334a45a8ff | 1288 | /* 1. Stop potential conversion on going, on regular group */ |
bogdanm | 0:9b334a45a8ff | 1289 | tmp_hal_status = ADC_ConversionStop(hadc); |
bogdanm | 0:9b334a45a8ff | 1290 | |
bogdanm | 0:9b334a45a8ff | 1291 | /* Disable ADC peripheral if conversions are effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 1292 | if (tmp_hal_status == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 1293 | { |
bogdanm | 0:9b334a45a8ff | 1294 | /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ |
bogdanm | 0:9b334a45a8ff | 1295 | hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN; |
bogdanm | 0:9b334a45a8ff | 1296 | |
bogdanm | 0:9b334a45a8ff | 1297 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
bogdanm | 0:9b334a45a8ff | 1298 | /* while DMA transfer is on going) */ |
bogdanm | 0:9b334a45a8ff | 1299 | tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); |
bogdanm | 0:9b334a45a8ff | 1300 | |
bogdanm | 0:9b334a45a8ff | 1301 | /* Check if DMA channel effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 1302 | if (tmp_hal_status != HAL_OK) |
bogdanm | 0:9b334a45a8ff | 1303 | { |
bogdanm | 0:9b334a45a8ff | 1304 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 1305 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
bogdanm | 0:9b334a45a8ff | 1306 | } |
bogdanm | 0:9b334a45a8ff | 1307 | |
bogdanm | 0:9b334a45a8ff | 1308 | /* Disable ADC overrun interrupt */ |
bogdanm | 0:9b334a45a8ff | 1309 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); |
bogdanm | 0:9b334a45a8ff | 1310 | |
bogdanm | 0:9b334a45a8ff | 1311 | /* 2. Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1312 | /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ |
bogdanm | 0:9b334a45a8ff | 1313 | /* in memory a potential failing status. */ |
bogdanm | 0:9b334a45a8ff | 1314 | if (tmp_hal_status == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 1315 | { |
bogdanm | 0:9b334a45a8ff | 1316 | tmp_hal_status = ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 1317 | } |
bogdanm | 0:9b334a45a8ff | 1318 | else |
bogdanm | 0:9b334a45a8ff | 1319 | { |
bogdanm | 0:9b334a45a8ff | 1320 | ADC_Disable(hadc); |
bogdanm | 0:9b334a45a8ff | 1321 | } |
bogdanm | 0:9b334a45a8ff | 1322 | |
bogdanm | 0:9b334a45a8ff | 1323 | /* Check if ADC is effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 1324 | if (tmp_hal_status == HAL_OK) |
bogdanm | 0:9b334a45a8ff | 1325 | { |
bogdanm | 0:9b334a45a8ff | 1326 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 1327 | ADC_STATE_CLR_SET(hadc->State, |
bogdanm | 0:9b334a45a8ff | 1328 | HAL_ADC_STATE_REG_BUSY, |
bogdanm | 0:9b334a45a8ff | 1329 | HAL_ADC_STATE_READY); |
bogdanm | 0:9b334a45a8ff | 1330 | } |
bogdanm | 0:9b334a45a8ff | 1331 | |
bogdanm | 0:9b334a45a8ff | 1332 | } |
bogdanm | 0:9b334a45a8ff | 1333 | |
bogdanm | 0:9b334a45a8ff | 1334 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1335 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1336 | |
bogdanm | 0:9b334a45a8ff | 1337 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1338 | return tmp_hal_status; |
bogdanm | 0:9b334a45a8ff | 1339 | } |
bogdanm | 0:9b334a45a8ff | 1340 | |
bogdanm | 0:9b334a45a8ff | 1341 | /** |
bogdanm | 0:9b334a45a8ff | 1342 | * @brief Get ADC regular group conversion result. |
bogdanm | 0:9b334a45a8ff | 1343 | * @note Reading DR register automatically clears EOC (end of conversion of |
bogdanm | 0:9b334a45a8ff | 1344 | * regular group) flag. |
bogdanm | 0:9b334a45a8ff | 1345 | * Additionally, this functions clears EOS (end of sequence of |
bogdanm | 0:9b334a45a8ff | 1346 | * regular group) flag, in case of the end of the sequence is reached. |
bogdanm | 0:9b334a45a8ff | 1347 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1348 | * @retval Converted value |
bogdanm | 0:9b334a45a8ff | 1349 | */ |
bogdanm | 0:9b334a45a8ff | 1350 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1351 | { |
bogdanm | 0:9b334a45a8ff | 1352 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1353 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1354 | |
bogdanm | 0:9b334a45a8ff | 1355 | /* Note: EOC flag is not cleared here by software because automatically */ |
bogdanm | 0:9b334a45a8ff | 1356 | /* cleared by hardware when reading register DR. */ |
bogdanm | 0:9b334a45a8ff | 1357 | |
bogdanm | 0:9b334a45a8ff | 1358 | /* Clear regular group end of sequence flag */ |
bogdanm | 0:9b334a45a8ff | 1359 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); |
bogdanm | 0:9b334a45a8ff | 1360 | |
bogdanm | 0:9b334a45a8ff | 1361 | /* Return ADC converted value */ |
bogdanm | 0:9b334a45a8ff | 1362 | return hadc->Instance->DR; |
bogdanm | 0:9b334a45a8ff | 1363 | } |
bogdanm | 0:9b334a45a8ff | 1364 | |
bogdanm | 0:9b334a45a8ff | 1365 | /** |
bogdanm | 0:9b334a45a8ff | 1366 | * @brief Handles ADC interrupt request. |
bogdanm | 0:9b334a45a8ff | 1367 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1368 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1369 | */ |
bogdanm | 0:9b334a45a8ff | 1370 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1371 | { |
bogdanm | 0:9b334a45a8ff | 1372 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1373 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1374 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
bogdanm | 0:9b334a45a8ff | 1375 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
bogdanm | 0:9b334a45a8ff | 1376 | |
bogdanm | 0:9b334a45a8ff | 1377 | /* ========== Check End of Conversion flag for regular group ========== */ |
bogdanm | 0:9b334a45a8ff | 1378 | if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || |
bogdanm | 0:9b334a45a8ff | 1379 | (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) |
bogdanm | 0:9b334a45a8ff | 1380 | { |
bogdanm | 0:9b334a45a8ff | 1381 | /* Update state machine on conversion status if not in error state */ |
bogdanm | 0:9b334a45a8ff | 1382 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
bogdanm | 0:9b334a45a8ff | 1383 | { |
bogdanm | 0:9b334a45a8ff | 1384 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 1385 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
bogdanm | 0:9b334a45a8ff | 1386 | } |
bogdanm | 0:9b334a45a8ff | 1387 | |
bogdanm | 0:9b334a45a8ff | 1388 | /* Determine whether any further conversion upcoming on group regular */ |
bogdanm | 0:9b334a45a8ff | 1389 | /* by external trigger, continuous mode or scan sequence on going. */ |
bogdanm | 0:9b334a45a8ff | 1390 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
bogdanm | 0:9b334a45a8ff | 1391 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
bogdanm | 0:9b334a45a8ff | 1392 | { |
bogdanm | 0:9b334a45a8ff | 1393 | /* If End of Sequence is reached, disable interrupts */ |
bogdanm | 0:9b334a45a8ff | 1394 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
bogdanm | 0:9b334a45a8ff | 1395 | { |
bogdanm | 0:9b334a45a8ff | 1396 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
bogdanm | 0:9b334a45a8ff | 1397 | /* ADSTART==0 (no conversion on going) */ |
bogdanm | 0:9b334a45a8ff | 1398 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 1399 | { |
bogdanm | 0:9b334a45a8ff | 1400 | /* Disable ADC end of single conversion interrupt on group regular */ |
bogdanm | 0:9b334a45a8ff | 1401 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
bogdanm | 0:9b334a45a8ff | 1402 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
bogdanm | 0:9b334a45a8ff | 1403 | /* by overrun IRQ process below. */ |
bogdanm | 0:9b334a45a8ff | 1404 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
bogdanm | 0:9b334a45a8ff | 1405 | |
bogdanm | 0:9b334a45a8ff | 1406 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 1407 | ADC_STATE_CLR_SET(hadc->State, |
bogdanm | 0:9b334a45a8ff | 1408 | HAL_ADC_STATE_REG_BUSY, |
bogdanm | 0:9b334a45a8ff | 1409 | HAL_ADC_STATE_READY); |
bogdanm | 0:9b334a45a8ff | 1410 | } |
bogdanm | 0:9b334a45a8ff | 1411 | else |
bogdanm | 0:9b334a45a8ff | 1412 | { |
bogdanm | 0:9b334a45a8ff | 1413 | /* Change ADC state to error state */ |
bogdanm | 0:9b334a45a8ff | 1414 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
bogdanm | 0:9b334a45a8ff | 1415 | |
bogdanm | 0:9b334a45a8ff | 1416 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 1417 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 1418 | } |
bogdanm | 0:9b334a45a8ff | 1419 | } |
bogdanm | 0:9b334a45a8ff | 1420 | } |
bogdanm | 0:9b334a45a8ff | 1421 | |
bogdanm | 0:9b334a45a8ff | 1422 | /* Conversion complete callback */ |
bogdanm | 0:9b334a45a8ff | 1423 | /* Note: into callback, to determine if conversion has been triggered */ |
bogdanm | 0:9b334a45a8ff | 1424 | /* from EOC or EOS, possibility to use: */ |
bogdanm | 0:9b334a45a8ff | 1425 | /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ |
bogdanm | 0:9b334a45a8ff | 1426 | HAL_ADC_ConvCpltCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 1427 | |
bogdanm | 0:9b334a45a8ff | 1428 | |
bogdanm | 0:9b334a45a8ff | 1429 | /* Clear regular group conversion flag */ |
bogdanm | 0:9b334a45a8ff | 1430 | /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ |
bogdanm | 0:9b334a45a8ff | 1431 | /* conversion flags clear induces the release of the preserved data.*/ |
bogdanm | 0:9b334a45a8ff | 1432 | /* Therefore, if the preserved data value is needed, it must be */ |
bogdanm | 0:9b334a45a8ff | 1433 | /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ |
bogdanm | 0:9b334a45a8ff | 1434 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); |
bogdanm | 0:9b334a45a8ff | 1435 | } |
bogdanm | 0:9b334a45a8ff | 1436 | |
bogdanm | 0:9b334a45a8ff | 1437 | /* ========== Check Analog watchdog flags ========== */ |
bogdanm | 0:9b334a45a8ff | 1438 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) |
bogdanm | 0:9b334a45a8ff | 1439 | { |
bogdanm | 0:9b334a45a8ff | 1440 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 1441 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
bogdanm | 0:9b334a45a8ff | 1442 | |
bogdanm | 0:9b334a45a8ff | 1443 | /* Level out of window callback */ |
bogdanm | 0:9b334a45a8ff | 1444 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 1445 | |
bogdanm | 0:9b334a45a8ff | 1446 | /* Clear ADC Analog watchdog flag */ |
bogdanm | 0:9b334a45a8ff | 1447 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
bogdanm | 0:9b334a45a8ff | 1448 | |
bogdanm | 0:9b334a45a8ff | 1449 | } |
bogdanm | 0:9b334a45a8ff | 1450 | |
bogdanm | 0:9b334a45a8ff | 1451 | |
bogdanm | 0:9b334a45a8ff | 1452 | /* ========== Check Overrun flag ========== */ |
bogdanm | 0:9b334a45a8ff | 1453 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) |
bogdanm | 0:9b334a45a8ff | 1454 | { |
bogdanm | 0:9b334a45a8ff | 1455 | /* If overrun is set to overwrite previous data (default setting), */ |
bogdanm | 0:9b334a45a8ff | 1456 | /* overrun event is not considered as an error. */ |
bogdanm | 0:9b334a45a8ff | 1457 | /* (cf ref manual "Managing conversions without using the DMA and without */ |
bogdanm | 0:9b334a45a8ff | 1458 | /* overrun ") */ |
bogdanm | 0:9b334a45a8ff | 1459 | /* Exception for usage with DMA overrun event always considered as an */ |
bogdanm | 0:9b334a45a8ff | 1460 | /* error. */ |
bogdanm | 0:9b334a45a8ff | 1461 | if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) || |
bogdanm | 0:9b334a45a8ff | 1462 | HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) ) |
bogdanm | 0:9b334a45a8ff | 1463 | { |
bogdanm | 0:9b334a45a8ff | 1464 | /* Set ADC error code to overrun */ |
bogdanm | 0:9b334a45a8ff | 1465 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
bogdanm | 0:9b334a45a8ff | 1466 | |
bogdanm | 0:9b334a45a8ff | 1467 | /* Clear ADC overrun flag */ |
bogdanm | 0:9b334a45a8ff | 1468 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
bogdanm | 0:9b334a45a8ff | 1469 | |
bogdanm | 0:9b334a45a8ff | 1470 | /* Error callback */ |
bogdanm | 0:9b334a45a8ff | 1471 | HAL_ADC_ErrorCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 1472 | } |
bogdanm | 0:9b334a45a8ff | 1473 | |
bogdanm | 0:9b334a45a8ff | 1474 | /* Clear the Overrun flag */ |
bogdanm | 0:9b334a45a8ff | 1475 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
bogdanm | 0:9b334a45a8ff | 1476 | } |
bogdanm | 0:9b334a45a8ff | 1477 | |
bogdanm | 0:9b334a45a8ff | 1478 | } |
bogdanm | 0:9b334a45a8ff | 1479 | |
bogdanm | 0:9b334a45a8ff | 1480 | |
bogdanm | 0:9b334a45a8ff | 1481 | /** |
bogdanm | 0:9b334a45a8ff | 1482 | * @brief Conversion complete callback in non blocking mode |
bogdanm | 0:9b334a45a8ff | 1483 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1484 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1485 | */ |
bogdanm | 0:9b334a45a8ff | 1486 | __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1487 | { |
bogdanm | 0:9b334a45a8ff | 1488 | /* NOTE : This function should not be modified. When the callback is needed, |
bogdanm | 0:9b334a45a8ff | 1489 | function HAL_ADC_ConvCpltCallback must be implemented in the user file. |
bogdanm | 0:9b334a45a8ff | 1490 | */ |
bogdanm | 0:9b334a45a8ff | 1491 | } |
bogdanm | 0:9b334a45a8ff | 1492 | |
bogdanm | 0:9b334a45a8ff | 1493 | /** |
bogdanm | 0:9b334a45a8ff | 1494 | * @brief Conversion DMA half-transfer callback in non blocking mode |
bogdanm | 0:9b334a45a8ff | 1495 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1496 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1497 | */ |
bogdanm | 0:9b334a45a8ff | 1498 | __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1499 | { |
bogdanm | 0:9b334a45a8ff | 1500 | /* NOTE : This function should not be modified. When the callback is needed, |
bogdanm | 0:9b334a45a8ff | 1501 | function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. |
bogdanm | 0:9b334a45a8ff | 1502 | */ |
bogdanm | 0:9b334a45a8ff | 1503 | } |
bogdanm | 0:9b334a45a8ff | 1504 | |
bogdanm | 0:9b334a45a8ff | 1505 | /** |
bogdanm | 0:9b334a45a8ff | 1506 | * @brief Analog watchdog callback in non blocking mode. |
bogdanm | 0:9b334a45a8ff | 1507 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1508 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1509 | */ |
bogdanm | 0:9b334a45a8ff | 1510 | __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1511 | { |
bogdanm | 0:9b334a45a8ff | 1512 | /* NOTE : This function should not be modified. When the callback is needed, |
bogdanm | 0:9b334a45a8ff | 1513 | function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file. |
bogdanm | 0:9b334a45a8ff | 1514 | */ |
bogdanm | 0:9b334a45a8ff | 1515 | } |
bogdanm | 0:9b334a45a8ff | 1516 | |
bogdanm | 0:9b334a45a8ff | 1517 | /** |
bogdanm | 0:9b334a45a8ff | 1518 | * @brief ADC error callback in non blocking mode |
bogdanm | 0:9b334a45a8ff | 1519 | * (ADC conversion with interruption or transfer by DMA) |
bogdanm | 0:9b334a45a8ff | 1520 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1521 | * @retval None |
bogdanm | 0:9b334a45a8ff | 1522 | */ |
bogdanm | 0:9b334a45a8ff | 1523 | __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) |
bogdanm | 0:9b334a45a8ff | 1524 | { |
bogdanm | 0:9b334a45a8ff | 1525 | /* NOTE : This function should not be modified. When the callback is needed, |
bogdanm | 0:9b334a45a8ff | 1526 | function HAL_ADC_ErrorCallback must be implemented in the user file. |
bogdanm | 0:9b334a45a8ff | 1527 | */ |
bogdanm | 0:9b334a45a8ff | 1528 | } |
bogdanm | 0:9b334a45a8ff | 1529 | |
bogdanm | 0:9b334a45a8ff | 1530 | |
bogdanm | 0:9b334a45a8ff | 1531 | /** |
bogdanm | 0:9b334a45a8ff | 1532 | * @} |
bogdanm | 0:9b334a45a8ff | 1533 | */ |
bogdanm | 0:9b334a45a8ff | 1534 | |
bogdanm | 0:9b334a45a8ff | 1535 | /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions |
bogdanm | 0:9b334a45a8ff | 1536 | * @brief Peripheral Control functions |
bogdanm | 0:9b334a45a8ff | 1537 | * |
bogdanm | 0:9b334a45a8ff | 1538 | @verbatim |
bogdanm | 0:9b334a45a8ff | 1539 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 1540 | ##### Peripheral Control functions ##### |
bogdanm | 0:9b334a45a8ff | 1541 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 1542 | [..] This section provides functions allowing to: |
bogdanm | 0:9b334a45a8ff | 1543 | (+) Configure channels on regular group |
bogdanm | 0:9b334a45a8ff | 1544 | (+) Configure the analog watchdog |
bogdanm | 0:9b334a45a8ff | 1545 | |
bogdanm | 0:9b334a45a8ff | 1546 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 1547 | * @{ |
bogdanm | 0:9b334a45a8ff | 1548 | */ |
bogdanm | 0:9b334a45a8ff | 1549 | |
bogdanm | 0:9b334a45a8ff | 1550 | /** |
bogdanm | 0:9b334a45a8ff | 1551 | * @brief Configures the the selected channel to be linked to the regular |
bogdanm | 0:9b334a45a8ff | 1552 | * group. |
bogdanm | 0:9b334a45a8ff | 1553 | * @note In case of usage of internal measurement channels: |
bogdanm | 0:9b334a45a8ff | 1554 | * VrefInt/Vbat/TempSensor. |
bogdanm | 0:9b334a45a8ff | 1555 | * Sampling time constraints must be respected (sampling time can be |
bogdanm | 0:9b334a45a8ff | 1556 | * adjusted in function of ADC clock frequency and sampling time |
bogdanm | 0:9b334a45a8ff | 1557 | * setting). |
bogdanm | 0:9b334a45a8ff | 1558 | * Refer to device datasheet for timings values, parameters TS_vrefint, |
bogdanm | 0:9b334a45a8ff | 1559 | * TS_vbat, TS_temp (values rough order: 5us to 17us). |
bogdanm | 0:9b334a45a8ff | 1560 | * These internal paths can be be disabled using function |
bogdanm | 0:9b334a45a8ff | 1561 | * HAL_ADC_DeInit(). |
bogdanm | 0:9b334a45a8ff | 1562 | * @note Possibility to update parameters on the fly: |
bogdanm | 0:9b334a45a8ff | 1563 | * This function initializes channel into regular group, following |
bogdanm | 0:9b334a45a8ff | 1564 | * calls to this function can be used to reconfigure some parameters |
bogdanm | 0:9b334a45a8ff | 1565 | * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting |
bogdanm | 0:9b334a45a8ff | 1566 | * the ADC. |
bogdanm | 0:9b334a45a8ff | 1567 | * The setting of these parameters is conditioned to ADC state. |
bogdanm | 0:9b334a45a8ff | 1568 | * For parameters constraints, see comments of structure |
bogdanm | 0:9b334a45a8ff | 1569 | * "ADC_ChannelConfTypeDef". |
bogdanm | 0:9b334a45a8ff | 1570 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1571 | * @param sConfig: Structure of ADC channel for regular group. |
bogdanm | 0:9b334a45a8ff | 1572 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1573 | */ |
bogdanm | 0:9b334a45a8ff | 1574 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
bogdanm | 0:9b334a45a8ff | 1575 | { |
bogdanm | 0:9b334a45a8ff | 1576 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1577 | __IO uint32_t wait_loop_index = 0; |
bogdanm | 0:9b334a45a8ff | 1578 | |
bogdanm | 0:9b334a45a8ff | 1579 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1580 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1581 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
bogdanm | 0:9b334a45a8ff | 1582 | assert_param(IS_ADC_RANK(sConfig->Rank)); |
bogdanm | 0:9b334a45a8ff | 1583 | |
bogdanm | 0:9b334a45a8ff | 1584 | if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) |
bogdanm | 0:9b334a45a8ff | 1585 | { |
bogdanm | 0:9b334a45a8ff | 1586 | assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); |
bogdanm | 0:9b334a45a8ff | 1587 | } |
bogdanm | 0:9b334a45a8ff | 1588 | |
bogdanm | 0:9b334a45a8ff | 1589 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 1590 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1591 | |
bogdanm | 0:9b334a45a8ff | 1592 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 1593 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
bogdanm | 0:9b334a45a8ff | 1594 | /* conversion on going on regular group: */ |
bogdanm | 0:9b334a45a8ff | 1595 | /* - Channel number */ |
bogdanm | 0:9b334a45a8ff | 1596 | /* - Channel sampling time */ |
bogdanm | 0:9b334a45a8ff | 1597 | /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ |
bogdanm | 0:9b334a45a8ff | 1598 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 1599 | { |
bogdanm | 0:9b334a45a8ff | 1600 | /* Configure channel: depending on rank setting, add it or remove it from */ |
bogdanm | 0:9b334a45a8ff | 1601 | /* ADC conversion sequencer. */ |
bogdanm | 0:9b334a45a8ff | 1602 | if (sConfig->Rank != ADC_RANK_NONE) |
bogdanm | 0:9b334a45a8ff | 1603 | { |
bogdanm | 0:9b334a45a8ff | 1604 | /* Regular sequence configuration */ |
bogdanm | 0:9b334a45a8ff | 1605 | /* Set the channel selection register from the selected channel */ |
bogdanm | 0:9b334a45a8ff | 1606 | hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 1607 | |
bogdanm | 0:9b334a45a8ff | 1608 | /* Channel sampling time configuration */ |
bogdanm | 0:9b334a45a8ff | 1609 | /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ |
bogdanm | 0:9b334a45a8ff | 1610 | /* (obsolete): sampling time set in this function with */ |
bogdanm | 0:9b334a45a8ff | 1611 | /* parameter "SamplingTime" (obsolete) only if not already set into */ |
bogdanm | 0:9b334a45a8ff | 1612 | /* ADC initialization structure with parameter "SamplingTimeCommon". */ |
bogdanm | 0:9b334a45a8ff | 1613 | if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) |
bogdanm | 0:9b334a45a8ff | 1614 | { |
bogdanm | 0:9b334a45a8ff | 1615 | /* Modify sampling time if needed (not needed in case of reoccurrence */ |
bogdanm | 0:9b334a45a8ff | 1616 | /* for several channels programmed consecutively into the sequencer) */ |
bogdanm | 0:9b334a45a8ff | 1617 | if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc)) |
bogdanm | 0:9b334a45a8ff | 1618 | { |
bogdanm | 0:9b334a45a8ff | 1619 | /* Channel sampling time configuration */ |
bogdanm | 0:9b334a45a8ff | 1620 | /* Clear the old sample time */ |
bogdanm | 0:9b334a45a8ff | 1621 | hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); |
bogdanm | 0:9b334a45a8ff | 1622 | |
bogdanm | 0:9b334a45a8ff | 1623 | /* Set the new sample time */ |
bogdanm | 0:9b334a45a8ff | 1624 | hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime); |
bogdanm | 0:9b334a45a8ff | 1625 | } |
bogdanm | 0:9b334a45a8ff | 1626 | } |
bogdanm | 0:9b334a45a8ff | 1627 | |
bogdanm | 0:9b334a45a8ff | 1628 | /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ |
bogdanm | 0:9b334a45a8ff | 1629 | /* internal measurement paths enable: If internal channel selected, */ |
bogdanm | 0:9b334a45a8ff | 1630 | /* enable dedicated internal buffers and path. */ |
bogdanm | 0:9b334a45a8ff | 1631 | /* Note: these internal measurement paths can be disabled using */ |
bogdanm | 0:9b334a45a8ff | 1632 | /* HAL_ADC_DeInit() or removing the channel from sequencer with */ |
bogdanm | 0:9b334a45a8ff | 1633 | /* channel configuration parameter "Rank". */ |
bogdanm | 0:9b334a45a8ff | 1634 | if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) |
bogdanm | 0:9b334a45a8ff | 1635 | { |
bogdanm | 0:9b334a45a8ff | 1636 | /* If Channel_16 is selected, enable Temp. sensor measurement path. */ |
bogdanm | 0:9b334a45a8ff | 1637 | /* If Channel_17 is selected, enable VREFINT measurement path. */ |
bogdanm | 0:9b334a45a8ff | 1638 | /* If Channel_18 is selected, enable VBAT measurement path. */ |
bogdanm | 0:9b334a45a8ff | 1639 | ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 1640 | |
bogdanm | 0:9b334a45a8ff | 1641 | /* If Temp. sensor is selected, wait for stabilization delay */ |
bogdanm | 0:9b334a45a8ff | 1642 | if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) |
bogdanm | 0:9b334a45a8ff | 1643 | { |
bogdanm | 0:9b334a45a8ff | 1644 | /* Delay for temperature sensor stabilization time */ |
bogdanm | 0:9b334a45a8ff | 1645 | /* Compute number of CPU cycles to wait for */ |
bogdanm | 0:9b334a45a8ff | 1646 | wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); |
bogdanm | 0:9b334a45a8ff | 1647 | while(wait_loop_index != 0) |
bogdanm | 0:9b334a45a8ff | 1648 | { |
bogdanm | 0:9b334a45a8ff | 1649 | wait_loop_index--; |
bogdanm | 0:9b334a45a8ff | 1650 | } |
bogdanm | 0:9b334a45a8ff | 1651 | } |
bogdanm | 0:9b334a45a8ff | 1652 | } |
bogdanm | 0:9b334a45a8ff | 1653 | } |
bogdanm | 0:9b334a45a8ff | 1654 | else |
bogdanm | 0:9b334a45a8ff | 1655 | { |
bogdanm | 0:9b334a45a8ff | 1656 | /* Regular sequence configuration */ |
bogdanm | 0:9b334a45a8ff | 1657 | /* Reset the channel selection register from the selected channel */ |
bogdanm | 0:9b334a45a8ff | 1658 | hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 1659 | |
bogdanm | 0:9b334a45a8ff | 1660 | /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ |
bogdanm | 0:9b334a45a8ff | 1661 | /* internal measurement paths disable: If internal channel selected, */ |
bogdanm | 0:9b334a45a8ff | 1662 | /* disable dedicated internal buffers and path. */ |
bogdanm | 0:9b334a45a8ff | 1663 | if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) |
bogdanm | 0:9b334a45a8ff | 1664 | { |
bogdanm | 0:9b334a45a8ff | 1665 | /* If Channel_16 is selected, disable Temp. sensor measurement path. */ |
bogdanm | 0:9b334a45a8ff | 1666 | /* If Channel_17 is selected, disable VREFINT measurement path. */ |
bogdanm | 0:9b334a45a8ff | 1667 | /* If Channel_18 is selected, disable VBAT measurement path. */ |
bogdanm | 0:9b334a45a8ff | 1668 | ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); |
bogdanm | 0:9b334a45a8ff | 1669 | } |
bogdanm | 0:9b334a45a8ff | 1670 | } |
bogdanm | 0:9b334a45a8ff | 1671 | |
bogdanm | 0:9b334a45a8ff | 1672 | } |
bogdanm | 0:9b334a45a8ff | 1673 | |
bogdanm | 0:9b334a45a8ff | 1674 | /* If a conversion is on going on regular group, no update on regular */ |
bogdanm | 0:9b334a45a8ff | 1675 | /* channel could be done on neither of the channel configuration structure */ |
bogdanm | 0:9b334a45a8ff | 1676 | /* parameters. */ |
bogdanm | 0:9b334a45a8ff | 1677 | else |
bogdanm | 0:9b334a45a8ff | 1678 | { |
bogdanm | 0:9b334a45a8ff | 1679 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 1680 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
bogdanm | 0:9b334a45a8ff | 1681 | |
bogdanm | 0:9b334a45a8ff | 1682 | tmp_hal_status = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1683 | } |
bogdanm | 0:9b334a45a8ff | 1684 | |
bogdanm | 0:9b334a45a8ff | 1685 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1686 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1687 | |
bogdanm | 0:9b334a45a8ff | 1688 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1689 | return tmp_hal_status; |
bogdanm | 0:9b334a45a8ff | 1690 | } |
bogdanm | 0:9b334a45a8ff | 1691 | |
bogdanm | 0:9b334a45a8ff | 1692 | |
bogdanm | 0:9b334a45a8ff | 1693 | /** |
bogdanm | 0:9b334a45a8ff | 1694 | * @brief Configures the analog watchdog. |
bogdanm | 0:9b334a45a8ff | 1695 | * @note Possibility to update parameters on the fly: |
bogdanm | 0:9b334a45a8ff | 1696 | * This function initializes the selected analog watchdog, following |
bogdanm | 0:9b334a45a8ff | 1697 | * calls to this function can be used to reconfigure some parameters |
bogdanm | 0:9b334a45a8ff | 1698 | * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting |
bogdanm | 0:9b334a45a8ff | 1699 | * the ADC. |
bogdanm | 0:9b334a45a8ff | 1700 | * The setting of these parameters is conditioned to ADC state. |
bogdanm | 0:9b334a45a8ff | 1701 | * For parameters constraints, see comments of structure |
bogdanm | 0:9b334a45a8ff | 1702 | * "ADC_AnalogWDGConfTypeDef". |
bogdanm | 0:9b334a45a8ff | 1703 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1704 | * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration |
bogdanm | 0:9b334a45a8ff | 1705 | * @retval HAL status |
bogdanm | 0:9b334a45a8ff | 1706 | */ |
bogdanm | 0:9b334a45a8ff | 1707 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
bogdanm | 0:9b334a45a8ff | 1708 | { |
bogdanm | 0:9b334a45a8ff | 1709 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1710 | |
bogdanm | 0:9b334a45a8ff | 1711 | uint32_t tmpAWDHighThresholdShifted; |
bogdanm | 0:9b334a45a8ff | 1712 | uint32_t tmpAWDLowThresholdShifted; |
bogdanm | 0:9b334a45a8ff | 1713 | |
bogdanm | 0:9b334a45a8ff | 1714 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1715 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1716 | assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); |
bogdanm | 0:9b334a45a8ff | 1717 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
bogdanm | 0:9b334a45a8ff | 1718 | |
bogdanm | 0:9b334a45a8ff | 1719 | /* Verify if threshold is within the selected ADC resolution */ |
bogdanm | 0:9b334a45a8ff | 1720 | assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); |
bogdanm | 0:9b334a45a8ff | 1721 | assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); |
bogdanm | 0:9b334a45a8ff | 1722 | |
bogdanm | 0:9b334a45a8ff | 1723 | if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) |
bogdanm | 0:9b334a45a8ff | 1724 | { |
bogdanm | 0:9b334a45a8ff | 1725 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
bogdanm | 0:9b334a45a8ff | 1726 | } |
bogdanm | 0:9b334a45a8ff | 1727 | |
bogdanm | 0:9b334a45a8ff | 1728 | /* Process locked */ |
bogdanm | 0:9b334a45a8ff | 1729 | __HAL_LOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1730 | |
bogdanm | 0:9b334a45a8ff | 1731 | /* Parameters update conditioned to ADC state: */ |
bogdanm | 0:9b334a45a8ff | 1732 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
bogdanm | 0:9b334a45a8ff | 1733 | /* conversion on going on regular group: */ |
bogdanm | 0:9b334a45a8ff | 1734 | /* - Analog watchdog channels */ |
bogdanm | 0:9b334a45a8ff | 1735 | /* - Analog watchdog thresholds */ |
bogdanm | 0:9b334a45a8ff | 1736 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 1737 | { |
bogdanm | 0:9b334a45a8ff | 1738 | /* Configuration of analog watchdog: */ |
bogdanm | 0:9b334a45a8ff | 1739 | /* - Set the analog watchdog enable mode: one or overall group of */ |
bogdanm | 0:9b334a45a8ff | 1740 | /* channels. */ |
bogdanm | 0:9b334a45a8ff | 1741 | /* - Set the Analog watchdog channel (is not used if watchdog */ |
bogdanm | 0:9b334a45a8ff | 1742 | /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ |
bogdanm | 0:9b334a45a8ff | 1743 | hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL | |
bogdanm | 0:9b334a45a8ff | 1744 | ADC_CFGR1_AWDEN | |
bogdanm | 0:9b334a45a8ff | 1745 | ADC_CFGR1_AWDCH ); |
bogdanm | 0:9b334a45a8ff | 1746 | |
bogdanm | 0:9b334a45a8ff | 1747 | hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode | |
bogdanm | 0:9b334a45a8ff | 1748 | ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) ); |
bogdanm | 0:9b334a45a8ff | 1749 | |
bogdanm | 0:9b334a45a8ff | 1750 | /* Shift the offset in function of the selected ADC resolution: Thresholds*/ |
bogdanm | 0:9b334a45a8ff | 1751 | /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ |
bogdanm | 0:9b334a45a8ff | 1752 | tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); |
bogdanm | 0:9b334a45a8ff | 1753 | tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); |
bogdanm | 0:9b334a45a8ff | 1754 | |
bogdanm | 0:9b334a45a8ff | 1755 | /* Set the high and low thresholds */ |
bogdanm | 0:9b334a45a8ff | 1756 | hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); |
bogdanm | 0:9b334a45a8ff | 1757 | hadc->Instance->TR |= ( ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | |
bogdanm | 0:9b334a45a8ff | 1758 | tmpAWDLowThresholdShifted ); |
bogdanm | 0:9b334a45a8ff | 1759 | |
bogdanm | 0:9b334a45a8ff | 1760 | /* Clear the ADC Analog watchdog flag (in case of left enabled by */ |
bogdanm | 0:9b334a45a8ff | 1761 | /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ |
bogdanm | 0:9b334a45a8ff | 1762 | /* or HAL_ADC_PollForEvent(). */ |
bogdanm | 0:9b334a45a8ff | 1763 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD); |
bogdanm | 0:9b334a45a8ff | 1764 | |
bogdanm | 0:9b334a45a8ff | 1765 | /* Configure ADC Analog watchdog interrupt */ |
bogdanm | 0:9b334a45a8ff | 1766 | if(AnalogWDGConfig->ITMode == ENABLE) |
bogdanm | 0:9b334a45a8ff | 1767 | { |
bogdanm | 0:9b334a45a8ff | 1768 | /* Enable the ADC Analog watchdog interrupt */ |
bogdanm | 0:9b334a45a8ff | 1769 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); |
bogdanm | 0:9b334a45a8ff | 1770 | } |
bogdanm | 0:9b334a45a8ff | 1771 | else |
bogdanm | 0:9b334a45a8ff | 1772 | { |
bogdanm | 0:9b334a45a8ff | 1773 | /* Disable the ADC Analog watchdog interrupt */ |
bogdanm | 0:9b334a45a8ff | 1774 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); |
bogdanm | 0:9b334a45a8ff | 1775 | } |
bogdanm | 0:9b334a45a8ff | 1776 | |
bogdanm | 0:9b334a45a8ff | 1777 | } |
bogdanm | 0:9b334a45a8ff | 1778 | /* If a conversion is on going on regular group, no update could be done */ |
bogdanm | 0:9b334a45a8ff | 1779 | /* on neither of the AWD configuration structure parameters. */ |
bogdanm | 0:9b334a45a8ff | 1780 | else |
bogdanm | 0:9b334a45a8ff | 1781 | { |
bogdanm | 0:9b334a45a8ff | 1782 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 1783 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
bogdanm | 0:9b334a45a8ff | 1784 | |
bogdanm | 0:9b334a45a8ff | 1785 | tmp_hal_status = HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1786 | } |
bogdanm | 0:9b334a45a8ff | 1787 | |
bogdanm | 0:9b334a45a8ff | 1788 | |
bogdanm | 0:9b334a45a8ff | 1789 | /* Process unlocked */ |
bogdanm | 0:9b334a45a8ff | 1790 | __HAL_UNLOCK(hadc); |
bogdanm | 0:9b334a45a8ff | 1791 | |
bogdanm | 0:9b334a45a8ff | 1792 | /* Return function status */ |
bogdanm | 0:9b334a45a8ff | 1793 | return tmp_hal_status; |
bogdanm | 0:9b334a45a8ff | 1794 | } |
bogdanm | 0:9b334a45a8ff | 1795 | |
bogdanm | 0:9b334a45a8ff | 1796 | |
bogdanm | 0:9b334a45a8ff | 1797 | /** |
bogdanm | 0:9b334a45a8ff | 1798 | * @} |
bogdanm | 0:9b334a45a8ff | 1799 | */ |
bogdanm | 0:9b334a45a8ff | 1800 | |
bogdanm | 0:9b334a45a8ff | 1801 | |
bogdanm | 0:9b334a45a8ff | 1802 | /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions |
bogdanm | 0:9b334a45a8ff | 1803 | * @brief Peripheral State functions |
bogdanm | 0:9b334a45a8ff | 1804 | * |
bogdanm | 0:9b334a45a8ff | 1805 | @verbatim |
bogdanm | 0:9b334a45a8ff | 1806 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 1807 | ##### Peripheral State and Errors functions ##### |
bogdanm | 0:9b334a45a8ff | 1808 | =============================================================================== |
bogdanm | 0:9b334a45a8ff | 1809 | [..] |
bogdanm | 0:9b334a45a8ff | 1810 | This subsection provides functions to get in run-time the status of the |
bogdanm | 0:9b334a45a8ff | 1811 | peripheral. |
bogdanm | 0:9b334a45a8ff | 1812 | (+) Check the ADC state |
bogdanm | 0:9b334a45a8ff | 1813 | (+) Check the ADC error code |
bogdanm | 0:9b334a45a8ff | 1814 | |
bogdanm | 0:9b334a45a8ff | 1815 | @endverbatim |
bogdanm | 0:9b334a45a8ff | 1816 | * @{ |
bogdanm | 0:9b334a45a8ff | 1817 | */ |
bogdanm | 0:9b334a45a8ff | 1818 | |
bogdanm | 0:9b334a45a8ff | 1819 | /** |
bogdanm | 0:9b334a45a8ff | 1820 | * @brief return the ADC state |
bogdanm | 0:9b334a45a8ff | 1821 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1822 | * @retval HAL state |
bogdanm | 0:9b334a45a8ff | 1823 | */ |
bogdanm | 0:9b334a45a8ff | 1824 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1825 | { |
bogdanm | 0:9b334a45a8ff | 1826 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1827 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1828 | |
bogdanm | 0:9b334a45a8ff | 1829 | /* Return ADC state */ |
bogdanm | 0:9b334a45a8ff | 1830 | return hadc->State; |
bogdanm | 0:9b334a45a8ff | 1831 | } |
bogdanm | 0:9b334a45a8ff | 1832 | |
bogdanm | 0:9b334a45a8ff | 1833 | /** |
bogdanm | 0:9b334a45a8ff | 1834 | * @brief Return the ADC error code |
bogdanm | 0:9b334a45a8ff | 1835 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1836 | * @retval ADC Error Code |
bogdanm | 0:9b334a45a8ff | 1837 | */ |
bogdanm | 0:9b334a45a8ff | 1838 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) |
bogdanm | 0:9b334a45a8ff | 1839 | { |
bogdanm | 0:9b334a45a8ff | 1840 | return hadc->ErrorCode; |
bogdanm | 0:9b334a45a8ff | 1841 | } |
bogdanm | 0:9b334a45a8ff | 1842 | |
bogdanm | 0:9b334a45a8ff | 1843 | /** |
bogdanm | 0:9b334a45a8ff | 1844 | * @} |
bogdanm | 0:9b334a45a8ff | 1845 | */ |
bogdanm | 0:9b334a45a8ff | 1846 | |
bogdanm | 0:9b334a45a8ff | 1847 | /** |
bogdanm | 0:9b334a45a8ff | 1848 | * @} |
bogdanm | 0:9b334a45a8ff | 1849 | */ |
bogdanm | 0:9b334a45a8ff | 1850 | |
bogdanm | 0:9b334a45a8ff | 1851 | /** @defgroup ADC_Private_Functions ADC Private Functions |
bogdanm | 0:9b334a45a8ff | 1852 | * @{ |
bogdanm | 0:9b334a45a8ff | 1853 | */ |
bogdanm | 0:9b334a45a8ff | 1854 | |
bogdanm | 0:9b334a45a8ff | 1855 | /** |
bogdanm | 0:9b334a45a8ff | 1856 | * @brief Enable the selected ADC. |
bogdanm | 0:9b334a45a8ff | 1857 | * @note Prerequisite condition to use this function: ADC must be disabled |
bogdanm | 0:9b334a45a8ff | 1858 | * and voltage regulator must be enabled (done into HAL_ADC_Init()). |
bogdanm | 0:9b334a45a8ff | 1859 | * @note If low power mode AutoPowerOff is enabled, power-on/off phases are |
bogdanm | 0:9b334a45a8ff | 1860 | * performed automatically by hardware. |
bogdanm | 0:9b334a45a8ff | 1861 | * In this mode, this function is useless and must not be called because |
bogdanm | 0:9b334a45a8ff | 1862 | * flag ADC_FLAG_RDY is not usable. |
bogdanm | 0:9b334a45a8ff | 1863 | * Therefore, this function must be called under condition of |
bogdanm | 0:9b334a45a8ff | 1864 | * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". |
bogdanm | 0:9b334a45a8ff | 1865 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1866 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 1867 | */ |
bogdanm | 0:9b334a45a8ff | 1868 | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1869 | { |
bogdanm | 0:9b334a45a8ff | 1870 | uint32_t tickstart = 0; |
bogdanm | 0:9b334a45a8ff | 1871 | __IO uint32_t wait_loop_index = 0; |
bogdanm | 0:9b334a45a8ff | 1872 | |
bogdanm | 0:9b334a45a8ff | 1873 | /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ |
bogdanm | 0:9b334a45a8ff | 1874 | /* enabling phase not yet completed: flag ADC ready not yet set). */ |
bogdanm | 0:9b334a45a8ff | 1875 | /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ |
bogdanm | 0:9b334a45a8ff | 1876 | /* causes: ADC clock not running, ...). */ |
bogdanm | 0:9b334a45a8ff | 1877 | if (ADC_IS_ENABLE(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 1878 | { |
bogdanm | 0:9b334a45a8ff | 1879 | /* Check if conditions to enable the ADC are fulfilled */ |
bogdanm | 0:9b334a45a8ff | 1880 | if (ADC_ENABLING_CONDITIONS(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 1881 | { |
bogdanm | 0:9b334a45a8ff | 1882 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 1883 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 1884 | |
bogdanm | 0:9b334a45a8ff | 1885 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 1886 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 1887 | |
bogdanm | 0:9b334a45a8ff | 1888 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1889 | } |
bogdanm | 0:9b334a45a8ff | 1890 | |
bogdanm | 0:9b334a45a8ff | 1891 | /* Enable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1892 | __HAL_ADC_ENABLE(hadc); |
bogdanm | 0:9b334a45a8ff | 1893 | |
bogdanm | 0:9b334a45a8ff | 1894 | /* Delay for ADC stabilization time */ |
bogdanm | 0:9b334a45a8ff | 1895 | /* Compute number of CPU cycles to wait for */ |
bogdanm | 0:9b334a45a8ff | 1896 | wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); |
bogdanm | 0:9b334a45a8ff | 1897 | while(wait_loop_index != 0) |
bogdanm | 0:9b334a45a8ff | 1898 | { |
bogdanm | 0:9b334a45a8ff | 1899 | wait_loop_index--; |
bogdanm | 0:9b334a45a8ff | 1900 | } |
bogdanm | 0:9b334a45a8ff | 1901 | |
bogdanm | 0:9b334a45a8ff | 1902 | /* Get tick count */ |
bogdanm | 0:9b334a45a8ff | 1903 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 1904 | |
bogdanm | 0:9b334a45a8ff | 1905 | /* Wait for ADC effectively enabled */ |
bogdanm | 0:9b334a45a8ff | 1906 | while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) |
bogdanm | 0:9b334a45a8ff | 1907 | { |
bogdanm | 0:9b334a45a8ff | 1908 | if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 1909 | { |
bogdanm | 0:9b334a45a8ff | 1910 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 1911 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 1912 | |
bogdanm | 0:9b334a45a8ff | 1913 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 1914 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 1915 | |
bogdanm | 0:9b334a45a8ff | 1916 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1917 | } |
bogdanm | 0:9b334a45a8ff | 1918 | } |
bogdanm | 0:9b334a45a8ff | 1919 | |
bogdanm | 0:9b334a45a8ff | 1920 | } |
bogdanm | 0:9b334a45a8ff | 1921 | |
bogdanm | 0:9b334a45a8ff | 1922 | /* Return HAL status */ |
bogdanm | 0:9b334a45a8ff | 1923 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1924 | } |
bogdanm | 0:9b334a45a8ff | 1925 | |
bogdanm | 0:9b334a45a8ff | 1926 | /** |
bogdanm | 0:9b334a45a8ff | 1927 | * @brief Disable the selected ADC. |
bogdanm | 0:9b334a45a8ff | 1928 | * @note Prerequisite condition to use this function: ADC conversions must be |
bogdanm | 0:9b334a45a8ff | 1929 | * stopped. |
bogdanm | 0:9b334a45a8ff | 1930 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1931 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 1932 | */ |
bogdanm | 0:9b334a45a8ff | 1933 | static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1934 | { |
bogdanm | 0:9b334a45a8ff | 1935 | uint32_t tickstart = 0; |
bogdanm | 0:9b334a45a8ff | 1936 | |
bogdanm | 0:9b334a45a8ff | 1937 | /* Verification if ADC is not already disabled: */ |
bogdanm | 0:9b334a45a8ff | 1938 | /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ |
bogdanm | 0:9b334a45a8ff | 1939 | /* disabled. */ |
bogdanm | 0:9b334a45a8ff | 1940 | if (ADC_IS_ENABLE(hadc) != RESET) |
bogdanm | 0:9b334a45a8ff | 1941 | { |
bogdanm | 0:9b334a45a8ff | 1942 | /* Check if conditions to disable the ADC are fulfilled */ |
bogdanm | 0:9b334a45a8ff | 1943 | if (ADC_DISABLING_CONDITIONS(hadc) != RESET) |
bogdanm | 0:9b334a45a8ff | 1944 | { |
bogdanm | 0:9b334a45a8ff | 1945 | /* Disable the ADC peripheral */ |
bogdanm | 0:9b334a45a8ff | 1946 | __HAL_ADC_DISABLE(hadc); |
bogdanm | 0:9b334a45a8ff | 1947 | } |
bogdanm | 0:9b334a45a8ff | 1948 | else |
bogdanm | 0:9b334a45a8ff | 1949 | { |
bogdanm | 0:9b334a45a8ff | 1950 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 1951 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 1952 | |
bogdanm | 0:9b334a45a8ff | 1953 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 1954 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 1955 | |
bogdanm | 0:9b334a45a8ff | 1956 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1957 | } |
bogdanm | 0:9b334a45a8ff | 1958 | |
bogdanm | 0:9b334a45a8ff | 1959 | /* Wait for ADC effectively disabled */ |
bogdanm | 0:9b334a45a8ff | 1960 | /* Get tick count */ |
bogdanm | 0:9b334a45a8ff | 1961 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 1962 | |
bogdanm | 0:9b334a45a8ff | 1963 | while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) |
bogdanm | 0:9b334a45a8ff | 1964 | { |
bogdanm | 0:9b334a45a8ff | 1965 | if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 1966 | { |
bogdanm | 0:9b334a45a8ff | 1967 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 1968 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 1969 | |
bogdanm | 0:9b334a45a8ff | 1970 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 1971 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 1972 | |
bogdanm | 0:9b334a45a8ff | 1973 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 1974 | } |
bogdanm | 0:9b334a45a8ff | 1975 | } |
bogdanm | 0:9b334a45a8ff | 1976 | } |
bogdanm | 0:9b334a45a8ff | 1977 | |
bogdanm | 0:9b334a45a8ff | 1978 | /* Return HAL status */ |
bogdanm | 0:9b334a45a8ff | 1979 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 1980 | } |
bogdanm | 0:9b334a45a8ff | 1981 | |
bogdanm | 0:9b334a45a8ff | 1982 | |
bogdanm | 0:9b334a45a8ff | 1983 | /** |
bogdanm | 0:9b334a45a8ff | 1984 | * @brief Stop ADC conversion. |
bogdanm | 0:9b334a45a8ff | 1985 | * @note Prerequisite condition to use this function: ADC conversions must be |
bogdanm | 0:9b334a45a8ff | 1986 | * stopped to disable the ADC. |
bogdanm | 0:9b334a45a8ff | 1987 | * @param hadc: ADC handle |
bogdanm | 0:9b334a45a8ff | 1988 | * @retval HAL status. |
bogdanm | 0:9b334a45a8ff | 1989 | */ |
bogdanm | 0:9b334a45a8ff | 1990 | static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) |
bogdanm | 0:9b334a45a8ff | 1991 | { |
bogdanm | 0:9b334a45a8ff | 1992 | uint32_t tickstart = 0; |
bogdanm | 0:9b334a45a8ff | 1993 | |
bogdanm | 0:9b334a45a8ff | 1994 | /* Check the parameters */ |
bogdanm | 0:9b334a45a8ff | 1995 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
bogdanm | 0:9b334a45a8ff | 1996 | |
bogdanm | 0:9b334a45a8ff | 1997 | /* Verification if ADC is not already stopped on regular group to bypass */ |
bogdanm | 0:9b334a45a8ff | 1998 | /* this function if not needed. */ |
bogdanm | 0:9b334a45a8ff | 1999 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) |
bogdanm | 0:9b334a45a8ff | 2000 | { |
bogdanm | 0:9b334a45a8ff | 2001 | |
bogdanm | 0:9b334a45a8ff | 2002 | /* Stop potential conversion on going on regular group */ |
bogdanm | 0:9b334a45a8ff | 2003 | /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ |
bogdanm | 0:9b334a45a8ff | 2004 | if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && |
bogdanm | 0:9b334a45a8ff | 2005 | HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) |
bogdanm | 0:9b334a45a8ff | 2006 | { |
bogdanm | 0:9b334a45a8ff | 2007 | /* Stop conversions on regular group */ |
bogdanm | 0:9b334a45a8ff | 2008 | hadc->Instance->CR |= ADC_CR_ADSTP; |
bogdanm | 0:9b334a45a8ff | 2009 | } |
bogdanm | 0:9b334a45a8ff | 2010 | |
bogdanm | 0:9b334a45a8ff | 2011 | /* Wait for conversion effectively stopped */ |
bogdanm | 0:9b334a45a8ff | 2012 | /* Get tick count */ |
bogdanm | 0:9b334a45a8ff | 2013 | tickstart = HAL_GetTick(); |
bogdanm | 0:9b334a45a8ff | 2014 | |
bogdanm | 0:9b334a45a8ff | 2015 | while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) |
bogdanm | 0:9b334a45a8ff | 2016 | { |
bogdanm | 0:9b334a45a8ff | 2017 | if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) |
bogdanm | 0:9b334a45a8ff | 2018 | { |
bogdanm | 0:9b334a45a8ff | 2019 | /* Update ADC state machine to error */ |
bogdanm | 0:9b334a45a8ff | 2020 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 2021 | |
bogdanm | 0:9b334a45a8ff | 2022 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 2023 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 2024 | |
bogdanm | 0:9b334a45a8ff | 2025 | return HAL_ERROR; |
bogdanm | 0:9b334a45a8ff | 2026 | } |
bogdanm | 0:9b334a45a8ff | 2027 | } |
bogdanm | 0:9b334a45a8ff | 2028 | |
bogdanm | 0:9b334a45a8ff | 2029 | } |
bogdanm | 0:9b334a45a8ff | 2030 | |
bogdanm | 0:9b334a45a8ff | 2031 | /* Return HAL status */ |
bogdanm | 0:9b334a45a8ff | 2032 | return HAL_OK; |
bogdanm | 0:9b334a45a8ff | 2033 | } |
bogdanm | 0:9b334a45a8ff | 2034 | |
bogdanm | 0:9b334a45a8ff | 2035 | |
bogdanm | 0:9b334a45a8ff | 2036 | /** |
bogdanm | 0:9b334a45a8ff | 2037 | * @brief DMA transfer complete callback. |
bogdanm | 0:9b334a45a8ff | 2038 | * @param hdma: pointer to DMA handle. |
bogdanm | 0:9b334a45a8ff | 2039 | * @retval None |
bogdanm | 0:9b334a45a8ff | 2040 | */ |
bogdanm | 0:9b334a45a8ff | 2041 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) |
bogdanm | 0:9b334a45a8ff | 2042 | { |
bogdanm | 0:9b334a45a8ff | 2043 | /* Retrieve ADC handle corresponding to current DMA handle */ |
bogdanm | 0:9b334a45a8ff | 2044 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
bogdanm | 0:9b334a45a8ff | 2045 | |
bogdanm | 0:9b334a45a8ff | 2046 | /* Update state machine on conversion status if not in error state */ |
bogdanm | 0:9b334a45a8ff | 2047 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) |
bogdanm | 0:9b334a45a8ff | 2048 | { |
bogdanm | 0:9b334a45a8ff | 2049 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 2050 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
bogdanm | 0:9b334a45a8ff | 2051 | |
bogdanm | 0:9b334a45a8ff | 2052 | /* Determine whether any further conversion upcoming on group regular */ |
bogdanm | 0:9b334a45a8ff | 2053 | /* by external trigger, continuous mode or scan sequence on going. */ |
bogdanm | 0:9b334a45a8ff | 2054 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
bogdanm | 0:9b334a45a8ff | 2055 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
bogdanm | 0:9b334a45a8ff | 2056 | { |
bogdanm | 0:9b334a45a8ff | 2057 | /* If End of Sequence is reached, disable interrupts */ |
bogdanm | 0:9b334a45a8ff | 2058 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
bogdanm | 0:9b334a45a8ff | 2059 | { |
bogdanm | 0:9b334a45a8ff | 2060 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
bogdanm | 0:9b334a45a8ff | 2061 | /* ADSTART==0 (no conversion on going) */ |
bogdanm | 0:9b334a45a8ff | 2062 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
bogdanm | 0:9b334a45a8ff | 2063 | { |
bogdanm | 0:9b334a45a8ff | 2064 | /* Disable ADC end of single conversion interrupt on group regular */ |
bogdanm | 0:9b334a45a8ff | 2065 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
bogdanm | 0:9b334a45a8ff | 2066 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
bogdanm | 0:9b334a45a8ff | 2067 | /* by overrun IRQ process below. */ |
bogdanm | 0:9b334a45a8ff | 2068 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
bogdanm | 0:9b334a45a8ff | 2069 | |
bogdanm | 0:9b334a45a8ff | 2070 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 2071 | ADC_STATE_CLR_SET(hadc->State, |
bogdanm | 0:9b334a45a8ff | 2072 | HAL_ADC_STATE_REG_BUSY, |
bogdanm | 0:9b334a45a8ff | 2073 | HAL_ADC_STATE_READY); |
bogdanm | 0:9b334a45a8ff | 2074 | } |
bogdanm | 0:9b334a45a8ff | 2075 | else |
bogdanm | 0:9b334a45a8ff | 2076 | { |
bogdanm | 0:9b334a45a8ff | 2077 | /* Change ADC state to error state */ |
bogdanm | 0:9b334a45a8ff | 2078 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
bogdanm | 0:9b334a45a8ff | 2079 | |
bogdanm | 0:9b334a45a8ff | 2080 | /* Set ADC error code to ADC IP internal error */ |
bogdanm | 0:9b334a45a8ff | 2081 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
bogdanm | 0:9b334a45a8ff | 2082 | } |
bogdanm | 0:9b334a45a8ff | 2083 | } |
bogdanm | 0:9b334a45a8ff | 2084 | } |
bogdanm | 0:9b334a45a8ff | 2085 | |
bogdanm | 0:9b334a45a8ff | 2086 | /* Conversion complete callback */ |
bogdanm | 0:9b334a45a8ff | 2087 | HAL_ADC_ConvCpltCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 2088 | } |
bogdanm | 0:9b334a45a8ff | 2089 | else |
bogdanm | 0:9b334a45a8ff | 2090 | { |
bogdanm | 0:9b334a45a8ff | 2091 | /* Call DMA error callback */ |
bogdanm | 0:9b334a45a8ff | 2092 | hadc->DMA_Handle->XferErrorCallback(hdma); |
bogdanm | 0:9b334a45a8ff | 2093 | } |
bogdanm | 0:9b334a45a8ff | 2094 | |
bogdanm | 0:9b334a45a8ff | 2095 | } |
bogdanm | 0:9b334a45a8ff | 2096 | |
bogdanm | 0:9b334a45a8ff | 2097 | /** |
bogdanm | 0:9b334a45a8ff | 2098 | * @brief DMA half transfer complete callback. |
bogdanm | 0:9b334a45a8ff | 2099 | * @param hdma: pointer to DMA handle. |
bogdanm | 0:9b334a45a8ff | 2100 | * @retval None |
bogdanm | 0:9b334a45a8ff | 2101 | */ |
bogdanm | 0:9b334a45a8ff | 2102 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) |
bogdanm | 0:9b334a45a8ff | 2103 | { |
bogdanm | 0:9b334a45a8ff | 2104 | /* Retrieve ADC handle corresponding to current DMA handle */ |
bogdanm | 0:9b334a45a8ff | 2105 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
bogdanm | 0:9b334a45a8ff | 2106 | |
bogdanm | 0:9b334a45a8ff | 2107 | /* Half conversion callback */ |
bogdanm | 0:9b334a45a8ff | 2108 | HAL_ADC_ConvHalfCpltCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 2109 | } |
bogdanm | 0:9b334a45a8ff | 2110 | |
bogdanm | 0:9b334a45a8ff | 2111 | /** |
bogdanm | 0:9b334a45a8ff | 2112 | * @brief DMA error callback |
bogdanm | 0:9b334a45a8ff | 2113 | * @param hdma: pointer to DMA handle. |
bogdanm | 0:9b334a45a8ff | 2114 | * @retval None |
bogdanm | 0:9b334a45a8ff | 2115 | */ |
bogdanm | 0:9b334a45a8ff | 2116 | static void ADC_DMAError(DMA_HandleTypeDef *hdma) |
bogdanm | 0:9b334a45a8ff | 2117 | { |
bogdanm | 0:9b334a45a8ff | 2118 | /* Retrieve ADC handle corresponding to current DMA handle */ |
bogdanm | 0:9b334a45a8ff | 2119 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
bogdanm | 0:9b334a45a8ff | 2120 | |
bogdanm | 0:9b334a45a8ff | 2121 | /* Set ADC state */ |
bogdanm | 0:9b334a45a8ff | 2122 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
bogdanm | 0:9b334a45a8ff | 2123 | |
bogdanm | 0:9b334a45a8ff | 2124 | /* Set ADC error code to DMA error */ |
bogdanm | 0:9b334a45a8ff | 2125 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); |
bogdanm | 0:9b334a45a8ff | 2126 | |
bogdanm | 0:9b334a45a8ff | 2127 | /* Error callback */ |
bogdanm | 0:9b334a45a8ff | 2128 | HAL_ADC_ErrorCallback(hadc); |
bogdanm | 0:9b334a45a8ff | 2129 | } |
bogdanm | 0:9b334a45a8ff | 2130 | |
bogdanm | 0:9b334a45a8ff | 2131 | /** |
bogdanm | 0:9b334a45a8ff | 2132 | * @} |
bogdanm | 0:9b334a45a8ff | 2133 | */ |
bogdanm | 0:9b334a45a8ff | 2134 | |
bogdanm | 0:9b334a45a8ff | 2135 | #endif /* HAL_ADC_MODULE_ENABLED */ |
bogdanm | 0:9b334a45a8ff | 2136 | /** |
bogdanm | 0:9b334a45a8ff | 2137 | * @} |
bogdanm | 0:9b334a45a8ff | 2138 | */ |
bogdanm | 0:9b334a45a8ff | 2139 | |
bogdanm | 0:9b334a45a8ff | 2140 | /** |
bogdanm | 0:9b334a45a8ff | 2141 | * @} |
bogdanm | 0:9b334a45a8ff | 2142 | */ |
bogdanm | 0:9b334a45a8ff | 2143 | |
bogdanm | 0:9b334a45a8ff | 2144 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |