en 129 / mbed-dev

fix LPC812 PWM

Dependents:   IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.c@129:2e517c56bcfb, 2016-05-16 (annotated)

Committer:
nameless129
Date:
Mon May 16 16:50:30 2016 +0000
Revision:
129:2e517c56bcfb
Parent:
0:9b334a45a8ff 
PWM Fix:Duty 0%??H???????????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 * @brief LPC43xx System Initialization
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * @note
bogdanm 0:9b334a45a8ff 5 * Copyright(C) NXP Semiconductors, 2012
bogdanm 0:9b334a45a8ff 6 * All rights reserved.
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * @par
bogdanm 0:9b334a45a8ff 9 * Software that is described herein is for illustrative purposes only
bogdanm 0:9b334a45a8ff 10 * which provides customers with programming information regarding the
bogdanm 0:9b334a45a8ff 11 * LPC products. This software is supplied "AS IS" without any warranties of
bogdanm 0:9b334a45a8ff 12 * any kind, and NXP Semiconductors and its licensor disclaim any and
bogdanm 0:9b334a45a8ff 13 * all warranties, express or implied, including all implied warranties of
bogdanm 0:9b334a45a8ff 14 * merchantability, fitness for a particular purpose and non-infringement of
bogdanm 0:9b334a45a8ff 15 * intellectual property rights. NXP Semiconductors assumes no responsibility
bogdanm 0:9b334a45a8ff 16 * or liability for the use of the software, conveys no license or rights under any
bogdanm 0:9b334a45a8ff 17 * patent, copyright, mask work right, or any other intellectual property rights in
bogdanm 0:9b334a45a8ff 18 * or to any products. NXP Semiconductors reserves the right to make changes
bogdanm 0:9b334a45a8ff 19 * in the software without notification. NXP Semiconductors also makes no
bogdanm 0:9b334a45a8ff 20 * representation or warranty that such application will be suitable for the
bogdanm 0:9b334a45a8ff 21 * specified use without further testing or modification.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 * @par
bogdanm 0:9b334a45a8ff 24 * Permission to use, copy, modify, and distribute this software and its
bogdanm 0:9b334a45a8ff 25 * documentation is hereby granted, under NXP Semiconductors' and its
bogdanm 0:9b334a45a8ff 26 * licensor's relevant copyrights in the software, without fee, provided that it
bogdanm 0:9b334a45a8ff 27 * is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm 0:9b334a45a8ff 28 * copyright, permission, and disclaimer notice must appear in all copies of
bogdanm 0:9b334a45a8ff 29 * this code.
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 * Modified by Micromint USA <support@micromint.com>
bogdanm 0:9b334a45a8ff 32 */
bogdanm 0:9b334a45a8ff 33 #include "LPC43xx.h"
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 #define COUNT_OF(a) (sizeof(a)/sizeof(a[0]))
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 /* Clock variables */
bogdanm 0:9b334a45a8ff 38 #if (CLOCK_SETUP)
bogdanm 0:9b334a45a8ff 39 uint32_t SystemCoreClock = MAX_CLOCK_FREQ;
bogdanm 0:9b334a45a8ff 40 #else
bogdanm 0:9b334a45a8ff 41 uint32_t SystemCoreClock = CRYSTAL_MAIN_FREQ_IN;
bogdanm 0:9b334a45a8ff 42 #endif
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 #if !defined(CORE_M0)
bogdanm 0:9b334a45a8ff 45 /* SCU pin definitions for pin muxing */
bogdanm 0:9b334a45a8ff 46 typedef struct {
bogdanm 0:9b334a45a8ff 47 __IO uint32_t *reg; /* SCU register address */
bogdanm 0:9b334a45a8ff 48 uint16_t mode; /* SCU pin mode and function */
bogdanm 0:9b334a45a8ff 49 } PINMUX_GRP_T;
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 /* Pins to initialize before clocks are configured */
bogdanm 0:9b334a45a8ff 52 static const PINMUX_GRP_T pre_clock_mux[] = {
bogdanm 0:9b334a45a8ff 53 /* SPIFI pins */
bogdanm 0:9b334a45a8ff 54 {SCU_REG(0x3, 3), (SCU_PINIO_FAST | 0x3)}, /* P3_3 SPIFI CLK */
bogdanm 0:9b334a45a8ff 55 {SCU_REG(0x3, 4), (SCU_PINIO_FAST | 0x3)}, /* P3_4 SPIFI D3 */
bogdanm 0:9b334a45a8ff 56 {SCU_REG(0x3, 5), (SCU_PINIO_FAST | 0x3)}, /* P3_5 SPIFI D2 */
bogdanm 0:9b334a45a8ff 57 {SCU_REG(0x3, 6), (SCU_PINIO_FAST | 0x3)}, /* P3_6 SPIFI D1 */
bogdanm 0:9b334a45a8ff 58 {SCU_REG(0x3, 7), (SCU_PINIO_FAST | 0x3)}, /* P3_7 SPIFI D0 */
bogdanm 0:9b334a45a8ff 59 {SCU_REG(0x3, 8), (SCU_PINIO_FAST | 0x3)} /* P3_8 SPIFI CS/SSEL */
bogdanm 0:9b334a45a8ff 60 };
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 /* Pins to initialize after clocks are configured */
bogdanm 0:9b334a45a8ff 63 static const PINMUX_GRP_T post_clock_mux[] = {
bogdanm 0:9b334a45a8ff 64 /* Boot pins */
bogdanm 0:9b334a45a8ff 65 {SCU_REG(0x1, 1), (SCU_PINIO_FAST | 0x0)}, /* P1_1 BOOT0 */
bogdanm 0:9b334a45a8ff 66 {SCU_REG(0x1, 2), (SCU_PINIO_FAST | 0x0)}, /* P1_2 BOOT1 */
bogdanm 0:9b334a45a8ff 67 {SCU_REG(0x2, 8), (SCU_PINIO_FAST | 0x0)}, /* P2_8 BOOT2 */
bogdanm 0:9b334a45a8ff 68 {SCU_REG(0x2, 9), (SCU_PINIO_FAST | 0x0)}, /* P2_9 BOOT3 */
bogdanm 0:9b334a45a8ff 69 /* Micromint Bambino 200/210 */
bogdanm 0:9b334a45a8ff 70 {SCU_REG(0x6, 11), (SCU_PINIO_FAST | 0x0)}, /* P6_11 LED1 */
bogdanm 0:9b334a45a8ff 71 {SCU_REG(0x2, 5), (SCU_PINIO_FAST | 0x0)}, /* P2_5 LED2 */
bogdanm 0:9b334a45a8ff 72 {SCU_REG(0x2, 7), (SCU_PINIO_FAST | 0x0)}, /* P2_7 BTN1 */
bogdanm 0:9b334a45a8ff 73 /* Micromint Bambino 210 */
bogdanm 0:9b334a45a8ff 74 {SCU_REG(0x6, 1), (SCU_PINIO_FAST | 0x0)}, /* P6_1 LED3 */
bogdanm 0:9b334a45a8ff 75 {SCU_REG(0x6, 2), (SCU_PINIO_FAST | 0x0)}, /* P6_2 LED4 */
bogdanm 0:9b334a45a8ff 76 };
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 #if (CLOCK_SETUP)
bogdanm 0:9b334a45a8ff 79 /* Structure for initial base clock states */
bogdanm 0:9b334a45a8ff 80 struct CLK_BASE_STATES {
bogdanm 0:9b334a45a8ff 81 CGU_BASE_CLK_T clk; /* Base clock */
bogdanm 0:9b334a45a8ff 82 CGU_CLKIN_T clkin; /* Base clock source */
bogdanm 0:9b334a45a8ff 83 uint8_t powerdn; /* Set to 1 if base clock is initially powered down */
bogdanm 0:9b334a45a8ff 84 };
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 /* Initial base clock states are mostly on */
bogdanm 0:9b334a45a8ff 87 static const struct CLK_BASE_STATES clock_states[] = {
bogdanm 0:9b334a45a8ff 88 {CLK_BASE_SAFE, CLKIN_IRC, 0},
bogdanm 0:9b334a45a8ff 89 {CLK_BASE_APB1, CLKIN_MAINPLL, 0},
bogdanm 0:9b334a45a8ff 90 {CLK_BASE_APB3, CLKIN_MAINPLL, 0},
bogdanm 0:9b334a45a8ff 91 {CLK_BASE_USB0, CLKIN_USBPLL, 1},
bogdanm 0:9b334a45a8ff 92 {CLK_BASE_PERIPH, CLKIN_MAINPLL, 0},
bogdanm 0:9b334a45a8ff 93 {CLK_BASE_SPI, CLKIN_MAINPLL, 0},
bogdanm 0:9b334a45a8ff 94 {CLK_BASE_PHY_TX, CLKIN_ENET_TX, 0},
bogdanm 0:9b334a45a8ff 95 #if defined(USE_RMII)
bogdanm 0:9b334a45a8ff 96 {CLK_BASE_PHY_RX, CLKIN_ENET_TX, 0},
bogdanm 0:9b334a45a8ff 97 #else
bogdanm 0:9b334a45a8ff 98 {CLK_BASE_PHY_RX, CLKIN_ENET_RX, 0},
bogdanm 0:9b334a45a8ff 99 #endif
bogdanm 0:9b334a45a8ff 100 {CLK_BASE_SDIO, CLKIN_MAINPLL, 0},
bogdanm 0:9b334a45a8ff 101 {CLK_BASE_SSP0, CLKIN_IDIVC, 0},
bogdanm 0:9b334a45a8ff 102 {CLK_BASE_SSP1, CLKIN_IDIVC, 0},
bogdanm 0:9b334a45a8ff 103 {CLK_BASE_UART0, CLKIN_MAINPLL, 0},
bogdanm 0:9b334a45a8ff 104 {CLK_BASE_UART1, CLKIN_MAINPLL, 0},
bogdanm 0:9b334a45a8ff 105 {CLK_BASE_UART2, CLKIN_MAINPLL, 0},
bogdanm 0:9b334a45a8ff 106 {CLK_BASE_UART3, CLKIN_MAINPLL, 0},
bogdanm 0:9b334a45a8ff 107 {CLK_BASE_OUT, CLKINPUT_PD, 0},
bogdanm 0:9b334a45a8ff 108 {CLK_BASE_APLL, CLKINPUT_PD, 0},
bogdanm 0:9b334a45a8ff 109 {CLK_BASE_CGU_OUT0, CLKINPUT_PD, 0},
bogdanm 0:9b334a45a8ff 110 {CLK_BASE_CGU_OUT1, CLKINPUT_PD, 0},
bogdanm 0:9b334a45a8ff 111
bogdanm 0:9b334a45a8ff 112 /* Clocks derived from dividers */
bogdanm 0:9b334a45a8ff 113 {CLK_BASE_LCD, CLKIN_IDIVC, 0},
bogdanm 0:9b334a45a8ff 114 {CLK_BASE_USB1, CLKIN_IDIVD, 1}
bogdanm 0:9b334a45a8ff 115 };
bogdanm 0:9b334a45a8ff 116 #endif /* defined(CLOCK_SETUP) */
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 /* Local functions */
bogdanm 0:9b334a45a8ff 119 static uint32_t SystemGetMainPLLHz(void);
bogdanm 0:9b334a45a8ff 120 static void SystemSetupClock(void);
bogdanm 0:9b334a45a8ff 121 static void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n);
bogdanm 0:9b334a45a8ff 122 static void SystemSetupMemory(void);
bogdanm 0:9b334a45a8ff 123 static void WaitUs(uint32_t us);
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 #endif /* !defined(CORE_M0) */
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 /*
bogdanm 0:9b334a45a8ff 128 * SystemInit() - Initialize the system
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130 void SystemInit(void)
bogdanm 0:9b334a45a8ff 131 {
bogdanm 0:9b334a45a8ff 132 #if !defined(CORE_M0)
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /* Initialize vector table in flash */
bogdanm 0:9b334a45a8ff 135 #if defined(__ARMCC_VERSION)
bogdanm 0:9b334a45a8ff 136 extern void *__Vectors;
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 SCB->VTOR = (unsigned int) &__Vectors;
bogdanm 0:9b334a45a8ff 139 #elif defined(__IAR_SYSTEMS_ICC__)
bogdanm 0:9b334a45a8ff 140 extern void *__vector_table;
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 SCB->VTOR = (unsigned int) &__vector_table;
bogdanm 0:9b334a45a8ff 143 #elif defined(TOOLCHAIN_GCC_ARM)
bogdanm 0:9b334a45a8ff 144 extern void *__isr_vector;
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 SCB->VTOR = (unsigned int) &__isr_vector;
bogdanm 0:9b334a45a8ff 147 #else /* defined(__GNUC__) and others */
bogdanm 0:9b334a45a8ff 148 extern void *g_pfnVectors;
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 SCB->VTOR = (unsigned int) &g_pfnVectors;
bogdanm 0:9b334a45a8ff 151 #endif
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
bogdanm 0:9b334a45a8ff 154 /* Initialize floating point */
bogdanm 0:9b334a45a8ff 155 fpuInit();
bogdanm 0:9b334a45a8ff 156 #endif
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 SystemSetupPins(pre_clock_mux, COUNT_OF(pre_clock_mux)); /* Configure pins */
bogdanm 0:9b334a45a8ff 159 SystemSetupClock(); /* Configure processor and peripheral clocks */
bogdanm 0:9b334a45a8ff 160 SystemSetupPins(post_clock_mux, COUNT_OF(post_clock_mux)); /* Configure pins */
bogdanm 0:9b334a45a8ff 161 SystemSetupMemory(); /* Configure external memory */
bogdanm 0:9b334a45a8ff 162 #endif /* !defined(CORE_M0) */
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 SystemCoreClockUpdate(); /* Update SystemCoreClock variable */
bogdanm 0:9b334a45a8ff 165 }
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 /*
bogdanm 0:9b334a45a8ff 168 * SystemCoreClockUpdate() - Update SystemCoreClock variable
bogdanm 0:9b334a45a8ff 169 */
bogdanm 0:9b334a45a8ff 170 void SystemCoreClockUpdate(void)
bogdanm 0:9b334a45a8ff 171 {
bogdanm 0:9b334a45a8ff 172 uint32_t reg, div, rate;
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /* Get main PLL rate */
bogdanm 0:9b334a45a8ff 175 rate = SystemGetMainPLLHz();
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 /* Get clock divider */
bogdanm 0:9b334a45a8ff 178 reg = LPC_CCU1->CLKCCU[CLK_MX_MXCORE].CFG;
bogdanm 0:9b334a45a8ff 179 if (((reg >> 5) & 0x7) == 0) {
bogdanm 0:9b334a45a8ff 180 div = 1;
bogdanm 0:9b334a45a8ff 181 }
bogdanm 0:9b334a45a8ff 182 else {
bogdanm 0:9b334a45a8ff 183 div = 2;
bogdanm 0:9b334a45a8ff 184 }
bogdanm 0:9b334a45a8ff 185 rate = rate / div;
bogdanm 0:9b334a45a8ff 186
bogdanm 0:9b334a45a8ff 187 SystemCoreClock = rate;
bogdanm 0:9b334a45a8ff 188 }
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /* Returns the frequency of the main PLL */
bogdanm 0:9b334a45a8ff 191 uint32_t SystemGetMainPLLHz(void)
bogdanm 0:9b334a45a8ff 192 {
bogdanm 0:9b334a45a8ff 193 uint32_t PLLReg = LPC_CGU->PLL1_CTRL;
bogdanm 0:9b334a45a8ff 194 uint32_t freq = CRYSTAL_MAIN_FREQ_IN;
bogdanm 0:9b334a45a8ff 195 uint32_t msel, nsel, psel, direct, fbsel;
bogdanm 0:9b334a45a8ff 196 uint32_t m, n, p;
bogdanm 0:9b334a45a8ff 197 const uint8_t ptab[] = {1, 2, 4, 8};
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 msel = (PLLReg >> 16) & 0xFF;
bogdanm 0:9b334a45a8ff 200 nsel = (PLLReg >> 12) & 0x3;
bogdanm 0:9b334a45a8ff 201 psel = (PLLReg >> 8) & 0x3;
bogdanm 0:9b334a45a8ff 202 direct = (PLLReg >> 7) & 0x1;
bogdanm 0:9b334a45a8ff 203 fbsel = (PLLReg >> 6) & 0x1;
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 m = msel + 1;
bogdanm 0:9b334a45a8ff 206 n = nsel + 1;
bogdanm 0:9b334a45a8ff 207 p = ptab[psel];
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 if (direct || fbsel) {
bogdanm 0:9b334a45a8ff 210 return m * (freq / n);
bogdanm 0:9b334a45a8ff 211 }
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 return (m / (2 * p)) * (freq / n);
bogdanm 0:9b334a45a8ff 214 }
bogdanm 0:9b334a45a8ff 215
bogdanm 0:9b334a45a8ff 216 #if !defined(CORE_M0)
bogdanm 0:9b334a45a8ff 217 /*
bogdanm 0:9b334a45a8ff 218 * SystemSetupClock() - Set processor and peripheral clocks
bogdanm 0:9b334a45a8ff 219 *
bogdanm 0:9b334a45a8ff 220 * Clock Frequency Source
bogdanm 0:9b334a45a8ff 221 * CLK_BASE_MX 204 MHz CLKIN_MAINPLL (CLKIN_PLL1)
bogdanm 0:9b334a45a8ff 222 * CLK_BASE_SPIFI 102 MHz CLKIN_IDIVE
bogdanm 0:9b334a45a8ff 223 * CLK_BASE_USB0 480 MHz CLKIN_USBPLL (Disabled) (CLKIN_PLL0USB)
bogdanm 0:9b334a45a8ff 224 * CLK_BASE_USB1 60 MHz CLKIN_IDIVE (Disabled)
bogdanm 0:9b334a45a8ff 225 * 120 MHz CLKIN_IDIVD (Disabled)
bogdanm 0:9b334a45a8ff 226 *
bogdanm 0:9b334a45a8ff 227 * 12 MHz CLKIN_IDIVB
bogdanm 0:9b334a45a8ff 228 * 12 MHz CLKIN_IDIVC
bogdanm 0:9b334a45a8ff 229 *
bogdanm 0:9b334a45a8ff 230 */
bogdanm 0:9b334a45a8ff 231 void SystemSetupClock(void)
bogdanm 0:9b334a45a8ff 232 {
bogdanm 0:9b334a45a8ff 233 #if (CLOCK_SETUP)
bogdanm 0:9b334a45a8ff 234 uint32_t i;
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 /* Switch main clock to Internal RC (IRC) while setting up PLL1 */
bogdanm 0:9b334a45a8ff 237 LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_IRC << 24);
bogdanm 0:9b334a45a8ff 238 /* Set prescaler/divider on SSP1 assuming 204 MHz clock */
bogdanm 0:9b334a45a8ff 239 LPC_SSP1->CR1 &= ~(1 << 1);
bogdanm 0:9b334a45a8ff 240 LPC_SSP1->CPSR = 0x0002;
bogdanm 0:9b334a45a8ff 241 LPC_SSP1->CR0 = 0x00006507;
bogdanm 0:9b334a45a8ff 242 LPC_SSP1->CR1 |= (1 << 1);
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 /* Enable the oscillator and wait 100 us */
bogdanm 0:9b334a45a8ff 245 LPC_CGU->XTAL_OSC_CTRL = 0;
bogdanm 0:9b334a45a8ff 246 WaitUs(100);
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 #if (SPIFI_INIT)
bogdanm 0:9b334a45a8ff 249 /* Setup SPIFI control register and no-opcode mode */
bogdanm 0:9b334a45a8ff 250 LPC_SPIFI->CTRL = (0x100 << 0) | (1 << 16) | (1 << 29) | (1 << 30);
bogdanm 0:9b334a45a8ff 251 LPC_SPIFI->IDATA = 0xA5;
bogdanm 0:9b334a45a8ff 252 /* Switch IDIVE clock to IRC and connect to SPIFI clock */
bogdanm 0:9b334a45a8ff 253 LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = ((1 << 11) | (CLKIN_IRC << 24));
bogdanm 0:9b334a45a8ff 254 LPC_CGU->BASE_CLK[CLK_BASE_SPIFI] = ((1 << 11) | (CLKIN_IDIVE << 24));
bogdanm 0:9b334a45a8ff 255 #endif /* SPIFI_INIT */
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /* Configure PLL1 (MAINPLL) for main clock */
bogdanm 0:9b334a45a8ff 258 LPC_CGU->PLL1_CTRL |= 1; /* Power down PLL1 */
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /* Change PLL1 to 108 Mhz (msel=9, 12 MHz*9=108 MHz) */
bogdanm 0:9b334a45a8ff 261 LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (8 << 16)
bogdanm 0:9b334a45a8ff 262 | (CLKIN_MAINPLL << 24);
bogdanm 0:9b334a45a8ff 263 while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
bogdanm 0:9b334a45a8ff 264 WaitUs(100);
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 /* Change PLL1 to 204 Mhz (msel=17, 12 MHz*17=204 MHz) */
bogdanm 0:9b334a45a8ff 267 LPC_CGU->PLL1_CTRL = (1 << 7) | (0 << 8) | (1 << 11) | (0 << 12) | (16 << 16)
bogdanm 0:9b334a45a8ff 268 | (CLKIN_MAINPLL << 24);
bogdanm 0:9b334a45a8ff 269 while (!(LPC_CGU->PLL1_STAT & 1)); /* Wait for PLL1 to lock */
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /* Connect main clock to PLL1 */
bogdanm 0:9b334a45a8ff 272 LPC_CGU->BASE_CLK[CLK_BASE_MX] = (1 << 11) | (CLKIN_MAINPLL << 24);
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /* Set USB PLL dividers for 480 MHz (for USB0) */
bogdanm 0:9b334a45a8ff 275 LPC_CGU->PLL[CGU_USB_PLL].PLL_MDIV = 0x06167FFA;
bogdanm 0:9b334a45a8ff 276 LPC_CGU->PLL[CGU_USB_PLL].PLL_NP_DIV = 0x00302062;
bogdanm 0:9b334a45a8ff 277 LPC_CGU->PLL[CGU_USB_PLL].PLL_CTRL = 0x0000081D | (CLKIN_CRYSTAL << 24);
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 /* Set IDIVE clock to PLL1/2 = 102 MHz */
bogdanm 0:9b334a45a8ff 280 LPC_CGU->IDIV_CTRL[CLK_IDIV_E] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282 /* Set IDIVD clock to ((USBPLL/4) / 2) = 60 MHz (for USB1) */
bogdanm 0:9b334a45a8ff 283 LPC_CGU->IDIV_CTRL[CLK_IDIV_A] = (3 << 2) | (1 << 11) | (CLKIN_USBPLL << 24); /* USBPLL/4 */
bogdanm 0:9b334a45a8ff 284 LPC_CGU->IDIV_CTRL[CLK_IDIV_D] = (1 << 2) | (1 << 11) | (CLKIN_IDIVA << 24); /* IDIVA/2 */
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 /* Configure remaining integer dividers */
bogdanm 0:9b334a45a8ff 287 LPC_CGU->IDIV_CTRL[CLK_IDIV_B] = (0 << 2) | (1 << 11) | (CLKIN_IRC << 24); /* IRC */
bogdanm 0:9b334a45a8ff 288 LPC_CGU->IDIV_CTRL[CLK_IDIV_C] = (1 << 2) | (1 << 11) | (CLKIN_MAINPLL << 24); /* PLL1/2 */
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290 /* Connect base clocks */
bogdanm 0:9b334a45a8ff 291 for (i = 0; i < COUNT_OF(clock_states); i++) {
bogdanm 0:9b334a45a8ff 292 LPC_CGU->BASE_CLK[clock_states[i].clk] =
bogdanm 0:9b334a45a8ff 293 ( clock_states[i].powerdn << 0)
bogdanm 0:9b334a45a8ff 294 | (1 << 11) | (clock_states[i].clkin << 24);
bogdanm 0:9b334a45a8ff 295 }
bogdanm 0:9b334a45a8ff 296 #endif /* CLOCK_SETUP */
bogdanm 0:9b334a45a8ff 297 /* Reset peripherals */
bogdanm 0:9b334a45a8ff 298 LPC_RGU->RESET_CTRL0 = 0x105F0000;
bogdanm 0:9b334a45a8ff 299 LPC_RGU->RESET_CTRL1 = 0x01DFF7FF;
bogdanm 0:9b334a45a8ff 300 }
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 /*
bogdanm 0:9b334a45a8ff 303 * SystemSetupPins() - Configure MCU pins
bogdanm 0:9b334a45a8ff 304 */
bogdanm 0:9b334a45a8ff 305 void SystemSetupPins(const PINMUX_GRP_T *mux, uint32_t n)
bogdanm 0:9b334a45a8ff 306 {
bogdanm 0:9b334a45a8ff 307 uint32_t i;
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 for (i = 0; i < n; i++) {
bogdanm 0:9b334a45a8ff 310 *(mux[i].reg) = mux[i].mode;
bogdanm 0:9b334a45a8ff 311 }
bogdanm 0:9b334a45a8ff 312 }
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 /*
bogdanm 0:9b334a45a8ff 315 * SystemSetupMemory() - Configure external memory
bogdanm 0:9b334a45a8ff 316 */
bogdanm 0:9b334a45a8ff 317 void SystemSetupMemory(void)
bogdanm 0:9b334a45a8ff 318 {
bogdanm 0:9b334a45a8ff 319 #if (MEMORY_SETUP)
bogdanm 0:9b334a45a8ff 320 /* None required for boards without external memory */
bogdanm 0:9b334a45a8ff 321 #endif /* MEMORY_SETUP */
bogdanm 0:9b334a45a8ff 322 }
bogdanm 0:9b334a45a8ff 323
bogdanm 0:9b334a45a8ff 324 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
bogdanm 0:9b334a45a8ff 325 /*
bogdanm 0:9b334a45a8ff 326 * fpuInit() - Early initialization of the FPU
bogdanm 0:9b334a45a8ff 327 */
bogdanm 0:9b334a45a8ff 328 void fpuInit(void)
bogdanm 0:9b334a45a8ff 329 {
bogdanm 0:9b334a45a8ff 330 /*
bogdanm 0:9b334a45a8ff 331 * from ARM TRM manual:
bogdanm 0:9b334a45a8ff 332 * ; CPACR is located at address 0xE000ED88
bogdanm 0:9b334a45a8ff 333 * LDR.W R0, =0xE000ED88
bogdanm 0:9b334a45a8ff 334 * ; Read CPACR
bogdanm 0:9b334a45a8ff 335 * LDR R1, [R0]
bogdanm 0:9b334a45a8ff 336 * ; Set bits 20-23 to enable CP10 and CP11 coprocessors
bogdanm 0:9b334a45a8ff 337 * ORR R1, R1, #(0xF << 20)
bogdanm 0:9b334a45a8ff 338 * ; Write back the modified value to the CPACR
bogdanm 0:9b334a45a8ff 339 * STR R1, [R0]
bogdanm 0:9b334a45a8ff 340 */
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
bogdanm 0:9b334a45a8ff 343 volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
bogdanm 0:9b334a45a8ff 344 volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
bogdanm 0:9b334a45a8ff 345 volatile uint32_t Cpacr;
bogdanm 0:9b334a45a8ff 346 volatile uint32_t Mvfr0;
bogdanm 0:9b334a45a8ff 347 volatile uint32_t Mvfr1;
bogdanm 0:9b334a45a8ff 348 char vfpPresent = 0;
bogdanm 0:9b334a45a8ff 349
bogdanm 0:9b334a45a8ff 350 Mvfr0 = *regMvfr0;
bogdanm 0:9b334a45a8ff 351 Mvfr1 = *regMvfr1;
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 if (vfpPresent) {
bogdanm 0:9b334a45a8ff 356 Cpacr = *regCpacr;
bogdanm 0:9b334a45a8ff 357 Cpacr |= (0xF << 20);
bogdanm 0:9b334a45a8ff 358 *regCpacr = Cpacr; /* enable CP10 and CP11 for full access */
bogdanm 0:9b334a45a8ff 359 }
bogdanm 0:9b334a45a8ff 360 }
bogdanm 0:9b334a45a8ff 361 #endif /* defined(__FPU_PRESENT) && __FPU_PRESENT == 1 */
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 /* Approximate delay function */
bogdanm 0:9b334a45a8ff 364 #define CPU_NANOSEC(x) (((uint64_t) (x) * SystemCoreClock) / 1000000000)
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 static void WaitUs(uint32_t us)
bogdanm 0:9b334a45a8ff 367 {
bogdanm 0:9b334a45a8ff 368 volatile uint32_t cyc = us * CPU_NANOSEC(1000) / 4;
bogdanm 0:9b334a45a8ff 369 while (cyc--)
bogdanm 0:9b334a45a8ff 370 ;
bogdanm 0:9b334a45a8ff 371 }
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 #endif /* !defined(CORE_M0) */