fix LPC812 PWM
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Diff: targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h
- Revision:
- 80:bdf1132a57cf
- Parent:
- 0:9b334a45a8ff
--- a/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h Wed Mar 02 10:15:13 2016 +0000 +++ b/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M3/SMM_MPS2.h Wed Mar 02 14:30:11 2016 +0000 @@ -1,36 +1,36 @@ /* MPS2 CMSIS Library * -* Copyright (c) 2006-2015 ARM Limited +* Copyright (c) 2006-2016 ARM Limited * All rights reserved. -* -* Redistribution and use in source and binary forms, with or without +* +* Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, +* +* 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. -* -* 3. Neither the name of the copyright holder nor the names of its contributors -* may be used to endorse or promote products derived from this software without +* +* 3. Neither the name of the copyright holder nor the names of its contributors +* may be used to endorse or promote products derived from this software without * specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* * File: smm_mps2.h -* Release: Version 1.0 +* Release: Version 1.1 *******************************************************************************/ #ifndef __SMM_MPS2_H @@ -46,7 +46,7 @@ /* FPGA System Register declaration */ /******************************************************************************/ -typedef struct +typedef struct { __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections // [31:2] : Reserved @@ -65,11 +65,14 @@ // Bit[31:0] : reload value for prescale counter __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. + // The Cycle Up Counter increment when the prescale down counter reach 0 + // The pre-scaler counter is reloaded with PRESCALE after reaching 0. uint32_t RESERVED4[9]; __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:7] : Reserved + // [31:10] : Reserved + // [9] : SHIELD_1_SPI_nCS + // [8] : SHIELD_0_SPI_nCS + // [7] : ADC_SPI_nCS // [6] : CLCD_BL_CTRL // [5] : CLCD_RD // [4] : CLCD_RS @@ -93,12 +96,18 @@ #define CLCD_RD_Msk (1UL<<CLCD_RD_Pos) #define CLCD_BL_Pos 6 #define CLCD_BL_Msk (1UL<<CLCD_BL_Pos) +#define ADC_nCS_Pos 7 +#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos) +#define SHIELD_0_nCS_Pos 8 +#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos) +#define SHIELD_1_nCS_Pos 9 +#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos) /******************************************************************************/ /* SCC Register declaration */ /******************************************************************************/ -typedef struct // +typedef struct // { __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT // [31:1] : Reserved @@ -308,10 +317,10 @@ typedef struct { union { - __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) - __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) }; - __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) } MPS2_I2C_TypeDef; #define SDA 1 << 1 @@ -346,7 +355,7 @@ // <4=> Undefined! // <5=> Undefined! // <6=> Undefined! - // <7=> Undefined! + // <7=> Undefined! // <o.14..12> RX Buffer Water Level // <0=> Undefined! // <1=> / IRQ triggers when less than 1 space available @@ -355,7 +364,7 @@ // <4=> / IRQ triggers when less than 4 space available // <5=> Undefined! // <6=> Undefined! - // <7=> Undefined! + // <7=> Undefined! // <o.16> FIFO reset // <0=> Normal operation // <1=> FIFO reset @@ -363,12 +372,12 @@ // <0=> Normal operation // <1=> Assert audio Codec reset /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // <h> STATUS </h> + __I uint32_t STATUS; // <h> STATUS </h> // <o.0> TX Buffer alert // <0=> TX buffer don't need service yet // <1=> TX buffer need service // <o.1> RX Buffer alert - // <0=> RX buffer don't need service yet + // <0=> RX buffer don't need service yet // <1=> RX buffer need service // <o.2> TX Buffer Empty // <0=> TX buffer have data @@ -383,33 +392,33 @@ // <0=> RX buffer not full // <1=> RX buffer full union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // <h> ERROR </h> + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; // <h> ERROR </h> // <o.0> TX error // <0=> Okay // <1=> TX overrun/underrun // <o.1> RX error - // <0=> Okay + // <0=> Okay // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // <h> ERRORCLR </h> + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; // <h> ERRORCLR </h> // <o.0> TX error // <0=> Okay // <1=> Clear TX error // <o.1> RX error - // <0=> Okay + // <0=> Okay // <1=> Clear RX error }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h> - // <o.9..0> TX error (default 0x80) + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h> + // <o.9..0> TX error (default 0x80) /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // <h> Transmit buffer </h> - // <o.15..0> Right channel + __O uint32_t TXBUF; // <h> Transmit buffer </h> + // <o.15..0> Right channel // <o.31..16> Left channel /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // <h> Receive buffer </h> - // <o.15..0> Right channel + __I uint32_t RXBUF; // <h> Receive buffer </h> + // <o.15..0> Right channel // <o.31..16> Left channel uint32_t RESERVED1[186]; __IO uint32_t ITCR; // <h> Integration Test Control Register </h> @@ -556,7 +565,12 @@ #define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */ #define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */ #define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */ +#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */ +#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */ +#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */ #define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */ +#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */ +#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */ #define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */ #ifdef CORTEX_M7 @@ -565,8 +579,8 @@ #define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */ #endif +#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */ #define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */ -#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */ /******************************************************************************/ /* Peripheral declaration */ @@ -575,11 +589,16 @@ #define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE ) #define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE ) #define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE ) +#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE ) +#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE ) #define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE ) #define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE ) #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE ) #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE ) #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE ) +#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE ) +#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE ) +#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE ) /******************************************************************************/ /* General Function Definitions */