en 129
fix LPC812 PWM
Fork of
mbed-dev
by 
mbed official
Diff: targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c
- Revision:
- 113:b3775bf36a83
- Parent:
- 0:9b334a45a8ff
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c Tue Apr 19 11:15:15 2016 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief Extended RCC HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -24,7 +24,7 @@
(##) Prepare synchronization configuration necessary for HSI48 calibration
(+++) Default values can be set for frequency Error Measurement (reload and error limit)
and also HSI48 oscillator smooth trimming.
- (+++) Macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE can be also used to calculate
+ (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
directly reload value with target and synchronization frequencies values
(##) Call function HAL_RCCEx_CRSConfig which
(+++) Reset CRS registers to their default values.
@@ -60,7 +60,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -94,14 +94,14 @@
* @{
*/
+#ifdef HAL_RCC_MODULE_ENABLED
+
/** @addtogroup RCCEx
* @brief RCC Extension HAL module driver
* @{
*/
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/** @defgroup RCCEx_Private_Constants
+/** @addtogroup RCCEx_Private
* @{
*/
/* Bit position in register */
@@ -109,6 +109,9 @@
#define CRS_CR_TRIM_BITNUMBER 8
#define CRS_ISR_FECAP_BITNUMBER 16
+#if defined(USB)
+extern const uint8_t PLLMulTable[];
+#endif //USB
/**
* @}
*/
@@ -144,25 +147,34 @@
* @note This function does not modify the configuration of the
* @note -Peripheral clocks
* @note -HSI48, LSI, LSE and RTC clocks
- * @param None
* @retval None
*/
void HAL_RCC_DeInit(void)
{
+ __IO uint32_t tmpreg;
+
/* Set MSION bit */
SET_BIT(RCC->CR, RCC_CR_MSION);
#if defined(STM32L073xx) || defined(STM32L083xx) || \
defined(STM32L072xx) || defined(STM32L082xx) || \
- defined(STM32L071xx) || defined(STM32L081xx)
+ defined(STM32L071xx) || defined(STM32L081xx) || \
+ defined(STM32L031xx) || defined(STM32L041xx)
/* Reset HSE, HSI, CSS, PLL */
CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
+#elif defined(STM32L011xx) || defined(STM32L021xx)
+ CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \
+ RCC_CR_HSEON | RCC_CR_PLLON);
#else
CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \
RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON);
#endif
+ /* Delay after an RCC peripheral clock */ \
+ tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \
+ UNUSED(tmpreg);
+
/* Reset HSEBYP bit */
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
@@ -177,6 +189,8 @@
* @brief Initializes the RCC extended peripherals clocks
* @note Initializes the RCC extended peripherals clocks according to the specified parameters in the
* RCC_PeriphCLKInitTypeDef.
+ * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with HAL_RCC_OscConfig()
+ * to possibly update HSE divider.
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1,
* I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks).
@@ -184,13 +198,88 @@
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0;
uint32_t tmpreg = 0;
/* Check the parameters */
- assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection));
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*---------------------------- RTC/LCD configuration -------------------------------*/
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
+ || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
+#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
+ )
+ {
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ if( ((RCC->CR & RCC_CR_RTCPRE) != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
+#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
+ || ((RCC->CR & RCC_CR_RTCPRE) != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
+#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
+ )
+ { /* Check HSE State */
+ if (((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) && HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+ {
+ /*To update HSE divider, first switch-OFF HSE clock oscillator*/
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable Power Clock*/
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
-#if !defined (STM32L031xx) && !defined (STM32L041xx)
+ while((PWR->CR & PWR_CR_DBP) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ if( ((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL))
+#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
+ || ((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL))
+#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
+ )
+ {
+ /* Store the content of CSR register before the reset of Backup Domain */
+ tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+ /* Restore the Content of CSR register */
+ RCC->CSR = tmpreg;
+
+ /* Wait for LSERDY if LSE was enabled */
+ if (HAL_IS_BIT_SET(tmpreg, RCC_CSR_LSERDY))
+ {
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* RTC Clock update*/
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+
+ }
+ }
+
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
/*------------------------------- USART1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
{
@@ -245,68 +334,7 @@
}
#endif /* defined (STM32L071xx) (STM32L072xx)|| (STM32L073xx)|| (STM32L081xx)|| (STM32L082xx) || (STM32L083xx) */
- /*---------------------------- RTC/LCD configuration -------------------------------*/
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
-#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
- || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
-#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
- )
- {
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* Enable write access to Backup domain */
- PWR->CR |= PWR_CR_DBP;
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while((PWR->CR & PWR_CR_DBP) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset the Backup domain only if the RTC Clock source selection is modified */
- if(((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL))
-#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
- || (tmpreg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL))
-#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
- )
- {
- /* Store the content of CSR register before the reset of Backup Domain */
- tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
- /* RTC Clock selection can be changed only if the Backup Domain is reset */
- __HAL_RCC_BACKUPRESET_FORCE();
- __HAL_RCC_BACKUPRESET_RELEASE();
- /* Restore the Content of CSR register */
- RCC->CSR = tmpreg;
- }
-
- /* If LSE is selected as RTC clock source, wait for LSE reactivation */
- if((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
-#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
- || (PeriphClkInit->LCDClockSelection == RCC_RTCCLKSOURCE_LSE)
-#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
- )
- {
- /* Get timeout */
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- }
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/*---------------------------- USB and RNG configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
{
@@ -337,7 +365,7 @@
{
/* Set all possible values for the extended clock type parameter -----------*/
/* Common part first */
-#if defined(STM32L031xx) || defined(STM32L041xx)
+#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \
RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPTIM1;
#endif
@@ -372,7 +400,7 @@
RCC_PERIPHCLK_LPTIM1;
#endif
-#if !defined (STM32L031xx) && !defined (STM32L041xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
/* Get the USART1 configuration --------------------------------------------*/
PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
#endif
@@ -395,15 +423,373 @@
PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/* Get the USB/RNG clock source -----------------------------------------------*/
PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
#endif
}
/**
+ * @brief Return the peripheral clock frequency for some peripherals
+ * @note Return 0 if peripheral clock identifier not managed by this API
+ * @param PeriphClk: Peripheral clock identifier
+ * This parameter can be one of the following values:
+ * @arg RCC_PERIPHCLK_RTC: RTC peripheral clock
+ * @arg RCC_PERIPHCLK_LCD: LCD peripheral clock (*)
+ * @arg RCC_PERIPHCLK_USB: USB or RNG peripheral clock (*)
+ * @arg RCC_PERIPHCLK_USART1: USART1 peripheral clock (*)
+ * @arg RCC_PERIPHCLK_USART2: USART2 peripheral clock
+ * @arg RCC_PERIPHCLK_LPUART1: LPUART1 peripheral clock
+ * @arg RCC_PERIPHCLK_I2C1: I2C1 peripheral clock
+ * @arg RCC_PERIPHCLK_I2C2: I2C2 peripheral clock (*)
+ * @arg RCC_PERIPHCLK_I2C3: I2C3 peripheral clock (*)
+ * @note (*) means that this peripheral is not present on all the STM32L0xx devices
+ * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+ uint32_t srcclk = 0, clkprediv = 0, frequency = 0;
+#if defined(USB)
+ uint32_t pllmul = 0, plldiv = 0, pllvco = 0;
+#endif /* USB */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
+
+ switch(PeriphClk)
+ {
+ case RCC_PERIPHCLK_RTC:
+ {
+ /* Get the current RTC source */
+ srcclk = __HAL_RCC_GET_RTC_SOURCE();
+
+ /* Check if LSE is ready and if RTC clock selection is LSE */
+ if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready and if RTC clock selection is LSI */
+ else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+ {
+ frequency = LSI_VALUE;
+ }
+ /* Check if HSE is ready and if RTC clock selection is HSE*/
+ else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
+ {
+ /* Get the current HSE clock divider*/
+ clkprediv=__HAL_RCC_GET_RTC_HSE_PRESCALER();
+
+ switch (clkprediv)
+ {
+ case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */
+ {
+ frequency = HSE_VALUE / 16;
+ break;
+ }
+ case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */
+ {
+ frequency = HSE_VALUE / 8;
+ break;
+ }
+ case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */
+ {
+ frequency = HSE_VALUE / 4;
+ break;
+ }
+ default:
+ {
+ frequency = HSE_VALUE / 2;
+ break;
+ }
+ }
+ }
+ /* Clock not enabled for RTC*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+
+#if defined(LCD)
+
+ case RCC_PERIPHCLK_LCD:
+ {
+ /* Get the current LCD source */
+ srcclk = __HAL_RCC_GET_LCD_SOURCE();
+
+ /* Check if LSE is ready and if LCD clock selection is LSE */
+ if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Check if LSI is ready and if LCD clock selection is LSI */
+ else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
+ {
+ frequency = LSI_VALUE;
+ }
+ /* Check if HSE is ready and if LCD clock selection is HSE*/
+ else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
+ {
+ /* Get the current HSE clock divider*/
+ clkprediv=__HAL_RCC_GET_RTC_HSE_PRESCALER();
+
+ switch (clkprediv)
+ {
+ case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */
+ {
+ frequency = HSE_VALUE / 16;
+ break;
+ }
+ case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */
+ {
+ frequency = HSE_VALUE / 8;
+ break;
+ }
+ case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */
+ {
+ frequency = HSE_VALUE / 4;
+ break;
+ }
+ default:
+ {
+ frequency = HSE_VALUE / 2;
+ break;
+ }
+ }
+ }
+ /* Clock not enabled for LCD*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* LCD */
+
+#if defined(USB)
+ case RCC_PERIPHCLK_USB:
+ {
+ /* Get the current USB source */
+ srcclk = __HAL_RCC_GET_USB_SOURCE();
+
+ if((srcclk == RCC_USBCLKSOURCE_PLL) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
+ {
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+ plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+ pllmul = PLLMulTable[(pllmul >> 18)];
+ plldiv = (plldiv >> 22) + 1;
+
+ /* Compute PLL clock input */
+ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)
+ {
+ if (READ_BIT(RCC->CR, RCC_CR_HSIDIVF) != 0)
+ {
+ pllvco = (HSI_VALUE >> 2);
+ }
+ else
+ {
+ pllvco = HSI_VALUE;
+ }
+ }
+ else /* HSE source */
+ {
+ pllvco = HSE_VALUE;
+ }
+ /* pllvco * pllmul / plldiv */
+ pllvco = (pllvco * pllmul);
+ frequency = (pllvco/ plldiv);
+
+ }
+ else if((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)))
+ {
+ frequency = HSI48_VALUE;
+ }
+ else /* RCC_USBCLKSOURCE_NONE */
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* USB */
+#if defined(USART1)
+ case RCC_PERIPHCLK_USART1:
+ {
+ /* Get the current USART1 source */
+ srcclk = __HAL_RCC_GET_USART1_SOURCE();
+
+ /* Check if USART1 clock selection is PCLK2 */
+ if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
+ {
+ frequency = HAL_RCC_GetPCLK2Freq();
+ }
+ /* Check if HSI is ready and if USART1 clock selection is HSI */
+ else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART1 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART1 clock selection is LSE */
+ else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART1*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* USART1 */
+ case RCC_PERIPHCLK_USART2:
+ {
+ /* Get the current USART2 source */
+ srcclk = __HAL_RCC_GET_USART2_SOURCE();
+
+ /* Check if USART2 clock selection is PCLK1 */
+ if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if USART2 clock selection is HSI */
+ else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if USART2 clock selection is SYSCLK */
+ else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if USART2 clock selection is LSE */
+ else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for USART2*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_LPUART1:
+ {
+ /* Get the current LPUART1 source */
+ srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
+
+ /* Check if LPUART1 clock selection is PCLK1 */
+ if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if LPUART1 clock selection is HSI */
+ else if ((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if LPUART1 clock selection is SYSCLK */
+ else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Check if LSE is ready and if LPUART1 clock selection is LSE */
+ else if ((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)))
+ {
+ frequency = LSE_VALUE;
+ }
+ /* Clock not enabled for LPUART1*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+ case RCC_PERIPHCLK_I2C1:
+ {
+ /* Get the current I2C1 source */
+ srcclk = __HAL_RCC_GET_I2C1_SOURCE();
+
+ /* Check if I2C1 clock selection is PCLK1 */
+ if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if I2C1 clock selection is HSI */
+ else if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if I2C1 clock selection is SYSCLK */
+ else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Clock not enabled for I2C1*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#if defined(I2C2)
+ case RCC_PERIPHCLK_I2C2:
+ {
+
+ /* Check if I2C2 on APB1 clock enabled*/
+ if (READ_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))==RCC_APB1ENR_I2C2EN)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* I2C2 */
+
+#if defined(I2C3)
+ case RCC_PERIPHCLK_I2C3:
+ {
+ /* Get the current I2C1 source */
+ srcclk = __HAL_RCC_GET_I2C3_SOURCE();
+
+ /* Check if I2C3 clock selection is PCLK1 */
+ if (srcclk == RCC_I2C3CLKSOURCE_PCLK1)
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ /* Check if HSI is ready and if I2C3 clock selection is HSI */
+ else if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
+ {
+ frequency = HSI_VALUE;
+ }
+ /* Check if I2C3 clock selection is SYSCLK */
+ else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK)
+ {
+ frequency = HAL_RCC_GetSysClockFreq();
+ }
+ /* Clock not enabled for I2C3*/
+ else
+ {
+ frequency = 0;
+ }
+ break;
+ }
+#endif /* I2C3 */
+ }
+ return(frequency);
+}
+
+/**
* @brief Enables the LSE Clock Security System.
- * @param None
* @retval None
*/
void HAL_RCCEx_EnableLSECSS(void)
@@ -413,15 +799,64 @@
/**
* @brief Disables the LSE Clock Security System.
- * @param None
* @retval None
*/
void HAL_RCCEx_DisableLSECSS(void)
{
+ /* Disable LSE CSS */
CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
+
+ /* Disable LSE CSS IT */
+ __HAL_RCC_DISABLE_IT(RCC_IT_CSSLSE);
+}
+
+/**
+ * @brief Enable the LSE Clock Security System IT & corresponding EXTI line.
+ * @note LSE Clock Security System IT is mapped on RTC EXTI line 19
+ * @retval None
+ */
+void HAL_RCCEx_EnableLSECSS_IT(void)
+{
+ /* Enable LSE CSS */
+ SET_BIT(RCC->CSR, RCC_CSR_LSECSSON) ;
+
+ /* Enable LSE CSS IT */
+ __HAL_RCC_ENABLE_IT(RCC_IT_CSSLSE);
+
+ /* Enable IT on EXTI Line 19 */
+ __HAL_RCC_LSECSS_EXTI_ENABLE_IT();
+ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
}
-#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+/**
+ * @brief Handle the RCC LSE Clock Security System interrupt request.
+ * @retval None
+ */
+void HAL_RCCEx_LSECSS_IRQHandler(void)
+{
+ /* Check RCC LSE CSSF flag */
+ if(__HAL_RCC_GET_IT(RCC_IT_CSSLSE))
+ {
+ /* RCC LSE Clock Security System interrupt user callback */
+ HAL_RCCEx_LSECSS_Callback();
+
+ /* Clear RCC LSE CSS pending bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_CSSLSE);
+ }
+}
+
+/**
+ * @brief RCCEx LSE Clock Security System interrupt callback.
+ * @retval none
+ */
+__weak void HAL_RCCEx_LSECSS_Callback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
+ */
+}
+
+#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
/**
* @brief Start automatic synchronization using polling mode
@@ -479,16 +914,15 @@
/* START AUTOMATIC SYNCHRONIZATION*/
/* Enable Automatic trimming */
- __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB();
+ __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE();
/* Enable Frequency error counter */
- __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER();
+ __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE();
}
/**
* @brief Generate the software synchronization event
- * @param None
* @retval None
*/
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
@@ -617,7 +1051,6 @@
}
/**
* @brief Enables Vrefint for the HSI48.
- * @param None
* @note This is functional only if the LOCK is not set
* @retval None
*/
@@ -630,7 +1063,6 @@
/**
* @brief Disables the Vrefint for the HSI48.
- * @param None.
* @note This is functional only if the LOCK is not set
* @retval None
*/
@@ -640,8 +1072,15 @@
/* and the EN_VREFINT bit in the CFGR3 register */
CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT));
}
-#endif /* !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
+#endif /* !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -652,9 +1091,6 @@
*/
#endif /* HAL_RCC_MODULE_ENABLED */
-/**
- * @}
- */
/**
* @}