en 129
fix LPC812 PWM
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by 
mbed official
Diff: targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h
- Revision:
- 113:b3775bf36a83
- Parent:
- 0:9b334a45a8ff
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h Tue Apr 19 11:15:15 2016 +0100
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32l0xx_hal_adc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 06-February-2015
+ * @version V1.5.0
+ * @date 8-January-2016
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -51,25 +51,49 @@
* @{
*/
-/** @addtogroup ADC
+/** @defgroup ADC ADC
* @{
*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+
/* Exported types ------------------------------------------------------------*/
/**
- * @brief HAL State structures definition
+ * @brief HAL ADC state machine: ADC states definition (bitfields)
*/
-typedef enum
-{
- HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */
- HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */
- HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
- HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */
- HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */
- HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */
- HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */
-}HAL_ADC_StateTypeDef;
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+ external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F0 device: End Of Sampling flag raised */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+ external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on STM32F0 device: Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */
/**
@@ -101,7 +125,10 @@
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t ClockPrescaler; /*!< Selects the ADC clock frequency.
This parameter can be a value of @ref ADC_ClockPrescaler
- Note: This parameter can be modified only if ADC is disabled. */
+ Note: This parameter can be modified only if ADC is disabled.
+ Note: In case of Synchronous clock mode divided by 1, this configuration must be enabled only
+ if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC
+ must be bypassed and the system clock must by 50% duty cycle). Refer to reference manual for details */
uint32_t Resolution; /*!< Configures the ADC resolution mode.
This parameter can be a value of @ref ADC_Resolution
Note: This parameter can be modified only if ADC is disabled. */
@@ -109,6 +136,9 @@
This parameter can be a value of @ref ADC_sampling_times
Note: This parameter can be modified only if there is no conversion ongoing. */
uint32_t ScanConvMode; /*!< The scan sequence direction.
+ If several channels are set: Conversions are performed in sequence mode
+ (ranks defined by each channel number: channel 0 fixed on rank 0,
+ channel 1 fixed on rank1, ...).
This parameter can be a value of @ref ADC_Scan_mode
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
@@ -122,11 +152,13 @@
Discontinuous mode can be enabled only if continuous mode is disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
- uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger.
- This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge
+ uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion.
+ If set to ADC_SOFTWARE_START, external triggers are disabled.
+ This parameter can be a value of @ref ADC_External_trigger_Source
Note: This parameter can be modified only if there is no conversion is ongoing. */
- uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion.
- This parameter can be a value of @ref ADC_External_trigger_Source
+ uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger.
+ If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
@@ -158,7 +190,7 @@
/**
* @brief ADC handle Structure definition
*/
-typedef struct __ADC_HandleTypeDef
+typedef struct
{
ADC_TypeDef *Instance; /*!< Register base address */
@@ -168,7 +200,7 @@
HAL_LockTypeDef Lock; /*!< ADC locking object */
- __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
}ADC_HandleTypeDef;
@@ -180,6 +212,12 @@
{
uint32_t Channel; /*!< the ADC channel to configure
This parameter can be a value of @ref ADC_channels */
+
+ uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
+ On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
+ (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
+ This parameter can be a value of @ref ADC_rank */
}ADC_ChannelConfTypeDef;
@@ -203,26 +241,30 @@
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
}ADC_AnalogWDGConfTypeDef;
+/**
+ * @}
+ */
+
/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADC_Exported_Constants
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
* @{
*/
-/** @defgroup ADC_Error_Code
+/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< OVR error */
-#define HAL_ADC_ERROR_DMA ((uint32_t)0x03) /*!< DMA transfer error */
+#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
/**
* @}
*/
-/** @defgroup ADC_TimeOut_Values
+/** @defgroup ADC_TimeOut_Values ADC TimeOut Values
* @{
*/
@@ -242,7 +284,7 @@
* @}
*/
-/** @defgroup ADC_ClockPrescaler
+/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode divided by 1 */
@@ -258,60 +300,34 @@
#define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */
#define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 1
+#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 1
This configuration must be enabled only if PCLK has a 50%
duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
must by 50% duty cycle)*/
-#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 4 */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 4 */
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
- ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\
- ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
/**
* @}
*/
-/** @defgroup ADC_Resolution
+/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
- ((RESOLUTION) == ADC_RESOLUTION_10B) || \
- ((RESOLUTION) == ADC_RESOLUTION_8B) || \
- ((RESOLUTION) == ADC_RESOLUTION_6B))
-
-#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
- ((RESOLUTION) == ADC_RESOLUTION_6B))
/**
* @}
*/
-/** @defgroup ADC_data_align
+/** @defgroup ADC_data_align ADC Data Align
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
- ((ALIGN) == ADC_DATAALIGN_LEFT))
/**
* @}
*/
@@ -323,63 +339,41 @@
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
+/**
+ * @}
+ */
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+/** @defgroup ADC_EOCSelection ADC EOC Selection
+ * @{
+ */
+#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
+#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
+#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
/**
* @}
*/
-/** @defgroup ADC_External_trigger_Source
+/** @defgroup ADC_Overrun ADC Overrun
* @{
- */
-#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)0x00000000)
-#define ADC_EXTERNALTRIGCONV_T21_CC2 ADC_CFGR1_EXTSEL_0
-#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_CFGR1_EXTSEL_1
-#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)0x000000C0)
-#define ADC_EXTERNALTRIGCONV_T22_TRGO ADC_CFGR1_EXTSEL_2
-#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_CFGR1_EXTSEL
-
-#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO ) || \
- ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2 ) || \
- ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO ) || \
- ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4 ) || \
- ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || \
- ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 ))
-
+ */
+#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
+#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
/**
* @}
*/
-/** @defgroup ADC_EOCSelection
+
+/** @defgroup ADC_rank ADC rank
* @{
*/
-#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
-#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
-#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
-
-#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
- ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \
- ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
+#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
+#define ADC_RANK_NONE ((uint32_t)0x00001001) /*!< Disable the selected rank (selected channel) from sequencer */
/**
* @}
- */
-
-/** @defgroup ADC_Overrun
- * @{
- */
-#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
-#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
+ */
-#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
- ((OVR) == ADC_OVR_DATA_OVERWRITTEN))
-/**
- * @}
- */
-/** @defgroup ADC_channels
+/** @defgroup ADC_channels ADC_Channels
* @{
*/
#define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0))
@@ -398,41 +392,23 @@
#define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
#define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
#define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
#define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)| ADC_CFGR1_AWDCH_4)
+#endif
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0)
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1)
/* Internal channels */
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
#define ADC_CHANNEL_VLCD ADC_CHANNEL_16
+#endif
#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
-
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
- ((CHANNEL) == ADC_CHANNEL_1) || \
- ((CHANNEL) == ADC_CHANNEL_2) || \
- ((CHANNEL) == ADC_CHANNEL_3) || \
- ((CHANNEL) == ADC_CHANNEL_4) || \
- ((CHANNEL) == ADC_CHANNEL_5) || \
- ((CHANNEL) == ADC_CHANNEL_6) || \
- ((CHANNEL) == ADC_CHANNEL_7) || \
- ((CHANNEL) == ADC_CHANNEL_8) || \
- ((CHANNEL) == ADC_CHANNEL_9) || \
- ((CHANNEL) == ADC_CHANNEL_10) || \
- ((CHANNEL) == ADC_CHANNEL_11) || \
- ((CHANNEL) == ADC_CHANNEL_12) || \
- ((CHANNEL) == ADC_CHANNEL_13) || \
- ((CHANNEL) == ADC_CHANNEL_14) || \
- ((CHANNEL) == ADC_CHANNEL_15) || \
- ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
- ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
- ((CHANNEL) == ADC_CHANNEL_VLCD))
-
/**
* @}
*/
-/** @defgroup ADC_Channel_AWD_Masks
+/** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks
* @{
*/
#define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFF)
@@ -442,7 +418,7 @@
*/
-/** @defgroup ADC_sampling_times
+/** @defgroup ADC_sampling_times ADC Sampling Cycles
* @{
*/
@@ -454,15 +430,6 @@
#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 55.5 CYCLES */
#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 71.5 CYCLES */
#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /*!< ADC sampling time 239.5 CYCLES */
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \
- ((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \
- ((TIME) == ADC_SAMPLETIME_13CYCLES_5 ) || \
- ((TIME) == ADC_SAMPLETIME_28CYCLES_5 ) || \
- ((TIME) == ADC_SAMPLETIME_41CYCLES_5 ) || \
- ((TIME) == ADC_SAMPLETIME_55CYCLES_5 ) || \
- ((TIME) == ADC_SAMPLETIME_71CYCLES_5 ) || \
- ((TIME) == ADC_SAMPLETIME_239CYCLES_5))
/**
* @}
*/
@@ -486,15 +453,11 @@
#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002) /*!< Scan direction backward: from channel 18 to channel 0 */
#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
-
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
- ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
-
/**
* @}
*/
-/** @defgroup ADC_Oversampling_Ratio
+/** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio
* @{
*/
@@ -506,19 +469,11 @@
#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014) /*!< ADC Oversampling ratio 64x */
#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018) /*!< ADC Oversampling ratio 128x */
#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001C) /*!< ADC Oversampling ratio 256x */
-#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \
- ((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
/**
* @}
*/
-/** @defgroup ADC_Right_Bit_Shift
+/** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift
* @{
*/
#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
@@ -530,67 +485,47 @@
#define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0) /*!< ADC 6 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0) /*!< ADC 7 bits shift for oversampling */
#define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100) /*!< ADC 8 bits shift for oversampling */
-#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || \
- ((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
/**
* @}
*/
-/** @defgroup ADC_Triggered_Oversampling_Mode
+/** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode
* @{
*/
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200) /*!< ADC No bit shift for oversampling */
-#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
- ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
/**
* @}
*/
-/** @defgroup ADC_analog_watchdog_mode
+/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
* @{
*/
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
-
-
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
/**
* @}
*/
-/** @defgroup ADC_conversion_type
+/** @defgroup ADC_conversion_type ADC Conversion Group
* @{
*/
#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
-#define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
/**
* @}
*/
-/** @defgroup ADC_Event_type
+/** @defgroup ADC_Event_type ADC Event
* @{
*/
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
-
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
- ((EVENT) == ADC_OVR_EVENT))
/**
* @}
*/
-/** @defgroup ADC_interrupts_definition
+/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
* @{
*/
#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready (ADRDY) interrupt source */
@@ -600,18 +535,13 @@
#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
#define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog 1 interrupt source */
#define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */
-
-/* Check of single flag */
-#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_RDY) || \
- ((IT) == ADC_IT_EOSMP) || ((IT) == ADC_IT_EOC) || \
- ((IT) == ADC_IT_EOS) || ((IT) == ADC_IT_OVR))
/**
* @}
*/
-/** @defgroup ADC_flags_definition
+/** @defgroup ADC_flags_definition ADC Flags Definition
* @{
*/
#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready (ADRDY) flag */
@@ -625,34 +555,6 @@
#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
ADC_FLAG_OVR | ADC_FLAG_AWD | ADC_FLAG_EOCAL)
-
-/* Check of single flag */
-#define IS_ADC_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
- ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \
- ((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_AWD) || \
- ((FLAG) == ADC_FLAG_EOCAL))
-/**
- * @}
- */
-
-
-/** @defgroup ADC_range_verification
- * in function of ADC resolution selected (12, 10, 8 or 6 bits)
- * @{
- */
-#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
- ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_nb_conv_verification
- * @{
- */
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
/**
* @}
*/
@@ -662,7 +564,7 @@
*/
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Macro
+/** @defgroup ADC_Exported_Macro ADC Exported Macro
* @{
*/
/** @brief Reset ADC handle state
@@ -727,14 +629,25 @@
* @retval None
*/
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
+/**
+ * @brief Test if conversion trigger of regular group is software start
+ * or external trigger.
+ * @param __HANDLE__: ADC handle
+ * @retval SET (software start) or RESET (external trigger)
+ */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
+ (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
+
+
/**
- * @brief Check if no conversion is ongoing on regular groups
+ * @brief Check if no conversion on going on regular group
* @param __HANDLE__: ADC handle
* @retval SET (conversion is on going) or RESET (no conversion is on going)
*/
-#define ADC_IS_CONVERSION_ONGOING(__HANDLE__) \
- (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART)) == RESET ) ? RESET : SET)
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
+ (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
+ ) ? RESET : SET)
/**
* @brief Enable ADC continuous conversion mode.
@@ -788,7 +701,7 @@
*/
#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
- /**
+/**
* @brief Enable the ADC Low Frequency mode.
* @param _LOW_FREQUENCY_MODE_: Low Frequency mode.
* @retval None
@@ -840,7 +753,8 @@
* @param __INTERRUPT__: ADC Interrupt.
* @retval None
*/
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable the ADC end of conversion interrupt.
@@ -848,14 +762,18 @@
* @param __INTERRUPT__: ADC interrupt.
* @retval None
*/
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the ADC Handle.
- * @param __INTERRUPT__: specifies the ADC interrupt source to check.
- * @retval The new state of __IT__ (TRUE or FALSE).
+ * @param __HANDLE__: ADC handle
+ * @param __INTERRUPT__: ADC interrupt source to check
+ * @arg ...
+ * @arg ...
+ * @retval State of interruption (TRUE or FALSE)
*/
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clear the ADC's pending flags
@@ -864,7 +782,8 @@
* @retval None
*/
/* Note: bit cleared bit by writing 1 */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (((__HANDLE__)->Instance->ISR) = (__FLAG__))
/**
* @brief Get the selected ADC's flag status.
@@ -872,7 +791,27 @@
* @param __FLAG__: ADC flag.
* @retval None
*/
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+
+/**
+ * @brief Simultaneously clears and sets specific bits of the handle State
+ * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Clear ADC error code (set it to error code: "no error")
+ * @param __HANDLE__: ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
+ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
@@ -900,6 +839,156 @@
} \
} while(0)
+
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\
+ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_10B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B))
+
+#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
+ ((RESOLUTION) == ADC_RESOLUTION_6B))
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+ ((ALIGN) == ADC_DATAALIGN_LEFT))
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
+
+#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
+ ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \
+ ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
+
+#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
+ ((OVR) == ADC_OVR_DATA_OVERWRITTEN))
+
+#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
+ ((WATCHDOG) == ADC_RANK_NONE))
+
+#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
+ ((CHANNEL) == ADC_CHANNEL_VLCD))
+#else
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
+ ((CHANNEL) == ADC_CHANNEL_1) || \
+ ((CHANNEL) == ADC_CHANNEL_2) || \
+ ((CHANNEL) == ADC_CHANNEL_3) || \
+ ((CHANNEL) == ADC_CHANNEL_4) || \
+ ((CHANNEL) == ADC_CHANNEL_5) || \
+ ((CHANNEL) == ADC_CHANNEL_6) || \
+ ((CHANNEL) == ADC_CHANNEL_7) || \
+ ((CHANNEL) == ADC_CHANNEL_8) || \
+ ((CHANNEL) == ADC_CHANNEL_9) || \
+ ((CHANNEL) == ADC_CHANNEL_10) || \
+ ((CHANNEL) == ADC_CHANNEL_11) || \
+ ((CHANNEL) == ADC_CHANNEL_12) || \
+ ((CHANNEL) == ADC_CHANNEL_13) || \
+ ((CHANNEL) == ADC_CHANNEL_14) || \
+ ((CHANNEL) == ADC_CHANNEL_15) || \
+ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((CHANNEL) == ADC_CHANNEL_VREFINT))
+#endif
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_13CYCLES_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_28CYCLES_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_41CYCLES_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_55CYCLES_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_71CYCLES_5 ) || \
+ ((TIME) == ADC_SAMPLETIME_239CYCLES_5))
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
+ ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
+
+#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \
+ ((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
+
+#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || \
+ ((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
+
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+ ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
+
+#define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
+ ((EVENT) == ADC_OVR_EVENT))
+
+
+/** @defgroup ADC_range_verification ADC Range Verification
+ * in function of ADC resolution selected (12, 10, 8 or 6 bits)
+ * @{
+ */
+#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
+ ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
+ * @{
+ */
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -908,13 +997,26 @@
#include "stm32l0xx_hal_adc_ex.h"
/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
/* Initialization and de-initialization functions **********************************/
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+/**
+ * @}
+ */
/* IO operation functions *****************************************************/
+/** @defgroup ADC_Exported_Functions_Group2 I/O operation functions
+ * @{
+ */
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
@@ -933,25 +1035,54 @@
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
/* Peripheral Control functions ***********************************************/
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+/**
+ * @}
+ */
/* Peripheral State functions *************************************************/
-HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
/**
* @}
*/
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup ADC_Private ADC Private
+ * @{
+ */
+/**
+ * @}
+ */
+/**************************************************************/
+
+/**
+ * @}
+ */
+
/**
* @}
*/